BITS Pilani, Pilani Campus

Once flowcharts(Level 2 flowcharts) have been optimized
using all the above techniques, one can begin to use them
for assigning the logic of
(a) Instruction Decoder

(b) control store design
(c) Next state control logic design
(d) Register decoding (Rx, Ry) and ALU opcode decoding
logic (with the aim of minimization of the decoding
logic)
BITS Pilani, Pilani Campus

Data Path & Control Design

Once flowcharts (Level 2 flowcharts), one can begin to use them
for assigning the logic of
(a) Instruction Decoder

(b) Control store design
(c) Next state control logic design
(d) Register decoding (Rx, Ry) and ALU opcode decoding
logic (with the aim of minimization of the decoding logic)

IB
Next
SB
Control State
control BC Instruction
Store DB decoders
Branch
OP TY NA Control
Unit
Control word IRE

decoders
IRF
Execution Unit

An instruction is fetched and placed in IRE
Translation of part of IRE provides the control store address
Each flow chart state address correspond to a control word
Control word specifies EU operations
Control word contains the next control word address

To personalize the control word
-The tasks become bits in the control fields (OP)
-The next state becomes the control store address select

(TY) and next address (NA)
- The state ID becomes the location of the control word

in a control store

OP TY NA
OP : Control Fields
fields of bits decoded to drive control lines in execution unit.
TY: Control store address Select

Next address type select
BC : Branch conditionally
NA modified by condition code from EU
DB: Direct Branch

Next control store address is NA
IB: Instruction branch- next control store address is from the control word
decoders using IRE (for next instruction)
SB: Sequence Branch : Next control store address is from control word decoders
using IRE (for next sequence)

Instruction Decoders
MIN Processor uses two instruction decoders
 One decoder points too the first control word in address mode sequence and
other points to the first control word in execution sequence
 The last state in any execution sequence shows IB in next state block . IB
instruction decoder points to the first control word sequence in the next
instruction sequence
 The last state in any address mode sequence shows SB in the next state block
SB instruction decoder points to the first control word in execution sequence
 Instruction with no address mode sequence IB points to first control word in

execution sequence

Example instruction execution
Instruction Control Next IB SB

word control Instruction Instruction
sequence word Decoder Decoder
address
POP popr1 popr2
popr2 brzz3
brzz3 brzz2
brzz2 - abdm1 oprm1
ADD RX (RY+d)@ abdm1 abdm2 oprm1
abdm2 abdm3 oprm1
abdm3 abdm4 oprm1
abdm4 - oprm1
oprm1 oprm2
oprm2 brzz3
brzz3 brzz2
brzz2 oprr1 BITS Pilani, Pilani Campus
Instruction Control Next IB SB
word control Instruction Instruction
sequence word Decoder Decoder
address
SUB RX, RY oprr1 oprr2

oprr2 brzz2
brzz2 - adrm1 test1
TEST RY @ adrm1 adrm1 test1

test1 ldrm2
ldrm2 push1
PUSH
Control word format
OP field contains fields for the execution unit
TY and NA fields for the next state address
AO PC T2 REGS T1 ALU K DI DO IRE IRF

Control word format
OP field contains fields for the execution unit
TY and NA fields for the next state address
AO PC T2 REGS T1 ALU K DI DO IRE IRF

PC control
Different uses off PC
pc  a
a  pc
b  pc
none
pc  a alu
pc  a rx

A-Bus
PC
0 1 B-Bus
0 none pc  a
1 b  pc
x
T2 control
Different uses off T2
t2  a
t2  b
a  t2
b  t2
none

A-Bus
t2a.t2b’
T2
t2a.t2b
t2b.t2a’
0 1 B-Bus
o none t2 a
1 b  t2 t2 b

ALU control
 All instructions use ALU for ADD to update PC
 ALU used for operand address calculation
 Arithmetic and logical instructions use ALU for the

requisite operation

Control word states
a  alu ; +1  alu ; add-n ; alu  t1
a  alu ; b  alu ; add-n ; alu  t1
a  alu ; 0  alu ; add-s ; alu  t1
a  alu ; b  alu ; op-s ; alu  t1
a  alu ; -1  alu ; add-n ; alu  t1

SEL
IRE
LOAD CCR MPX
ADD
FLAGS
FUNC
A-BUS
A
L
T1 U 1
0
MPX
-1
LOAD T1
SEL
B-BUS

Building a 32-bit ALU
CarryIn Operation
a0 CarryIn
Multiplexor control line Result0
Operation ALU0
b0
CarryIn CarryOut
a
0 a1 CarryIn
Result1
ALU1
b1
1 CarryOut
Result
2 a2 CarryIn
b Result2
ALU2
b2
CarryOut
CarryOut
1-bit ALU for AND, OR and add
a31 CarryIn
Result31
ALU31
b31
Ripple-Carry Logic for 32-bit ALU

B inv e rt O p era tion
C arryIn
a
0 Binvert CarryIn Operation
R esult a0 CarryIn
b 0 2 b0 ALU0 Result0
Less
1
CarryOut
Less input of
L ess 3 the 31 most
significant ALUs
is always 0
a1 CarryIn
a. C arryO u t
b1 ALU1 Result1
1- bit ALU for the 31 least significant bits 0 Less
Extra set bit, to be routed to the Less input of the least significant 1-bit CarryOut
ALU, is computed from the most significant Result bit and the Overflow bit
Bin ve rt Op eration
a2 CarryIn
C arryIn
b2 ALU2 Result2
0 Less
a CarryOut
0
R esu lt CarryIn
b 0 2
1
a31 CarryIn Result31
Le ss 3 b31 ALU31 Set
0 Less Overflow
Set
Ov erflo w
O ve rflow
de tection
b.
32-bit ALU from 31 copies of ALU at top left and 1 copy
1-bit ALU for the most significant bit of ALU at bottom left in the most significant position
Control lines
load t1
load ccr
add / op select
alu b input select ( 2 bits)

Control word states decoder
pattern
a  alu ; +1  alu ; add-n ; alu  t1 101
a  alu ; b  alu ; add-n ; alu  t1 010
a  alu ; 0  alu ; add-s ; alu  t1 100
a  alu ; b  alu ; op-s ; alu  t1 110
a  alu ; -1  alu ; add-n ; alu  t1 111
none 000

Control lines decoder pattern
load t1 xxx i000
load ccr 1x0
add / op select 110
alu b input select ( 2 bits) x10

REG CONTROL
ry  a rx  a, ry  b
b  rx b  ry
ry  b; b  rx b  rx; a  ry
rx  a rx  a, b  ry
rx  b, b  ry none

REG CONTROL rx  a  alu
ry  b  alu
ry  a rx  a, ry  b edb  di
ry  a ao
b  rx b  ry
ry  b; b  rx b  rx; a  ry
rx  a rx  a, b  ry di  b  alu
rx  a  alu
rx  b, b  ry none
di  b  rx
t1  a  ry
ar3/(b r3)’
r3a
r3
MPX R3
r3b

OP RX MODE RY
AO PC T2 REGS T1 …
Control word reg MPX

Control field decoder
n- 2 n decoder
r
a  r / (b  r )’
ra
rb
OP RX MODE RY
AO PC T2 REGS T1 …
Control word reg RY

n- 2 n decoder
 ry
a  ry / (b  ry )’
ry  a
n- 2 n decoder
ry b
Control word reg
r3 a = (rx  a ).x3 + (ry a).y3 to A
r3 b = (rx  b ).x3 + (ry b).y3 to B

Control word states Control lines
ry  a ry  a
b  rx b  rx; rx
ry  b; b  rx b  rx; rx ; ry  b
rx  a rx  a
rx  b; b  ry rx  b; ry ;b  ry

Control word states Control lines
rx  a; ry  b rx  a; ry  b
b  ry b  ry; ry
b rx; a  ry b  rx; rx ; a  ry; ry
rx  a; b  ry rx  a; ry ; b  ry;
none none

Control lines for execution unit
rx  a
ry  a
rx  b
ry  b
ry
rx
a  ry
b  ry
b  rx
Control word Control field bit
states assignments
none 0000
b  rx 0001
ry  a 0010
rx  a 0011
b  ry 0100

Control word Control field bit
states assignments
rx  b, b  ry 0110
rx  a, b  ry 0111
ry  b, b  rx 1001
rx  a, ry  b 1011
b  rx, a  ry 1101

00 01 11 10
00 none b  rx rx  a ry  a
rx  a rx  b
01 b  ry b  ry
b  ry b  ry  ry
b  rx
11 a  ry
a  ry
b  rx rx  a
10
ry  b ry  b
b  rx rx  a
 rx
Control Decoder patterns
Lines
rx  a xx11
ry  a 0010
rx  b 0110
ry  b 10xx

Control Decoder patterns
Lines
 rx xx01
 ry x1xx
a  ry 11xx
b  rx xx01
b  ry 01xx

ry  a  alu
0010
ry  a  do
t1  b  a0, ry
0111

Input bit pattern 0111
Active control lines
rx  a xx11
 ry x1xx
b  ry 01xx

rx b  ry, t2 from strr1
Input bit pattern 0110
Active control lines
rx  b 0110
 ry x1xx
b  ry 01xx

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Once flowcharts(Level 2 flowcharts) have been optimized

(a) Instruction Decoder