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Analog Electronics

Lecture -3
16-01-2019

BITS Pilani, K K Birla Goa Campus


Op Amp stages with pin-outs of IC741

BITS Pilani, K K Birla Goa Campus


Op-amp Symbol

A A A

Manufacturer Code
Fairchild A A 741
National Semiconductor LM, LH, LF, TBA
Motorola MC, MFC
RCA CA, CD
Texas Instruments SN
Signetics N/S, NE/Se
BITS Pilani, K K Birla Goa Campus
Op-amp transfer Characteristics

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Op-amp Equivalent Circuit

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PSPICE Code

.SUBCKT OPAMP 2 1 4 0
RID 2 1 2MEG
RO 3 4 75
EA 3 0 2 1 2E5
.ENDS

.SUBCKT OPAMP Non-inverting inverting output ground


RID non-inverting inverting value
RO upper-end-of-AVid output
EA upper-end-of-Avid lower-end-of-AVid non-inverting inverting value
.ENDS

BITS Pilani, K K Birla Goa Campus


Open Loop configurations of op-amp

A A A

Vo=AVid=A (VS1-VS2)

BITS Pilani, K K Birla Goa Campus


Characteristics of an Ideal Op-amp

1. Input Offset Voltage , 6 mV for op-amp 741C


2. Input Offset Current, Iio=|IB1-IB2|=200 nA
3. Input Bias Current , IB=(IB1+IB2)/2, 500 nA
4. Differential Input Resistance, Rid=2 M
5. Input Capacitance, 1.4 pF
6. Input Voltage Range, 13V
7. Common Mode Rejection Ratio (CMRR), 90 dB
8. Power Supply Rejection Ratio(PSRR), 20V/V

BITS Pilani, K K Birla Goa Campus


Characteristics of an Ideal Op-amp

Parameter Ideal Practical Unit


Op-amp op-amp

Open Loop voltage gain A  100 dB -


Differential Input resistance Rid  1-10 M
Output resistance Ro 0 75 
Bandwidth ,BW  10 MHz

Output voltage with zero input 0 200 mV

Input offset current 0 20 nA

Common mode rejection ratio,  100 dB -


CMRR

Slew rate, SR  0.5 - 20 V/s

BITS Pilani, K K Birla Goa Campus


Feedback Configurations

a) Voltage -series feedback


b) Voltage -shunt feedback
c) Current-series feedback
d) Current-shunt feedback

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Feedback Configurations

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Ideal Operational Amplifier

I1 = I2 = 0
R0 = 0

BITS Pilani, K K Birla Goa Campus


Opamp Configurations

Basic Configurations of Op-amp

Inverting Amplifier

Current-to-voltage Amplifier

A Summing Amplifier

An Inverting Integrator

An Inverting Differentiator

Non-Inverting Amplifier

BITS Pilani, K K Birla Goa Campus


• The op-amp with negative feedback forces the two inputs v+ and
v- to have the same voltage, even though no current flows into
either input.
• This is sometimes called a “virtual short” or Virtual ground
• As long as the op-amp stays in its linear region, the output will
change up or down until v- is almost equal to v+
• The negative feedback forces the “virtual short” condition to
occur

BITS Pilani, K K Birla Goa Campus


Current – to - Voltage converter

V0  I RF
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A Summing Amplifier

BITS Pilani, K K Birla Goa Campus


+ I1 IF

+ I2

+
I3

V1  0 V2  0 V3  0 0  V0
  
R1 R2 R3 RF

 RF RF RF 
V0   V1  V2  V3 
 R1 R2 R3 

BITS Pilani, K K Birla Goa Campus


Basic Configurations of Op-amp

Inverting Amplifier

Current-to-voltage Amplifier

A Summing Amplifier

An Inverting Integrator

An Inverting Differentiator

Non-Inverting Amplifier

BITS Pilani, K K Birla Goa Campus


An Inverting Integrator

iR  iC
Vs  0 d (0  V0 )
C
R dt
t
1
V0 (t )   
RC 0
VS dt  V0 (0)
BITS Pilani, K K Birla Goa Campus
High Frequencies
Low Frequencies

Vout Zf Rf Vout Zf 1
   
Vin Z in R Vin Z in jRC

inverting amplifier ideal integrator

BITS Pilani, K K Birla Goa Campus


Low Frequencies
High Frequencies
Vout Zf Rf
  Vout Zf 1
Vin Z in R  
Vin Z in jRC

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Op-amp Integrator Example

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Op-amp Integrator Example with Long Pulse

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Circuit to set the initial condition

RF S2 is closed with S1 open – SET MODE


VC  Vcc
R2  RF S2 is Open with S1 Closed – RUN MODE
S2 and S1 are Open – HOLD MODE

BITS Pilani, K K Birla Goa Campus


Modified Sample and Hold circuit

BITS Pilani, K K Birla Goa Campus


Modified Sample and Hold circuit

BITS Pilani, K K Birla Goa Campus


Basic Configurations of Op-amp

Inverting Amplifier

Current-to-voltage Amplifier

A Summing Amplifier

An Inverting Integrator

An Inverting Differentiator

Non-Inverting Amplifier

BITS Pilani, K K Birla Goa Campus


Differentiator Circuit

iC  iR
d (Vs  0) 0  V0 analysis:
C  Vout Zf R
dt R     j R C
Vin Z in 1
dV
V0 (t )   RC s j C
dt
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Ideal Real

1
Z in  Rin 
j Cin
Vout Zf Rf j R f Cin
  
Vin Z in Rin 
1 j RinCin  1
j Cin
Low Frequencies High Frequencies

Vout Vout Rf
  j R f Cin 
Vin Vin Rin
ideal differentiator inverting amplifier
BITS Pilani, K K Birla Goa Campus
Low Frequencies High Frequencies

Vout Vout Rf
  j R f Cin 
Vin Vin Rin
BITS Pilani, K K Birla Goa Campus
Differentiator Circuit

BITS Pilani, K K Birla Goa Campus


Basic Configurations of Op-amp

Inverting Amplifier

Current-to-voltage Amplifier

A Summing Amplifier

An Inverting Integrator

An Inverting Differentiator

Non-Inverting Amplifier

BITS Pilani, K K Birla Goa Campus

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