EM78P418N

8-Bit Microprocessor with OTP ROM

EM78P418N Errata Document

Specification Revision History
Doc. Version Revision Description Date
1.0 Initial official version 2005/06/23
1.1 Added the IRC drift rate in the feature 2006/01/06
1.2 Added the EM78P418NAM SSOP 20Pins package 2006/02/22
1.3 Revised RE, RF, and IOCF0 registers contents 2006/06/01
1.4 1. Modified general description,pin assignment and features 2006/10/2
allotment.
2. Added green product information.
3. Modified functional block diagram.
1.5 Deleted the EM78P418NAM SSOP 20-pin package 2007/11/13
1.6 1.Modified package type name 2007/11/27
1. Added the EM78P418NSS24 SSOP 24-pin package
1.7 2008/09/17
2. Added EM78P418N Program Pin
1.8 Modified Appendix C EM78P418N Program Pin diagram 2009/11/03
1.9 Fixed HLP to “0” at Bit 3 of Code Option Word 0. 2011/1/11
2.0 Added back “HLP” for more function selection 2011/9/29

Version1.2 to Version1.3

A. attached items
N.A.
B. modified items
6.1.13 RE (WUCR: Wake-up Control
Register) Revised RE, RF
1 Page 15~17
registers contents
6.1.14 RF (Interrupt Status Register)

6.1.13 RE (WUCR: Wake-up Control Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EM78P417/8/9N “0” “0” “0” “0” ADWE CMPWE ICWE “0”
ICE418N Simulator C3 C2 C1 C0 ADWE CMPWE ICWE “0”

Bit 7 ~ Bit 4: [For EM78P417/8/9N]: Unimplemented, read as ‘0’

[With Simulator (C3~C0)]: IRC calibration bits in IRC oscillator mode. For
ICE418N simulator, these are the IRC calibration bits in IRC
oscillator mode.
C3 C2 C1 C0 Frequency (MHz)
0 0 0 0 (1-36%) x F
0 0 0 1 (1-31.5%) x F

Errata Document (V1.7) 09.29.2011 •1

EM78P418N
8-Bit Microprocessor with OTP ROM

0 0 1 0 (1-27%) x F
0 0 1 1 (1-22.5%) x F
0 1 0 0 (1-18%) x F
0 1 0 1 (1-13.5%) x F
0 1 1 0 (1-9%) x F
0 1 1 1 (1-4.5%) x F
1 1 1 1 F (default)
1 1 1 0 (1+4.5%) x F
1 1 0 1 (1+9%) x F
1 1 0 0 (1+135%) x F
1 0 1 1 (1+18%) x F
1 0 1 0 (1+22.5%) x F
1 0 0 1 (1+27%) x F
1 0 0 0 (1+31.5%) x F
Note: 1. Frequency values shown are theoretical and taken from an instance of a
high frequency mode. Hence are shown for reference only. Definite
values will depend on the actual process.
2. Similar way of calculation is also applicable to low frequency mode.

Bit 3 (ADWE): ADC wake-up enable bit

0 = Disable ADC wake-up
1 = Enable ADC wake-up

When the ADC Complete is used to wake-up EM78P417/8/9N

from sleep with AD conversion running, the ADWE bit must be set
to “Enable“.

Bit 2 (CMPWE): Comparator wake-up enable bit

0 = Disable Comparator wake-up
1 = Enable Comparator wake-up

When the Comparator output status change is used to wake-up

EM78P418/9N from sleep, the CMPWE bit must be set to
“Enable“.

Bit 1 (ICWE): Port 6 input change to wake-up status enable bit

0 = Disable Port 6 input change to wake-up status
1 = Enable Port 6 input change wake-up status

When the Port 6 Input Status Change is used to wake-up

EM78P417/8/9N from sleep, the ICWE bit must be set to “Enable“.

Bit 0: Not implemented, read as ‘0’

6.1.14 RF (Interrupt Status Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CMPIF PWM3IF PWM2IF PWM1IF ADIF EXIF ICIF TCIF

2• Errata Document (V1.7) 09.29.2011

 EM78P418N
8-Bit Microprocessor with OTP ROM

NOTE
■ “1” means interrupt request; “0” means no interrupt occurs.
■ RF can be cleared by instruction but cannot be set.
■ IOCF0 is the interrupt mask register.
■ Reading RF will result to "logic AND" of RF and IOCF0.

Bit 7 (CMPIF): Comparator interrupt flag. Set when a change occurs in the
Comparator output. Reset by software.

Bit 6 (PWM3IF): PWM3 (Pulse Width Modulation) interrupt flag. Set when a
selected period is reached. Reset by software.

Bit 5 (PWM2IF): PWM2 (Pulse Width Modulation) interrupt flag. Set when a
selected period is reached. Reset by software.

Bit 4 (PWM1IF): PWM1 (Pulse Width Modulation) interrupt flag. Set when a
selected period is reached. Reset by software.

Bit 3 (ADIF): Interrupt flag for analog to digital conversion. Set when AD
conversion is completed. Reset by software.

Bit 2 (EXIF): External interrupt flag. Set by falling edge on /INT pin. Reset by
software.

Bit 1 (ICIF): Port 6 input status change interrupt flag. Set when Port 6 input
changes. Reset by software.

Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows. Reset by
software.

Revised IOCF0
2 Page 24 6.2.11 IOCF0 (Interrupt Mask Register) register contents

6.2.11 IOCF0 (Interrupt Mask Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CMPIE PWM3IE PWM2IE PWM1IE ADIE EXIE ICIE TCIE

NOTE
■ IOCF0 register is both readable and writable
■ Individual interrupt is enabled by setting its associated control bit in the IOCF0 to
"1."
■ Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. Refer to Fig. 6-8 (Interrupt Input Circuit) under Section 6.6
(Interrupt).

Bit 7 (CMPIE): CMPIF interrupt enable bit

0 = Disable CMPIF interrupt

Errata Document (V1.7) 09.29.2011 •3

EM78P418N
8-Bit Microprocessor with OTP ROM

1 = Enable CMPIF interrupt

When the Comparator output status change is used to enter interrupt

vector, the CMPIE bit must be set to “Enable“.

Bit 6 (PWM3IE): PWM3IF interrupt enable bit

0 = Disable PWM3 interrupt
1 = Enable PWM3 interrupt

Bit 5 (PWM2IE): PWM2IF interrupt enable bit

0 = Disable PWM2 interrupt
1 = Enable PWM2 interrupt

Bit 4 (PWM1IE): PWM1IF interrupt enable bit

0 = Disable PWM1 interrupt
1 = Enable PWM1 interrupt

Bit 3 (ADIE): ADIF interrupt enable bit

0 = Disable ADIF interrupt
1 = Enable ADIF interrupt

When the ADC Complete is used to enter interrupt vector, the ADIE
bit must be set to “Enable“.

Bit 2 (EXIE): EXIF interrupt enable bit

0 = Disable EXIF interrupt
1 = Enable EXIF interrupt

Bit 1 (ICIE): ICIF interrupt enable bit

0 = Disable ICIF interrupt
1 = Enable ICIF interrupt

If Port 6 Input Status Change Interrupt is used to enter interrupt

vector, the ICIE bit must be set to “Enable“.

Bit 0 (TCIE): TCIF interrupt enable bit.

0 = Disable TCIF interrupt
1 = Enable TCIF interrupt

C. deleted items
N.A.

4• Errata Document (V1.7) 09.29.2011

 EM78P418N
8-Bit Microprocessor with OTP ROM

Version1.3 to Version1.4

A. attached items
N.A.
B. modified items
1 General Description Modified the General
Description,
1 Page 1~3 2 Features Pin Assignment and Features
sections.
3 Pin Assignment

1 General Description
The EM78P417N, EM78P418N and EM78P419N are 8-bit microprocessor designed and developed with low-power,
high-speed CMOS technology. The devices in this series have on-chip 4K×13-bit Electrical One Time Programmable
Read Only Memory (OTP-ROM). It provides Protection bits to prevent intrusion of user’s code in the OTP memory as
well as from unwanted external accesses. Three Code Option bits are also available to meet user’s application
requirements.
With its enhanced OTP-ROM features, the EM78P417N, EM78P418N and EM78P419N provide a convenient way of
developing and verifying user’s programs. Moreover, this OTP devices offer the advantages of easy and effective
program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his
development code.

2 Features
„ CPU configuration
z 4K×13 bits on-chip ROM
z 144×8 bits on-chip registers (SRAM)
z 8 level stacks for subroutine nesting
z Less than 2.2 mA at 5V/4MHz
z Typically 15 μA, at 3V/32KHz
z Typically 1 μA, during sleep mode
„ I/O port configuration
z 3 bi-directional I/O ports
z Wake-up port : P6
z 8 Programmable pull-down I/O pins
z 8 programmable pull-high I/O pins
z 8 programmable open-drain I/O pins
z External interrupt : P50
„ Operating voltage range:
z 2.3V~5.5V at 0°C~70°C(commercial)
z 2.5V~5.5V at -40°C~85°C(industrial)
„ Operating frequency range(base on 2 clocks):
z Crystal mode: DC ~ 20MHz,5V; DC ~
8MHz,3V
z ERC mode: DC ~ 16MHz,5V; DC ~ 4MHz,3V
z IRC mode: 4MHz at 2.3~5.5V
Drift Rate
Internal
RC
Temperature Voltage
Frequency Process
(-40°C+85°C) (2.3V~5.5V)
4MHz ±10% ±5% ±4%
„ All these four main frequencies can be trimmed by
programming with four calibrated bits in the ICE418N
Simulator. OTP is auto trimmed by ELAN Writer.
„ Fast set-up time requires only 2ms in high Crystal and
32 CLKS in IRC mode from wake up to operating mode
„ Peripheral configuration
z 8-bit real time clock/counter (TCC) with selective
signal sources, trigger edges, and overflow interrupt
z 8-bit multi-channel Analog-to-Digital Converter with
12-bit resolution in Vref mode
z Three Pulse Width Modulation (PWM ) with 10-bit
resolution
z One pair of comparator (Can be set as an OP)
z Power-down (SLEEP) mode
„ Six available interruptions
z TCC overflow interrupt
z Input-port status changed interrupt (wake up from
the sleep mode)
z External interrupt
z ADC completion interrupt
z PWM period match completion
z Comparator high/low interrupt
„ Programmable free running watchdog timer
„ Power-on voltage detector provided(2.0V+0.1V)
„ Package types:
z 18 pin DIP 300mil : EM78P417NPS/J
Total z 18 pin SOP 300mil : EM78P417NMS/J
z 20 pin DIP 300mil : EM78P418NPS/J
±19% z 20 pin SOP 300mil : EM78P418NMS/J

Errata Document (V1.7) 09.29.2011 •5

EM78P418N
8-Bit Microprocessor with OTP ROM

8Hz ±10% ±6% ±4% ±20% z 20 pin SSOP 209mil: EM78P418NAMS/J

z 24 pin skinny DIP 300mil : EM78P419NKS/J
1MHz ±10% ±5% ±4% ±19%
z 24 pin SOP 300mil : EM78P419NMS/J
455MHz ±10% ±5% ±4% ±19%
S/J: Green product is not contain hazardous substance

3 Pin Assignment
3.1 EM78P419NK/M 3.2 EM78P417NP/M

P72 1 24 P73 P60/ADC0 1 18 P56/TCC

P71 2 23 P74 P61/ADC1 2 17 P55/OSCI
P70/C IN + 3 22 P57/C IN -
P62/ADC2 3 16 P54/OSCO

EM78P417NM
EM78P417NP
P60/A D C 0/C O 4 21 P56/T C C
EM78P419NM
EM78P419NK

P61/A D C 1 5 20 P55/O S C I Vss 4 15 VDD

P62/A D C 2 6 19 P54/O SC O
P63/ADC3 5 14 P53/PWM3/VREF
V ss 7 18 VDD
P63/A D C 3 8 17 P53/PW M 3/V R E F
P64/ADC4 6 13 P52/PWM2
P64/A D C 4 9 16 P52/PW M 2 P65/ADC5 7 12 P51/PWM1
P65/A D C 5 10 15 P51/PW M 1
P66/ADC6 8 11 /RESET
P66/A D C 6 11 14 /R E SE T
P67/A D C 7 12 13 P50/IN T P67/ADC7 9 10 P50/INT

Fig 3-1 EM78P419NK/M Pin Assignment Fig 3-2 EM78P417NP/M Pin Assignment

3.3 EM78P418NP/M/AM

P70/CIN+ 1 20 P57/CIN- Vss 1 20 P63/ADC3

P60/ADC0/CO 2 19 P56/TCC P64/ADC4 2 19 P62/ADC2
P61/ADC1 3 18 P55/OSCI P65/ADC5 3 18 P61/ADC1
EM78P418NAM

P62/ADC2 4 17 P54/OSCO 4 17
EM78P418NM

P60/ADC0/CO
EM78P418NP

P66/ADC6
Vss 5 16 VDD P67/ADC7 5 16 P70/CIN+
P63/ADC3 6 15 P53/PWM3/VREF P50/INT 6 15 P57/CIN-
P64/ADC4 7 14 P52/PWM2 /RESET 7 14 P56/TCC
P65/ADC5 8 13 P51/PWM1 P51/PWM1 8 13 P55/OSCI
P66/ADC6 9 12 /RESET P52/PWM2 9 12 P54/OSCO
P67/ADC7 10 11 P50/INT VDD 10 11 P53/PWM3/VREF

Fig 3-3 EM78P418NP/M/AM Pin Assignment

6• Errata Document (V1.7) 09.29.2011

 EM78P418N
8-Bit Microprocessor with OTP ROM

Page 2 2 Features
2 Added green product information.
Page 73 APPENDIX A Package type
„ Package types:
z 18 pin DIP 300mil : EM78P417NPS/J
z 18 pin SOP 300mil : EM78P417NMS/J
z 20 pin DIP 300mil : EM78P418NPS/J
z 20 pin SOP 300mil : EM78P418NMS/J
z 20 pin SSOP 209mil: EM78P418NAMS/J
z 24 pin skinny DIP 300mil : EM78P419NKS/J
z 24 pin SOP 300mil : EM78P419NMS/J

S/J: Green product is not contain hazardous substance

APPENDIX

A Package Types
OTP MCU Package Type Pin Count Package Size
EM78P417NP DIP 18 pin 300mil
EM78P417NPS/NPJ DIP 18 pin 300mil
EM78P417NM SOP 18 pin 300mil
EM78P417NMS/NMJ SOP 18 pin 300mil
EM78P418NP DIP 20 pin 300mil
EM78P418NPS/NPJ DIP 20 pin 300mil
EM78P418NM SOP 20 pin 300mil
EM78P418NMS/NMJ SOP 20 pin 300mil
EM78P418NAM SSOP 20 pin 209mil
EM78P418NAMS/NAMJ SSOP 20 pin 209mil
EM78P419NK Skinny DIP 24 pin 300mil
EM78P419NKS/NKJ Skinny DIP 24 pin 300mil
EM78P419NM SOP 24 pin 300mil
EM78P419NMS/NMJ SOP 24 pin 300mil

S/J: Green product is not contain hazardous substances

The third edition of Sony SS-00259 standard.
Pb content should be less the 100ppm
Pb content to fit in with Sony spec.
Part no. EM78P417/8/9NS/J
Electroplate type Pure Tin
Ingredient (%) Sn:100%
Melting point(℃) 232℃
Electrical resistivity 11.4

Errata Document (V1.7) 09.29.2011 •7

EM78P418N
8-Bit Microprocessor with OTP ROM

(μ uohm-cm)
Hardness (hv) 8~10
Elongation (%) >50%

3 Page 5 4 Block Diagram Modified the Functional Block Diagram

4 Block Diagram

Int. Ext.
ROM PC Crystal
RC RC

Oscillation
Instruction 8-level stack Generation
Register (13 bit)

P7
Reset
P70 Instruction
P71 Decoder WDT
P72
P73 PWM1
PWM1
P74
(Timer 1) PWM2
Mux. PWM2
ALU (Timer 2)
PWM3 PWM3
(Timer 3) TCC
P6 TCC
R4
P60
P61
P62
P63
P64 RAM
P65
P66
Interrupt
R3(Status
P67 ACC control
Reg.)
register
P5
P50
Interrupt
P51 Comparator
P52 circuit ADC
P53
(CO) or OP
P54
P55
P56
P57

Ext INT Ain0~7 Cin+ Cin- CO

Fig 4-1 EM78P417/8/9N Block Diagram

C. deleted items
N.A.

8• Errata Document (V1.7) 09.29.2011

 EM78P418N
8-Bit Microprocessor with OTP ROM

Version1.4 to Version1.5

A. attached items
N.A.
B. modified items
N.A.
C. deleted items
2 Features
Deleted the EM78P418NAM
1 Page 1~2,72 3 Pin Assignment SSOP 20-pin package
APPENDIX A Package type
„ Package types:
z 18 pin DIP 300mil : EM78P417NPS/J
z 18 pin SOP 300mil : EM78P417NMS/J
z 20 pin DIP 300mil : EM78P418NPS/J
z 20 pin SOP 300mil : EM78P418NMS/J
z 24 pin skinny DIP 300mil : EM78P419NKS/J
z 24 pin SOP 300mil : EM78P419NMS/J

3 Pin Assignment
3.1 EM78P419NK/M 3.2 EM78P417NP/M

P 72 1 24 P 73 P60/ADC0 1 18 P56/TCC
P 71 2 23 P 74
P61/ADC1 2 17 P55/OSCI
P 70 /C IN + 3 22 P 57/C IN -
P62/ADC2 3 16 P54/OSCO
P 60/A D C 0/C O 4 21 P 56/T C C
EM78P419NM
EM78P419NK

EM78P417NM
EM78P417NP

P 61/A D C 1 5 20 P 55/O S C I Vss 4 15 VDD

P 62/A D C 2 6 19 P 54/O S C O
P63/ADC3 5 14 P53/PWM3/VREF
V ss 7 18 VDD
P64/ADC4 6 13 P52/PWM2
P 63/A D C 3 8 17 P 53/P W M 3/V R E F
P 64/A D C 4 9 16 P 52/P W M 2 P65/ADC5 7 12 P51/PWM1
P 65/A D C 5 10 15 P 51/P W M 1
P66/ADC6 8 11 /RESET
P 66/A D C 6 11 14 /R E S E T
P 67/A D C 7 12 13 P 50/IN T P67/ADC7 9 10 P50/INT

Fig. 3-1 EM78P419NK/M Pin Assignment Fig. 3-2 EM78P417NP/M Pin Assignment

3.3 EM78P418NP/M

Errata Document (V1.7) 09.29.2011 •9

EM78P418N
8-Bit Microprocessor with OTP ROM

P70/CIN+ 1 20 P57/CIN-

P60/ADC0/CO 2 19 P56/TCC

P61/ADC1 3 18 P55/OSCI

P62/ADC2 4 17 P54/OSCO

EM78P418NM
EM78P418NP
Vss 5 16 VDD

P63/ADC3 6 15 P53/PWM3/VREF

P64/ADC4 7 14 P52/PWM2

P65/ADC5 8 13 P51/PWM1

P66/ADC6 9 12 /RESET

P67/ADC7 10 11 P50/INT

Fig. 3-3 EM78P418NP/M Pin Assignment

APPENDIX

A Package Type

OTP MCU Package Type Pin Count Package Size

EM78P417NPS/NPJ DIP 18 pin 300mil
EM78P417NMS/NMJ SOP 18 pin 300mil
EM78P418NPS/NPJ DIP 20 pin 300mil
EM78P418NMS/NMJ SOP 20 pin 300mil
EM78P419NKS/NKJ Skinny DIP 24 pin 300mil
EM78P419NMS/NMJ SOP 24 pin 300mil

10 • Errata Document (V1.7) 09.29.2011

 EM78P418N
8-Bit Microprocessor with OTP ROM

Version1.5 to Version1.6

A. attached items
N.A.
B. modified items
2 Features
1 Page 1~2,72 3 Pin Assignment Modify package type name
APPENDIX A Package type
„ Package types:
z 18 pin DIP 300mil : EM78P418ND18J/S
z 18 pin SOP 300mil : EM78P418NSO18J/S
z 20 pin DIP 300mil : EM78P418ND20J/S
z 20 pin SOP 300mil : EM78P418NSO20J/S
z 24 pin skinny DIP 300mil : EM78P418NK24J/S
z 24 pin SOP 300mil : EM78P418NSO24J/S

3 Pin Assignment
3.1 EM78P418N-Pin24 3.2 EM78P418N-Pin18

P72 1 24 P73 P60/ADC0 1 18 P56/TCC

P71 2 23 P74
P61/ADC1 2 17 P55/OSCI
P70/C IN + 3 22 P57/C IN -
P60/A D C 0/C O 4 21 P56/T C C
P62/ADC2 3 16 P54/OSCO
EM78P418N-Pin18
EM78P418N-Pin24

P61/A D C 1 5 20 P55/O SC I Vss 4 15 VDD

P62/A D C 2 6 19 P54/O SC O
P63/ADC3 5 14 P53/PWM3/VREF
V ss 7 18 VDD
P63/A D C 3 8 17 P53/PW M 3/V R E F P64/ADC4 6 13 P52/PWM2
P64/A D C 4 9 16 P52/PW M 2 P65/ADC5 7 12 P51/PWM1
P65/A D C 5 10 15 P51/PW M 1
P66/A D C 6 11 14 /R E S E T
P66/ADC6 8 11 /RESET
P67/A D C 7 12 13 P50/IN T P67/ADC7 9 10 P50/INT

Fig 3-1 EM78P418N-Pin24 Pin Assignment Fig 3-2 EM78P418N-Pin18 Pin Assignment

3.3 EM78P418N-Pin20

Errata Document (V1.7) 09.29.2011 • 11

EM78P418N
8-Bit Microprocessor with OTP ROM

P70/CIN+ 1 20 P57/CIN-
P60/ADC0/CO 2 19 P56/TCC
P61/ADC1 3 18 P55/OSCI

EM78P418N-Pin20
P62/ADC2 4 17 P54/OSCO
Vss 5 16 VDD
P63/ADC3 6 15 P53/PWM3/VREF
P64/ADC4 7 14 P52/PWM2
P65/ADC5 8 13 P51/PWM1
P66/ADC6 9 12 /RESET
P67/ADC7 10 11 P50/INT

Fig 3-3 EM78P418N-Pin20 Pin Assignment

APPENDIX

A Package Types
OTP MCU Package Type Pin Count Package Size
EM78P418ND18J/S DIP 18 pin 300mil
EM78P418NSO18J/S SOP 18 pin 300mil
EM78P418ND20J/S DIP 20 pin 300mil
EM78P418NSO20J/S SOP 20 pin 300mil
EM78P418NK24J/S Skinny DIP 24 pin 300mil
EM78P418NSO24J/S SOP 24 pin 300mil

C. deleted items
N.A

12 • Errata Document (V1.7) 09.29.2011

 EM78P418N
8-Bit Microprocessor with OTP ROM

Version1.6 to Version1.7

A. attached items
APPENDIX C
1 Page 80 Added EM78P418N Program Pin
EM78P418N Program Pin
In the following IC diagram, “Pin # number” means the Pin to be connected to the Socket in
DWTR.
DWTR Socket
P72 1 24 P73
1 40
P71 2 23 P74
P70/CIN + 3 22 P57 /CIN -
EM78P418NK24/SO24

P60 /ADC0/CO 4 21 P56 /TCC

P61/ADC1 5 20 P55 /OSCI
5.6KΩ
P62/ADC2 6 19 P54 /OSCO #26
#15 Vss 7 18 VDD #26
P63 /ADC3 8 17 P53 /PWM3/VREF
P64 /ADC4 9 16 P52/PWM 2 #15 15 26 #26
#18 P65 /ADC5 10 15 P51/PWM 1 #23
#19 P66 /ADC6 11 14 /RESET #22 #18 18 23 #23
#19 19 22 #22
#20 P67 /ADC7 12 13 P50/INT #21 #20 20 21 #21

P72 1 24 P73
DWTR Socket
1 40
P71 2 23 P74
P70/CIN + 3 22 P57 /CIN -
EM78P418NSS24

P 61/ADC1 4 21 P 55 /OSCI
5.6KΩ
P62/ADC2 5 20 P54 /OSCO #26
P60 /ADC0/CO 6 19 P56 /TCC
P64 /ADC4 7 18 P52/PWM 2
#15 Vss 8 17 VDD #26
P63 /ADC3 9 16 P53 /PWM3/VREF
#15 15 26 #26
#18 P65 /ADC5 10 15 P51/PWM 1 #23
#19 P66 /ADC6 11 14 /RESET #22 #18 18 23 #23
#19 19 22 #22
#20 P67 /ADC7 12 13 P50/INT #20 20 21 #21
#21

B. modified items
1 Page 1~2,72
Errata Document (V1.7) 09.29.2011
2 Features
Added the EM78P418NSS24
3 Pin Assignment SSOP 24-pin package
APPENDIX A Package type
• 13
EM78P418N
8-Bit Microprocessor with OTP ROM

„ Package types:
z 18 pin DIP 300mil : EM78P418ND18J/S
z 18 pin SOP 300mil : EM78P418NSO18J/S
z 20 pin DIP 300mil : EM78P418ND20J/S
z 20 pin SOP 300mil : EM78P418NSO20J/S
z 24 pin skinny DIP 300mil : EM78P418NK24J/S
z 24 pin SOP 300mil : EM78P418NSO24J/S
z 24 pin SSOP 150mil : EM78P418NSS24J/S

3 Pin Assignment

P70/CIN+ 1 20 P57/CIN-
P60/ADC0 1 18 P56/TCC
P60/ADC0/CO 2 19 P56/TCC

EM78P418N-20Pin
P61/ADC1 2 17 P55/OSCI
P61/ADC1 3 18 P55/OSCI
P62/ADC2 3 16 P54/OSCO
EM78P418N-18Pin

P62/ADC2 4 17 P54/OSCO
Vss 4 15 VDD Vss 5 16 VDD
P63/ADC3 5 14 P53/PWM3/VREF P63/ADC3 6 15 P53/PWM3/VREF
P64/ADC4 6 13 P52/PWM2 P64/ADC4 7 14 P52/PWM2
P65/ADC5 7 12 P51/PWM1 P65/ADC5 8 13 P51/PWM1

P66/ADC6 8 11 /RESET P66/ADC6 9 12 /RESET

P67/ADC7 9 10 P50/INT P67/ADC7 10 11 P50/INT

Figure 3-1 EM78P418ND18/SO18 Figure 3-2 EM78P418ND20/SO20

P72 1 24 P73 P72 1 24 P73

P71 2 23 P74 P71 2 23 P74
P70/CIN + 3 22 P57 /CIN - P70/CIN + 3 22 P57 /CIN -
EM78P418NK24/SO24

P60 /ADC0/CO 4 21 P56 /TCC

EM78P418NSS24

P61/ADC1 4 21 P55/OSCI
P61/ADC1 5 20 P55 /OSCI P62/ADC2 5 20 P54 /OSCO
P62/ADC2 6 19 P54 /OSCO P60 /ADC0/CO 6 19 P56 /TCC
Vss 7 18 VDD P64 /ADC4 7 18 P52/PWM 2
P63 /ADC3 8 17 P53 /PWM3/VREF Vss 8 17 VDD
P64 /ADC4 9 16 P52/PWM 2 P63 /ADC3 9 16 P53 /PWM3/VREF
P65 /ADC5 10 15 P51/PWM 1 P65 /ADC5 10 15 P51/PWM 1
P66 /ADC6 11 14 /RESET P66 /ADC6 11 14 /RESET
P67 /ADC7 12 13 P50/INT P67 /ADC7 12 13 P50/INT

Figure 3-3 EM78P418NK24/SO24 Figure 3-4 EM78P418NSS24

APPENDIX
14 • Errata Document (V1.7) 09.29.2011
 EM78P418N
8-Bit Microprocessor with OTP ROM

A Package Types
OTP MCU Package Type Pin Count Package Size
EM78P418ND18J/S DIP 18 pin 300mil
EM78P418NSO18J/S SOP 18 pin 300mil
EM78P418ND20J/S DIP 20 pin 300mil
EM78P418NSO20J/S SOP 20 pin 300mil
EM78P418NK24J/S Skinny DIP 24 pin 300mil
EM78P418NSO24J/S SOP 24 pin 300mil
EM78P418NSS24J/S SSOP 24 pins 150 mil

C. deleted items
N.A

Errata Document (V1.7) 09.29.2011 • 15

EM78P418N
8-Bit Microprocessor with OTP ROM

Version1.7 to Version1.8

A. attached items
N.A.
B. modified items
Appendix C EM78P418N Modify EM78P418N Program
1 Page 80 Pin
Program Pin

C EM78P418N Program Pin

In the following IC diagram, “Pin # number” means the Pin to be connected to the Socket in
DWTR.

C. deleted items
N.A.
16 • Errata Document (V1.7) 09.29.2011
 EM78P418N
8-Bit Microprocessor with OTP ROM

Version1.8 to Version1.9

A. attached items
N.A.
B. modified items
6.13.1 Code Option Register Fixed HLP to “0” at Code Option
1 Page 62 Word 0.
(Word 0)

6.13.1 Code Option Register (Word 0)

Word 0
Bit Bit Bit Bit Bit Bit Bit Bit
Bit Bit 9 Bit 8 Bit 7 Bit 6 Bit 5
12 11 10 4 3 2 1 0

Mnemonic – – – TYPE CLKS ENWDTB OSC2 OSC1 OSC – Protect

0
1 – – – High 4clocks Disable High High High – Disable

0 – – – Low 2clocks Enable Low Low Low – Enable

Bits 12 ~ 10: Not used (reserved). These bits are set to “1” all the time
Bit 9 (TYPE): Type selection Pin.
0 : EM78P418N-24Pin
1 : EM78P418N-18Pin/EM78P418N-20Pin (default)
Bit 8 (CLKS): Instruction time period option bit
0 : two oscillator time periods
1 : four oscillator time periods (default)
Refer to the Section 6.15 for Instruction Set
Bit 7 (ENWDTB): Watchdog timer enable bit
0 : Enable
1 : Disable (default)
Bits 6, 5 and 4 (OSC2, OSC1 and OSC0): Oscillator Modes Selection bits
Oscillator Modes OSC2 OSC1 OSC0
1
ERC (External RC oscillator mode); P54/OSCO is configured as P54 0 0 0
1
ERC (External RC oscillator mode); P54/OSCO is configured as OSCO 0 0 1
2
IRC (Internal RC oscillator mode); P54/OSCO is configured as P54 0 1 0
2
IRC (Internal RC oscillator mode); P54/OSCO is configured as OSCO 0 1 1
3
LXT (Low Crystal oscillator mode) 1 1 0
3
HXT High Crystal oscillator mode) (default) 1 1 1
Note: The transient point of the system frequency between HXT and LXT is 400kHz.
1
In ERC mode, OSCI is used as oscillator pin. OSCO/P54 is defined by code option Word 0
Bit 6 ~ Bit 4.
2
In IRC mode, P55 is normal I/O pin. OSCO/P54 is defined by code option Word 0 Bit 6 ~
Bit 4.
3
In LXT and HXT modes; OSCI and OSCO are used as oscillator pins. These pins cannot
and should not be defined as normal I/O pins.

Errata Document (V1.7) 09.29.2011 • 17

EM78P418N
8-Bit Microprocessor with OTP ROM

Bit 3 : Not used (reserved). This bit is set to “0” all the time
Bits 2 ~ 0 (Protect): Protect Bit
0 : Enable
1 : Disable

C. deleted items
N.A.

Version1.9 to Version2.0

A. attached items
N.A.
B. modified items
1 Page 61 6.13.1 Code Option Register Recovered HLP to selection
(Word 0)

6.13.1 Code Option Register (Word 0)

Word 0
Bit 2 ~ Bit
Bit Bit 12 ~ Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
0
Mnemonic – TYPE CLKS ENWDTB OSC2 OSC1 OSC0 HLP Protect

1 – High 4 clocks Disable High High High High Disable

0 – Low 2 clocks Enable Low Low Low Low Enable

Bits 12 ~ 10: Not used (reserved). These bits are set to “1” all the time.

Bit 9 (TYPE): Type selection Pin.

0 : EM78P418N-24Pin
1 : EM78P418N-18Pin/EM78P418N-20Pin (default)
Bit 8 (CLKS): Instruction time period option bit
0 : two oscillator time periods
1 : four oscillator time periods (default)
Refer to the Section 6.15 for Instruction Set

18 • Errata Document (V1.7) 09.29.2011

 EM78P418N
8-Bit Microprocessor with OTP ROM

Bit 7 (ENWDTB): Watchdog timer enable bit

0 : Enable
1 : Disable (default)
Bits 6, 5 and 4 (OSC2, OSC1 and OSC0): Oscillator Modes Select bits

Oscillator Modes OSC2 OSC1 OSC0

1
ERC (External RC oscillator mode); P54/OSCO is configured as P54 0 0 0
1
ERC (External RC oscillator mode); P54/OSCO is configured as OSCO 0 0 1
2
IRC (Internal RC oscillator mode); P54/OSCO is configured as P54 0 1 0
2
IRC (Internal RC oscillator mode); P54/OSCO is configured as OSCO 0 1 1
3
LXT (Low Crystal oscillator mode) 1 1 0
3
HXT High Crystal oscillator mode) (default) 1 1 1

Note: The transient point of the system frequency between HXT and LXT is 400kHz.
1
In ERC mode, OSCI is used as oscillator pin. OSCO/P54 is defined by code option Word 0
Bit 6 ~ Bit 4.
2
In IRC mode, P55 is normal I/O pin. OSCO/P54 is defined by code option Word 0 Bit 6 ~
Bit 4.
3
In LXT and HXT modes; OSCI and OSCO are used as oscillator pins. These pins cannot
and should not be defined as normal I/O pins.

Bit 3 (HLP): Power consumption selection

0 = Low power consumption, applies to working frequency at 4MHz or

below 4MHz
1 = High power consumption, applies to working frequency above 4MHz
Bits 2 ~ 0 (Protect): Protect Bit
0 : Enable
1 : Disable
C. Deleted Items
N.A.

Errata Document (V1.7) 09.29.2011 • 19

EM78P418N
8-Bit Microprocessor with OTP ROM

20 • Errata Document (V1.7) 09.29.2011