ARM CORTEX-M

INSTRUCTION SET
Outline

• Arithmetic Operations
• Logic Operations
• Shift and Rotate Operations
• Conversion Operations: extend, reverse ordering
• Bit field processing
• Program Flow
Instruction Groups - ARM

• Moving Data within the CPU

• Memory Access
• Arithmetic Operations
• Logic Operations
• Shift and Rotate Operations
• Conversion Operations: extend, reverse ordering
• Bit field processing
• Program Flow
• Multiply Accumulate (MAC) operations
• Divide
• Memory Barrier
The Assembly Language Syntax - ARM
The Assembly Language Syntax - ARM
Instruction Groups - ARM

• Moving Data within the CPU

– Move instruction were covered earlier
• Memory Access
– Memory access instructions were covered earlier
Arithmetic Operations

• Arm Cortex-M support many arithmetic instructions,

e.g. ADD, SUB, MUL, UDIV/SDIV
• Instructions have many flavors, e.g. register-based,
using immediate operand, or memory reference
• Math instructions may use suffix S to indicate whether
the APSR should be updated as a result or not
Arithmetic Operations

• Arm Cortex-M supports

– ADD (add),
– SUB (subtract),
– MUL (multiply),
– UDIV/SDIV (unsigned/signed division)
• Instructions can be used with/without ‘S’ suffix to
specify whether or not ASPR will update as a result
Multiply Accumulate Operations
Logic & Shift Operations

• Arm Cortex-M support various instructions for logic

operations, e.g. AND, OR, XOR, etc.
– Logic instruction can use ‘S’ suffix to indicate that
the Flags are going to be updated accordingly
• Arm Cortex-M support various instructions for Shift and
rotate, e.g. shift-right, shift-left
– If suffix ‘S’ is used these instructions will update the
Carry flag in ASPR
– If the instruction indicate multiple bit shift, the carry
flag will correspond to the last bit shifted out
– There is rotate-left, but no rotate right (because you
can achieve the same effect with a different n-bits)
Logic Operations
Shift Operations
Data Conversion Operations

• Arm Cortex-M support signed/unsigned extension of

data, i.e. from 8bit/16bit to 32bit
Data Conversion Operations

• Example:

• With Rotate:
Data Reversing

• Little Endian & Big Endian are different formats for

representing data.
– Intel use Little Endian
– Motorola use Big Endian
• Data Reversing instructions help modify one format to
another quickly and efficiently
Data Reversing
Data Reversing
Compare & Test Instruction

• Compare & Test instructions are used to update the

flags in ASPR, which may be used to conditionally
branch or conditionally execute instructions –
– used in if-then-else program flow
– Used in loops
Program Flow Control

• Several types of instructions for program flow:

– Branch
– Function call
– Conditional branch
– Combined compare and conditional branch
– Conditional execution (if-then)
– Table branch (switch)
Brach

• Branch can be cause by:

– Branch instruction, e.g. B, BX
– Process data and store result to program counter
(PC) or R15
– Memory Load instruction destined to PC
• Branch instruction, e.g. B, BX, are commonly used
Function Call

• Very similar to branch, with the addition of an extra

step to store the return address of the caller function,
this is called link step
– The return address is stored in the link register (LR),
or R14
– Branch & Link instructions: BL, BLX
Conditional Branches

• Conditional branches are executed conditionally based

on the flags of APSR (N, Z, C, V)
Conditional Branches
Conditional Branches
Table Branches

• Used with branch table to implement switch statement

in C
• TBB: Table branch Byte
– The branch table entries are 8bit
– Offset from base address is < 2x28 = 512
• TBH: Table branch Half word
– The branch table entries are 16bit
– Offset from base address is < 2x216 = 128K
Table Branches - TBB
Table Branches - TBH
References

• The definitive Guide to ARM Cortex-M3 & Cortex-M4,

chapter 5: Instruction Set