Roverbook Voyager H570L Compal - La-1381 - r2b - Schematics

A B C D E F G H I J
1 1
2 2
3 3
4
LA-1381 REV0.5 Schematics Document 4
uFCBGA/uFCPGA Northwood with

5
Brookdale chipset(845MP/MZ+ICH3-M) 5
6 6
BOM 記號
DT@ SKU W/Desktop CPU 要打
M@ SKU W/Mobile CPU 要打 PCB Layer
7 LAN@ SKU W/LAN 要打 Structure: 7
1394@ SKU W/1394 controller 要打 TOP

S@ SKU W/TVOUT 要打 GND1
FIR@ SKU W/FIR module 要打 IN1
MDC@ SKU W/MODEM module 要打 IN2
DK@ SKU W/DOCKING 要打 VCC
SD@ SKU W/SD CARD 要打 IN3
8
GND2 Compal Electronics, Inc. 8
BT@ SKU W/Bluetooth module 要打 Title
SCHEMATIC, M/B LA-1381
MLED@ SKU Media LED supper 要打 BOT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
SUB@ SKU W/SUBWOOFER要打 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Custom
401212 2B
Date: 星期一, 十二 ?30, 2002 Sheet 1 of 46

A B C D E F G H I J
A B C D E F G H I J
Compal confidential
Model Name :APL11
File Name : LA-1381
1 1
Mobile Northwood Thermal Sensor Clock Generator

uFCBGA/uFCPGA CPU MAX6654 W320-04
page 4,5
CPU Bypass page 5 page 14
2 Fan Control & CPUVID HA#( 3..31)
System Bus HD#(0..63) 2
page 6
page 6 400MHz
LM75 thermal Memory

CRT Connector Brookdale-M BUS(DDR)
page 15 sensor SO-DIMM X2
MCH-M 2.5V 200MHz BANK 0, 1, 2, 3 page 11,12
AGP4X(1.5V)
625 BGA
3
VGA AGP Conn page 8,9 3
Board page 15
LAN
USB2.0 conn X2 LAN interface
RJ45
page 32
Kinnereth page 20
page 20
HUB Link
1.8V 266MHz
Mini PCI VIA_VT6202 USB interface
Bluetooth
4 4
Conn. USB2.0 page 32
page 36 page 26
PCI BUS ICH3-M 3.3V 48MHz

USB conn X1
IDSEL:AD20 3.3V 33MHz page 32
(PIRQA/B#,GNT#2,REQ#2)
421 BGA 3.3V 24.576MHz AC-LINK
TI TSB43AB22 MDC
CardBus Controller 3.3V ATA100
page 32
5 5
page 16,17
1394 PCI 1410
page 25 page 23
LPC BUS
3.3V 33MHz
Slot 0 IDE Connector AC97

DC/DC Interface Codec
Suspend
page 24 (HDD/CR-ROM)
ALC202
6 page 19 page 21 6
page 37
14M_5V
EC 87591 SD/MS CARD SMsC
Power Circuit AMP& Phone
page 30
page 27 LPC47N227 Jack
DC/DC page 28 page 22
page
38,39,40,41,42,43,44,45 Touch Pad
page 29
7 LPT SUB WOOFER 7
EC Ext. I/O Int.KBD Port.
page 33 page 29
page 31 page 37
BIOS PS/2 conn FIR FDD

page 31 page 29
page 29 page 19
8
Title
Compal Electronics, Inc. 8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 2B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401212
Custom
A B C D E F G H I J
10 9 8 7 6 5 4 3 2 1
Power Managment table
+3VS
H H
Signal +5VS NB Chip Rev SB Chip Rev
+3VALW +3V +1.8VS
+5VALW +5V +1.5VS
State +1.8VALW +2.5V +1.2VP
+12VALW +CPU_CORE
+1.25V
ON ON ON
S0
G G
S1 ON ON ON
S3 ON ON OFF
S5 S4/AC ON OFF OFF
F
S5 S4/AC don't exist F
OFF OFF OFF
E E
D D
C C
B B
A
Title
Compal Electronics, Inc. A
401212
Custom
10 9 8 7 6 5 4 3 2 1
A B C D E F G H I J
1 1
+CPU_CORE
AC10
AC12
AC14
AC16
AC18
AD11
AD13
AD15
AD17
AD19
AA10
AA12
AA14
AA16
AA18
AB11
AB13
AB15
AB17
AB19
AE10
AE12
AE14
AE16
AE18
AE20
AF11
AF13
AF15
AF17
AF19
AF21
AC8
AD7
AD9
AA8
AB7
AB9
AE6
AE8
AF2
AF5
AF7
AF9
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
A10
A12
A14
A16
A18
A20
B11
B13
B15
B17
B19
E10
2 2
C8
D7
D9
A8
B7
B9
H A#[3..31] U41A HD#[0..63]
<8> HA#[3..31] HD#[0..63] <8>
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
HA#3 K2 B21 HD#0
HA#4 A#3 D#0 HD#1
K4 A#4 D#1 B22
HA#5 L6 A23 HD#2
HA#6 A#5 D#2 HD#3
K1 A#6 D#3 A25
HA#7 L3 C21 HD#4
HA#8 A#7 D#4 HD#5
M6 A#8 D#5 D22
HA#9 L2 B24 HD#6
HA#10 A#9 D#6 HD#7
M3 A#10 D#7 C23
HA#11 M4 C24 HD#8
HA#12 A#11 D#8 HD#9
N1 A#12 D#9 B25
HA#13 M1 G22 HD#10
3 HA#14 A#13 D#10 HD#11 3
N2 A#14 D#11 H21
HA#15 N4 C26 HD#12
HA#16 A#15 D#12 HD#13
N5 A#16 D#13 D23
HA#17 T1 J21 HD#14
HA#18 A#17 D#14 HD#15
R2 A#18 D#15 D25
HA#19 P3 H22 HD#16
HA#20 A#19 D#16 HD#17
P4 A#20 D#17 E24
HA#21 R3 G23 HD#18
HA#22 A#21 D#18 HD#19
T2 A#22 D#19 F23
HA#23 U1 F24 HD#20
HA#24 A#23 D#20 HD#21
P6 A#24 D#21 E25
HA#25 U3 F26 HD#22
HA#26 A#25 D#22 HD#23
T4 A#26 D#23 D26
HA#27 V2 L21 HD#24
HA#28 A#27 D#24 HD#25
R6 G26
HA#29 A#28 D#25 HD#26
W1 H24
4 HA#30
HA#31
T5
U4
V3
A#29
A#30
A#31
Mobile D#26
D#27
D#28
M21
L22
J24
HD#27
HD#28
HD#29
4
A#32 D#29 HD#30

W2 K23
A#33 D#30 HD#31
Y1 H25
A#34 D#31 HD#32
AB1 M23
<8> HREQ#[0..4]
HR EQ#[0..4]
HREQ#0 J1
A#35
NorthWood D#32
D#33
D#34
N22
P21
M24
HD#33
HD#34
HD#35
HREQ#1 REQ#0 D#35 HD#36
K5 N23
J4 M26
J3 N26
H3 N25
REQ#4 D#39 HD#40
<8> HADS# G1 R21
ADS# D#40 HD#41
P24
D#41 HD#42
5 R25 5
D#42 HD#43
AC1 R24
+CPU_CORE AP#0 D#43 HD#44
V5 T26
AP#1 D#44 HD#45
R148 not plant R148 M@10K_0402 AA3
BINIT# D#45
T25
1 2 AC3 T22 HD#46
for DT CPU. IERR# D#46
T23 HD#47
D#47 HD#48
1 2 R96 200_0402 U26
D#48 HD#49
<8> HBR0# H6 U24
BR0# D#49 HD#50
<8> HBPRI# D2 U23
BPRI# D#50 HD#51
<8> HBNR# G2 V25
BNR# D#51 HD#52
<8> HLOCK# G4 U21
LOCK# D#52 HD#53
V22
D#53 HD#54
V24
CLK_HCLK D#54 HD#55
<14> CLK_HCLK AF22 W26
CLK_HCLK# BCLK0 D#55 HD#56
<14> CLK_HCLK# AF23 Y26
BCLK1 D#56 HD#57
W25
D#57 HD#58
6 Y23 6
D#58 HD#59
Y24
D#59 HD#60
<8> HIT# F3 Y21
HIT# D#60 HD#61
<8> HITM# E3 AA25
HITM# D#61 HD#62
<8> HDEFER# E2 AA22
DEFER# D#62 HD#63
AA24
D#63
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
H1
H4
H23
H26
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD1
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8
F13
F15
F17
F19
F9
F11
E8
E20
E18
E16
E14
E12
NorthWood
7 7
+CPU_CORE
8
Title
401212
Custom
A B C D E F G H I J
A B C D E F G H I J
2 1 H_SKTOCC#
R34 M@0_0402
+CPU_CORE R125 1 2 DT@56_0402 +CPU_CORE
DT : REMOVE
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE26
AF10
AF12
AF14
AF16
AF18
AF20
AF26
R116 200_0402
AE7
AE9
AF1
AF6
AF8
C11
C13
C15
C17
C19
C22
C25
D10
D12
D14
D16
D18
D20
D21
D24
B10
B12
B14
B16
B18
B20
B23
B26
E11
E13
E15
E17
E19
E23
E26
F10
F12
F14
F16
F18
F22
F25
H_A20M# H _GHI# 2 PM_CPUPERF#
C2
C5
C7
C9
D3
D6
D8
B4
B8
E1
E4
E7
E9
F2
F5
2 1 1 PM_CPUPERF# <16>
U41B R123 M@0_0402
R119 200_0402
2 1 H_SMI#
SKTOCC#
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
1 R120 200_0402 DT : REMOVE 1
2 1 H_IGNNE#
R100 200_0402
2 1 H_STPCLK#
R26 200_0402 <8> H_RS#0 F1 J26
H_DPSLPR# RS#0 DP#0
2 1 <8> H_RS#1 G5 K25
RS#1 DP#1
R99 200_0402 <8> H_RS#2 F4 K26
H_NMI RS#2 DP#2 +H_GTLREF1
2 1 AB2 L25
RSP# DP#3
R101 200_0402 <8> H_TRDY# J6
H_INIT# TRDY#
2 1
R146 200_0402 DT : REMOVE GTLREF0
AA21 All of these pin
2 1 H_INTR H_A20M# C6 AA6
<16> H_A20M#
H_F_FERR# A20M# GTLREF1 connect ed inside
R115 56_0402 <16> H_F_FERR# B6 F20
H_F_FERR# H_IGNNE# FERR# GTLREF2
2 1 <16> H_IGNNE# B2
IGNNE# GTLREF3
F6
R28 300_0402 H_SMI# B5 A22 +CPU_CORE
H_PWRGD <16> H_SMI# H_PWRGD AB23 SMI# NC1
2 1 <16> H_PWRGD PWRGOOD NC2
A7
2 M@0_0402 H_STPCLK# Y4 2
<16> H_STPCLK# STPCLK#
R20 2 1 H_DPSLPR# AD25
<16> H_DPSLP# DPSLP#
H_INTR D1 AD24 TESTTHI0_1 R25 1 2 56_0402
<16> H_INTR H_NMI LINT0 TESTHI0
<16> H_NMI E5 LINT1 TESTHI1 AA2
R19 2 1 H_INIT# W5 AC21 TESTTHI2_7 R27 1 2 56_0402
+CPU_CORE <16> H_INIT# H_RESET# AB25 INIT# TESTHI2
<8> H_RESET# RESET# TESTHI3 AC20
DT@56_0402 AC24
TESTHI4
TESTHI5 AC23
R30 51.1_1% H5 AA20 ITPCLKOUT0 R49 1 2 56_0402
H_RESET# <8> H_DBSY# DBSY# ITPCLKOUT0 ITPCLKOUT1
2 1 H2 AB22 R50 1 2 56_0402
<8> H_DRDY# DRDY# ITPCLKOUT1 TESTTHI8_10
AD6 U6 R102 1 2 56_0402
<14> H_BSEL0 BSEL0 TESTHI8
R114 200_0402 <14> H_BSEL1 AD5 W4
PM_CPUPERF# BSEL1 TESTHI9
2 1 Y3
Place resistor <100mils from +1.2VP

H_THERMDA
H_THERMDC
B3
C4
THERMDA
Mobile TESTHI10
GHI# A6 H _GHI#
H_DSTBN#[0..3]
H_DSTBN#[0..3] <8>
3 THERMDC H_DSTBN#0 3
CPU pin DSTBN#0 E22
1 2 H_THERMTRIP# A2 K22 H_DSTBN#1
R124 56_0402 THERMTRIP# DSTBN#1 H_DSTBN#2
R22
DT : INSTALL
ITP_BPM0
ITP_BPM1
AC6
AB5
BPM#0
NorthWood DSTBN#2
DSTBN#3 W22 H_DSTBN#3
H_DSTBP#[0..3]
H_DSTBP#[0..3] <8>
ITP_BPM2 BPM#1 H_DSTBP#0
AC4 BPM#2 DSTBP#0 F21
ITP_BPM3 Y6 J23 H_DSTBP#1
L50 DT@4.7UH_80mA ITP_PRDY# BPM#3 DSTBP#1 H_DSTBP#2
AA5 BPM#4 DSTBP#2 P23
1 2 ITP_PREQ# AB4 W23 H_DSTBP#3
+CPU_CORE DT@4.7UH_80mA BPM#5 DSTBP#3
L19
1 2
ITP_TCK D4 L5
ITP_TDI TCK ADSTB#0 H_ADSTB#0 <8>
C1 TDI ADSTB#1 R5 H_ADSTB#1 <8>
D5
ITP_TMS TDO H_D BI#[0..3]
F7 H_DBI#[0..3] <8>
4 DT : REMOVE ITP_TRST# E6
TMS
E21 H_DBI#0 4
TRST# DBI#0 H_DBI#1
G25
L51 M@4.7UH_80mA DBI#1 H_DBI#2
P26
H_VCCA DBI#2 H_DBI#3
1 2 AD20
VCCA DBI#3
V21
+1.2VP M@4.7UH_80mA TP1 +CPU_CORE
L12 1 A5
VCCSENSE
1 2 H_VCCIOPLL AE23 AE25 H_DBR# 1 2
VCCIOPLL DBR# ITP_DBR# <33>
R210 @0_0402
Murata LQG21F4R7N00 AF25
NC7 H_PROCHOT#
AF3 C3 1 2
NC8 PROCHOT#
1
V6 R145 56_0402
C67 C94 MCERR# H_SLP#
If used ITP port must depop + +
SLP#
AB26 H_SLP# <16>
22U_1206_10V4Z
RP6 8P4R_1.5K 22U_1206_10V4Z AC26 2 1
2
ITP_TDI ITP_CLK0 H_VSSA +CPU_CORE

1 8 AD26
ITP_CLK1 VSSA
AD22
2 7 ITP_TMS H_VSSA A4 1 R29 200_0402
ITP_TRST# VSSSENSE
5 3 6 L24
COMP0 5
4 5 ITP_TCK P1 TP2
COMP1
AD2
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
NC3
2
VCCVID
AD3
R142 NC4
VID0
VID1
VID2
VID3
VID4
NC5
NC6
<14> CLK_ITPP
<14> CLK_ITPP#
+CPU_CORE 51.1_1%
1
F8
G21
G24
G3
G6
J2
J22
J25
J5
K21
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
R4
T21
T24
T3
T6
U2
U22
U25
U5
V1
V23
V26
V4
W21
W24
W3
W6
Y2
Y22
Y25
Y5
AE5
AE4
AE3
AE2
AE1
AE21
AF24
AF4
R56 NorthWood
51.1_1%
R147 2 1 51.1_1% ITP_PREQ# +1.2VP
2 1 ITP_PRDY#
R87 51.1_1%
R88 2 1 51.1_1% ITP_BPM0
2 1 ITP_BPM1 C145
R89 51.1_1% GTL Reference Voltage CPU_VR_VID4 <7>
6 R158 2 1 51.1_1% ITP_BPM2 +CPU_CORE Layout note : CPU_VR_VID3 <7> .1UF_0402 6
2 1 ITP_BPM3
CPU_VR_VID2 <7>
R159 51.1_1% 1. Place R_A and R_B near CPU. CPU_VR_VID1 <7>
2. Place decoupling cap 220PF near CPU.(Within CPU_VR_VID0 <7>
1
+3VALW
50 0mils)
R57
Thermal Sensor R_A
+5VALW 49.9_1%
MAX6654MEE
2
2
W =1 5mil Trace width>=7mila +5VS R171
2
+H_GTLREF1
2
C198 1K_0402 R176

1
R190
1
.1UF_0402 R58 C443 C442 PROCHOT# 470_0402
1
10K_0402 <30> PROCHOT#
2
R_B
1
<8,15,16,19,23,25,26,28,34> PCIRST#
1
100_1% 1UF 220PF R632
1
7 Q14 2 7
2
2
U11 @301_1%_0402 3904
1
1 16 Q12
3
NC NC
1
2 15 1 3 R153 2
H_THERMDA VCC STBY <37,40,41> MAINPWON R143
C155 3 14 @470_0402
S
H_THERMDC DXP SMBCLK EC_SMC2 <30,39> H_PROCHOT#
2200PF 4 13 Q15 1 2
2
3
DXN NC
1
5 12 @2N7002 Q13 3904
1
NC SMBDATA EC_SMD2 <30,39>
6 11 2 470_0402
ADD1 ALERT Q76
7 GND ADD0 10
1
8 9 @3904 R144
3
GND NC CPU_THRM# 2 1 PROCHOT# 21 2 H_THERMTRIP#
2 1 MAX6654MEE R172 @0_0402
+5VALW R197 1K_0402 @3904 @470_0402
3
2
R199 R195 4/29 update

Johnny
8 1K_0402 10K_0402
Title
1
Address:1001_110X SCHEMATIC, M/B LA-1381

+5VALW R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 2B
401212
Custom
A B C D E F G H I J
A B C D E F G H I J
Layout note : +CPU_CORE

Layout note :
Place close t o CPU, Use 2~3 vias per PAD.
Place .22uF caps underneath balls on solder side. Place close to CPU power and
Place 10uF caps on the peripheral near balls. gr ound pin as possible
1
Use 2~3 vias per PAD. (<1inch)
1 + C462 + C449 + C441 + C492 + C419 1
DT@470UF_D4_2.5V_10m DT@470UF_D4_2.5V_10m DT@470UF_D4_2.5V_10m DT@470UF_D4_2.5V_10m DT@470UF_D4_2.5V_10m
2
For Desktop's CPU: +CPU_CORE
Please place these cap in the socket cavity area ESR total=0.75m ohm
C total=6350uF
1
+CPU_CORE
For Mobile's CPU: + C485 + C420 + C474 + C421 + C434
ESR total=1.875m ohm 470UF_D4_2.5V_10m 470UF_D4_2.5V_10m DT@470UF_D4_2.5V_10m DT@470UF_D4_2.5V_10m DT@470UF_D4_2.5V_10m
C total=2590uF
2
1
1
C95 C122 C89 C113 C98
2 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 2
2
2
+CPU_CORE
+CPU_CORE
1
+ C149 + C99 + C50 + C49 + C48
1
1
330UF_D2_2.5V_15m 330UF_D2_2.5V_15m 330UF_D2_2.5V_15m 330UF_D2_2.5V_15m 330UF_D2_2.5V_15m
C107 C106 C465 C461 C445
2
10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R
2
2
+CPU_CORE
Please place these cap on the socket north side
3 3
1
+CPU_CORE
C456 C455 C480 C479 C478 C477 C476 C475 C450 C451
.22UF_X7R .22UF_X7R .22UF_X7R .22UF_X7R .22UF_X7R .22UF_X7R .22UF_X7R .22UF_X7R .22UF_X7R .22UF_X7R
2
1
1
C80 C92 C104 C428 C118
10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R
2
2
+12VS Fan1 Control circuit
New add
2
+CPU_CORE
5/15 Johnny
R292
4 3.48K_1% Q23 +5VS 4
1
1
FMMT619
1
C128 C61 C59 C57 C56 2 D16 C234
10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R +12VS 1SS355
2
2
C190 1000PF_0402
3
.1UF_0402 D27
2
2
1N4148 +5VFAN1
C367
+CPU_CORE 2.2UF_16V_0805 C751 JP22
3 1
1
8
1
U27B C752
D15 .1uF_0402 1
<30> EN_FAN1 5 + 2
7 2 Q32 33PF_0402
3
1
6 - 2SA1036K 1N4148
C429 C430 C423 C53 LM358 53398-0310
2
10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R
2
4
+3VS
5 5
1
New add
Please place these cap on the socket south side 2 1 5/15 Johnny R433
10K_0402
1
R294
+CPU_CORE R295 7.32K_1% C746
2
FAN_SPEED <30>
13K_1%
+12VS 220PF_0402
2
1
C123 C115 C159 C116 C448 New add
2
10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 5/15 Johnny
2
R434
6 3.48K_1% Q24 +5VS
Fan2 Control circuit 6
1
FMMT619
1
+CPU_CORE 2 D13 C222
+12VS 1SS355
2
1000PF_0402
3
D40
2
1
2
1N4148 +5VFAN2
C447 C83 C495 C174 C175 C225
10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 2.2UF_16V_0805 C753 JP23
2
3 1
1
8
1
U27A C754
D12 .1uF_0402 1
<30> EN_FAN2 3 +
Q51 33PF_0402 2
1 2
2SA1036K 1N4148 3
2 -
+CPU_CORE LM358 53398-0310
2
4
+3VS
7 7
1
1
C176 C426 C427 C55 New add
10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 2 1 5/15 Johnny R220
2
10K_0402
R293
1
7.32K_1% C747
2
R296
FAN_SPEED2 <30>
13K_1% 220PF_0402
EMI Clip PAD for CPU
2
PAD1
1
8
Title
PAD-2.5X3 SCHEMATIC, M/B LA-1381
401212
Custom
A B C D E F G H I J
10 9 8 7 6 5 4 3 2 1
H H
For Mobile CPU Mobil CPU Destop CPU

G NB/DT_CPU G
+3VS 1 0
VID 4 3 2 1 0 4 3 2 1 0
VCC
1
2
3
4
R173 RP8 1.750V
1K_0402 8P4R_1K
0 0 0 0 0 0 0 1 0 0
1.700V 0 0 0 0 1 0 0 1 1 0
8
7
6
5
RP90 M@8P4R_0
CPU_VR_VID0 4 5 CPU_VID0
1.650V 0 0 0 1 0 0 1 0 0 0
<5> CPU_VR_VID0 CPU_VR_VID1 CPU_VID1 CPU_VID0 <43>
<5> CPU_VR_VID1 CPU_VR_VID2
3
2
6
7 CPU_VID2 CPU_VID1 <43> 1.600V 0 0 0 1 1 0 1 0 1 0
<5> CPU_VR_VID2 CPU_VID2 <43>
CPU_VR_VID3 CPU_VID3
F <5> CPU_VR_VID3
CPU_VR_VID4
1
R178 1
8
2 M@0_0402 CPU_VID4
CPU_VID3 <43> 1.550V 0 0 1 0 0 0 1 1 0 0 F
<5> CPU_VR_VID4 CPU_VID4 <43>
1.500V 0 0 1 0 1 0 1 1 1 0
1.450V 0 0 1 1 0 1 0 0 0 0
1.400V 0 0 1 1 1 1 0 0 1 0
1.350V 0 1 0 0 0 1 0 1 0 0
1.300V 0 1 0 0 1 1 0 1 1 0
1.250V 0 1 0 1 0 1 1 0 0 0
1.200V 0 1 0 1 1 1 1 0 1 0
E 1.150V 0 1 1 0 0 1 1 1 0 0 E
1.100V 0 1 1 0 1 1 1 1 1 0
1.050V 0 1 1 1 0 X X X X X
1.000V 0 1 1 1 1 X X X X X
For Desktop CPU 0.975V 1 0 0 0 0 X X X X X
+3VALW
0.950V 1 0 0 0 1 X X X X X
0.925V 1 0 0 1 0 X X X X X
2
R390 DT : REMOVE 0.900V 1 0 0 1 1 X X X X X

M@100K_0402
D 0.875V 1 0 1 0 0 X X X X X D
1
NB/DT#_CPU <31,43> 0.850V 1 0 1 0 1 X X X X X

0.825V 1 0 1 1 0 X X X X X
2
R389
+5VS 0.800V 1 0 1 0 1 X X X X X
DT@100K_0402
0.775V 1 1 0 1 0 X X X X X
1
0.750V 1 1 0 0 1 X X X X X
1
2
3
4
R404 RP86
0.725V 1 1 0 1 0 X X X X X
@10K_0402 @8P4R_10K
0.700V 1 1 0 1 1 X X X X X
8
7
6
5
C 0.675V 1 1 1 0 0 X X X X X C
CPU_VR_VID0 1 CPU_VID0
R399
2
DT@0_0402
CPU_ECVID0 <31> <31> EC_CPUVID0 R403
1 2
DT@0_0402
0.650V 1 1 1 0 1 X X X X X
RP89 RP87 0.625V 1 1 1 1 0 X X X X X
CPU_VR_VID2
4
3
5
6
CPU_ECVID1 <31> <31> EC_CPUVID1
4
3
5
6 CPU_VID2
0.600V 1 1 1 1 1 X X X X X
CPU_VR_VID4
2
1
7
8
2
1
7
8 CPU_VID4
VRM output off 1 1 1 1 1
DT@8P4R_0 DT@8P4R_0
B B
A
Title
401212
Custom
10 9 8 7 6 5 4 3 2 1
A B C D E F G H I J
HD#[0..63]
H A#[3..31] HD#[0..63] <4>
<4> HA#[3..31]
1 1
U43A AGP_AD[0..31] U43B H UB_PD[0..10]
<15> AGP_AD[0..31] HUB_PD[0..10] <16>
HA#3 T4 AA2 HD#0 AGP_AD0 R27 P25 HUB_PD0
HA#4 HA#3 HD#0 HD#1 AGP_AD1 G_AD0 HI_0 HUB_PD1
T5 AB5 R28 P24
T3 AA5 T25 N27
U3 AB3 R25 P23
R3 AB4 T26 M26
P7 AC5 T27 M25
R2 AA3 U27 L28
P4 AA6 U28 L27
HA#10 HD#7 G_AD7 HI_7
HUB
HA#11 R6 AE3 HD#8 AGP_AD8 V26 M27 HUB_PD8
P5 AB7 V27 N28
P3 AD7 T23 M24
HA#14 HA#13 HD#10 HD#11 AGP_AD11 G_AD10 HI_10
N2 AC7 U23
HA#15 HA#14 HD#11 HD#12 AGP_AD12 G_AD11
N7 AC6 T24
2 HA#16 HA#15 HD#12 HD#13 AGP_AD13 G_AD12 2
N3 AC3 U24 N25 HUB_PSTRB <16>
HA#17 HA#16 HD#13 HD#14 AGP_AD14 G_AD13 HI_STB
K4 AC8 U25 N24 HUB_PSTRB# <16>
HA#18 HA#17 HD#14 HD#15 AGP_AD15 G_AD14 HI_STB# +1.8VS +VS_HUBREF
M4 HA#18 HD#15 AE2 V24 G_AD15
HA#19 M3 AG5 HD#16 AGP_AD16 Y27
HA#20 HA#19 HD#16 HD#17 AGP_AD17 G_AD16 HLRCOMP R85 1 36.5_1%
L3 HA#20 HD#17 AG2 Y26 G_AD17 HLRCOMP P27 2
HA#21 L5 AE8 HD#18 AGP_AD18 AA28 P26
HA#22 HA#21 HD#18 HD#19 AGP_AD19 G_AD18 HI_REF
K3 HA#22 HD#19 AF6 AB25 G_AD19
1
HA#23 J2 AH2 HD#20 AGP_AD20 AB27 C120
HA#24 HA#23 HD#20 HD#21 AGP_AD21 G_AD20 AGP_SBA[0..7] .01UF_0402
M5 HA#24 HD#21 AF3 AA27 G_AD21 AGP_SBA[0..7] <15>
HA#25 J3 AG3 HD#22 AGP_AD22 AB26
2
HA#26 HA#25 HD#22 HD#23 AGP_AD23 G_AD22 AGP_SBA0
L2 HA#26 HD#23 AE5 Y23 G_AD23 SBA0 AH28
HA#27 H4 AH7 HD#24 AGP_AD24 AB23 AH27 AGP_SBA1 Place this cap near MCH
HA#28 HA#27 HD#24 HD#25 AGP_AD25 G_AD24 SBA1 AGP_SBA2
N5 HA#28 HD#25 AH3 AA24 G_AD25 SBA2 AG28 Place closely
HA#29 G2 AF4 HD#26 AGP_AD26 AA25 AG27 AGP_SBA3 +AGPREF ball P26
HA#30 HA#29 HD#26 HD#27 AGP_AD27 G_AD26 SBA3 AGP_SBA4
M6 HA#30 HD#27 AG8 AB24 G_AD27 SBA4 AE28
HA#31 L7 AG7 HD#28 AGP_AD28 AC25 AE27 AGP_SBA5
3 HA#31 HD#28 HD#29 AGP_AD29 G_AD28 SBA5 AGP_SBA6 3
HD#29 AG6 AC24 G_AD29 SBA6 AE24
1
R5 AF8 HD#30 AGP_AD30 AC22 AE25 AGP_SBA7 C84
<5> H_ADSTB#0 HADSTB#0 HD#30 G_AD30 SBA7
AGP
N6 AH5 HD#31 AGP_AD31 AD24 .1UF_0402
<5> H_ADSTB#1 HADSTB#1 HD#31 HD#32 G_AD31
AC11 Place closely pin P22
2
HD#32 HD#33
HD#33 AC12 <15> AGP_C/BE#[0..3]
<5> H_RESET# AE17 AE9 HD#34 AGP_C/BE#0 V25 AA21
CPURST# HD#34 HD#35 AGP_C/BE#1 G_C/BE#0 AGPREF R53 CLK_AGP_MCH
<5> H_TRDY# U7 HTRDY# HD#35 AC9 V23 G_C/BE#1
HOST
Y4 AE10 HD#36 AGP_C/BE#2 Y25 AD25 2 1 36.5_1%
<4> HDEFER# DEFER# HD#36 G_C/BE#2 GRCOMP
2
Y7 AD9 HD#37 AGP_C/BE#3 AA23
<4> HBPRI# BPRI# HD#37 G_C/BE#3
W5 AG9 HD#38 P22 CLK_AGP_MCH R94
<4> HLOCK# HLOCK# HD#38 HD#39 66IN CLK_AGP_MCH <14>
J27 AC10 @33_0402
<5,15,16,19,23,25,26,28,34> PCIRST# RSTIN# HD#39 HD#40
H26 TESTIN# HD#40 AE12 <15> AGP_ST[0..2]
V5 AF10 HD#41 AGP_ST0 AG25
1
<5> H_DBSY# DBSY# HD#41 HD#42 AGP_ST1 ST0 AGP_RBF#
<5> H_DRDY# V4 DRDY# HD#42 AG11 AF24 ST1 RBF# AE22 AGP_RBF# <15>
Y5 AG10 HD#43 AGP_ST2 AG26 AE23 AGP_WBF# C121
<4> HIT# HIT# HD#43 HD#44 ST2 WBF# AGP_WBF# <15>
Y3 AH11 @10PF_0402
4 <4> HITM# HITM# HD#44 HD#45 4
<4> HBR0# V7 AG12
BREQ#0 HD#45 HD#46 AGP_ADSTB0
<4> HADS# V3 AE13 <15> AGP_ADSTB0 R24
ADS# HD#46 HD#47 AGP_ADSTB0# AD_STB0
<4> HBNR# W3 AF12 <15> AGP_ADSTB0# R23 A19
BNR# HD#47 HD#48 AGP_ADSTB1 AD_STB#0 VSS11
AG13 AC27 A23
HD#48 HD#49 <15> AGP_ADSTB1 AGP_ADSTB1# AD_STB1 VSS12 +1.5VS
AH13 <15> AGP_ADSTB1# AC28 A27
HD#49 HD#50 AGP_SBSTB AD_STB#1 VSS13
<5> H_RS#0 W2 AC14 <15> AGP_SBSTB AF27 D5
RS#0 HD#50 HD#51 AGP_SBSTB# SB_STB VSS14
<5> H_RS#1 W7 AF14 AF26 D9
RS#1 HD#51 HD#52 <15> AGP_SBSTB# SB_STB# VSS15
<5> H_RS#2 W6 AG14 D13
RS#2 HD#52 VSS16
1
HR EQ#[0..4] AE14 HD#53 D17 Place this cap near AGP
<4> HREQ#[0..4] HREQ#0 HD#53 HD#54 AGP_FRAME# VSS17 R22
U6 AG15 <15> AGP_FRAME# Y24 D21
HREQ#1 HREQ#0 HD#54 HD#55 AGP_DEVSEL# G_FRAME# VSS18 1K_1%
T7 AG16 <15> AGP_DEVSEL# W28 E1
HREQ#2 HREQ#1 HD#55 HD#56 AGP_IRDY# G_DEVSEL# VSS19
R7 AG17 W27 E4
HREQ#3 HREQ#2 HD#56 HD#57 <15> AGP_IRDY# AGP_TRDY# G_IRDY# VSS20
U5 AH15 W24 E26
2
HREQ#4 HREQ#3 HD#57 HD#58 <15> AGP_TRDY# AGP_STOP# G_TRDY# VSS21
U2 AC17 <15> AGP_STOP# W23 E29 AGP_NBREF
HREQ#4 HD#58 HD#59 AGP_PAR G_STOP# VSS22
AF16 <15> AGP_PAR W25 F8
HD#59 G_PAR VSS23
1
AE15 HD#60 AGP_REQ# AG24 F12
5 HD#60 <15> AGP_REQ# G_REQ# VSS24 5
1
CLK_GHT J8 AH17 HD#61 AGP_GNT# AH25 F16 R23 C47
<14> CLK_GHT CLK_GHT# BCLK HD#61 HD#62 <15> AGP_GNT# AGP_PIPE# G_GNT# VSS25 1K_1% .1UF_0402
<14> CLK_GHT# K8 AD17 AF22 F20
BCLK# HD#62 HD#63 PIPE# VSS26
AE16 F24
2
H_D BI#[0..3] HD#63 VSS27
<5> H_DBI#[0..3] G26
2
H_DBI#0 VSS28
AD5 H9
H_DBI#1 DBI#0 H_DSTBN#0 VSS29
AG4 AD4 N22 H11
H_DBI#2 DBI#1 HDSTBN#0 H_DSTBN#1 VSS0 VSS30
AH9 AE6 K27 H13
H_DBI#3 DBI#2 HDSTBN#1 H_DSTBN#2 VSS1 VSS31
AD15 AE11 K5 H15
+CPU_CORE DBI#3 HDSTBN#2 H_DSTBN#3 VSS2 VSS32
AC15 L24 H17
HDSTBN#3 H_DSTBP#0 VSS3 VSS33
AD3 M23 H19
HDSTBP#0 H_DSTBP#1 VSS4 VSS34
AE7 K7 H21
HDSTBP#1
AD11 H_DSTBP#2 +CPU_CORE J26
VSS5 VSS35
J1
HUB Interface Reference
HDSTBP#2 VSS6 VSS36
1
H_SWNG0 AA7 AC16 H_DSTBP#3 A3 J4 Layout note :

HSWNG0 HDSTBP#3 VSS7 VSS37
1
R68 C88 H_SWNG1 AD13 A7 J6 +1.8VS

HSWNG1 VSS8 VSS38
1
301_1% .01UF_0402 +V_MCH_GTLREF A11 J22 1. Place R_C and R_D in middle of Bus.
R66 VSS9 VSS39
6 M7 A15 J29 2. Place capacitors near MCH. 6
2
HVREF0 VSS10 VSS40

R8 R_E
2
HVREF1 49.9_1% Trace

Y8
HVREF2
1
AC2 AB11 width>=7mila BROOKDALE(MCH-M)
2
HRCOMP0 HVREF3
1
1
AC13 AB17 R78 C108
R72 HRCOMP1 HVREF4 301_1% @470PF
1
150_1% +1.5VS
2
1
BROOKDALE(MCH-M) R65 C102 C103 R_C
2
R48 R75 R_F
2
1
100_1% RP4 @8P4R_8.2K
24.9_0603_1% 24.9_0603_1% 1UF 220PF AGP_FRAME# 1 8 R84
2
AGP_TRDY# 2 7 @56.2_1%
2
AGP_PAR 3 6
AGP_STOP# 4 5
2
H_DSTBN#[0..3] +VS_HUBREF
+CPU_CORE RP83 @8P4R_8.2K
H_DSTBN#[0..3] <5>
1
H_DSTBP#[0..3] AGP_GNT# 1 8
7 H_DSTBP#[0..3] <5> GTL Reference Voltage AGP_REQ# 2 7 R71
7
Layout note : AGP_IRDY# 3 6 0_0402
1
AGP_DEVSEL# 4 5
1
1
R63 C90 1. Place R_E and R_F near MCH
1 2
301_1% .01UF_0402 2. Place decoupling cap 220PF near MCH pin.(Within RP3 @8P4R_8.2K R69
AGP_WBF# 1 8 R_D 301_1% C100
50 0mils)
2
+1.5VS AGP_PIPE# 2 7 .01UF_0402

2
AGP_RBF# 3 6
2
R90 8.2K_0402 R83 @8.2K_0402 4 5
1
2 1 AGP_ADSTB0 2 1 AGP_ADSTB0# AGP_ST1

R64 R337 2K_0402 R336 @1K_0402 R62 6.2K_0402 0=533Mhz
150_1% R45 8.2K_0402 R44 @8.2K_0402 AGP_ST0 AGP_ST0 2 1 2 1 AGP_ST1 2 1
AGP_ADSTB1 AGP_ADSTB1# 1=400Mhz
2 1 2 1 0=System memory is DDR
R39 6.2K_0402
2
R41 8.2K_0402 R40 @8.2K_0402 1=System memory is SDR AGP_ST2 2 1

8 2 1 AGP_SBSTB 2 1 AGP_SBSTB#
Title
401212
Custom
A B C D E F G H I J
A B C D E F G H I J
U43D
U43C
M8 R22 DD R_SDQ[0..63]
+CPU_CORE VTT_0 VCC1_5_0 +1.5VS <11> DDR_SDQ[0..63]
U8 R29 DDR_SDQ0 G28 E14
VTT_1 VCC1_5_1 DDR_SDQ1 SDQ0 SCK0 DDR_CLK0 <11>
AA9 VTT_2 VCC1_5_2 U22 F27 SDQ1 SCK#0 F15 DDR_CLK0# <11>
1 AB8 VTT_3 VCC1_5_3 U26 DDR_SDQ2 C28 SDQ2 SCK1 J24 DDR_CLK1 <11> 1
AB18 W22 DDR_SDQ3 E28 G25
VTT_4 VCC1_5_4 DDR_SDQ4 SDQ3 SCK#1 DDR_CLK1# <11>
AB20 VTT_5 VCC1_5_5 W29 H25 SDQ4 SCK2 G6 DDR_CLK2 <11>
AC19 AA22 DDR_SDQ5 G27 G7
VTT_6 VCC1_5_6 DDR_SDQ6 SDQ5 SCK#2 DDR_CLK2# <11>
AD18 AA26 F25
VTT_7 VCC1_5_7 DDR_SDQ7 SDQ6
AD20 AB21 B28 G15 DDR_CLK3 <12>
VTT_8 VCC1_5_8 DDR_SDQ8 SDQ7 SCK3
AE19 AC29 E27 G14 DDR_CLK3# <12>
VTT_9 VCC1_5_9 DDR_SDQ9 SDQ8 SCK#3
AE21 AD21 C27 E24 DDR_CLK4 <12>
AF18 AD23 B25 G24 DDR_CLK4# <12>
AF20 AE26 C25 H5 DDR_CLK5 <12>
AG19 AF23 B27 F5 DDR_CLK5# <12>
AG21
VTT_14 VCC1_5_14
AG29 Layout note : D27
SDQ13
AG23 AJ25 DDR_SDQ14 D26 K25
AJ19
VTT_16 Trace width 5mil ; Spacing E25
SDQ15 SCK#6
J25
AJ21 N14 DDR_SDQ16 D24 G17
AJ23
VTT_17 VCC1_5_16
N16 10mil DDR_SDQ17 E23
SDQ16 SCK7
G16
2 VTT_18 VCC1_5_17 SDQ17 SCK#7 2
VCC1_5_18
P13 Trace A to ball U13/T13 or DDR_SDQ18 C22
SDQ18 SCK8
H7
P15 DDR_SDQ19 E21 H6
A5
VCC1_5_19
P17
U17/T7 =1.5" Max DDR_SDQ20 C24
SDQ19 SCK#8
+2.5V VCCSM1 VCC1_5_20 DDR_SDQ21 SDQ20 DDR_SCS#0
A9 VCCSM2 VCC1_5_21 R14 B23 SDQ21 SCS#0 E9 DDR_SCS#0 <11>
A13 R16 DDR_SDQ22 D22 F7 DDR_SCS#1
VCCSM3 VCC1_5_22 DDR_SDQ23 SDQ22 SCS#1 DDR_SCS#2 DDR_SCS#1 <11>
A17 VCCSM4 VCC1_5_23 T15 B21 SDQ23 SCS#2 F9 DDR_SCS#2 <12>
A21 U14 +1.5VS DDR_SDQ24 C21 E7 DDR_SCS#3
VCCSM5 VCC1_5_24 SDQ24 SCS#3 DDR_SCS#3 <12>
A25 U16 DDR_SDQ25 D20 G9
VCCSM6 VCC1_5_25 DDR_SDQ26 SDQ25 SCS#4
C1 VCCSM7 C19 SDQ26 SCS#5 G10
MEMORY
C29 Murata LQG21N4R7K10 DDR_SDQ27 D18
VCCSM8 SDQ27
1
D7 L29 DDR_SDQ28 C20
VCCSM9 VCC1_8_0 +1.8VS L22 L21 DDR_SDQ29 SDQ28 DDR_SDQS0
D11 VCCSM10 VCC1_8_1 N26 E19 SDQ29 SDQS0 F26 DDR_SDQS0 <11>
D15 L25 DDR_SDQ30 C18 C26 DDR_SDQS1
VCCSM11 VCC1_8_2 DDR_SDQ31 SDQ30 SDQS1 DDR_SDQS2 DDR_SDQS1 <11>
D19 M22 4.7UH_30mA 4.7UH_30mA E17 C23
VCCSM12 VCC1_8_3 DDR_SDQ32 SDQ31 SDQS2 DDR_SDQS3 DDR_SDQS2 <11>
D23 VCCSM13 VCC1_8_4 N23 E13 SDQ32 SDQS3 B19 DDR_SDQS3 <11>
D25 DDR_SDQ33 C12 D12 DDR_SDQS4
2
3 VCCSM14 SDQ33 SDQS4 DDR_SDQS4 <11> 3
F6 "Trace A" DDR_SDQ34 B11 C8 DDR_SDQS5
VCCSM15 VCC_MCH_PLL1 DDR_SDQ35 SDQ34 SDQS5 DDR_SDQS6 DDR_SDQS5 <11>
F10 VCCSM16 VCCGA1 T17 "Trace A" C10 SDQ35 SDQS6 C5 DDR_SDQS6 <11>
F14 T13 VCC_MCH_PLL0 DDR_SDQ36 B13 E3 DDR_SDQS7
VCCSM17 VCCHA1 DDR_SDQ37 SDQ36 SDQS7 DDR_SDQS8 DDR_SDQS7 <11>
F18 VCCSM18 C13 SDQ37 SDQS8 E15 DDR_SDQS8 <11>
1
F22 DDR_SDQ38 C11
VCCSM19 VSS_MCH_PLL1 DDR_SDQ39 SDQ38 DDR_SMA[0..12]
G1 U17 + C169 + C168 D10 DDR_SMA[0..12] <11>
VCCSM20 VSSGA2 VSS_MCH_PLL0 DDR_SDQ40 SDQ39 DDR_SMA0
G4 VCCSM21 VSSHA2 U13 E10 SDQ40 SMA0/CS#11 E12
G29 "Trace A" 33UF_D2_16V 33UF_D2_16V DDR_SDQ41 C9 F17 DDR_SMA1
2
VCCSM22 DDR_SDQ42 SDQ41 SMA1/CS#10 DDR_SMA2
H8 VCCSM23 D8 SDQ42 SMA2/CS#6 E16
POWER/GND
H10 AA4 DDR_SDQ43 E8 G18 DDR_SMA3

VCCSM24 VSS83 DDR_SDQ44 SDQ43 SMA3/CS#9 DDR_SMA4
H12 VCCSM25 VSS84 AA8 "Trace A" E11 SDQ44 SMA4/CS#5 G19
H14 AA29 DDR_SDQ45 B9 E18 DDR_SMA5
H16 VCCSM27 VSS86 AB6 B7 SDQ46 SMA6/CS#7 F19
H18 AB9 DDR_SDQ47 C7 G21 DDR_SMA7
H20 AB10 C6 G20
H22 AB12 D6 F21
4 H24
VCCSM30 VSS89
AB13 DDR_SDQ50 D4
SDQ49 SMA9/CS#0
F13 DDR_SMA10 4
VCCSM31 VSS90 DDR_SDQ51 SDQ50 SMA10 DDR_SMA11
K22 AB14 B3 E20
K24 AB15 E6 G22
VCCSM33 VSS92 DDR_SDQ53 SDQ52 SMA12/CS#1
K26 AB16 B5
VCCSM34 VSS93 DDR_SDQ54 SDQ53 DDR_SBS0
L23 AB19 C4 G12 DDR_SBS0 <11>
VCCSM35 VSS94 DDR_SDQ55 SDQ54 SBS0 DDR_SBS1
K6 AB22 E5 G13 DDR_SBS1 <11>
VCCSM36 VSS95 DDR_SDQ56 SDQ55 SBS1
J5 AC1 C3
VCCSM37 VSS96 DDR_SDQ57 SDQ56 DDR_CKE0
J7 AC4 D3 G23 DDR_CKE0 <11>
VCCSM38 VSS97 DDR_SDQ58 SDQ57 SCKE0 DDR_CKE1
AC18 F4 E22 DDR_CKE1 <11>
VSS98 DDR_SDQ59 SDQ58 SCKE1 DDR_CKE2
AC20 F3 H23 DDR_CKE2 <12>
VSS99 DDR_SDQ60 SDQ59 SCKE2 DDR_CKE3
L1
VSS41 VSS100
AC21 B2
SDQ60 SCKE3
F23 DDR_CKE3 <12> Layout note
L4 AC23 DDR_SDQ61 C2 J23
L6
VSS42 VSS101
AC26 DDR_SDQ62 E2
SDQ61 SCKE4
K23 R113 27.4_1% Place R113
VSS43 VSS102 DDR_SDQ63 SDQ62 SCKE5 +1.25VS closely ball
L8 AD6 G5 2 1
VSS44 VSS103 DDR_CB[0..7] SDQ63
L22 AD8 <11> DDR_CB[0..7] J28
VSS45 VSS104 DDR_CB0 SM_RCOMP
5 L26 AD10 C16 J28 5
VSS46 VSS105 DDR_CB1 SDQ64/CB0 SMRCOMP R CVIN# C142 .1UF_0402_X5R
N1 AD12 D16 G3
VSS47 VSS106 DDR_CB2 SDQ65/CB1 RCVENIN# RCVOUT# 2
N4 AD14 B15 H3 1
VSS48 VSS107 DDR_CB3 SDQ66/CB2 RCVENOUT# C143 @47PF_0402
N8 AD16 C14 R112 0_0402
VSS49 VSS108 DDR_CB4 SDQ67/CB3
N13 AD19 B17 H27 R_J
VSS50 VSS109 DDR_CB5 SDQ68/CB4 SSI_ST
N15 AD22 C17
VSS51 VSS110 DDR_CB6 SDQ69/CB5 DDR_SRAS#
N17 AE1 C15 F11 DDR_SRAS# <11>
VSS52 VSS111 DDR_CB7 SDQ70/CB6 SRAS# DDR_SWE#
N29 AE4 D14 G11 DDR_SWE# <11>
VSS53 VSS112 SDQ71/CB7 SWE# DDR_SCAS#
P6 AE18 G8 DDR_SCAS# <11>
VSS54 VSS113 SDREF SCAS#
P8 AE20
VSS55 VSS114
P14 AE29 J21
VSS56 VSS115 SDREF_M SDREF0
P16 AF5 2 1 J9 AD26
VSS57 VSS116 SDREF1 NC0
R1
VSS58 VSS117
AF7 R108 0_0402 NC1
AD27 Layout note
R4 AF9 Place R_J closely Ball
VSS59 VSS118
1
R13 AF11
VSS60 VSS119 C141 C134 BROOKDALE(MCH-M) H3<40mil,Ball H3 to G3
R15 AF13
VSS61 VSS120 .1UF_0402_X5R .1UF_0402_X5R
6 R17 AF15 trace must 6
2
VSS62 VSS121
R26 AF17
T6
VSS63 VSS122
AF19
routing 1"
VSS64 VSS123
T8 AF21
VSS65 VSS124
T14 AF25
VSS66 VSS125
T16
VSS67 VSS126
AG1 Layout note
T22 AG18 Please closely
VSS68 VSS127
U1 AG20
VSS69 VSS128 pin J21 and J9
U4 AG22
VSS70 VSS129
U15 AH19
VSS71 VSS130
U29 AH21
VSS72 VSS131
V6 AH23
VSS73 VSS132
V8 AJ3
VSS74 VSS133
V22 AJ5
VSS75 VSS134
W1 AJ7
VSS76 VSS135
W4 AJ9
VSS77 VSS136
7 W8 AJ11 7
VSS78 VSS137
W26 AJ13
VSS79 VSS138
Y6 AJ15
VSS80 VSS139
Y22 AJ17
VSS81 VSS140
AA1 AJ27
VSS82 VSS141
BROOKDALE(MCH-M)
8
Title
401212
Custom
A B C D E F G H I J
10 9 8 7 6 5 4 3 2 1
Layout note : DDR Memory interface

Layout note : Processor system bus
Di stribute as close as possible
Di stribute as close as possible t o MCH P rocessor Quadrant.(between VCCSM and VSS pin)
to MCH Processor Quadrant.(between VTTFSB and VSS pin)
H H
+CPU_CORE +2.5V
1
1
C63 C62 C66 C78 C125 C136 C137 C139 C140 C135 C144 C150 C166
.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R 22UF_10V_1206 22UF_10V_1206
2
2
+2.5V
G G
+CPU_CORE
1
C146 C160 C164 C165 C162
1
1
.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R
2
C109 C82 C70 C69 C81
.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R
2
2
+2.5V
+CPU_CORE
1
F C163 C157 C158 C152 F
1
.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R
2
C52 C54 C425
10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R
2
+2.5V
1
+ C167
Layout note : AGP/CORE 220UF_D2_4V
2
E Di stribute as close as possible E
t o MCH Processor Quadrant.(between VCCAGP/VCCCORE
and VSS pin)
+1.5VS
1
C114 C96 C105 C85 C97 C119

.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R
2
D D
+1.5VS
1
C126 C86 + C75

10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 100UF_D_16V
2
C C
Layout note : Hub-Link
t o MCH Processor Quadrant.(between VCCHL and VSS pin)
+1.8VS
1
B C130 C127 C132 C133 B

10UF_6.3V_1206_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R
2
A
Title
401212
Custom
10 9 8 7 6 5 4 3 2 1
A B C D E F G H I J
+2.5V +2.5V DDR _DQ[0..63]
DDR _F_CB[0..7] DDR_DQ[0..63] <12>
SDREF_DIMM
DDR _DQS[0..8] DDR_F_CB[0..7] <12>
Layout note RP109 4P2R_22 RP115 4P2R_22
DDR_SDQ0 DDR_DQ0 DDR_SDQ30 DDR_DQ30 DDR_DQS[0..8] <12>
1 4 1 4 JP25
Place these resistor DDR_SDQ4 2 3 DDR_DQ4 DDR_SDQ26 2 3 DDR_DQ26 1 2 2 1
VREF VREF SDREF
closely DIMM0, 3 VSS VSS 4 R229 0_0402
1
DDR_DQ4 5 6 DDR_DQ0 C254
all trace length<750mil DQ0 DQ4
1 RP130 4P2R_22 RP98 4P2R_22 DDR_DQ5 7 DQ1 DQ5 8 DDR_DQ1 1
DDR_SDQ1 1 4 DDR_DQ1 DDR_SDQ31 1 4 DDR_DQ31 9 10 .1UF_0402
2
DDR_SDQ5 DDR_DQ5 DDR_SDQ27 DDR_DQ27 DDR_DQS0 VDD VDD
2 3 2 3 11 DQS0 DM0 12
DDR_DQ3 13 14 DDR_DQ6
DQ2 DQ6 DDR_SMA[0..12] <9>
15 16
RP131 4P2R_22 RP116 4P2R_22 DDR_DQ7 VSS VSS DDR_DQ2
17 18
DDR_SDQ6 DDR_DQ6 DDR_CB5 DDR_F_CB5 DDR_DQ12 DQ3 DQ7 DDR_DQ8 RP18 4P2R_10
1 4 1 4 19
DQ8 DQ12
20
DDR_SDQS0 2 3 DDR_DQS0 DDR_CB4 2 3 DDR_F_CB4 21 22 DDR_SMA12 1 4 DDR_F_SMA12
DDR_DQ13 VDD VDD DDR_DQ9 DDR_SMA9 2
23 24 3 DDR_F_SMA9
DDR_DQS1 DQ9 DQ13
25 26
RP110 4P2R_22 RP99 4P2R_22 DQS1 DM1
27 28
DDR_SDQ2 DDR_DQ2 DDR_CB1 DDR_F_CB1 DDR_DQ14 VSS VSS DDR_DQ10 RP16 4P2R_10
1 4 1 4 29
DQ10 DQ14
30
DDR_SDQ3 2 3 DDR_DQ3 DDR_CB0 2 3 DDR_F_CB0 DDR_DQ11 31 32 DDR_DQ15 DDR_SMA8 1 4 DDR_F_SMA8
DQ11 DQ15 DDR_SMA11 2
33
VDD VDD
34 3 DDR_F_SMA11
<9> DDR_CLK1 35 36
RP132 4P2R_22 RP121 4P2R_22 CK0 VDD
<9> DDR_CLK1# 37 38
2 DDR_SDQ8 DDR_DQ8 DDR_CB2 DDR_F_CB2 CK0# VSS RP14 4P2R_10 2
1 4 1 4 39 40
DDR_SDQ7 DDR_DQ7 DDR_SDQS8 DDR_DQS8 VSS VSS DDR_SMA7 1
2 3 2 3 4 DDR_F_SMA7
DDR_SMA5 2 3 DDR_F_SMA5
RP92 4P2R_22 RP100 4P2R_22 DDR_DQ17 DQ16 DQ20 DDR_DQ21
43 DQ17 DQ21 44
DDR_SDQ9 1 4 DDR_DQ9 DDR_CB3 1 4 DDR_F_CB3 45 46 RP19 4P2R_10
DDR_SDQ12 DDR_DQ12 DDR_CB6 DDR_F_CB6 DDR_DQS2 VDD VDD DDR_SMA4 1
2 3 2 3 47 DQS2 DM2 48 4 DDR_F_SMA4
DDR_DQ22 49 50 DDR_DQ18 DDR_SMA6 2 3 DDR_F_SMA6
DQ18 DQ22
51 VSS VSS 52
RP111 4P2R_22 RP117 4P2R_22 DDR_DQ23 53 54 DDR_DQ19
DDR_SDQS1 DDR_DQS1 DDR_DQ28 DQ19 DQ23 DDR_DQ24 RP13 4P2R_10
1 4 1 4 55 DQ24 DQ28 56
DDR_SDQ13 2 3 DDR_DQ13 DDR_CB7 2 3 DDR_F_CB7 57 58 DDR_SMA3 1 4 DDR_F_SMA3
DDR_DQ29 VDD VDD DDR_DQ25 DDR_SMA1 2
59 DQ25 DQ29 60 3 DDR_F_SMA1
DDR_DQS3 61 62
RP93 4P2R_22 RP122 4P2R_22 DQS3 DM3
63 VSS VSS 64
DDR_SDQ10 1 4 DDR_DQ10 DDR_SDQ36 1 4 DDR_DQ36 DDR_DQ26 65 66 DDR_DQ30 RP12 4P2R_10
3 DDR_SDQ14 DDR_DQ14 DDR_SDQ32 DDR_DQ32 DDR_DQ27 DQ26 DQ30 DDR_DQ31 DDR_SMA0 1 3
2 3 2 3 67 DQ27 DQ31 68 4 DDR_F_SMA0
69 70 DDR_SMA2 2 3 DDR_F_SMA2
DDR_F_CB4 VDD VDD DDR_F_CB5
71 CB0 CB4 72
RP112 4P2R_22 RP102 4P2R_22 DDR_F_CB0 73 74 DDR_F_CB1
DDR_SDQ15 DDR_DQ15 DDR_SDQ33 DDR_DQ33 CB1 CB5 R224 10_0402
1 4 1 4 75 76
DDR_SDQ11 DDR_DQ11 DDR_SDQ37 DDR_DQ37 DDR_DQS8 VSS VSS DDR_SMA10 1
2 3 2 3 77 DQS8 DM8 78 2 DDR_F_SMA10
DDR_F_CB6 79 80 DDR_F_CB2
CB2 CB6
81 VDD VDD 82
RP94 4P2R_22 RP123 4P2R_22 DDR_F_CB7 83 84 DDR_F_CB3
CB3 CB7 <12> DDR_F_SMA[0..12]
DDR_SDQ16 1 4 DDR_DQ16 DDR_SDQ38 1 4 DDR_DQ38 85 86
DDR_SDQ20 DDR_DQ20 DDR_SDQS4 DDR_DQS4 DU DU/RESET#
2 3 2 3 87 VSS VSS 88
<9> DDR_CLK0 89 CK2 VSS 90 Layout note
<9> DDR_CLK0# 91 CK2# VDD 92
RP113 4P2R_22 RP103 4P2R_22 93 94 Place these resistor
DDR_SDQ21 DDR_DQ21 DDR_SDQ39 DDR_DQ39 DDR_CKE1 VDD VDD DDR_CKE0
1 4 1 4 <9> DDR_CKE1 95 96 DDR_CKE0 <9> closely DIMM0,
DDR_SDQ17 DDR_DQ17 DDR_SDQ34 DDR_DQ34 CKE1 CKE0
2 3 2 3 97 98
4 DDR_SMA12 99
DU/A13 DU/BA2
100 DDR_SMA11 all trace length<=750mil 4
DDR_SMA9 A12 A11 DDR_SMA8
101 102
RP95 4P2R_22 RP118 4P2R_22 A9 A8
103 104
DDR_SDQ18 DDR_DQ18 DDR_SDQ44 DDR_DQ44 DDR_SMA7 VSS VSS DDR_SMA6
1 4 1 4 105
A7 A6
106
DDR_SDQS2 2 3 DDR_DQS2 DDR_SDQ35 2 3 DDR_DQ35 DDR_SMA5 107 108 DDR_SMA4
109 110
111
A1 A0
112 Layout note
RP120 4P2R_22 RP119 4P2R_22 113 114
DDR_SDQ19 DDR_DQ19 DDR_SDQ45 DDR_DQ45 DDR_SMA10 VDD VDD DDR_SBS1
1 4 1 4 115
A10/AP BA1
116 Place these resistor
DDR_SDQ22 2 3 DDR_DQ22 DDR_SDQ40 2 3 DDR_DQ40 DDR_SBS0 117 118 DDR_SRAS#
DDR_SWE# BA0 RAS# DDR_SCAS# closely DIMM0,
119 120
DDR_SCS#0 WE# CAS# DDR_SCS#1 all trace length
<9> DDR_SCS#0 121 122 DDR_SCS#1 <9>
RP96 4P2R_22 RP101 4P2R_22 S0# S1#
123 124 Max=1.3"
DDR_SDQ24 DDR_DQ24 DDR_SDQS5 DDR_DQS5 DU DU +1.25VS
1 4 1 4 125
VSS VSS
126
DDR_SDQ23 2 3 DDR_DQ23 DDR_SDQ41 2 3 DDR_DQ41 DDR_DQ36 127 128 DDR_DQ32
DDR_DQ33 DQ32 DQ36 DDR_DQ37
5 129 130 5
DQ33 DQ37
131 132
RP114 4P2R_22 RP104 4P2R_22 DDR_DQS4 VDD VDD RP28 4P2R_56
133 134
DDR_SDQ25 DDR_DQ25 DDR_SDQ43 DDR_DQ43 DDR_DQ38 DQS4 DM4 DDR_DQ34 DDR_CKE1 1
1 4 1 4 135 136 4
DDR_SDQ28 DDR_DQ28 DDR_SDQ42 DDR_DQ42 DQ34 DQ38 DDR_CKE0 2
2 3 2 3 137 138 3
DDR_DQ39 VSS VSS DDR_DQ35
139 140
141 142
RP97 4P2R_22 RP124 4P2R_22 DQ40 DQ44 RP24 4P2R_56
143 144
DDR_SDQS3 DDR_DQS3 DDR_SDQ47 DDR_DQ47 DDR_DQ45 VDD VDD DDR_DQ41 DDR_SCS#0 1
1 4 1 4 145 146 4
DDR_SDQ29 DDR_DQ29 DDR_SDQ46 DDR_DQ46 DDR_DQS5 DQ41 DQ45 DDR_SCS#1 2
2 3 2 3 147
DQS5 DM5
148 3
149 150
151 152
153 154
DQ43 DQ47
155 156
DD R_SDQ[0..63] VDD VDD
<9> DDR_SDQ[0..63] 157 158 DDR_CLK2# <9>
DDR_CB[0..7] VDD CK1#
<9> DDR_CB[0..7] 159 160 DDR_CLK2 <9>
DD R_SDQS[0..8] RP125 4P2R_22 VSS CK1
6 <9> DDR_SDQS[0..8] 161 162 6
DDR_SDQ49 DDR_DQ49 DDR_DQ49 VSS VSS DDR_DQ48
1 4 163 164
DDR_SDQ48 DDR_DQ48 DDR_DQ53 DQ48 DQ52 DDR_DQ52
2 3 165 166
DQ49 DQ53
167 168
RP127 4P2R_22 DDR_DQS6 VDD VDD
169 170
DDR_SDQ56 DDR_DQ56 RP105 4P2R_22 DDR_DQ54 DQS6 DM6 DDR_DQ50
1 4 171 172
DDR_SDQ51 DDR_DQ51 DDR_SDQ53 DDR_DQ53 DQ50 DQ54
2 3 1 4 173 174
DDR_SDQ52 DDR_DQ52 DDR_DQ55 VSS VSS DDR_DQ51
2 3 175
DQ51 DQ55
176
DDR_DQ56 177 178 DDR_DQ57 Layout note
RP106 4P2R_22 DQ56 DQ60
179 180
DDR_SDQ60 DDR_DQ60 RP126 4P2R_22 DDR_DQ60 VDD VDD DDR_DQ61
1 4 181
DQ57 DQ61
182 Place these resistor
DDR_SDQ57 2 3 DDR_DQ57 DDR_SDQ54 1 4 DDR_DQ54 DDR_DQS7 183 184
DDR_SDQS6 2 3 DDR_DQS6 185
DQS7 DM7
186
closely DIMM0,
DDR_DQ62 VSS VSS DDR_DQ58 all trace
187 188
189 190 length<=750mil
RP128 4P2R_22 RP107 4P2R_22 DQ59 DQ63
191 192
DDR_SDQS7 DDR_DQS7 DDR_SDQ55 DDR_DQ55 VDD VDD
7 1 4 1 4 <12,14> DIMM_SMDATA 193
SDA SA0
194 7
DDR_SDQ61 2 3 DDR_DQ61 DDR_SDQ50 2 3 DDR_DQ50 195 196 RP15 4P2R_10
<12,14> DIMM_SMCLK SCL SA1 DDR_SBS0
197 198 <9> DDR_SBS0 1 4 DDR_F_SBS0 DDR_F_SBS0 <12>
+3VS VDD_SPD SA2 DDR_SWE#
199 200 <9> DDR_SWE# 2 3 DDR_F_SWE# DDR_F_SWE# <12>
VDD_ID DU
RP108 4P2R_22
DDR_SDQ62 1 4 DDR_DQ62 RP17 4P2R_10
DDR-SODIMM_200_Normal
DDR_SDQ58 2 3 DDR_DQ58 <9> DDR_SCAS# DDR_SCAS# 1 4 DDR_F_SCAS#
DDR_SRAS# DDR_F_SCAS# <12>
2 3 DDR_F_SRAS#
DIMM0 <9> DDR_SRAS# DDR_F_SRAS# <12>
Front side / H=5.2mm
RP129 4P2R_22 R223 10_0402
DDR_SDQ63 1 4 DDR_DQ63 DDR_SBS1 1 2 DDR_F_SBS1
DDR_SDQ59 DDR_DQ59 <9> DDR_SBS1 DDR_F_SBS1 <12>
2 3
8
Title
401212
Custom
A B C D E F G H I J
A B C D E F G H I J
+2.5V +2.5V
+1.25VS +1.25VS
DDR _F_CB[0..7] SDREF_DIMM
DDR_F_CB[0..7] <11>
JP28
RP78 4P2R_56 RP62 4P2R_56 RP46 4P2R_56 DDR _DQS[0..8]
DDR_DQS[0..8] <11> 1 VREF VREF 2
DDR_DQ4 1 4 4 1 DDR_DQ26 4 1 DDR_DQ48 3 4
VSS VSS
1
DDR_DQ0 2 3 3 2 DDR_DQ30 3 2 DDR_DQ49 DDR _DQ[0..63] DDR_DQ0 5 6 DDR_DQ4
DDR_DQ[0..63] <11> DQ0 DQ4
1 DDR_DQ1 7 DQ1 DQ5 8 DDR_DQ5 C253 1
DDR_F_SMA[0..12] 9 10 .1UF_0402
2
RP61 4P2R_56 RP45 4P2R_56 DDR_F_SMA[0..12] <11> DDR_DQS0 VDD VDD
RP77 4P2R_56 11 12
DDR_DQ5 DQS0 DM0
1 4 4 1 DDR_DQ27 4 1 DDR_DQ52 DDR_DQ6 13 DQ2 DQ6 14 DDR_DQ3
DDR_DQ1 2 3 3 2 DDR_DQ31 3 2 DDR_DQ53 15 16
17 18
DDR_DQ8 DQ3 DQ7 DDR_DQ12 +1.25VS
19 20
RP76 4P2R_56 RP60 4P2R_56 RP44 4P2R_56 DQ8 DQ12
21 22
DDR_DQS0 1 VDD VDD RP27 4P2R_56
4 4 1 DDR_F_CB4 4 1 DDR_DQ54 DDR_DQ9 23 24 DDR_DQ13
DDR_DQ6 2 DQ9 DQ13
3 3 2 DDR_F_CB5 3 2 DDR_DQS6 DDR_DQS1 25 26 4 1 DDR_F_SMA9
DQS1 DM1
27 28 3 2 DDR_F_SMA12
29 30
RP75 4P2R_56 RP59 4P2R_56 RP43 4P2R_56 DDR_DQ15 DQ10 DQ14 DDR_DQ11
31 32
DDR_DQ3 DQ11 DQ15 RP23 4P2R_56
1 4 4 1 DDR_F_CB0 4 1 DDR_DQ50 33
VDD VDD
34
DDR_DQ2 2 3 3 2 DDR_F_CB1 3 2 DDR_DQ55 35 36 4 1 DDR_F_SMA11
<9> DDR_CLK4 CK0 VDD
<9> DDR_CLK4# 37
CK0# VSS
38 3 2 DDR_F_SMA8
2 39 40 2
RP74 4P2R_56 RP58 4P2R_56 VSS VSS
DDR_DQ7 RP42 4P2R_56 RP26 4P2R_56
1 4 4 1 DDR_F_CB2
DDR_DQ8 2 3 3 2 DDR_DQS8 4 1 DDR_DQ51 DDR_DQ16 41 42 DDR_DQ20 4 1 DDR_F_SMA5
DQ16 DQ20
3 2 DDR_DQ56 DDR_DQ21 43 44 DDR_DQ17 3 2 DDR_F_SMA7
DQ17 DQ21
45 VDD VDD 46
RP73 4P2R_56 RP57 4P2R_56 DDR_DQS2 47 DQS2 DM2 48
DDR_DQ12 1 RP41 4P2R_56 RP22 4P2R_56
4 4 1 DDR_F_CB3 DDR_DQ18 49 DQ18 DQ22 50 DDR_DQ22
DDR_DQ9 2 3 3 2 DDR_F_CB6 4 1 DDR_DQ57 51 52 4 1 DDR_F_SMA6
VSS VSS
3 2 DDR_DQ60 DDR_DQ19 53 DQ19 DQ23 54 DDR_DQ23 3 2 DDR_F_SMA4
RP72 4P2R_56 RP29 4P2R_56 DQ24 DQ28
57 VDD VDD 58
DDR_DQS1 1 RP40 4P2R_56 DDR_DQ25 DDR_DQ29 RP25 4P2R_56
4 4 1 59 DQ25 DQ29 60
DDR_DQ13 2 3 3 2 DDR_F_CB7 4 1 DDR_DQ61 DDR_DQS3 61 62 4 1 DDR_F_SMA1
DQS3 DM3
3 2 DDR_DQS7 63 VSS VSS 64 3 2 DDR_F_SMA3
3 RP71 4P2R_56 RP55 4P2R_56 DDR_DQ31 DQ26 DQ30 DDR_DQ27 3
67 DQ27 DQ31 68
DDR_DQ14 1 RP39 4P2R_56 RP21 4P2R_56
4 4 1 DDR_DQ36 69 70
DDR_DQ10 2 VDD VDD
3 3 2 DDR_DQ32 4 1 DDR_DQ58 DDR_F_CB5 71 CB0 CB4 72 DDR_F_CB4 4 1 DDR_F_SMA2
3 2 DDR_DQ62 DDR_F_CB1 73 74 DDR_F_CB0 3 2 DDR_F_SMA0
CB1 CB5
75 VSS VSS 76
RP70 4P2R_56 RP54 4P2R_56 DDR_DQS8 77 DQS8 DM8 78
DDR_DQ11 1 RP38 4P2R_56
4 4 1 DDR_DQ37 DDR_F_CB2 79 CB2 CB6 80 DDR_F_CB6 R242 56_0402
DDR_DQ15 2 3 3 2 DDR_DQ33 4 1 DDR_DQ59 81 82 1 2 DDR_F_SMA10
VDD VDD
3 2 DDR_DQ63 DDR_F_CB3 83 CB3 CB7 84 DDR_F_CB7
85 DU DU/RESET# 86
RP69 4P2R_56 RP53 4P2R_56 RP37 4P2R_56
87 VSS VSS 88
DDR_DQ20 1 4 4 1 DDR_DQ38 89 90 4 1 DDR_F_SWE#
DDR_DQ16 2 <9> DDR_CLK3 CK2 VSS
3 3 2 DDR_DQS4 <9> DDR_CLK3# 91 CK2# VDD 92 3 2 DDR_F_SBS0
93 VDD VDD 94
DDR_CKE3 95 96 DDR_CKE2
RP52 4P2R_56 <9> DDR_CKE3 CKE1 CKE0 DDR_CKE2 <9> RP20 4P2R_56
RP68 4P2R_56 97 98
4 DDR_DQ17 1 4 4 1 DDR_DQ39 DDR_F_SMA12 99
DU/A13 DU/BA2
100 DDR_F_SMA11 4 1 DDR_F_SRAS#
4
DDR_DQ21 2 A12 A11
3 3 2 DDR_DQ34 DDR_F_SMA9 101 102 DDR_F_SMA8 3 2 DDR_F_SCAS#
A9 A8
103 104
DDR_F_SMA7 VSS VSS DDR_F_SMA6
105 106
RP66 4P2R_56 RP50 4P2R_56 DDR_F_SMA5 A7 A6 DDR_F_SMA4 R230 56_0402
107 108
DDR_DQS2 1 A5 A4
4 4 1 DDR_DQ35 DDR_F_SMA3 109 110 DDR_F_SMA2 1 2 DDR_F_SBS1
DDR_DQ18 2 A3 A2
3 3 2 DDR_DQ44 DDR_F_SMA1 111
A1 A0
112 DDR_F_SMA0
113 114
DDR_F_SMA10 VDD VDD DDR_F_SBS1
115 116 DDR_F_SBS1 <11>
RP67 4P2R_56 RP51 4P2R_56 DDR_F_SBS0 A10/AP BA1 DDR_F_SRAS#
117 118 DDR_F_SRAS# <11>
DDR_DQ22 1 DDR_DQ40 <11> DDR_F_SBS0 DDR_F_SWE# BA0 RAS# DDR_F_SCAS#
4 4 1 <11> DDR_F_SWE# 119
WE# CAS#
120 DDR_F_SCAS# <11>
DDR_DQ19 2 3 3 2 DDR_DQ45 DDR_SCS#2 121 122 DDR_SCS#3
<9> DDR_SCS#2 S0# S1# DDR_SCS#3 <9>
123 124
DU DU
125 126
RP65 4P2R_56 RP49 4P2R_56 DDR_DQ32 VSS VSS DDR_DQ36
127 128
DDR_DQ23 1 DQ32 DQ36
5 4 4 1 DDR_DQ41 DDR_DQ37 129
DQ33 DQ37
130 DDR_DQ33
5
DDR_DQ24 2 3 3 2 DDR_DQS5 131 132
DDR_DQS4 VDD VDD
133 134
DDR_DQ34 DQS4 DM4 DDR_DQ38
135 136
RP64 4P2R_56 RP48 4P2R_56 DQ34 DQ38
137 138
DDR_DQ28 1 VSS VSS
4 4 1 DDR_DQ42 DDR_DQ35 139
DQ35 DQ39
140 DDR_DQ39
DDR_DQ25 2 3 3 2 DDR_DQ43 DDR_DQ40 141 142 DDR_DQ44
DQ40 DQ44
143 144
DDR_DQ41 VDD VDD DDR_DQ45
145 146
RP63 4P2R_56 RP47 4P2R_56 DDR_DQS5 DQ41 DQ45
147 148
DDR_DQS3 1 DQS5 DM5
4 4 1 DDR_DQ46 149 150
DDR_DQ29 2 VSS VSS
3 3 2 DDR_DQ47 DDR_DQ42 151
DQ42 DQ46
152 DDR_DQ43
DQ43 DQ47
155 156
VDD VDD
157 158 DDR_CLK5# <9>
VDD CK1#
Layout note 159
VSS CK1
160 DDR_CLK5 <9>
6 161 162 6
Place these resistor 163
DQ48 DQ52
164
closely DIMM1, DQ49 DQ53
167 168
all trace DDR_DQS6 VDD VDD
169 170
DDR_DQ50 DQS6 DM6 DDR_DQ54 +1.25VS
length<=800mil 171 172
DQ50 DQ54
173 174
175 176
177 178
DQ56 DQ60 RP56 4P2R_56
179 180
DDR_DQ61 VDD VDD DDR_DQ60 DDR_CKE2 1
181 182 4
DDR_DQS7 DQ57 DQ61 DDR_CKE3 2
183 184 3
DQS7 DM7
185 186
187 188
DDR_DQ59 DQ58 DQ62 DDR_DQ63 RP36 4P2R_56
189 190
DQ59 DQ63 DDR_SCS#2 1
191 192 4
VDD VDD DDR_SCS#3 2
7 <11,14> DIMM_SMDATA 193 194 +3VS 3 7
SDA SA0
<11,14> DIMM_SMCLK 195 196
SCL SA1
197 198
+3VS VDD_SPD SA2
199 200
VDD_ID DU
Layout note
DDR-SODIMM_200_Normal Place these resistor
closely DIMM1,
DIMM1 all trace length
Back side / H=9.2mm Max=1.3"
EMI Clip PAD for Memory Door
8 PAD10 PAD11 PAD12

Title
1 1 1
PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 2B
401212
Custom
A B C D E F G H I J
A B C D E F G H I J
Layout note :
to DDR-SODIMM.
1 1
+2.5V
1
1
C559 C577 C560 C562 C571 C558 C576 C555 C575 C557
.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R
2
2
2 +2.5V +2.5V 2
1
1
C574 C556 C570 C561 C573 C572 + C255 + C273
.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R 220UF_D2_6.3V 220UF_D2_6.3V
2
2
3 Layout note : 3
Place one cap close to every 2 pull up resistors termination to

+1.25V
+1.25VS
1
1
C259 C324 C271 C260 C347 C326 C310 C311 C307 C308
2
2
4 4
+1.25VS
1
1
C323 C325 C319 C309 C312 C313 C314 C332 C315 C335
2
2
5 5
+1.25VS
1
1
C336 C316 C317 C305 C306 C346 C333 C334 C320 C327
2
2
+1.25VS
6 6
1
C344 C328 C330 C318 C331 C322 C270 C329 C345 C343
2
+1.25VS
1
C268 C269 C266 C267 C272 C342 C338 C339 C340 C341
7 .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R 7
2
+1.25VS
1
C258 C257 C337 C321

.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R
2
8
Title
401212
Custom
A B C D E F G H I J
A B C D E F G H I J
1 +3VS L23 +3V_CLK 1

BLM21A601SPT Width=40 mils
1 2
1
L52
1
BLM21A601SPT +
1 2 C507 C151 C483 C458 C488 C138 C124 C464 C486 C489
SEL1 SEL0 Function 22UF_10V_1206 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 470PF_0402 47PF_0402
2
0 0 66Mhz Host CLK
0 1 100Mhz Host CLK
1 0 200Mhz Host CLK
14
19
32
37
46
50
1
8
2 1 1 133Mhz Host CLK U6 +3VS_CLKVDD 2
VDD_PCI
VDD_PCI
VDD_REF
VDD_3V66
VDD_3V66
VDD_48MHZ
VDD_CPU
VDD_CPU
Place Crystal within 500 mils of CK_Titan L20 +3VS
+3VS +3VS Width=15 mils BLM21A601SPT
2 1 2 26 1 2
C154 @10PF_0402 XTAL_IN VDD_CORE
1
caps are internal Y1
1
to CK_TITAN 14.318MHZ C93 C87

R130 R128 .1UF_0402 10UF_10V_1206
2
@1K_0402 1K_0402 2 1 3 27
C147 @10PF_0402 XTAL_OUT GND_CORE
2
45 CLK_BCLK 1 2
H_BSEL2 CPUCLKT2 CLK_HCLK <4>
40 R92 33.2_1% 1 2
H_BSEL0 SEL2 R91 49.9_1%
<5> H_BSEL0 55 SEL1
3 1 2 BSEL0 54 R_1 Place resistor near R_1,R_2 ;Trace 3
<5> H_BSEL1 SEL0
<=400mils
R127 @0_0402 R70 1 2 DT@1K_0402 R_2
+3VS
1
R129 +3VS R671 1 2 DT@1K_0402 R81 1 2 49.9_1%

R350 R134 @1K_0402 25 44 CLK_BCLK# R82 1 2 33.2_1%
PWR_DWN# CPU_CLKC2 CLK_HCLK# <4>
1K_0402 34
1K_0402 PCI_STOP# CLK_HT
53 CPU_STOP# CPUCLKT1 49 1 2 CLK_GHT <8>
R105 33.2_1% 1 2
2
R365 1 2 DT@1K_0402 R106 49.9_1%

+3VS
R_3 Place resistor near R_3,R_4 ;Trace
<33> CK408_PWRGD# 28 VTT_PWRGD# <=400mils
R67 1 2 M@0_0402 R_4
<16,30> SLP_S1#
R672 1 2 M@0_0402 R97 1 2 49.9_1%
<16> PM_STPPCI# CLK_HT#
R126 1 2 M@0_0402 R360 1 2 10K_0402 48 R98 1 2 33.2_1% CLK_GHT# <8>
<16,43> PM_STPCPU# +3VS CPUCLKC1
R351 1 2 @10K_0402 43
MULT0 CLK_ITP
52 1 2 CLK_ITPP <5>
4 CPUCLKT0 R118 @33.2_1% 1 2
4
R121 @49.9_1%
DIMM_SMDATA 29 R_5 Place resistor near R_5,R_6 ;Trace
DIMM_SMCLK SDATA
30 <=500mils
SCLK
R_6
R1111 2 @49.9_1%
51 CLK_ITP# R1091 2 @33.2_1%
CPUCLKC0 CLK_ITPP# <5>
33
3V66_0/DRCG
35 24
3V66_1/VCH_CLK 66MHZ_IN/3V66_5
Please closely pin42 23 CLK66_MCH R74 1 2 33.2_1%

66MHZ_OUT2/3V66_4 CLK66_AGP CLK_AGP_MCH <8>
R76 1 2 475_1% 42 22 R80 1 2 33.2_1%
IREF 66MHZ_OUT1/3V66_3 CLKICH_HUB CLK_AGP <15>
21 R79 1 2 33.2_1%
66MHZ_OUT0/3V66_2 CLK_ICHHUB <16>
5 R77 CLK_ICH48M CLKPCI_F2 5

<16> CLK_ICH48 1 2 22_0402 39 7 R117 1 2 33.2_1% CLK_ICHPCI <16>
48MHZ_USB PCICLK_F2
6
PCICLK_F1
5 CLKPCI_F0 R521 1 2 USB20@33.2_1% CLK_PCI_USB20 <26>
PCICLK_F0
<27> CLK_SD48
R73 1 2 22_0402 CLK_SD48M 38
48MHZ_DOT
18 CLKPCI_MIN R86 1 2 33.2_1%
PCICLK6 CLKPCI_SD CLK_PCI_MIN <34>
17 R95 1 2 33.2_1%
PCICLK5 CLK_PCI_SD <27>
16
R131 1 CLK_ICH14M PCICLK4 CLKPCI_LPC
<16> CLK_ICH14 2 10_0402 56
REF PCICLK3
13 R103 1 2 33.2_1%
CLK_PCI_LPC <30>
R133 1 2 10_0402 12 CLKPCI_SIO R104 1 2 33.2_1%
<28> CLK_14M_SIO GND_48MHZ PCICLK2 CLKPCI_PCM_F CLK_PCI_SIO <28>
R132 1 2 10_0402 11 R107 1 2 33.2_1%
<21> CLK_14M_AUD PCICLK1 CLK_PCI_PCM <23>
GND_3V66
GND_3V66
GND_IREF
GND_CPU
CLKPCI_1394_F
GND_REF
10 R110 1 2 33.2_1%
GND_PCI
GND_PCI
PCICLK0 CLK_PCI_1394 <25>
6 6
W320-04
4
9
15
20
31
36
41
47
1
or ICS 9508-05
Note:
2
CPU_CLK[2:0] needs to be running in C3, C4.
C101 C112 C117

+12VS @10PF_0402 @10PF_0402 @10PF_0402
1
R154
7 7
22_0402
22
G
1 3 DIMM_SMDATA
<16,18> SMB_DATA DIMM_SMDATA <11,12>
D
Q47 2N7002
G
1 3 DIMM_SMCLK
<16,18> SMB_CLK DIMM_SMCLK <11,12>
D
8
Q11 2N7002 Title
401212
Custom
A B C D E F G H I J
A B C D E F G H I J
AGP 100X2 Pin connector JP33

1
JP3 JP2 INVPWR_B+ 1
2
<30> INVT_PWM INVT _PWM 2
1 2 1 2 3
GND GND AGP_ST[0..2] AGP_ST0 GND GND VGA_D ECT D ISPOFF# 3
<22> INT_MIC 3 4 EC_SMC1 <30,31,39> <8> AGP_ST[0..2] 3 4 4
GN DA 3 4 AGP_ST2 3 4 AGP_ST1 D A C_BRIG 4
5 6 EC_SMD1 <30,31,39> 5 6 5
5 6 AGP_SBA[0..7] AGP_SBA0 5 6 AGP_SBA1 <30> D AC_BRIG 5
1 7 8 <8> AGP_SBA[0..7] 7 8 6 1
7 8 AGP_SBA2 7 8 AGP_SBA3 6
9 10 9 10 7
CRT_R 9 10 AGP_AD[0..31] AGP_SBA4 9 10 AGP_SBA5 7
11 12 SUS_STAT# <16,28> <8> AGP_AD[0..31] 11 12
11 12 AGP_SBA6 11 12 AGP_SBA7 H E ADER 7
13 14 13 14
CRT _G 13 14 T V_SYNC AGP_C/B#[ 0..3] AGP_AD30 13 14
15 16 <8> AGP_C/BE#[0..3] 15 16
15 16 AGP_AD28 15 16
17 18 17 18 AGP_SBSTB <8>
CRT _B 17 18 T V_LUMA AGP_AD26 17 18
19 20 19 20 AGP_SBSTB# <8>
19 20 19 20
21 22 21 22
C R T _ HSYNC GND GND TV_CRMA GND GND AGP_C/ BE#3
23 24 <8> AGP_ADSTB1# 23 24
C R T _VSYNC 23 24 23 24 AGP_AD31
25 26 <8> AGP_ADSTB1 25 26
3VD DCDA 25 26 TV_COMPS 25 26 AGP_AD29
27 28 27 28
3VD DCCL 27 28 AGP_AD24 27 28 AGP_AD27
29 30 29 30
P ID0 29 30 AGP_AD22 29 30 AGP_AD25
31 32 KSO16 <30> 31 32
R634 <28> P ID0 P ID1 31 32 31 32 AGP_C/ BE#2
33 34 KSI0 <30,33> 33 34
SCRLED@0_0402 <28> P ID1 P ID2 33 34 33 34 AGP_AD23
35 36 KSI1 <30,33> 35 36
<28> P ID2 P ID3 35 36 AGP_AD20 35 36 AGP_AD21
<30> S CROLLED# 1 2 37 38 KSI2 <30,33> 37 38
<28> P ID3 P ID4 37 38 AGP_AD18 37 38 AGP_AD19
39 40 KSI3 <30,33> 39 40
<28> P ID4 39 40 39 40
41 42 41 42
GND GND AGP_AD16 GND GND AGP_AD17
43 44 KSI4 <30,33> 43 44
2 <27> MEDIA_LED# New add 5/3 <30> NUMLED# 45
43 44
46 LID_SW# <30,31>
AGP_AD14 45
43 44
46 AGP_C/ BE#1 2
45 46 AGP_AD12 45 46 AGP_AD15
JOHNNY <30> CAPSLED# 47 48 D RV0# <19,28> 47 48
47 48 AGP_AD10 47 48 AGP_AD13
<30> MAIL_LED# 49 50 ON/OFFBTN# <33> 49 50
49 50 AGP_AD8 49 50 AGP_AD11
51 52 51 52
51 52 AGP_AD6 51 52 AGP_AD9
53 54 +3VS 53 54
53 54 53 54 AGP_C/ BE#0
55 56 55 56
55 56 55 56 AGP_AD7
57 58 <8> AGP_ADSTB0 57 58
57 58 57 58 AGP_AD5
59 60 <8> AGP_ADSTB0# 59 60
59 60 59 60
61 62 61 62
GND GND AGP_AD4 GND GND AGP_AD3
A GP_NBREF 63 64 63 64
63 64 AGP_AD2 63 64 AGP_AD1
65 66 65 66
65 66 AGP_AD0 65 66 R339 0_0402
+1.8VS 67 68 67 68 PM_C3_STAT# <16>
67 68 67 68 AGP_RST#
69 70 <14> CLK_AGP 69 70 1 2 PCIRST# <5,8,16,19,23,25,26,28,34>
69 70 +1.25VS_VGA 69 70
71 72 <8> AGP_PAR 71 72 AGP_DEVSEL# <8>
71 72 71 72
73 74 <8> AGP _IRDY# 73 74 AGP_STOP# <8> 1 2 G_RST# <23,24,25,30>
73 74 Change 1.25VS to 1.25VS_VGA 73 74 R338 @0_0402
75 76 75 76 AGP_FRAME# <8>
75 76 5/3 JOHNNY <8> AGP_TRDY# 75 76
+1.5VS 77 78 77 78 PIRQA# <16,18,23,25,26>
77 78 <8> AGP_GNT# 77 78
79 80 79 80 AGP_RBF# <8>
79 80 <8> AGP_REQ# 79 80
81 82 81 82
3 83
GND GND
84 83
GND GND
84 M_SEN# +3VS 3
83 84 <16> A GP_BUSY# 83 84
85 86 <8> AGP_WBF# 85 86
85 86 85 86 LVDS_BLON#
87 88 +12VALW 87 88
87 88 87 88
89 90 +AGPREF 89 90
89 90 89 90
2
91 92 91 92 +2.5VS
91 92 +2.5VS 91 92 R513
93 94 93 94
93 94 93 94
+5VS 95 96 95 96
95 96 95 96 4.7K_0402_5%
97 98 97 98
97 98 97 98
99 100 99 100
1
GND GND GND GND D 42
1 2 D ISPOFF#
FOXCONN-100P FOXCONN-100P <30> BKOFF#
RB751V
D 43
L10 1 2
+AGPREF +1.5VS +1.8VS +2.5VS +3VS +5VS +5VALW +12VALW <30> ENABLT
B++ FBM-L11-201209-221 INVPWR_B+ +3VS RB751V
4 4
INV_B+
1
C 46 C 35 C406 C129 C431 C432 C 22 C 65 C 64 Q42 Width=60 mils
1
Width=60 mils 1 8
.1UF_0402 .1UF_0402 22UF_10V_1206 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 2 7 R514
2
3 6
10K_0402_5%
5
2
1
C440 R344 FDS4435 FDS4435: P CHANNAL
1
.1UF_0402 100K_0402 Q62
2
LVDS_BLON# 2
2
R 342 +5V 2N7002
1 2
3
1
D Q41
75K 2
G
S
3
5 2N7002 5
+3VS
1
D1 D4 D2 +5VS
R _CRT_VCC CRT_VCC
D 33 F4
2 1 1 2
TV_OUT CONNECTOR CRT CONNECTOR
1
@DAN217 @DAN217 @DAN217 FUSE_1A
RB411D
2
C4
2
D6 D5 D3 TV_VCC .1UF_0402 R359 R358
@DAN217 @DAN217 @DAN217 2.2K_0402 2.2K_0402
1
JP14
1
M_SEN# 6
<30,31> M_SEN#
L3 11
1 2 CRT_R 1 2 CRTL_R 1
6 R 13 S@0_0402 +3VS FCM2012C80_0805 6
7
L2 12
2
CRT _G 1 2 CRTL_G 2
1 2 FCM2012C80_0805 8
R 14 @0_0402 +5VS
L4 13
L5 CRT _B 1 2 CRT L_B 3
FCM2012C80_0805 CRT_VCC 9
2
2
T V_SYNC 1 2 C 32 C 33 14
1
1
@FBM-11-160808-121 10PF_0402 10PF_0402 C 34 C 10 C 11 C 12 4
1 2 R9 R7 R8 10
C 15 S@22PF_0402 75_0402 75_0402 75_0402 10PF_0402 22PF_0402 22PF_0402 22PF_0402 15
2
2
L6 5
1
T V_LUMA 1 2
S@FBM-11-160808-121 L8 C R T CONN.
C R T _ HSYNC 1 2 C R T _ HSYNCRFL 1 3 3VD DCDA
1 2 CHB1608B121
C 14 S@22PF_0402 Q85
L9 JP13 L1 2N7002
2
1
7 1 2 C R T _VSYNC 1 2 C R T _VSYNCRFL 7
S@FBM-11-160808-121 T V_SYNCL 1 3VD DCCL
CHB1608B121 1 3
2
1
2
TV_CRMA T V_LUMAL 3 C6 C3
1 2
C 21 S@22PF_0402 4 22PF_0402 220PF_0402 Q86
2
L7 TV_CRMAL 5 2N7002
TV_COMPS TV_COMPSL 6 C 13 +3VS
1 2
S@FBM-11-160808-121 7 C7 220PF_0402
22PF_0402 C9
S @S CONN.
220PF_0402 2 R667 1
1
4.7K_0402
1
R 12 R 11 R 10 C 26 C 25 C 24 C 16 C 17 C 20
C 19 +12VS 2 R668 1
R661 100K_0402 4.7K_0402
S@75_0402 S@330PF_0402 S@330PF_0402
2
2
2
S@75_0402 S@270PF_0402 S@330PF_0402 @470PF_0402

S@75_0402 S@270PF_0402
8 S@270PF_0402 8
Title
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C
401212
Date: 星期 @, 十二月 30, 2002 Sheet 15 of 46
A B C D E F G H I J
A B C D E F G H I J
EC_ SMI#
<30> EC_SMI#
EC_SCI#
<30> EC_SCI# LAD0 <27,28,30>
LID_ OUT# LAN_DET# 1 2 +3VS
<30> LID_OUT# LAD1 <27,28,30>
R167 100K_0402
LAD2 <27,28,30>
C519 @33PF_0402
<33> ICH_VGATE LAD3 <27,28,30>
2 1 <5> PM_CPUPERF# 1 2 R381 1 2 LAN@0_0402
+3VALW LDRQ#1 <28>
R226 10K_0402 <43> PM_GMUXSEL LFRAME# <27,28,30>
<30> EC_THRM# R_LAN
1 <15,28> SUS_STAT# 1
1 2 BATTLOW# LAN enable: Mount R_LAN.
<30> VLBA#
2
D17 1SS355 <14> PM_STPPCI# PM_STPPCI# R383
@22_0402 1 2 LAN disable: Delete R_LAN.
<14,43> PM_STPCPU# +3VS
R222 10K_0402
<30> SLP_S5#
<30> SLP_S3# SIDE PWR <19>
2 IAC_ SY NC
GPIO4 1 2
<14,30> SLP_S1# GAIN_SEL# <22>
1
RSMRST# R310 @0_0402
R200 <20,33> RSMRST#
RSMRST# 1 2 0_0402 PM_AUXPWROK USB20_SMI#
1 2 +3VALW
<18,30> ICH _SWI# <26> USB20_SMI# +3VS
PM_PWROK 1 2 R384 8.2K_0402
<33> PM_PWROK
R417 10K_0402 GPIO3 1 2
<30> PBTN_OUT#
IDE_PATADET
1
R380 8.2K_0402
USB20_SMI#
1 2
IAC_BITCLK
<43> PM_DPRSLPVR
SDATA_IN1
SDATA_IN0
C202 .1UF_0402 GPIO4 1
LAN_DET#
2 R219
LID_ OUT#
AC_RST#
<18,23,25,28,30,34> PM_CLKRUN# IRQ14 <18,19>
EC_SCI#
EC_ SMI#
R382
SDATAO
P IRQC#
P IRQD#
R379 8.2K_0402
PIRQ A#
PIRQ B#
<15> PM_C3_STAT# IRQ15 <18,19>
GPIO4
GPIO5
GPIO3
BATTLOW# GPIO5 1 2 @10K_0402
SI RQ <18,23,27,28,30>
PM_PWROK 1 2 PM_AUXPWROK 33_0402 R166 8.2K_0402
2
2 R221 @0_0402 D 14 2
<15> AGP_BUSY#
1
1 2 ICH_WAKE_UP#
<31> EC_WAKEUP#
AB21
AB14
1 2 10K_0402
W20
W19
AC2
AB3
AB1
AA6
AA1
AA7
AA5
AA2
AA4
AB4
U21
U20
D11
C11
H22
V21
Y20
V19
B11
+3VS
J19
J20
J21
W2
W3
W4
U5
C7
U3
U2
U4
U1
C1
C5
V4
Y5
V5
B7
A7
V1
V2
Y4
Y2
Y3
B1
B2
A2
A6
B5
A5
R208 PIRQ A# RB751V
T3
T2
U52A <15,18,23,25,26> PIRQA#
PIRQ B#
<23,25,26,34> AD[0..31] <18,26> PIRQB#
P IRQC#
INT_SERIRQ
INT_PIRQF#/GPIO3
PM_PWRBTN#
PM_AGPBUSY#/GPIO6
PM_BATLOW#
PM_C3_STAT#/GPIO21
PM_CLKRUN#/GPIO24
PM_RI#
GPIO_7
GPIO_8
PM_RSMRST#
PM_SLP_S1#/GPIO19
PM_SLP_S3#
PM_SLP_S5#
PM_STPCPU#/GPIO20
PM_STPPCI#/GPIO18
PM_SUS_STAT#
PM_THRM#
PM_GMUXSEL/GPIO23
PM_CPUPREF#/GPIO22
AC_RST#
AC_SDATAIN0
AC_SDATAIN1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ#0
LPC_DRQ#1
LPC_FRAME#
GPIO_12
GPIO_13
GPIO_25
GPIO_27
GPIO_28
INT_APICD0
INT_APICD1
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
INT_PIRQE#/GPIO2
INT_PIRQG#/GPIO4
INT_PIRQH#/GPIO5
INT_IRQ14
INT_IRQ15
PM_AUXPWROK
PM_PWROK
PM_SUS_CLK
PM_VGATE/VRMPWRGD
AC_BITCLK
AC_SDATAOUT
INT_APICCLK
PM_DPRSLPVR
AC_SYNC
<18,26,34> P IRQC#
P IRQD#
<18,34> P IRQD#
IAC_BITCLK
<21,32,34> IAC_BITCLK
Place closely to
1 2 ICH3-M
R162 10K_0402 A D0 J2 T5 CL K_ICHPCI
PCI_AD0 PCI_CLK CL K _ICHPCI <14>
A D1 K1 M3 CL K_ICHPCI
PCI_AD1 PCI_DEVSEL# DEVSEL# <18,23,25,26,34>
SDATA_IN0 A D2 J4 F1
<21> SDATA_IN0 PCI_AD2 PCI_FRAME# FRAME# <18,23,25,26,34>
1
A D3 K3 C4
PCI_AD3 PCI_GPIO0/REQA# PCI_REQA# <18>
1 2 A D4 H5 D4 R225
PCI_AD4 PCI_GPIO1/REQB#/REQ5# PCI_REQB# <18>
R378 10K_0402 A D5 K4 AC'97 LPC unMUX Interrupt B6
A D6 PCI_AD5 PCI_GPIO16/GNTA# @10_0402
3 H3
PCI_AD6 Power Management Geyserville Interface Interface GPIO Interface PCI_GPIO17/GNTB#/GNT5#
B3 3
SDATA_IN1 A D7 L1 N3
1 2
<32,34> SDATA_IN1 PCI_AD7 PCI_IRDY# I R DY# <18,23,25,26,34>
A D8 L2 G5
PCI_AD8 PCI_PAR PAR <18,23,25,26,34>
2 1 A D9 G2 M2 C224
PCI_AD9 PCI_PERR# PE RR# <18,23,25,34>
SDATAO
R385 10K_0402 AD10 L4 M1

PCI_AD10 PCI_LOCK# PLOCK# <18,23>
AD11 H4 PCI W1 ICH_WAKE_UP# @15PF_0402
2
AD12 PCI_AD11 PCI_PME#
+3VS 1 2 M4 Interface Y1 2 R264 1 33_0402
R376 @10K_0402 AD13 PCI_AD12 PCI_RST# PCIRST# <5,8,15,19,23,25,26,28,34>
J3 L5 SE RR# <18,23,25,34>
R165 AD14 PCI_AD13 PCI_SERR#
M5 H2 STOP# <18,23,25,26,34>
IAC_SDATAO AD15 PCI_AD14 STOP#
<21,32,34> IAC_SDATAO 2 1 J1 H1 TRDY# <18,23,25,26,34>
AD16 PCI_AD15 PCI_TRDY#
F5
22_0402 AD17 PCI_AD16
N2
PCI_AD17
1
C516 AD18 G4 Y6 +CPU_CORE

PCI_AD18 SM_INTRUDER# SM_INTRUDER# <18>
AD19 P2 AC3
PCI_AD19 SMLINK0 SMLINK0 <18>
@27PF AD20 G1 AB2
System SMLINK1 <18>
2
AD21 PCI_AD20 SMLINK1

P1 Managment SMB_CLK AC4 SMB_CLK <14,18>
1
AD22 PCI_AD21
4 F2 Interface SMB_DATA AB5 SMB_DATA <14,18> 4
AD23 PCI_AD22 R228
P3 AC5
IAC_ SY NC AD24 PCI_AD23 SMB_ALERT#/GPIO11 SMB_ALERT# <18> @10K_0402
F3 PCI
ICH3-M (1/2)
<21,32,34> IAC_ S YNC PCI_AD24
AD25 R1 Interface
1
C515 AD26 PCI_AD25

E2 Y22
2
PCI_AD26 CPU_A20GATE GATEA20 <30>
AD27 N4 V23
PCI_AD27 CPU_A20M# H_A20M# <5>
@27PF AD28 D1 AB22 R233 1 2 0_0402
2
AD29 PCI_AD28 CPU_DPSLP# H_ F ERR#

P4 J22
AD30 PCI_AD29 CPU_FERR#
E1 AA21 H _IGNNE# <5>
AC_RST# AD31 PCI_AD30 CPU_IGNNE# <5> H_DPSLP#
<21,32,34> AC97_RST# 1 2 P5 AB23 H_INIT# <5>
PCI_AD31 CPU_INIT# +3VS (for use if CPU unable
CPU CPU_INTR
AA23 H_ INTR <5>
R377 33_0402 Interface Y21 to support DPSLP#)
CPU_NMI H _NMI <5>
<23,25,26,34> C/BE#0 K2 W23 H_ PW RGD <5>
1
PCI_C/BE#0 CPU_PWRGOOD
<23,25,26,34> C/BE#1 K5 U22 KBRST# <30>
PCI_C/BE#1 CPU_RCIN# R201
<23,25,26,34> C/BE#2 N1 W21 H_SLP# <5>
1
PCI_C/BE#2 CPU_SLP# 300_0402
<23,25,26,34> C/BE#3 R2 Y23 H_SMI# <5>
PCI_C/BE#3 CPU_SMI# R204
U23 H_STPCLK# <5>
5 STPCLK# 470_0402 5
2
A4 H_ F ERR#
<18,25> GNT#0 PCI_GNT#0
E3 L22 H UB_PD0
2
<18,34> GNT#1
1
PCI_GNT#1 HUB_PD0 H UB_PD1 Q21
<18,23> GNT#2 D2 M21
PCI_GNT#2 HUB_PD1 H UB_PD2
Place closely to <18,26> GNT#3 D5
PCI_GNT#3 HUB_PD2
M23 2
ICH3-M B4 N20 H UB_PD3
<18,34> GNT#4
1
PCI_GNT#4 HUB_PD3 H UB_PD4 Q19
P21
3
HUB_PD4 H UB_PD5 3904
R22 2
CLK_ICH14 CLK_ICH48 HUB_PD5 H UB_PD6
<18,25> REQ#0 D3 R20
PCI_REQ#0 HUB_PD6 H UB_PD7
F4 VSS Clocks LAN EEPROM HubLink T23
3
<18,34> REQ#1
1
PCI_REQ#1 HUB_PD7 H UB_PD8 3904

<18,23> REQ#2 A3
PCI_REQ#2 Interface Interface Interface HUB_PD8
M19
R194
R421 R411 R4 P19 H UB_PD9
<18,26> REQ#3 PCI_REQ#3 HUB_PD9
E4 N19 HUB_PD10 <5> H_ F _FERR# 1 2
<18,34> REQ#4
LAN_RSTSYNC
@10_0402 @10_0402 PCI_REQ#4 HUB_PD10
HUB_VSWING
HUB_PSTRB#
HUB_RCOMP
CLK_RTEST#
HUB_PSTRB
EEP_SHCLK
CLK_RTCX1
CLK_RTCX2
470_0402
CLK_VBIAS
EEP_DOUT
HUB_VREF
1 2
1 2
LAN_RXD2
LAN_RXD1
LAN_RXD0
LAN_TXD2
LAN_TXD1
LAN_TXD0
LAN_JCLK
HUB_PD[0..1 0]
HUB_PAR
HUB_CLK
EEP_DIN
6 HUB_PD[0..10] <8> 6
EEP_CS
CLK_14
CLK_48
C540 C532
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
CL K _ICHHUB
@10PF_0402 @10PF_0402 + ICH _HUBREF
2
2
+VS_HUBVSWING R227
ICH3-M
A1
A13
A16
A17
A20
A23
B8
B10
B13
B14
B15
B18
B19
B20
B22
C3
C6
F19
C14
C15
C16
C17
C18
C19
C20
C21
C22
D9
D13
D16
D17
D20
D21
D22
E5
J23
F20
RTC_ RST# Y7
RTC_X1 AC7
RTC_X2 AC6
AB7
D7
C9
A10
C10
B9
A9
A8
C8
D10
E8
D8
E9
L19
L20
K19
P23
N22
R19
T19
@10_0402
RTC_VBIAS
CL K _ICHHUB
1
+ RTCVCC CL K _ICHHUB <14>
CLK_ICH14 HUB_PSTRB <8> C252
<14> CLK_ICH14 HUB_PSTRB# <8>
CLK_ICH48 H UB_ICH_RCOMP 1 2 @10PF_0402
LAN_CLK_ICH
<14> CLK_ICH48
1 2 +R_VBAIS C276 1 2 RTC_VBIAS R209 36.5_1%
R248 1K_0402 . 047UF 1 2
+ RTCVCC
RTC_X1
1
RTC_X2 R185 15K
1
1 2 1 2 1 2 EEP_CS <20>
R245 @22M R247 10M R441 10M C219 C215
7 C189 J1 EEP_DIN <20> 7
.01UF_0402 .01UF_0402
2
J OPEN EEP_DOUT <20>
X4 1 UF
2
EEP_SHCLK <20> Close t o ICH3-M.

2
+1.8VS R246
HUB Interface VSwing Voltage
1
@2.4M_1%
LAN_RXD0 <20>
1
32.768KHZ R192
LAN_RXD1 <20>
1
C566 C582 +1.8VS 1K_0402

R_RTC LAN_RXD2 <20>
2
R211 12PF 12PF
1
LAN_TXD0 <20>
301_1% R_K HUB Reference Voltage R161
2
LAN_TXD1 <20>
1
1. Place R_G and R_H in middle of Bus. LAN_TXD2 <20>

R_G R205 Place R_K and R_L R1641 2 22_0402 @1K_0402
LAN_JCLK <20>
2
301_1% Closely ICH3
1
L A N_RSTSYNC <20>
+VS_HUBVSWING
Layout note:
2
1
+ ICH _HUBREF Locate J1 and R_RTC on bottom side and with

1
R216 C544 R_L easy access through memory door

1
301_1% .1UF_0402
8 R202 Compal Electronics, Inc. 8
2
R_H 301_1% Title

2
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Cu stom
401212
Date: 星薑 @, 十二月 30, 2002 Sheet 16 of 46
A B C D E F G H I J
A B C D E F G H I J
USBP0+
<32> USBP0+ +5VS +3VS +5VALW
USBP0-
<32> USBP0-
1 1
1
1 2
C171 5PF_0402 R163 D11 R188
USBP1+ 1K_0402 1SS355 0_0402

<32> USBP1+
USBP1-
<32> USBP1-
2
Width=15 mils +VCC_RTC + RTCVCC
1
1 2 VCC5 REF
C172 5PF_0402 C185
1
.1UF_0402 R437
2
USBP2+ VCC1.8SUS : Width=40 mils C229 C208 1 2
<32> USBP2+
USBP2- .1UF_0402 1 UF +1.8VALW
2
<32> USBP2-
1
+3VALW
+1.8_ICHLAN : Width=20 mils 1K_0402
+3V +CPU_CORE C565
1
1 2 .1UF_0402 Closely Pin AB6
2
1
2 C173 5PF_0402 R181 2
+1.8VALW VCC1.8SUS +V1.8_ICHLAN
VCCRE FSUS
R186
USBP3+ L25 0_0805
<32,34> USBP3+ R217
USBP3- 2 1 O VCUR#2 1 2 1 2 +VCC_RTC 0_0805
VCC1.8SUS 2
<32,34> USBP3-
R630 100K_0402 0_0805
VCC1.8SUS
VCC PAU 2
2 1 O VCUR#4 BLM21A601SPT +3VS +1.8VS
1 2 R169 100K_0402
C170 5PF_0402 2 1 O VCUR#5
R157 100K_0402
2 1 O VCUR#3
R160 100K_0402
2 1 OVCUR_R#0
M10
M14
AB6
G18
C13
U18
C23
H18
R18
E13
K12
P10
K10
P14
V22
B23
A21
A22
P12
V15
V16
V17
V18
E11
K18
P18
V10
V14
F14
F15
F16
F10
T21
T18
J18
W8
W5
G6
D6
C2
H6
R6
U6
V6
V7
E6
E7
K6
P6
R623 USB20@100K_0402
F7
F8
F9
T1
F6
T6
J6
U52B
2 1 OVCUR_R#1
R624 USB20@100K_0402
VCC_SUS0
VCC_SUS1
VCC_SUS2
VCC_SUS3
VCC_SUS4
VCC_SUS5
VCC_USB0/VCC_SUS6
VCC_USB1/VCC_SUS7
VCC_AUX0/VCCLAN1_8
VCC_AUX1/VCCLAN1_8
VCC_AUX2/VCCLAN1_8
VCC5REF1
VCC5REF2
VCC5REFSUS1
VCC5REFSUS2
VCCPAUX0/VCCLAN3_3
VCCPAUX1/VCCLAN3_3
VCCPCPU0
VCCPCPU1
VCCPCPU2
VCCUSBBG/VCC_SUS8
VCCUSBPLL/VCC_SUS9
N/C0
N/C1
N/C2
N/C3
N/C4
VSS102
VSS103
VCCPPCI0
VCCPPCI1
VCCPPCI2
VCCPPCI3
VCCPPCI4
VCCPPCI5
VCCPPCI6
VCCPPCI7
VCCP0
VCCP1
VCCPHL0
VCCPHL1
VCCPHL2
VCCPHL3
VCCPIDE0
VCCPIDE1
VCCPIDE2
VCCPIDE3
VCCPIDE4
VCCCORE0
VCCCORE1
VCCCORE2
VCCCORE3
VCCCORE4
VCCCORE5
VCCCORE6
VCC_RTC
3 3
AC15
IDE_PDCS1# PDCS1# <19>
AB15
USBP0+ IDE_PDCS3# PDCS3# <19>
D19 AC21
USBP1+ USB_PP0 IDE_SDCS1# SDCS1# <19>
A19 AC22
USBP2+ USB_PP1 IDE_SDCS3# SDCS3# <19>
E17
USBP3+ USB_PP2
B17 AA14
USBP4+ USB_PP3 IDE_PDA0 PDA0 <19>
D15
USB_PP4 Power IDE_PDA1
AC14
PDA1 <19>
USBP5+ A15 AA15
USBP0- USB_PP5 IDE_PDA2 PDA2 <19>
D18 AC20
USBP1- USB_PN#0 IDE_SDA0 SDA0 <19>
A18 AA19
E16 AB20
B16 PDD[0..15] <19>
USBP4- USB_PN#3 PD D0
D14 W12
USBP5- USB_PN#4 IDE_PDD0 PD D1
Layout note The Cap close to A14
USB_PN#5 IDE_PDD1
AB11
ICH3-M(< 1 inch) AA10 PD D2
IDE_PDD2 PD D3
4 AC10 4
OVCUR_R#0 E12 IDE_PDD3 PD D4
W11
OVCUR_R#1 D12 USB_OC#0 IDE_PDD4 PD D5
Y9
O VCUR#2 USB_OC#1 IDE_PDD5 PD D6
<32> O VCUR#2 C12 AB9
R625 USB11@100K_0402 O VCUR#3 USB_OC#2 IDE_PDD6 PD D7
B12 AA9
OVCUR_R#0 O VCUR#4 USB_OC#3 IDE_PDD7 PD D8
<26> O VCUR#0 2 1 A12
USB_OC#4 USB IDE_PDD8
AC9
2 1 OVCUR_R#1 O VCUR#5 A11 Interface Y10 PD D9
<26> O VCUR#1 USB_OC#5 IDE_PDD9
R626 USB11@100K_0402 W9 P DD10
R207 0_0402 IDE_PDD10 P DD11
Y11
IDE_PDD11 P DD12
<19> PIDERST# 1 2 H20 AB10
ICH_IDE_SRST# USB_LEDA#0/GPIO32 IDE_PDD12 P DD13
<19> ICH_IDE_SRST# G22 AC11
USB_LEDA#1/GPIO33 IDE_PDD13 P DD14
<18> BT_DET# F21 AA11
USB_LEDA#2/GPIO34 IDE_PDD14 P DD15
G19 AC12
ICH3-M (2/2)
<18,32> MDC_DET# USB_LEDA#3/GPIO35 IDE_PDD15 SDD[0..15] <19>
<18> FIR_DET# E22
USB_LEDA#4/GPIO36 IDE
E21 Interface Y17 SD D0
USB_LEDA#5/GPIO37 IDE_SDD0 SD D1
H21 W17
USB_LEDG#0/GPIO38 IDE_SDD1 SD D2
<18> MS_DET# G23 AC17
5 F23
USB_LEDG#1/GPIO39 IDE_SDD2
AB16 SD D3 5
<18> SD_DET# USB_LEDG#2/GPIO40 IDE_SDD3
G21 W16 SD D4
<31> EC_FLASH# USB_LEDG#3/GPIO41 IDE_SDD4
ICH_ ACIN D23 Y14 SD D5
E23 AA13
W15
Cancel 5/16 JOHNNY IDE_SDD7
W13 SD D8
IDE_SDD8 SD D9
B21 Y16
USB_RBIAS IDE_SDD9 S DD10
Y15
1
IDE_SDD10 S DD11
AC16
* R394 IC H_SPKR IDE_SDD11 S DD12
<21> IC H_SPKR H23
SPKR Misc IDE_SDD12
AB17
AA17 S DD13
18.2_1% IDE_SDD13 S DD14
Y18
IDE_SDD14 S DD15
+1.8VS U19 AC18
2
VCCA IDE_SDD15
Power
Y13 PD DACK# <19>
R400 IDE_PDDACK#
+3VALW 1 2 F17 Y19 SD DACK# <19>
6 VCCPSUS3/VCCPUSB0 IDE_SDDACK# 6
0_0805 F18 AB12 PDD REQ <19>
VCCPSUS4/VCCPUSB1 IDE_PDDREQ
K14 AB18 SDD REQ <19>
VCCPSUS5/VCCPUSB2 IDE_SDDREQ
AC13 P DIOR# <19>
IDE_PDIOR#
VSS IDE_SDIOR#
AC19 S DIOR# <19>
VC CPSUS E10 Y12 PD IOW# <19>
VCCPSUS0 IDE_PDIOW#
V8 AA18 SD IOW# <19>
VCCPSUS1 IDE_SDIOW#
V9 AB13 P DIO RDY <19>
VCCPSUS2 IDE_PIORDY
AB19 S DIO RDY <19>
IDE_SIORDY
VSS100
VSS101
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
ICH3-M
E14
E15
E18
E19
E20
F22
G3
G20
H19
AA22
J5
K11
K13
K20
K21
K22
K23
L3
L10
L11
L12
L13
L14
L21
L23
M11
M12
M13
M20
M22
N5
N10
N11
N12
N13
N14
N21
N23
P11
P13
P20
P22
R3
R5
R21
R23
T4
T20
T22
V3
AC23
V20
W6
W7
W10
W14
W18
W22
Y8
AA3
AA8
AA12
AA16
AA20
AB8
AC1
AC8
7 7
Note:
R376=22.6_1% for B0(QB63 part)
R376=18.2_1% for B0(QB62 & SL5LF part)
+3VS
1
R414
R180 1 2 IC H_SPKR
+3VS
100K_0402
@1K_0402
2
8 8
Title
ICH_ ACIN
Disable Timeout feature
<30,37,40> ACIN
1
D38
2
RB751V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
401212
A B C D E F G H I J
A B C D E F G H I J
1 1
+3VS +3VS
RP11
<16,23,25,26,34> FRAME# 1 10
<16,23,25,26,34> I R DY# 2 9 S ERR# <16,23,25,34>
<16,23,25,26,34> TRD Y# 3 8 DEVSEL# <16,23,25,26,34>
<16,23,25,26,34> STOP# 4 7 P ERR# <16,23,25,34>
2 5 6 PLOCK# <16,23> 2
10P8R_8.2K +CPU_CORE
+3VS +3VS
1
RP10 +
<16> PCI_REQA# 1 10 C217 C235 C244
2 9 1 UF .1UF_0402 .1UF_0402
<16> PCI_REQB# REQ#2 <16,23>
2
<16,25> REQ#0 3 8 REQ#3 <16,26>
<16,34> REQ#1 4 7 REQ#4 <16,34>
5 6 S IRQ <16,23,27,28,30>
10P8R_8.2K
+3VS
3 +3VS +3VS 3
1
R P9
1
<16,34> GNT#1 1 10 + +
2 9 C529 C523 C204 C199 C236 C250 C240 C200 C205 C212 C251 C213 C237 C227
<16,23> GNT#2 IRQ15 <16,19>
3 8 22UF_10V_1206 22UF_10V_1206 .1UF_0402 .1UF_0402 47PF_0402 .1UF_0402 .1UF_0402 47PF_0402 .1UF_0402 .1UF_0402 47PF_0402 .1UF_0402 .1UF_0402 .1UF_0402
2
<16,34> P IRQD# PIRQA# <15,16,23,25,26>
<16,19> IRQ14 4 7 PIRQB# <16,26>
5 6 P IRQC# <16,26,34>
10P8R_8.2K +3VS
+3VS
1
R168 1 2 8.2K_0402 C242 C203 C243 C238 C239 C216
<16,25> GNT#0
47PF_0402 .1UF_0402 .1UF_0402 47PF_0402 .1UF_0402 .1UF_0402 SD_DET# 1 2
4 +3VS 4
2
<17> SD_DET#
R152 1 2 8.2K_0402 R621 100K_0402
<16,26> GNT#3
R151 1 2 8.2K_0402 R622 1 2 SD@10K_0402
<16,34> GNT#4
R150 1 10K_0402 VC CPSUS
<16,23,25,28,30,34> PM_CLKRUN# 2 R_SD
SD enable: Mount R_SD
1
SD disable: Delete R_SD.
1
+3VALW +
C218 C247 C245 C211 C194
22UF_10V_1206 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402
2
R155 1 2 4.7K_0402
<14,16> SMB_DATA
R156 1 2 4.7K_0402
<14,16> SMB_CLK
+1.8VS
5 MS_DET# 1 2
5
<17> MS_DET# +3VS
R611 100K_0402
+3VALW
1
R612 1 2 MS@10K_0402
1
R187 1 2 8.2K_0402 +
<16,30> IC H_SWI#
C513 C210 C214 C221 C226 C232 C241 C249 R_MS
100UF_D2_6.3V .1UF_0402 33PF_0402 .1UF_0402 .1UF_0402 33PF_0402 .1UF_0402 .1UF_0402
2
2
R397 1 2 10K_0402 MS enable: Mount R_MS
<16> SMB_ALERT#
V CC1.8SUS
MS disable: Delete R_MS.
+3VALW
1
R395 1 2 4.7K_0402
<16> SMLINK0
1
1
R398 1 2 4.7K_0402 C228
6 <16> SMLINK1 6
10UF_6.3V_P C248 C246 C196
2
.1UF_0402 .1UF_0402 .1UF_0402

2
2
+ RTCVCC
R218 1 2 100K_0402
<16> SM_INTRUDER#
R170 1 2 100_0402
<16,23,25,26,34> PAR
7 7
BT_DET# 1 2 +3VS MDC_ DET# 1 2 +3VS FIR_DET# 1 2 +3VS
<17> BT_DET#
R531 100K_0402 <17,32> MDC_DET# R532 100K_0402 <17> FIR_DET# R527 100K_0402
R533 1 2 LAN@10K_0402 R534 1 2 @10K_0402 R529 1 2 FIR@10K_0402
R_BT R_MDC R_FIR

Blue Tooth enable: Mount R_BT MDC enable: Mount R_MDC FIR enable: Mount R_FIR
Blue Tooth disable: Delete R_BT. MDC disable: Delete R_MDC. FIR disable: Delete R_FIR.
8
Title
401212
A B C D E F G H I J
A B C D E F G H I J
<17> PDD[0..15]
PDD[0..15]
HDD Connector
1 1
+3VS
C369
2 1
.1UF_0402 U28
5
PCIRST# 1
<5,8,15,16,23,25,26,28,34> PCIRST#
4 PIDE_ RST#
<17> PIDERST# 2
3
7SH08FU
Place closely to
JP31
2 2
PD IOW# P DIOR# Correct HDD pin define ,pls update layout +5VS Placea caps. near HDD CONN.
1
JP31
R517 R518 PIDE_ RST#
PD D7 1 2 PD D8
2 1
1
10_0402 10_0402 R297 @10K_0402 PD D6 3 4 PD D9 C370 C363 C373 C371 C375
PD D5 5 6 P DD10
1 2
1 2
PD D4 7 8 P DD11 1000PF_0402 10UF_16V_1206 10UF_16V_1206 1UF_25V_0805 .1UF_0402
2
C675 C676 PD D3 9 10 P DD12
PD D2 11 12 P DD13
15PF_0402 15PF_0402 PD D1 13 14 P DD14
2
PD D0 15 16 P DD15
17 18
SI3456DV: N CHANNEL
19 20 VGS: 4.5V, RDS: 65 mOHM
<17> PD DREQ PDD REQ
R304 1 PD IOW# 21 22 Id(MAX): 5.1A
3 +3VS 2 4.7K_0402 3
<17> PD IOW# P DIOR# 23 24 VGS,+-20V
<17> P DIOR# P DIO RDY 25 26 PCSEL 1 R298
<17> P DIO RDY 2
R305 1 RPD DACK# 27 28 PDD REQ +5VS
<17> PD DACK# 2 0_0402 1 2 Q30 +5VSCD
RIRQ14 29 30 470_0402 R302 @5.6K_0402 SI3456DV
<16,18> IRQ14 1 2
31 32
R306 0_0402
<17> P DA1 33 34
6 WITH: 100 mils
+5VS 1 2 <17> PDA0 P DA2 <17> 1 2 5 4
R301 100K_0402 35 36
<17> PDCS1# PDCS3# <17> 2
1
P HDD_LED# 37 38 C374 33PF_0402 1
39 40 + C581 R443
+5VS 41 42 +5VS
4.7UF_10V_0805
3
43 44 +5VS <1st Part Field> 1K_0402
2
H DD_CONN_44P +12VALW
2
R436
2 1
1
R444
4 Q55 4
1
100K_0402 DTC144EKA 2 S IDE_PWR#
10K_0402
Q56
3
SDD[0..15] 2 47K 2N7002
<17> SDD[0..15]
CD-ROM Connector
1
C568
R627 1 2 0_0402 .01UF_0402
47K
2
1
+3VS Q54
C282 +5VS 2
3
C717 <16> SIDE PWR
2 1 2N7002
2 1
3
.1UF_0402 U22
5
@.1UF_0402 U71
5
PCIRST# 1
4 SIDERST# P HDD_LED# 1
2 4 ACT_LED#
5 <17> ICH_IDE_SRST# ACT_LED# <29> 5
S HDD_LED# 2
3
7 SH08FU 3
@7SH08FU
1 2
C587 @47PF_0402
1 2 1 2
C588 @47PF_0402
JP29
C589 @47PF_0402 Extend Module ID list
<21> INT_CD_L 1 2 IN T_CD_R <21>
CD_ AGND CD_ AGND DEVICE EXTID2 EXTID1 EXTID0
<21> CD_ AGND 3 4
SIDERST# SD D8
SD D7 5 6 SD D9
2 1
6 R263 @10K_0402 SD D6 7 8 S DD10 6
9 10
FDD 0 0 0
SD D5 S DD11 Placea caps. near CDROM
SD D4 11 12 S DD12
SD D3 13 14 S DD13 CD-ROM 0 0 1 CONN.
SD D2 15 16 S DD14
SD D1 17 18 S DD15 +5VSCD
SD D0 19 20 SDD REQ LS-120 0 1 0
+3VS 1
R260
2 4.7K_0402 +5VSCD
21
23
22
24
SDD REQ <17>
S DIOR# <17>
W=100 mils
RSD DACK# 1 2
<17> SD IOW# 25 26 SD DACK# <17>
S DIO RDY R258 0_0402 2'nd HDD 0 1 1
<17> S DIO RDY S DA2 <17>
1
RIRQ15 27 28 C285 C283 C586 C580
<16,18> IRQ15 1 2 SDCS3# <17>
R259 0_0402 29 30 EXTID0
<17> S DA1 31 32 EXTID0 <31>
+5VS 1 2 EXTID1 1000PF_0402 .1UF_0402 1UF_25V_0805 10UF_16V_1206
2
<17> S DA0 33 34 EXTID1 <31>
R257 100K_0402 EXTID2
<17> SDCS1# 35 36 EXTID2 <31>
S HDD_LED# HDSEL#
37 38 HDSEL# <28>
2 1 SEC_CSEL
7 R446 470_0402 39 40 WG ATE# 7
41 42 WGATE# <28>
+5VSCD
RDATA# 43 44
<28> RDATA# NONE 1 1 1
W P# 45 46
<28> WP# 47 48
TRACK0# FDDIR#
<28> TRACK0# 49 50 FDDIR# <28>
WDATA#
<28> WDATA# 3MODE# <28>
1
STEP# 51 52 C281 C284 C578 C579
<28> STEP# 53 54
MTR0# SDD REQ 1 2
<28> MTR0# 55 56
DI SKCHG# INDEX# R262 @5.6K_0402 1000PF_0402 .1UF_0402 1UF_25V_0805 10UF_16V_1206
<28> DI SKCHG# INDEX# <28>
2
D RV0# 57 58
<15,28> D RV0# 59 60 +5VSCD
1 2
HEADER 2X30
C585 33PF_0402
8
Title
401212
A B C D E F G H I J
10 9 8 7 6 5 4 3 2 1
+3VALW
H LAN@.1UF_0402 LAN@.1UF_0402 H
1 2 VC CR_LAN
+ + L54 LAN@4.7UH
1
+ C466
C473 C508 C505 C471 C468 C469 C470
LAN@4.7UF_10V_0805 LAN@.1UF_0402 LAN@4.7UF_10V_0805
2
LAN@4.7UF_10V_0805 LAN@.1UF_0402 LAN@.1UF_0402 Layout note :
25
36
40
12
14
17
19
23
1
2
7
9
Cassis LAN_GND
C511 R371 LAN_TX+ 1 2 LAN_TX- should cover part
VCCA2
VCCT
VCCT
VCCT
VCCT
VCCP
VCCP
VCCA
VCC
VCC
VCCR
VCCR
2 1 2 1 R354 LAN@100_1%_0402
of U15.
@10PF_0402 @33_0402 LAN_RX+ 1 2 LAN_RX-
LAN_JCLK 39 10 LAN_TX+ R357 LAN@100_1%_0402
<16> LAN_JCLK JCLK TDP U39
L A N_RSTSYNC 42 11 LAN_TX-
<16> L A N_RSTSYNC JRSTSYNC TDN
G LAN_TXD2 45 G
<16> LAN_TXD2 JTXD[2]
LAN_TXD1 44 15 LAN_RX+ LAN_RX+ 1 16 LAN_RJ45R+
<16> LAN_TXD1 JTXD[1] RDP RD+ RX+
LAN_TXD0 43 16 LAN_RX- LAN_RX- 2 15 LAN_RJ4 5R-
<16> LAN_TXD0 JTXD[0] RDN RD- RX-
LAN_RXD2 37 3 14
<16> LAN_RXD2 LAN_RXD1 JRXD[2] R355 1 CT CT
35 5 2 LAN@619_1%_0402
<16> LAN_RXD1 LAN_RXD0 JRXD[1] RBIAS100 R356 1
34 Kinnereth 4 2 LAN@549_1%_0402
<16> LAN_RXD0 JRXD[0] RBIAS10
6 11
LAN_ACTLED# LAN_TX+ CT CT LAN_RJ45T+
32 7 10
TP_L AN_ADV ACTLED# LAN_TX- TD+ TX+ LAN_RJ45T-
41 31 8 9
LAN_ TCK ADV10 SPDLED# LAN_L ILED# TD- TX-
30 27
LAN_TI ISOL_TCK LILED#
28
LAN_EX ISOL_TI LAN@Pulse-H0022
29
TP_LAN_TOUT ISOL_TEX LAN_X2 X3
1 2 26 47
LAN_TESTEN TOUT X2 LAN_X1
R372 @0_0402 21 46
TESTEN X1
Layout Note:
LAN@25MHZ H0022 Pls closely to
VSSA2
1
VSSR
VSSR
VSSP
VSSP
VSSA
F C501 C502 F
VSS
VSS
VSS
VSS
VSS
+3VALW RJ45 Conn. R341 R340
LAN@22PF_0402 LAN@22PF_0402
2
1
LAN@82562ET U46 LAN@75_1% LAN@75_1%
8
13
18
24
48
33
38
3
6
20
22
R370
2
LAN@100K_0402
L AN_GND
2
2
C436
LAN_ TCK
LAN_TI LAN@1000PF_1206_2KV
1
LAN_EX EEPROM for ICH3-m LAN
LAN_TESTEN +3VALW
(Atmel AT93C46-10PC-2.7)
U40
E <16> EEP_CS 1 8 E
CS VCC
1
D
<16> EEP_SHCLK 2 7
Q48 SK DC
<16,33> RSMRST# 2 <16> EEP_DOUT 3 6 1 2
G LAN@2N7002 DI ORG R345 LAN@10K_0402
<16> E EP_DIN 4 5
DO GND
= LAN_RST# S
3
LAN@AT93C46-10SC-2.7
JP18
12
Amber LED-
ORE_ LED_1 1 2 ORE_ LED_2 11
D R36 LAN@510_0603 Amber LED+
16
D
SHLD4
8
1
C60 PR4-
15
1
SHLD3
7
LAN@47PF_0402 PR4+
2
C
10K LAN_RJ4 5R- 6
LAN_ACTLED# ORE_LED_N PR2-
2
R60 LAN@0_0402 5
B
47K Q8 PR3-
E
LAN@DTA114YKA 4
PR3+
LAN_RJ45R+ 3
3
PR2+
LAN_RJ45T- 2
+3V PR1-
14
LAN_RJ45T+ SHLD2
1
C PR1+ C
13
SHLD1
10
Green LED-
GRN_LED_1 1 2 GRN_LED_2 9
R6 LAN@510_0603 Green LED+
1
LAN@AMP RJ45 with LED

1
C C36
10K
1
LAN_L ILED# GRN_LED_N 2 LAN@47PF_0402
2
R16 LAN@0_0402 B
47K
E R32 R 31
LAN@75_0402 LAN@75_0402
Q4
2
LAN@DTA114YKA L AN_GND
3
B B
+3V
+3VALW
LED1_GRNN
R24 @100K_0402
LED2_YELN
R59 @100K_0402
A
Title
401212
10 9 8 7 6 5 4 3 2 1
A B C D E F G H I J
New add
5/16 JOHNNY
VDDA
L91
+3VALW 1 2
+5VS
1
<30> BEEP#
+3VALW @0_0805 reserve for AC97 coedc using only
1 +5VS R463 L92 1
10K_0402 1 2 VDDA
+5VALW
1
0_0805
R449 U55
2
C609 W=40Mil 5VDDA 4 5
VIN VOUT
1
100K_0402 1 2 R309
1
R319 2 6 1 2
2
DELAY SENSE
1
.1UF_0402 C607 C592 C594 C598 C597
13
14
1
U21D U12F @100K_0402 7 1 28.7K_1%
2
74LVC14 R462 10UF_16V_1206 4.7UF_10V_0805 .1UF_0402 ERROR CNOISE 10K_1% .1UF_0402
R318 4.7UF_10V_0805
2
1
12 11 1 2 13 12 C387 R452 10K_0402 8 3
Close to AC97 CODEC ON/OFF# GND C593 R308
1 2 1 2
74LVC125 10K_0402 SI9182DH-AD
2
1
1UF_0603 560_0402
7
C605
.22UF_0603 <30,36,42> SUSP# .01UF_0402
2
2 C615 2
2 1 MONO_IN_R
1 2 MONO_IN
R488 0_0402
1UF_10_0603
1
New update C613 R464
1
5/16 JOHNNY 1 2 1 2 2
<23> PCM_SPK# Q60 R489
1UF_0603 560_0402 2SC2411EK
3
2.4K_0402
2
C388 R454
<17> ICH_SPKR 1 2 1 2
3 3
560_0402
1UF_0603
1
R320 D31
2 R493 1 C DL
<19> INT_CD_L 1SS355
2 1 6.8K_0402 @10K_0402 VDDC
R494 6.8K_0402
2
1 2 +3VS
2 R495 1 CDR R471 0_0805
<19> INT_CD_R
2 1 6.8K_0402
1
R496 6.8K_0402 C634
C630
.1UF_0402 10UF_10V_1206
2
4 ID1# ID0# FREQ. SEL 4
AVDD_AC97 NC NC 24.576MHZ
L62
2 1
HB-1M2012-121JT
VDDA 0 NC 14.318MHZ
R492
<14> CLK_14M_AUD 1 2
NC 0 48MHZ
1
C629 C614
@0_0402 1M_0402
R475 .1UF_0402 10UF_10V_1206
2
Y2
2
C647 C645
25
38
5 5
1
9
24.576MHz U62
C648 C649 1000PF_0402 1000PF_0402
VDD
VDD
AVDD
AVDD
1
22PF_0402 22PF_0402
2
XTL-IN LINEL C646 1
3
XTL-OUT LINE-OUTL
35 2 4.7UF_10V_0805 LEFT <22,35>
2 1 36 LINER C651 1 2 4.7UF_10V_0805
LINE-OUTR MDMIC RIGHT <22,35>
C644 15PF_0402 37 1 2 MD_MIC <32,34>
MONO-OUT C657 1UF_25V_0805
11 27 AUD_REF 1 2
<16,32,34> AC97_RST# RESET# VREF
1 2 6 28 C653 1000PF_0402
<16,32,34> IAC_BITCLK BIT-CLK VREFOUT +AUD_VREF
1
R473 22_0402 10 + C628 C631
<16,32,34> IAC_SYNC SYNC C637 1000PF_0402 1UF_10V .1UF_0402
<16,32,34> IAC_SDATAO 5 29
SDATA-OUT AFILT1
<16> SDATA_IN0 1 2 8 30
2
R472 22_0402 SDATA-IN AFILT2
C640 1000PF_0402
31
MONO_IN VRAD
6 12 32 6
PC-BEEP VRDA
<32,34> MD_SPK 2 1 MD_SPKR 1 2 C620 MD_SPKRC 13 33
R470 20K_0402 .1UF_0402 PHONE CAP1
14 34
AUX-L NC C643 C641 C636
15 43 C642 @1000PF_0402
AUX-R JD/SDIN1
16 44
VIDEO-L TEST1 1UF_10V 1UF_10V 1UF_10V
2 1 17 45
R469 33K_0402 C DL VIDEO-R ID0#
1 2 18 46
CDR C6261 CD-L ID1#
21UF_10V 20
CD-R EAPD
47
C625 1UF_10V 21 48 L63
MD_MONRC MIC1 SPDIFO
22 39 1 2
LINEL_IN_C MIC2 HP-OUT-L 0_0805
23 40
LINER_IN_C LINE-L NC L66
24 41
<22> MICIN LINE-R HP-OUT-R
1 2
CD-GND
2 1 MD_MONR 1 2 1UF_10V 0_0805

<34> MD_MON
AVSS
AVSS
R466 10K_0402 C624 L60

VSS
VSS
+AUD_VREF
2
C110 C111 C616 C622 1 2

1
1
7 C627 0_0805 7
2 1 .1UF_0402 .1UF_0402 .1UF_0402
.1UF_0402 ALC202 R480 R476 L56
1
4
7
19
26
42
R467 1K_0402 .1UF_0402 @0_0402 @0_0402 1 2

2
0_0805
1
C633 C635 L65
2
2
1 2 GNDA
.1UF_0402 @10UF_10V_1206 0_0805
2
6.8K_0402
2 1 CD_AGNDR 1 2 C D_AGNDRC
<19> CD_AGND R465
C617 .1UF_0402 DGND AGND
R468
2 1
6.8K_0402
8
Title
401212
Custom
A B C D E F G H I J
A B C D E F G H I J
New update
Layout note:
5/24 JOHNNY
1 Trace width=15 mils. 1
L33 1.SPK_R+,SPK_L+,SPKF_R+,SPKF_L+
+5V_AMP 1 2 VDDA
BLM21A05_0805 2.INTSPK_R+/-,INTSPK_L+/-
3
S
C389 3.LINEOUT_L,LINEOUT_R
W=40mils .1UF_0402 EC_MUTEO 2
G
Q34
2N7002
D
15 mils trace
1
+ C386 JP4
C384 INTSPK_R+ 1
U59 100UF_10V_D2 INTSPK_R- 1
1 R456
13
18
2 +12VALW 2
2
3
8
1000PF_0402 100K_0402
R-SPK CONN.
VDD1
VDD2
VDD3
VDD4
2
G
Q35 Q57
G
2 2N7002 2N7002 JP1 2
R455 12 SPK_R+ 3 1 SPKF_R+ 1 3 INTSPK_R+ INTSPK_L+ 1
RIGHT 1 RIGHT_R ROUT+ INTSPK_L- 1
D
2 17 2
S
<21,35> RIGHT RLINEIN 2
0_0402 19 INTSPK_R- L-SPK CONN
ROUT-
1
C42 C45 C44 C43
R313 Q58 2N7002
D
LEFT LEFT_R SPK_L+ SPKF_L+ INTSPK_L+ @220PF_0402
S
1 2 15 2 3 1 1 3
2
<21,35> LEFT LLINEIN LOUT+
0_0402 Q59
1
2N7002 @220PF_0402 @220PF_0402
G
9
G
2
2
R312 R453 LOUT- @220PF_0402
INTSPK_L-
@100K_0402 @100K_0402
2
+ DIS_ADJVOL <30>
C382
3 3
10UF_16V_1206 +5VALW
LINE_OUT_PLUG R461 16V
4 HPS R_UP/DOWN# 6 1 2
1K_0402
5
U61
R458 7
L_UP/DOWN#
+5VALW 1 2 4 2 ADJVOL_UP/DW# <31>
100K_0402
GAINSEL 14
3
R459 74AHCT1G125GW
R317
GND1
GND2
GND3
GND4
EC_MUTEO 1 2 5 16 1 2
<31,33,35> EC_MUTEO MODE SVR +5V_AMP
100K_0402
100K_0402 30dB/20dB#
GAIN_SEL# <16> HEADPHONE OUT
1
1
10
11
20
1
R460 TDA8552TS C603 C604 Q37 D
4 2 LINE_OUT_PLUG 4
100K_0402 .1UF_0402 2.2UF_16V_0805 2N7002 G
S
2
7
8
JP9
LINE_OUT_PLUG 5
4
C618 150UF_63V_D2
INTSPK_R+ LINEC_OUT_R LINECL_OUT_R
+
1 2 1 2 3
L58 BLM11A121S 6
INTSPK_L+ LINEC_OUT_L LINECL_OUT_L
+
1 2 1 2 2
L59 BLM11A121S 1
C638 150UF_63V_D2
1
LINE OUT
5 C639 C632
5
2
47PF_0402
47PF_0402
VDDA
6 R615 Q75 6
1
9.09K_1%_0603 2SC2411K
VDDA 1 2 2
MIC_PWR
VDDA L84 1 2
3
1 2 R616
+AUD_VREF
@0_0603
EXT. MIC
1
@0_0805
8
1
U72A R605 C734
3 + @TDA1308 @100_0402
+AUD_VREF
1 1 2
2
MIC_PWR
1
2 - 1UF_10V_0603
2
1
C719 C720 R617 R618 R619

1
7
8
C721 C722 100K_1%_0402 JP10
4
@1UF 2.2K_0402 @2.2K_0402 5

2
@4.7UF_10V_0805 @.1UF_0402
2
2
7 @.1UF_0402 4 7
VDDA
U72B L64 BLM11A121S 3
@TDA1308 INT_MIC 1 2 INT_MICL 6
<15> INT_MIC
8
MIC_IN 1 2 EXT_MICL 2
C723 + 5 L61 BLM11A121S 1
M ICIN 1 2 AFOPMIC_IN 7 C724
<21> MICIN R608
1
- 6 BFOPMIC_IN 1 2 BFOPRMIC_IN 1 2 MIC_IN C654 C664
1UF EXT. MIC
@10K_1%
@.22UF 47PF_0402 47PF_0402
4
2
1 2
R609 @18K_1%
1 2
8 C725 @15PF_NPO_0402
Title
R610
1 2
0_0402 R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 2B
401212
Custom
A B C D E F G H I J
A B C D E F G H I J
S1_VCC
1
C481 C503
8 .1UF_0402 .1UF_0402 3V_CB 8
2
3V_CB
R_OZ
1
1 2 +3VS C504 C499 C517 C524 C525 C509 C496
3V_CB R393 0_1206
.1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402
2
R_TI/ENE
3V_CB 1 2 +3V
R396 @0_1206
2
C472 C482
R566
4.7UF_10V_0805 .1UF_0402 Stuff R_OZ for OZ6912.
6912@0_0402
Stuff R_TI/ENE for TI/ENE CB1410.
1
7 7
+3V
<24> VPPD0
C522
<24> VPPD1
<24> VCCD0# 1 2
<24> VCCD1#
.1UF_0402
126
138
122
102
74
73
72
71
44
18
90
86
50
30
14
63
U47
VCCI
VCCD1#
VCCD0#
VPPD1
VPPD0
VCCP
VCCP
VCCCB
VCCCB
VCCP
VCCP
VCC
VCC
VCC
VCC
VCC
AD [0..31]
<16,25,26,34> AD[0..31]
AD0 57 144 S1_D10

6 AD1 AD0 CAD31/D10 S1_D9 6
56 AD1 CAD30/D9 142
AD2 55 141 S1_D1 S1_A[0..25]
AD3 AD2 CAD29/D1 S1_D8 S1_A[0..25] <24>
54 AD3 CAD28/D8 140
AD4 53 139 S1_D0
AD5 AD4 CAD27/D0 S1_A0 S1_D[0..15]
52 AD5 CAD26/A0 129 S1_D[0..15] <24>
AD6 51 128 S1_A1
AD7 AD6 CAD25/A1 S1_A2
49 AD7 CAD24/A2 127
AD8 47 124 S1_A3 S1_A23 1 2
AD9 AD8 CAD23/A3 S1_A4 R412 22K_0402 S1_VCC
46 AD9 CAD22/A4 121
AD10 45 120 S1_A5 S1_WP 1 2
AD11 AD10 CAD21/A5 S1_A6 R410 @22K_0402 S1_VCC
43 AD11 CAD20/A6 118
AD12 41 116 S1_A25
AD13 AD12 CAD19/A25 S1_A7
40 AD13 CAD18/A7 115
AD14 39 113 S1_A24
AD15 AD14 CAD17/A24 S1_A17
38 98
AD16 AD15 CAD16/A17 S1_IOWR#
26 96 S1_IOWR# <24>
5 AD17 25
AD16 CAD15/IOWR#
97 S1_A9 5
AD18 AD17 CAD14/A9 S1_IORD#
24 93 S1_IORD# <24>
AD19 AD18 CAD13/IORD# S1_A11
23 95
AD20 AD19 CAD12/A11 S1_OE#
19 92 S1_OE# <24>
AD21 AD20 CAD11/OE# S1_CE2#
17 91 S1_CE2# <24>
AD22 AD21 CAD10/CE2# S1_A10 S1_OE# R206 1
16 89 2 S1_VCC
AD23 AD22 CAD9/A10 S1_D15
15 87 @47K_0402
AD24 AD23 CAD8/D15 S1_D7
11
AD24 CAD7/D7
85 Stuff this resistor
AD25 10 82 S1_D13
AD26
AD27
9
8
AD25
AD26 PCI1410 CAD6/D13
CAD5/D6
83
80
S1_D6
S1_D12
for ENE CB1410 only.
7 81
5 77
4 79
3 76
AD31 CAD0/D3
4 S1_REG# 4
<16,25,26,34> C/BE#0 48 125 S1_REG# <24>
C/BE0# CCBE3#/REG# S1_A12
<16,25,26,34> C/BE#1 37 112
C/BE1# CCBE2#/A12 S1_A8
<16,25,26,34> C/BE#2 27 99
C/BE2# CCBE1#/A8 S1_CE1#
<16,25,26,34> C/BE#3 12 88 S1_CE1# <24>
C/BE3# CCBE0#/CE1#
PCIRST# 20 119 S1_RST
<5,8,15,16,19,25,26,28,34> PCIRST# PCIRST# CRST#/RESET S1_A23 S1_RST <24>
<16,18,25,26,34> FRAME# 28 111
PCIFRAME# CFRAME#/A23 S1_A15
<16,18,25,26,34> IR D Y# 29 110
PCIIRDY# CIRDY#/A15 S1_A22
<16,18,25,26,34> TRDY# 31 109
PCITRDY# CTRDY#/A22 S1_A21
<16,18,25,26,34> DEVSEL# 32 107
PCIDEVSEL# CDEVSEL#/A21 S1_A20
<16,18,25,26,34> STOP# 33 105
PCISTOP# CSTOP#/A20 S1_A14
<16,18,25,34> PERR# 34 104
PCM_RI# PCIPERR# CPERR#/A14 S1_WAIT#
+3V 1 2 <16,18,25,34> SERR# 35 133 S1_WAIT# <24>
R174 22K_0402 PCISERR# CSERR#/WAIT# S1_A13
<16,18,25,26,34> PAR 36 101
PCIPAR CPAR/A13 S1_INPACK#
<16,18> REQ#2 1 123 S1_INPACK# <24>
PCIREQ# CREQ#/INPACK# S1_WE#
3 +3V 1 2 New update <16,18> GNT#2 2
PCIGNT# CGNT#/WE#
106 S1_WE# <24> 3
R392 10K_0402 5/16 JOHNNY CLK_PCI_PCM 21 108 1 2 S1_A16
<14> CLK_PCI_PCM PCIPCLK CCCLK/A16 R362 33_0402
D39 <31> PCM_PME# 1 2 59 135 S1_BVD1
RI_OUT#/PME# CSTSCHNG/BVD1 S1_BVD1 <24>
1 2 1 2 R391 0_0402 70 136 S1_WP
<30> PCM_SUSP# SUSPEND# CCLKRUN#/WP S1_WP <24>
R568 6912@0_0402
RB751V AD20 1 2 13 103 S1_A19
R367 100_0402 IDSEL CBLOCK#/A19
1 2
+3VALW R261 10K_0402 S1_RDY#
<15,16,18,25,26> PIRQA# 60 132 S1_RDY# <24>
MF0 CINT#/READY
61
PCM_RI# 1 MF1 PCM_SPK#
<29> PCM_RI# 2 64 62 PCM_SPK# <21>
R5706912@0_0402 MF2 SPKROUT S1_BVD2
<16,18,27,28,30> SIRQ 65 134 S1_BVD2 <24>
MF3 CAUDIO#/BVD2
<16,18> PLOCK# 1 2 67
R571 6912@0_0402 MF4 S1_CD2#
68 137 S1_CD2# <24>
MF5 CCD2#/CD2#
RSVD/D14
RSVD/A18
CLK_PCI_PCM 69 75 S1_CD1#
RSVD/D2
<16,18,25,28,30,34> PM_CLKRUN# MF6 CCD1#/CD1# S1_VS2 S1_CD1# <24>

117 S1_VS2 <24>
CVS2/VS2#
1
2 66 131 S1_VS1 2
GND
GND
GND
GND
GND
GND
GND
GND
G_RST# CVS1/VS1# S1_VS1 <24>

R373 <15,24,25,30> G_RST#
@10_0402
6
22
42
58
78
94
114
130
84
100
143
1 2
C510 S1_D2
S1_A18
@15PF_0402 S1_D14
2
1
Title
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 401212 2B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Custom
A B C D E F G H I J
A B C D E F G H I J
1 1
PCMCIA Power Controller

+12VALW S1_VCC
U51
1
C547 6912@TPS2211 C536
13
.1UF_0402 VCC 4.7UF_10V_0805
12
2
VCC
9 11
12V VCC S1_VPP
2 2
+5VALW
10 C541 JP21AS1
VPP
C539 5 .1UF_0402
5V
6 5V
.1UF_0402
VCCD0 1 VCCD0# <23>
VCCD1 2 VCCD1# <23> CARDBUS HOUSING
+3VALW 15
VPPD0 VPPD0 <23>
VPPD1 14 VPPD1 <23>
CardBus Socket
3 3.3V
4 3.3V OC 8
SHDN
C535 GND S1_A[0..25]
3 <23> S1_A[0..25] S1_D[0..15] C191 3
.1UF_0402 <23> S1_D[0..15]
1 2
7
16
JP21 1000PF_0402
1 1 2 2
G_RST# S1_D3 3 4 S1_CD1#
G_RST# <15,23,25,30> S1_D4 3 4 S1_D11 S1_CD1# <23>
5 5 6 6
S1_D5 7 8 S1_D12
S1_D6 7 8 S1_D13
9 9 10 10
S1_D7 11 12 S1_D14
S1_CE1# 11 12 S1_D15
<23> S1_CE1# 13 13 14 14
S1_A10 15 16 S1_CE2#
S1_OE# 15 16 S1_VS1 S1_CE2# <23>
<23> S1_OE# 17 17 18 18
S1_A11 S1_IORD# S1_VS1 <23>
19 20
S1_A9 19 20 S1_IOWR# S1_IORD# <23>
21 22
4 S1_A8 23
21 22
24 S1_A17 S1_IOWR# <23> 4
S1_A13 23 24 S1_A18
25 26
S1_A14 25 26 S1_A19
27 28
S1_WE# 27 28 S1_A20
<23> S1_WE# 29 30
L24 S1_RDY# 29 30 S1_A21
<23> S1_RDY# 31 32
S1_VCCL 31 32 S1_VCCL
S1_VCC 1 2 33 34
FBM-11-160808-800LMT 33 34
S1_VPP 35 36 S1_VPP
35 36
1
C498 C506 S1_A16 37 38 S1_A22
S1_A15 37 38 S1_A23
39 40
.1UF_0402 10UF_10V_1206 S1_A12 39 40 S1_A24
41 42
2
S1_A7 41 42 S1_A25
43 44
S1_A6 43 44 S1_VS2
45 46
S1_A5 45 46 S1_RST S1_VS2 <23>
47 48
S1_A4 47 48 S1_WAIT# S1_RST <23>
49 50
S1_A3 49 50 S1_INPACK# S1_WAIT# <23>
51 52
S1_A2 51 52 S1_REG# S1_INPACK# <23>
5 53 54 5
S1_A1 53 54 S1_BVD2 S1_REG# <23>
55 56
S1_A0 55 56 S1_BVD1 S1_BVD2 <23>
57 58
S1_D0 57 58 S1_D8 S1_BVD1 <23>
59 60
S1_D1 59 60 S1_D9
61 62
S1_D2 61 62 S1_D10
63 64
S1_WP 63 64 S1_CD2#
<23> S1_WP 65 66
65 66 S1_CD2# <23>
67 68
67 68
69 70
GND GND
1
71 72 C91
GND GND
73 74
GND GND 1000PF_0402
75 76
2
GND GND
77 78
GND GND
79 80
GND GND
81 82
GND GND
83 84
GND GND
6 6
+3VALW +5VALW FOXCONN_1CA415M1-TA_68P

S1_VPP
1
C153
1
C528 C545 + C494

.01UF_0402
2
10UF_10V_1206 10UF_10V_1206 4.7UF_10V_0805

2
7 7
8
Title
401212
Custom
A B C D E F G H I J
10 9 8 7 6 5 4 3 2 1
H H
+3VALW R285
1394@100K_0402 R272
1394@100K_0402
1
1
1
R286 R291 R269
1394@100K_0402 1394@100K_0402 1394@100K_0402
2
2
2
20
35
48
62
78
87
86
96
10
11
U26 +3VALW
G L28 +3VALW G
TEST17
TEST16
VDDP
VDDP
VDDP
VDDP
VDDP
CYCLEOUT
CNA
CYCLEIN
<16,23,26,34> AD[0..31] 15 1 2 1394@.1UF_0402
AD31 DVDD 1394@0_0805 1394@.1UF_0402
22 PCI_AD31 DVDD 27
AD30 24 39 1394@.1UF_0402
AD29 PCI_AD30 DVDD
25 PCI_AD29 DVDD 51
1
AD28 26 59 VPLL_1394 C296 C289 C297 C301
AD27 PCI_AD28 DVDD
28 PCI_AD27 DVDD 72
AD26 29 88 1394@.1UF_0402
2
PCI_AD26 DVDD
1
AD25 31 100 C288
PCI_AD25 DVDD
1
AD24 32 7 C292 1394@.1UF_0402
AD23 37
PCI_AD24
TSB43AB22 PLLVDD
1 1394@4.7UF_10V_0805 1394@.1UF_0402
2
AD22 PCI_AD23 AVDD 1394@.01UF_0402 1394@.1UF_0402
38 2
2
AD21 PCI_AD22 AVDD
40 PCI_AD21 AVDD 107
1
AD20 41 108 C349 C350 C351 C353
AD19 PCI_AD20 AVDD
42 PCI_AD19 AVDD 120
AD18 43 1394@.1UF_0402
2
F PCI_AD18 F
AD17 45 PCI_AD17
PCI BUS INTERFACE
CLK_PCI_1394 AD16 46 106 R283 1 2 1394@1K_0402
AD15 PCI_AD16 CPS 1394@1000PF_0402
61 PCI_AD15
AD14 63 1394@1000PF_0402
PCI_AD14
1
AD13 65 125 C298 1 2 1394@.1UF_0402

PCI_AD13 PHY PORT 2 TPBIAS1
1
R270 AD12 66 124 C359 C362 C360
AD11 PCI_AD12 TPA1+
67 PCI_AD11 TPA1- 123
@10_0402 AD10 69 122 R273 1 2 1394@1K_0402 1394@1000PF_0402
2
AD9 PCI_AD10 TPB1+ R274 1
70 121 2 1394@1K_0402
1 2
AD8 PCI_AD9 TPB1-

71 PCI_AD8
C291 AD7 74 118 1 R276 2
AD6 PCI_AD7 BIAS CURRENT R0
76 1394@6.34K_1%_0402 1394@1000PF_0402
@15PF_0402 AD5 PCI_AD6
77
2
PCI_AD5
1
AD4 79 C356 C302
AD3 PCI_AD4
80
PCI_AD3 Near 1394 IC
AD2 81 119 1394@1000PF_0402
2
E AD1 82
PCI_AD2 R1 C293 1 2 1394@15PF_0402
E
AD0 PCI_AD1
84 OSCILLATOR 6
PCI_AD0 X0
<16,23,26,34> C/BE#3 34
PCI_C/BE3 X2
<16,23,26,34> C/BE#2 47 PCI_C/BE2
<16,23,26,34> C/BE#1 60 PCI_C/BE1
73 5 1394@24.576MHz
<16,23,26,34> C/BE#0 CLK_PCI_1394 PCI_C/BE0 X1
16 C294 1 2 1394@15PF_0402
<14> CLK_PCI_1394 PCI_CLK
<16,18> GNT#0 18
PCI_GNT C295 1
<16,18> REQ#0 19 FILTER 3 2 1394@.1UF_0402
PCI_REQ FILTER0
1
AD16 R275 1 2 1394@100_0402 36
PCI_IDSEL
1
49 4 R278 R279 C303
<16,18,23,26,34> FRAME# PCI_FRAME FILTER1
<16,18,23,26,34> IR DY# 50
PCI_IRDY SDA_1395 R290 1
52 EEPROM 2 WIRE BUS SDA 92 2 1394@220_0402 1394@56.2_1% 1394@56.2_1% 1394@1UF_25V_0805
2
<16,18,23,26,34> TRDY# PCI_TRDY
53
2
<16,18,23,26,34> DEVSEL# PCI_DEVSEL
54 91 SCL_1394 R289 1 2 1394@220_0402
<16,18,23,26,34> STOP# PCI_STOP SCL
56 XTPBIAS0 JP30
D <16,18,23,34> PERR# PCI_PERR D
13 POWER CLASS 99 XTPA0+ L72 1 21394@0_0603 PA0+_C
<15,16,18,23,26> PIRQA# PCI_INTA PC0 4
21 98 XTPA0- L71 1 21394@0_0603 PA0-_C
<31> 1394_PME# PCI_PME PC1 XTPB0+ PB0+_C 3
57 97 L70 1 21394@0_0603
<16,18,23,34> SERR# PCI_SERR PC2 2
58 XTPB0- L69 1 21394@0_0603 PB0-_C
<16,18,23,26,34> PAR PCI_PAR XTPBIAS0 1
<16,18,23,28,30,34> PM_CLKRUN# 12 PCI_CLKRUN PHY PORT 1 TPBIAS0
116
85 115 XTPA0+
<5,8,15,16,19,23,26,28,34> PCIRST# PCI_RST TPA0+
1
114 XTPA0- 1394@1394_CONN 4PIN
TPA0- XTPB0+ R281 R280
113
TPB0 + XTPB0-
112
TPB0 - 1394@56.2_1% 1394@56.2_1%
2
94
TEST9
95
TEST8
1
<15,23,24,30> G_RST# 14 G_RST
1
1394@220_0402 101 C354 R284
TEST3
REG_EN#
2 1 89 102
PLLGND1
C GPIO3 TEST2 C
R287 2 1 90 104 1394@220PF_0402 1394@5.11K_1%
REG18
REG18
2
GPIO2 TEST1
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
R288 105
2
1394@220_0402 TEST0
9
30
93
109
110
111
117
126
127
128
17
23
33
44
55
64
68
75
83
103
1
C290 C361
1394@.1UF_0402 1394@.1UF_0402
2
B B
A
Title
401212
Custom
10 9 8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
+3VS +2.5VS +3V_USB20
H C688 H
1
+3V_USB20
USB20@.1UF_0402
2
101
110
120
128
115
OVCUR#0
10
18
26
34
44
52
62
35
53
70
2 1
U66
4
R628 USB20@100K_0402 L73
2 1 OVCUR#1 USB20@0_0603
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC25
VCC25
VCC25
VCC25
VSUS
R629 USB20@100K_0402 1 2
<16,23,25,34> AD[0..31]
1 2 USB0D- <32>
AD31 116 85 USB20P1-
AD30 AD31 USBP1- USB20P1+ L74
117
AD30 USBP1+
86 4 3 @DLW21SN900SQ2 USB0D+ <32>
AD29 118
AD28 AD29
121 81 1 2
G AD27 AD28 USBP2- USB20@0_0603 G
122 82
AD26 AD27 USBP2+ L75
123
AD25 AD26 USB20P3-
124 AD25 USBP3- 77
AD24 125 78 USB20P3+
AD23 AD24 USBP3+ L76
126 AD23
AD22 1 73 USB20@0_0603
AD21 AD22 USBP4-
2 AD21 USBP4+ 74 1 2
AD20 7 +3V_USB20
AD19 AD20 OVCUR#0
8 AD19 -USBOC0 71 OVCUR#0 <17> 1 2 USB1D- <32>
AD18 11 68 OVCUR#1 L78
AD17 AD18 -USBOC1 OVCUR#1 <17>
12 USB20@BLM21A601SPT_0805 L77 4 3 @DLW21SN900SQ2
CLK_PCI_USB20 AD16 AD17 USB1D+ <32>
13 AD16 VCCUSB 84 1 2 +3V
AD15 14 80 1 2
AD14 AD15 VCCUSB USB20@0_0603
15 AD14 VCCUSB 76 1 2 +3VS
1
AD13 16 72 L80 L79

R552 AD12 AD13 VCCUSB @BLM21A601SPT_0805
29 AD12
F AD11 30 88 R553 1 2 R554 1 2 F
@10_0402 AD10 AD11 REXT
31 AD10
AD9 32 87 USB20@2.2K_0603_1% USB20@3.92K_0603_1%
1 2
AD8 AD9 GNDUSB U67

37 AD8 GNDUSB 83
C689 AD7 38 79
AD6 AD7 GNDUSB +2.5VS_USB20 OVCUR#0
39 AD6 GNDUSB 75 1 GND OC1# 8
@15PF_0402 AD5 40 2 7
2
AD4 AD5 +5V IN OUT1 USB_VCCA

42 89 1 2 +2.5VS 3 6
AD4 VCCPLLA EN1# OUT2 OVCUR#1 USB_VCCB
1
AD3 45 96 4 5
AD2 AD3 VCCOSC L81 R663 EN2# OC2#
46 AD2 VCCPLL 91
AD1 47 USB20@BLM21A601SPT_0805
AD0 AD1 USB20@100K_0402 TPS2042
48 AD0 GNDPLLA 90
93
1 2
GNDOSC
<16,23,25,34> C/BE#3 3 -CBE3 GNDPLL 92
R662 D
<16,23,25,34> C/BE#2 19
-CBE2
1
28 60 2 1 2 Q87
E <16,23,25,34> C/BE#1 -CBE1 NC <36> SUSON E
1
41 63 G C755 R664
<16,23,25,34> C/BE#0 -CBE0 NC
97 USB20@3M_0402 S USB20@2N7002
3
NC
1
CLK_PCI_USB20 109 103 R555 USB20@4.7K_0402 New update
USB11@0_0402
2
<14> CLK_PCI_USB20 PCICLK NC
104 1 2 C748 USB20@.1UF_0402 5/16 JOHNNY
New update 5/16 JOHNNY
2
NC +3V_USB20
112 102
2
<16,18> GNT#3 -GNT NC
113 R557 @4.7K_0402 USB20@.22UF_0603
AD27 <16,18> REQ#3 -REQ
R556 1 2 USB20@100_0402 6 98 1 2
IDSEL WAKEUP_EN
<16,18,23,25,34> FRAME# 20 49
-FRAME EECS
<16,18,23,25,34> IR D Y# 21
-IRDY EESK
50 R620 USB20@4.7K_0402 Close to USB Port
<16,18,23,25,34> TRDY# 22 55 1 2
-TRDY EEDO
<16,18,23,25,34> DEVSEL# 23 56
-DEVSEL EEDI
<16,18,23,25,34> STOP# 24
-STOP USB20ATPGEN USB20TEST1 RP138 USB20@8P4R_4.7K
<16,18,23,25,34> PAR 27 65 4 5
PAR ATPGEN USB20TESTMODE USB20TEST2
66 3 6
TESTMODE USB20TEST1 USB20ATPGEN
D <15,16,18,23,25> PIRQA# 105 57 2 7 D
-INTA TEST1 USB20TEST2 USB20TESTMODE
<16,18> PIRQB# 106 58 1 8
-INTB TEST2 R558 1 USB20@4.7K_0402
<16,18,34> PIRQC# 107 59 2
-INTC TEST3 R559 1 USB20@4.7K_0402
99 2
TEST4
111
<5,8,15,16,19,23,25,28,34> PCIRST# PCIRST USB20XIN
94
XIN
67
GNDSUS
<31> USB20_PME# -PME USB20XOUT X5

64 95
<16> USB20_SMI# -SMI XOUT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
USB20@24MHz
5
9
17
25
33
36
43
51
54
61
100
108
119
114
127
69
2
USB20@VT6202 C690 C691
1
C C
USB20@20PF_0603 USB20@20PF_0603
+3VS +2.5VS +3V_USB20 +2.5VS_USB20

B C693 C695 C697 C699 C701 C703 C705 C707 C709 B
USB20@.1UF_0402 USB20@.1UF_0402 USB20@.1UF_0402 USB20@.1UF_0402 USB20@.1UF_0402 USB20@.1UF_0402 USB20@.1UF_0402 USB20@.1UF_0402 USB20@.1UF_0402
1
1
2
2
C692 C694 C696 C698 C700 C702 C704 C706 C708 C710
USB20@.01UF_0402 USB20@.01UF_0402 USB20@.01UF_0402 USB20@.01UF_0402 USB20@.01UF_0402 USB20@.01UF_0402 USB20@.1UF_0402 USB20@.1UF_0402 USB20@.1UF_0402 USB20@.1UF_0402
A
Title
401212
Custom
10 9 8 7 6 5 4 3 2 1
5 4 3 2 1
New add 5/3 JOHNNY
+3VS MSLED
MSPWCTL#
MSCLK
MS1
MS2
WR_PT MS3
1
C207 C197 SDPWCTL# MS4
D D
SD@.1UF_0402 SD@10UF_10V_0805
36
35
34
33
32
31
30
29
28
27
26
25
U8
SDPWCTL#
SCC4
SCC8
MSPWCTL#
MS1
MS2
MS3
MS4
VSS
MSCLK
SDLED
MSLED
SD_CLK R137 1 2 SD@10_0402 37 24 MS5
SD1 SDCLK MS5 CLK_SD48
38 SD1 XIN 23
SD2 39 22 CLK_SD48 <14> CLK_SD48
SD2 XOUT
40 VDD3V SCRST# 21
+3VS
2
SD3 41 20
SD4 SD3 SCIO R141
42 SD4 SCCLK 19
SD5
LAD[0..3] LAD3
43
44
SD5 W83L518D (LPC) SCPSNT 18
17 @10_0402
<16,28,30> LAD[0..3] LAD2 LAD3 SCPWCTL#
45 16
1
LAD1 LAD2 SCLED
46 LAD1 VDD 15 +5VS
LAD0 47 14 C161
SD_CLK CLK_PCI_SD LAD0 SCBLED MMC_DET#
<16,18,23,28,30> SIRQ 48 SERIRQ SCBPWCTL# 13
1
C417 C418 @10PF_0402
2
1
R136 R175 SD@.1UF_0402 SD@10UF_10V_0805
2
R666
@10_0402 @10_0402 SD@4.7K_0402
RESERVED
SCBPSNT
SCBRST#
LFRAME#
1
2
SCBCLK
PCICLK
lESET#
SCBC4
SCBC8
SCBIO
PME#
C C156 C181 +5VS C
VSS
+5VS
@10PF_0402 @15PF_0402
1
SD@W83L518D (LPC)
1
2
3
4
5
6
7
8
9
10
11
12
5
U76
WR_PT 2 R654
CLK_PCI_SD 4 MEDIALED MLED@10K_0402
<14> CLK_PCI_SD
MSLED 1
2
<16,28,30> LFRAME#
<28,30> LPC_RST# MEDIA_LED# <15>
MLED@7SH32FU
3
R645
1
+3VS D
MLED@10K_0402 R646 MEDIALED 2 Q79
G MLED@2N7002
1
R549 MLED@10K_0402 S
3
8
7
6
5
1
SD@10K_0402 R138
2
RP5
SD@4.7K_0402
SD@8P4R_4.7K_0804
2
499_1% change to 4.7K New add 5/3 JOHNNY
1
2
3
4
2
2002/4/16 Johnny
+3VS JP6
MMC_DET# 10 11
MMC_DET# Wr_Pt_Vss
1
SD4 8
+3VS SD_3VCC SD3 SD4
7 12
R122 U7 SD3 Vss3 R631 SD@1K_0402
6 13
SD@10K_0402 SD_CLK Vss2 Vss4 WR_P WR_PT
5 14 1 2
SDCLK Wr_Pt
3 1 4
2
VIN VOUT Vdd Add 1K

4 5 3
B VIN/CE VOUT SD2 Vss1 2002/4/16 Johnny B
2
SD1 SD2 +3VS
2 1
GND SD1
1
D SD@RT9701-CB C148 SD5 9

SD5
1
SDPWCTL# 2 Q10 +3VS
G SD@2N7002 SDOR711@4.7UF_10V_0805 SDOR711@SD_SOCKET R578
2
S R149
3
1
MS@4.7K_0402
SD@1M +3VS MS_3VCC JP35
2
R579 U69 1
MS@10K_0402 MS1 GND
2
BS
3 1 3
2
VIN VOUT MS2 VCC
4 5 4
VIN/CE VOUT MS3 SDIO
5
MS4 RSVD
2 6
GND MS5 INS
7
RSVD
1
D MS@RT9701-CB C714 MSCLK 8
MSPWCTL# 2 Q66 SCLK
9
G MS@2N7002 MS@4.7UF_10V_0805 VCC
10
2
GND
1
S
3
R584 11
GND
12
GND
1
MS@200K_0402 C716 13
GND
14
2
MS@.1UF_0402 GND
2
MS@HRS_CB1EBB
A A
Title
401212
Custom
5 4 3 2 1
A B C D E F G H I J
1 1
BOARD ID
+3VS
SUPER I/O SMsC FDC47N227
1
R408 R407 R315
LAD[0..3] LPD[0..7]
<16,27,30> LAD[0..3] LPD[0..7] <29>
U48 @10K_0402 @10K_0402 @10K_0402
LAD0 20 68 LPD0
2
LAD1 LAD0 PD0/INDEX# LPD1
21 69
LAD2 LAD1 PD1/TRK0 LPD2
22 70
LAD3 LAD2 PD2/WRTPRT# LPD3
23 71
2 LAD3 PD3/RDATA# LPD4 2
72 BD_ID2 <31>
PD4/DSKCHG# LPD5
<16,27,30> LFRAME# 24 73 BD_ID1 <31>
LFRAME# PD5 LPD6
<16> LDRQ#1 25 LDRQ# PD6/MTR0# 74 BD_ID0 <31>
75 LPD7
LPC_RST# PD7
26 PCIRST#
27 79 LPTBUSY
<15,16> SUS_STAT# LPCPD# BUSY/MTR1# LPTBUSY <29>
1
78 LPTPE
PE/WDATA# LPTSLCT LPTPE <29> R409 R402 R316
+3VS 1 2 50 GPIO12/IO_SMI# SLCT/WGATE# 77 LPTSLCT <29>
R369 10K 1 2 17 81 LPTERR#
R386 10K IO_PME# ERROR#/HDSEL# LPTACK# LPTERR# <29> 10K_0402 10K_0402 10K_0402
<16,18,23,27,30> SIRQ 30 SIRQ ACK#/DS1# 80
LPTINIT# LPTACK# <29>
28 66
2
<16,18,23,25,30,34> PM_CLKRUN# CLK_PCI_SIO CLKRUN# INIT#/DIR# LPTAFD# LPTINIT# <29>
<14> CLK_PCI_SIO 29 PCICLK AUTOFD#/DRVDEN0# 82 LPTAFD# <29>
CLK_PCI_SIO 83 LPTSTB#
CLK_14M_SIO STROBE#/DS0# LPTSLCTIN# LPTSTB# <29>
<14> CLK_14M_SIO 19 CLK14 SLCTIN#/STEP# 67 LPTSLCTIN# <29>
2
R368 PID0 48 100

3 <15> PID0 GPIO10 DTR2# 3
PID1 54 99 CTS#2
<15> PID1 PID2 GPIO15 CTS2#
@10_0402 55 98
<15> PID2 PID3 GPIO16 RTS2# DSR#2
56 97 RP141 +3VS
2 1
<15> PID3 PID4 GPIO17 DSR2#

<15> PID4 57 GPIO20 TXD2 96 BD_ID2 BD_ID1 BD_ID0
C500 58 95 1 2 CTSA# 1 8
GPIO21 RXD2 DCD#2 R415 1K DSRA#
59 GPIO22 DCD2# 94 2 7 SST 0 0 0
@15PF_0402 6 92 R I#2 DCDA# 3 6
1
+3VS GPIO24 RI2# RIA#

32 GPIO30 4 5 PT 0 0 1
33 GPIO31 DTR1# 89
RP84 34 88 CTSA# New add 8P4R_4.7K ST 0 1 0
PID0 GPIO32 CTS1#
1 8 35 GPIO33 RTS1# 87 5/16 JOHNNY
2 7 PID1 36 86 DSRA# RP91 +3VS QT 0 1 1
PID2 GPIO34 DSR1#
3 6 37 GPIO35 TXD1 85
CLK_14M_SIO 4 5 PID3 38 84 RXDA CTS#2 1 8
GPIO36 RXD1 DCDA# DSR#2
39 91 2 7
GPIO37 DCD1#
2
1
8P4R-100K 40 90 RIA# DCD#2 3 6
4 R375 41
GPIO40 RI1# R633 R I#2 4 5
4
PID4 GPIO41 IRMODE
1 2 42 63 IRMODE <29>
@10_0402 R387 100K_0402 GPIO42 IRMODE/IRRX3 IRRX 1K_0402
43 61 IRRX <29> 8P4R_4.7K
GPIO43 IRRX2 IRTXOUT
44 62
2 1
2
GPIO44 IRTX2 IRTXOUT <29>
45 +5VS
C514 GPIO45 RDATA#
New add RP85
46 16 RDATA# <19>
GPIO46 RDATA# WDATA# 5/16 JOHNNY TRACK0#
47 10 WDATA# <19> 1 8
@15PF_0402 GPIO47 WDATA# WGATE# WP#
11 2 7
1
WGATE# HDSEL# WGATE# <19> INDEX#

1 2 51 12 HDSEL# <19> 3 6
R374 10K GPIO13/IRQIN1 HDSEL# FDD IR# DISKCHG#
52 8 FDDIR# <19> 4 5
GPIO14/IRQIN2 DIR# STEP#
1 2 64
GPIO23/FDC_PP STEP#
9 STEP# <19>
R388 10K 5 8P4R_1K
DS0# INDEX# DRV0# <15,19>
18 13 INDEX# <19>
+3VS VTR INDEX# DISKCHG#
4 DISKCHG# <19>
DSKCHG# WP# RP88
53 15 WP# <19>
VCC WRTPRT# TRACK0# HDSEL#
5 65 14 TRACK0# <19> 6 5 +5VS 5
VCC TRK0# MTR0# WGATE# STEP#
93 3 MTR0# <19> 7 4
VCC MTR0# 3MODE# WDATA# MTR0#
1 3MODE# <19> 8 3
DRVDEN0
1
C521 C534 C512 7 C518 FDD IR# 9 2 RDATA#

VSS DRV0#
31 2 2 1 +5VS +5VS 10 1
4.7UF_10V_0805 .1UF_0402 .1UF_0402 .1UF_0402 60 VSS DRVDEN1 R405 10K
2
10V VSS 10P8R_1K

76 49
VSS GPIO11/SYSOPT
1 2 +3VS
SMsC LPC47N227 R491 @10K_0402
1 2
R135 10K_0402
Base I/O Address

0 = 02Eh
6 * 1 = 04Eh 6
+3VS
2
.1UF_0402
C180 R303
1 2 10K_0402
U29
5 6 LPCRST
1
+3V VCC Y1
<5,8,15,16,19,23,25,26,34> PCIRST# 1
A1 LPC_RST#
4 1 2 LPC_RST# <27,30>
LPCRST 1 Y2
2 3
A2
7 2 D29 7
GND
1
R299 C372 RB751V
10K_0402 NC7WZ14
.1UF_0402
8
Title
401212
Custom
A B C D E F G H I J
A B C D E F G H I J
Touch Pad & Status LED Conn.

+5VS
JP7
1 1 1
1
2 2
<31> TPAD_ON/OFF# 3 3
<30> TPAD_LED# 4 4
5
<19> ACT_LED# 5
6
<31> PMLED_0#
<31> PMLED_1#
<31> BATLED_0#
7
8
6
7
8
Parallel Port
9 +5V_PRN
<31> BATLED_1# 9
+5VALW 10 +5V_PRN
10 LPD[0..7]
<30> TP_DATA 11
11 <28> LPD[0..7] D7
<30> TP_CLK 12
12
1
13 C39 C38 +5VS 2 1w=10mils
13
14
14
1
C583 C584 4.7UF_10V_0805 .1UF_0402
2
96212-1411S 1SS355 R5
2 22PF_0402 22PF_0402 2
2
R4 2.7K_0402
CP10 33_0402 C18
2
AFD/3M# 1 8 LPTSTB# 1 2 PWRPRN 1 2
ERR# <28> LPTSTB#
w=10mils
2 7
PRNINIT# 3 6 47PF_0402
+5V_PRN SLCTIN# 4 5
1
RP1 8P4C_220PF 1 2 AFD/3M# 14
FD0 CP3 <28> LPTAFD# LPD0 L47 68 FD0
1 10 1 2 2
FD1 2 9 FD7 ACK# 1 8 L46 1 2 68 ERR# 15
FD2 FD6 BUSY <28> LPTERR# LPD1 L45 68 FD1
3 8 2 7 1 2 3
3
FD3 4 7 FD5 PE 3 6 L44 1 2 68 PRNINIT# 16
<28> LPTINIT#
1
Q72 5 6 FD4 SLCT 4 5 LPD2 L43 1 2 68 FD2 4 JP15
@SM05 C726 C727 +5V_PRN L42 68 SLCTIN#
<28> LPTSLCTIN# 1 2 17
10P8R_2.7K 8P4C_220PF LPD3 L41 1 2 68 FD3 5 LPTCN-25-SUYIN
2
3 L40 68 18 3
220PF_0402 220PF_0402 LPD4 1 2 FD4 6
1
CP11 L39 68 19
FD0 1 8 LPD5 1 2 FD5 7
L85 FBM-11-160808-121 FD1 2 7 L38 68 20
PS2_CLK 1 2 FD2 3 6 LPD6 1 2 FD6 8
<30> PS2_CLK FD3
L86 FBM-11-160808-121 4 5 L37 68 21
PS2_DATA 1 2 LPD7 1 2 FD7 9
<30> PS2_DATA +5V_PRN 8P4C_220PF L13 68 22
RP2 1 2 ACK# 10
SLCTIN# CP12 <28> LPTACK# L16 68
1 10 23
+5VS PS2KB_VCC KB_AS PRNINIT# 2 9 ACK# FD4 1 8 1 2 BUSY 11
ERR# BUSY FD5 <28> LPTBUSY
F2 W=40mils JP17 3 8 2 7 L15 68 24
W=40mils 1 2 AFD/3M# 4 7 PE FD6 3 6 1 2 PE 12
L18 4 6 SLCT FD7 <28> LPTPE L14 68
5 6 4 5 25
2 +5V_PRN
1
POLYSWITCH_1.1A FBM-11-451616-800T C728 1 2 SLCT 13

4 4516 1 <28> LPTSLCT 4
C729 C730 10P8R_2.7K 8P4C_220PF L17 68
4.7UF_25V_0805 3 5
EXTFDD must connect
2
KBD/PS2_6
to docking.
1000PF_0402 220PF_0402 KBD-35136S
L87 FBM-11-160808-121
KBD_DATA 1 2
<30> KBD_DATA
L88 FBM-11-160808-121
KBD_CLK 1 2
<30> KBD_CLK
1
Q73
C731 C732
5 @SM05 5
2
220PF_0402 220PF_0402
3
+3VS
FIR Module +5VS
+3V
1
6 T = 40mil 6
R332 R490
1
+ C400 C670
1
C402 C403 FIR@10_1206 FIR@10_1206 FIR@.1UF_0402

R335
+ + FIR@10UF_10V_1206
2
FIR@10UF_10V_1206 2 FIR@22UF_10V_1206
2
100K_0402
T = 40mil +5VS_IR
2
U64
D34 1
LED_A
<23> PCM_RI# 1 2 2
LED_C TXD
3 T = 12mil IRTXOUT IRTXOUT <28>
C404 4
RXD SD
5 T = 12mil IRMODE IRMODE <28>
RB751V FIR@.1UF_0402 6
VCC MODE
7 T = 12mil IRRX IRRX <28>
D35 8
GND
<34> MD_RI# 1 2
FIR@TFDU6101E
7 RB751V 7
<30> RING#
8
Title
401212
Custom
A B C D E F G H I J
A B C D E
.1UF_0402 EC_AVCC
+3VALW +3VALW EC_3VDD +RTCVCC
+3VS 1 2
2
C368 C355 C300 C280 R268 0_0402 C277
123
136
157
166
161
.1UF_0402 1000PF_0402 C299 C304 1UF_0603 C366 @.01UF_0402
16
34
45
95
2
1
U24 ADI_P 1 2 ECAGND
22UF_10V_1206 22UF_10V_1206 .1UF_0402
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VBAT
VDD
AVCC
2
2
C364 .01UF_0402 C365 .01UF_0402
L31 BATT_TEMPA BATT_TEMPB
+3VALW 1 2 EC_AVCC 1 2 2 1
BLM11A20
1
C358 C357 7 81 BATT_TEMPA
<16,18,23,27,28> SIRQ SERIRQ AD0 BATT_TEMPA <39>
8 82 BATT_TEMPB
1 LDRQ AD1 BATT_TEMPB <39> 1
L29 .1UF_0402 1000PF_0402 9 83 R51910K_0402
2
ECAGND <16,27,28> LFRAME# LAD0 LFRAME AD2 ADI_PR PROCHOT# <5>
1 2 15
LAD0 AD3
84 2 1 ADI_P ADI_P <38>
BLM11A20 LAD[0..3] LAD1 14 Host interface 87
<16,27,28> LAD[0..3] LAD1 IOPE0AD4 ALI/NIMH# <39>
2
LAD2 13 88 C677
LAD3 LAD2 IOPE1/AD5 VOL_IN_UP# BLI/NIMH# <39>
10 89 VOL_IN_UP# <33>
CLK_PCI_LPC LAD3 AD Input IOPE2/AD6 VOL_IN_DN#
18 90 I/O Address
1
<14> CLK_PCI_LPC LCLK IOPE3/AD7 VOL_IN_DN# <33>
<33> EC_RST# 19
LREST1 DP/AD8
93 .22UF_0603 BADDR1-0 Index Data
22 94 0 0 2E 2F
SMI DN/AD9 0 1 4E 4F
23 PWUREQ
99 DAC_BRIG <15> * 1 0 (HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
DA0 1 1 Reserved
100 EN_FAN1 <6>
EC_SCI# DA output DA1
<16> EC_SCI# 31 IOPD3/ECSCI DA2 101 EN_FAN2 <6>
DA3 102 IREF <38>
ENV0 ENV1 TRIS
RB751V 5 32
GA20/IOPB5 IOPA0/PWM0 INVT_PWM <15>
GATEA20 2 1 6 33 IRE 0 0 0
<16> GATEA20 KBRST/IOPB6 IOPA1/PWM1 BEEP# <21>
IOPA2/PWM2 36 M_SEN# <15,31>
D25 KSI[0..7] PWM OBD 0 1 0
RB751V
<15,33> KSI[0..7] KSO[0..15] KSI0 71 or PORTA IOPA3/PWM3 37
38
ACOFF <38> *
<33> KSO[0..15] KBSIN0 IOPA4/PWM4 VLBA# <16>
KBRST# 2 1 KSI1 72 39 DEV 1 0 0
<16> KBRST# KBSIN1 IOPA5/PWM5 EC_ON <33>
KSI2 73 40
KSI3 KBSIN2 IOPA6/PWM6 LID_OUT# <16>
D26 74 KBSIN3 IOPA7/PWM7 43 CONA# <31>
PROG 1 1 0
KSI4 77
CLK_PCI_LPC KSI5 KBSIN4 KSO16
78 KBSIN5 IOPB0/URXD 153 KSO16 <15>
KSI6 79 154 KSO17 SHBM=1: Enable shared memory with host BIOS
KBSIN6 IOPB1/UTXD
1
RP35 KSI7 80 Key matrix scan 162 MAIL_LED# TRIS=1: While in IRE and OBD, float all the
KBD_DATA KBSIN7 IOPB2/USCLK EC_SMC1 MAIL_LED# <15>
10 1 R277 163 signals for clip-on ISE use
+5VS KBD_CLK KSO0 PORTB IOPB3/SCL1 EC_SMD1 EC_SMC1 <15,31,39>
9 2 49 KBSOUT0 IOPB4/SDA1 164 EC_SMD1 <15,31,39> EEROM/BATTERY
8 3 PS2_DATA @10_0402 KSO1 50 165 LPC_RST#
KBSOUT1 IOPB7/RING/PFAIL/LRESET2 LPC_RST# <27,28> +3VALW
TP_CLK 7 4 PS2_CLK KSO2 51
1 2
TP_DATA KSO3 KBSOUT2
6 5 +5VS 52 KBSOUT3 IOPC0 168 PBTN_OUT# <16>
C348 KSO4 53 169 EC_SMC2 KBA0 (ENV0) R239 @10K_0402
2 KSO5 KBSOUT4 IOPC1/SCL2 EC_SMD2 EC_SMC2 <5,39> 2
10P8R_10K 56 KBSOUT5 IOPC2/SDA2 170 EC_SMD2 <5,39> THERMAL/DOCKING
@15PF_0402 KSO6 57 171 KBA1 (ENV1) R267 10K_0402
2
+3VS KSO7 KBSOUT6 PORTC IOPC3/TA1 PME_EC# FAN_SPEED <6>

58 KBSOUT7 IOPC4/TB1/EXWINT22 172 PME_EC# <31> EC_THRM#
RP32 KSO8 59 175 1 2 KBA2 (BADDR0) R254 @10K_0402
KBRST# KSO9 KBSOUT8 IOPC5/TA2 EC_THRM# <16>
1 8 60 176 D24 RB751V
GATEA20 KSO10 KBSOUT9 IOPC6/TB2/EXWINT23 FAN_SPEED2 <6> KBA3
2 7 61 KBSOUT10 IOPC7/CLKOUT 1 WL_ON <32,34> (BADDR1) R252 10K_0402
3 6 EC_THRM# KSO11 64
KSO12 KBSOUT11 KBA4
4 5 65
KBSOUT12 IOPD0/RI1/EXWINT20
26 ACIN <17,37,40> (TRIS) R215 @10K_0402
KSO13 66 29
KSO14 KBSOUT13 PORTD-1 IOPD1/RI2/EXWINT21 RING# <29> KBA5
+3VALW
8P4R_10K_0804 67
KBSOUT14 IOPD2/EXWINT24/LRESET2
30 SLP_S3# <16> (SHBM) R251 10K_0402
KSO15 68
RP31 KBSOUT15 +5VALW
2 ON/OFF# <33>
FSEL# EC_TINIT# IOPE4/SWIN RP30
8 1 105 TINT IOPE5/EXWINT40
44 SLP_S5# <16>
7 2 SELIO# EC_TCK 106 PORTE 24 EC_MUTEI# EC_SMC1 8 1
FR D# EC_TDO TCK IOPE6/LPCPD/EXWIN45 EC_MUTEI# <33> EC_SMD1
6 3 107
TDO IOPE7/CLKRUN/EXWINT46 25 PM_CLKRUN# <16,18,23,25,28,34> 7 2
5 4 EC_SMI# EC_TDI 108 JTAG debug port EC_SMC2 6 3
EC_TMS TDI KBA0 AD B[0..7] EC_SMD2
109 124 ADB[0..7] <31> 5 4
8P4R_10K_0804 TMS IOPH0/A0/ENV0 KBA1
125
+3VALW KBD_CLK IOPH1/A1/ENV1 KBA2 KBA[0..19] 8P4R_10K_0804
<29> KBD_CLK 110 126 KBA[0..19] <31>
RP79 KBD_DATA PSCLK1/IOPF0 IOPH2/A2/BADDR0 KBA3
<29> KBD_DATA 111 127
VOL_IN_UP# PS2_CLK PSDAT1/IOPF1 IOPH3/A3/BADDR1 KBA4
8 1 <29> PS2_CLK 114 128
VOL_IN_DN# PS2_DATA PSCLK2/IOPF2 PORTH IOPH4/A4/TRIS KBA5
7 2 <29> PS2_DATA 115 131
EC_MUTEI# TP_CLK PSDAT2/IOPF3 PS2 interface IOPH5/A5/SHBM KBA6
6 3 <29> TP_CLK 116 132
TP_DATA PSCLK3/IOPF4 IOPH6/A6 KBA7
5 4 <29> TP_DATA 117 133
LID_SW# PSDAT3/IOPF5 IOPH7/A7
118
8P4R_10K_0804 <15,31> LID_SW# PSCLK4/IOPF6 ADB0
<22> DIS_ADJVOL 119 138
PSDAT4/IOPF7 IOPI0/D0 ADB1
139
IOPI1/D1 ADB2
140
R249 20M IOPI2/D2 ADB3
141
C R Y1 PORTI IOPI3/D3 ADB4
1 2 158 144
32KX1/32KCLKOUT IOPI4/D4 ADB5
145
R250 C R Y2 IOPI5/D5 ADB6
2 1 160 146
3 32KX2 IOPI6/D6 ADB7 3
120K_0402 147
IOPI7/D7
1
C279 32.768KHZ C278

X1 150 FR D#
PORTJ-1 IOPJ0/RD FWR# FRD# <31>
10PF_0402 10PF_0402 151
2
IOPJ1/WR0 FWR# <31>

152 SELIO#
SELIO SELIO# <31>
EC_SMI# 62 41
<16> EC_SMI# IOPJ2/BST0 IOPD4 SCROLLED# <15>
<34> EN_WOL# 63 42 NUMLED# <15>
IOPJ3/BST1 PORTD-2 IOPD5
<15,23,24,25> G_RST# 69 54 CAPSLED# <15>
IOPJ4/BST2 PORTJ-2 IOPD6
<16,18> ICH_SWI# 70 IOPJ5/PFS IOPD7
55 A/B#USE <39>
<29> TPAD_LED# 75
R401 IOPJ6/PLI KBA8 JP27
76 IOPJ7/BRKL_RSTO IOPK0/A8
143
<14,16> SLP_S1# KBA9
+3VS 2 1 142 1 +5VALW
IOPK1/A9 KBA10 1 EC_TINIT#
<36> SYSON 148 135 2
10K_0402 D18 IOPM0/D8 PORTK IOPK2/A10 KBA11 2 EC_TCK
<21,36,42> SUSP# 149 134 3
MMO_ON IOPM1/D9 IOPK3/A11 KBA12 3 EC_TDO
<36,43> VR_ON 2 1 155 130 4
IOPM2/D10 PORTM IOPK4/A12 KBA13 4 EC_TDI
<39> TRICKLE 156 129 5
RB751V IOPM3/D11 IOPK5/A13/BE0 KBA14 5 EC_TMS
<23> PCM_SUSP# 3 121 6
IOPM4/D12 IOPK6/A14/BE1 KBA15 6
<33> EC_RSMRST# 4 120 7
IOPM5/D13 IOPK7/A15/CBRD 7 KSO16
<15> ENABLT 27 8
IOPM6/D14 KBA16 8 KSO17
28 113 9
<15> BKOFF# IOPM7/D15 IOPL0/A16 KBA17 9 MAIL_LED#
112 10
FSEL# PORTL IOPL1/A17 KBA18 10
<31> FSEL# 173 SEL0 IOPL2/A18
104
174 103 KBA19
SEL1 IOPL3/A19 @96212-1011S
47 48 FSTCHG <39>
CLK IOPL4/WR1
AGND
GND1
GND2
GND3
GND4
GND5
GND6
GND7
NC10
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
PC87591VPC
17
35
46
122
159
167
137
96
11
12
20
21
85
86
91
92
97
98
4 4
L32
ECAGND 1 2
CHB1608U800
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1381
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Custom 401212
A B C D E
A B C D E
<30> ADB[0..7]
AD B[0..7]
INPUT
<30> KBA[0..19]
KBA[0..19] +3VALW
C601
OUTPUT
1 2
+5VALW
.1UF_0402 +3VALW C599
RP133
20
1 2
U56 S_TSR 1 8
EXTID0 2 18 ADB0 EXTID0 2 7 .1UF_0402
VCC
<19> EXTID0 1A1 1Y1
EXTID1 ADB1 EXTID1
20
<19> EXTID1 4 16 3 6
1 EXTID2 1A2 1Y2 ADB2 EXTID2 U58 1
<19> EXTID2 6 14 4 5
1A3 1Y3 ADB3 ADB0
8 12 3 2
VCC
<7> CPU_ECVID0 1A4 1Y4 ADB4 ADB1 D0 Q0 ADJVOL_UP/DW# <22>
11 9 8P4R_100K_0804 4 5
<7> CPU_ECVID1 2A1 2Y1 ADB5 ADB2 D1 Q1 BT_RST# <32,34>
<7> CPU_ECVID2 13 7 7 6 BT_DETACH <32,34>
2A2 2Y2 ADB6 RP80 +3VALW ADB3 D2 Q2
<7> CPU_ECVID3 15 5 8 9 BT_ON# <32,34>
2A3 2Y3 ADB7 CONA# C379 ADB4 D3 Q3
<7> CPU_ECVID4 17 3 <30> CONA# 1 8 13 12 PMLED_0# <29>
2A4 2Y4 BT_PRES# ADB5 D4 Q4
2 7 1 2 14 15 PMLED_1# <29>
U17A ADB6 D5 Q5
14
1 3 6 17 16
GND
1G 74LVC32 ADB7 D6 Q6 BATLED_0# <29>
19 4 5 .1UF_0402 18 19
+3VALW 2G <15,30> LID_SW# D7 Q7 BATLED_1# <29>
KBA2 1
74LVC244 8P4R-100K 3 11
GND
10
U17B SELIO# LARST# CLK
14
2 1 CLR
74LVC32
KBA1 4 +3VALW 74HCT273
10
6 RP81
SELIO# 5 1394_PME# 1 8
<30> SELIO# PCM_PME# C602
2 7
+3VALW MDM_PME# 3 6 1 R450 2 1 2
7
LAN_PME# +3VALW
C377 4 5 20K_0402
1 2 1UF_0603
8P4R_100K_0804
.1UF_0402 +5VALW
C378
20
U33 1 2 .1UF_0402
2 18 ADB0
VCC
<28> BD_ID0 1A1 1Y1 ADB1 +3VALW
<28> BD_ID1 4 1A2 1Y2 16
ADB2 RP82
20
<28> BD_ID2 6 1A3 1Y3 14
8 12 ADB3 DS_PME# 1 8 U31
<7,43> NB/DT#_CPU TPAD_ON/OFF# 1A4 1Y4 ADB4 DOCKINTR# +3VALW ADB0
11 9 2 7 3 2
VCC
<29> TPAD_ON/OFF# 2A1 2Y1 D0 Q0 EC_WAKEUP# <16>
BT/WL_ON/OFF# 13 7 ADB5 UNDOCK# 3 6 ADB1 4 5
<32> BT/WL_ON/OFF# BT_PRES# 2A2 2Y2 ADB6 BT/WL_ON/OFF# 4 ADB2 D1 Q1 EC_GRST <33>
<32,34> BT_PRES# 15 5 5 C381 7 6
BT_WAKE_UP 2A3 2Y3 ADB7 ADB3 D2 Q2 EC_MUTEO <22,33,35>
<32,34> BT_WAKE_UP 17 2A4 2Y4 3 1 2 8 D3 Q3 9 EC_CPUVID0 <7>
2 8P4R_100K_0804 ADB4 2
1 2 13 D4 Q4 12 EC_CPUVID1 <7>
R311 100K_0402 1 .1UF_0402 ADB5 14 15
GND
1G U17C ADB6 D5 Q5 EC_CPUVID2 <7>

RP134
14
19 2G 17 D6 Q6 16 EC_CPUVID3 <7>
+3VALW IN4 1 8 74LVC32 ADB7 18 19
IN3 KBA4 D7 Q7 EC_CPUVID4 <7>
74LVC244 2 7 9
10
U17D IN2
14
3 6 8 11
GND
74LVC32 IN1 SELIO# LARST# CLK
4 5 10 1 CLR
KBA3 12
11 8P4R_100K_0804 74HCT273
10
SELIO# 13 QVCC_OK 1 2
R46 100K_0402
7
+3VS
R509
<15,30> M_SEN# M_SEN# 1 2
10K_0402
update from 100K to 10K

5/3 JOHNNY
3 3
VCC_FLASH
U18 1 2 +5VS
+3VALW
R435 0_0402 +3VALW
1
KBA18 1 32
NC VCC
2
KBA16 2 31 FWE# C563 + C564 +3V

KBA15 A16 WE* KBA17 R431
3 30
A15 A17
1
KBA12 4 29 KBA14 .1UF_0402 +3VALW

2
KBA7 A12 A14 KBA13 R238 100K_0402

5 28
A7 A13
1
KBA6 6 27 KBA8 4.7UF_10V_0805 +3VALW
2
A6 A8 100K_0402
1
KBA5 7 26 KBA9 C220 R669 R670
KBA4 A5 A9 KBA11
8 25 1 2 U15
2
A4 A11
2
KBA3 FR D# Q52 10K_0402 22K_0402 R240

G
9 24
A3 OE*
5
KBA2 10 23 KBA10 .1UF_0402 2N7002 100K_0402
22
KBA1 A2 A10 FSEL#
11 22 2 1 3
2
A1 CE* EC_FLASH# <17> +3VALW +3VALW
KBA0 12 21 ADB7 FWE# 4
D
ADB0 A0 DQ7 ADB6 PCM_PME# 3 PEM_EC#

13 20 1 <23> PCM_PME# 1 PME_EC# <30>
ADB1 DQ0 DQ6 ADB5
14 19 Q88
DQ1 DQ5
1
ADB2 15 18 ADB4 7SH32FU
3
DQ2 DQ4
1
16 17 ADB3 D20 C265 R430
VSS DQ3 FWR# <30> 1394_PME# 1 3904
<25> 1394_PME# 2
.1UF_0402 100K_0402
2
29F040/SST39VF040_PLCC RB751V U16
2
D21 8 1
MDM_PME# 1 VCC A0
<34> MDM_PME# 2 7 2
U20 U19 WC A1
<15,30,39> EC_SMC1 6 3
RB751V SCL A2
<15,30,39> EC_SMD1 5 4
KBA11 FR D# KBA11 FR D# D22 SDA GND
1 32 1 32
A11 OE# FRD# <30> A11 OE#
1
KBA9 2 31 KBA10 KBA9 2 31 KBA10 LAN_PME# 1 2 NM24C16-27
A9 A10 A9 A10 <34> LAN_PME#
KBA8 3 30 FSEL# KBA8 3 30 FSEL# R237 R426
KBA13 A8 CE# ADB7 FSEL# <30> KBA13 A8 CE# ADB7 RB751V
4 A13 DQ7 29 4 A13 DQ7 29
4 VCC_FLASH KBA14 ADB6 VCC_FLASH KBA14 ADB6 100K_0402 100K_0402 4
5 A14 DQ6 28 5 A14 DQ6 28
KBA17 6 27 ADB5 KBA17 6 27 ADB5
2
FWE# A17 DQ5 ADB4 FWE# A17 DQ5 ADB4
7 WE# DQ4 26 7 WE# DQ4 26
8 25 ADB3 8 25 ADB3
KBA18 VCC DQ3 KBA18 VCC DQ3 D44
9 A18 VSS 24 9 A18 VSS 24
KBA16 10 23 ADB2 KBA16 10 23 ADB2 USB20_PME#1 2
KBA15 A16 DQ2 ADB1 KBA15 A16 DQ2 ADB1 <26> USB20_PME#
11 A15 DQ1 22 11 A15 DQ1 22
KBA12 12 21 ADB0 KBA12 12 21 ADB0 RB751V
KBA7
KBA6
13
A12
A7
DQ0
A0 20 KBA0
KBA1
KBA7
KBA6
13
A12
A7
DQ0
A0 20 KBA0
KBA1 Title
14 A6 A1 19 14 A6 A1 19
KBA5 15 18 KBA2 KBA5 15 18 KBA2 SCHEMATIC, M/B LA-1381
KBA4 A5 A2 KBA3 KBA4 A5 A2 KBA3 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
16 A4 A3 17 16 A4 A3 17
@SST39VF040_TSOP TSOP 8x14 @29F040_TSOP TSOP 8x20 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Custom
A B C D E
10 9 8 7 6 5 4 3 2 1
MDC Note +3V MDC Conn.

Pin 1 is NC for Pctel and connexant MDC modem
H H
1
Pin 2 is NC for Pctel and connexant MDC modem C392 C393 +5VMDC 1 2
+5V
1
C666 R329 @0_0805 JP34
@1000PF_0402 @.1UF_0402 1 3
2
C665 MDC@.1UF_0402 C758 1 3
2 4
2
+3VMDC C759 2 4
1 2
MDC@1000PF_0402 1 2 JP11
1 2 @1000PF_0402 RJ11 CONN.
+3V R487 MDC@0_0805 @1000PF_0402
<21,34> MD_MIC 1 2
MONO_OUT/PC_BEEP AUDIO_PWDN
1 2 3 4 MD_SPK <21,34>
+3VALW R486 @0_0805 AGND MONO_PHONE
5 6
AUXA_RIGHT RESERVED
7 8 MDC_DET# <17,18>
AUXA_LEFT GND
2
C668 C667 9 10
CD_GND +5V
11 12
MDC@4.7UF_10V_0805 MDC@.1UF_0402 CD_RIGHT RESERVED
13 14
1
CD_LEFT RESERVED
15 16 1 2 +3V
G GND RESERVED R326 MDC@10K_0402 G
17 18
+3VMDC 3.3Vaux RESERVED
19 20
GND RESERVED
21 3.3Vmain AC97_SYNC 22 IAC_SYNC <16,21,34>
23 24 2 R328 1
<16,21,34> IAC_SDATAO AC97_SDATA_OUT AC97_SDATA_IN1 SDATA_IN1 <16,34> 0: Have primary CODEC on mother board
25 26 MDC@22_0402
<16,21,34> AC97_RST# AC97_RESET# AC97_SDATA_IN0 R327 1
27 28 2
BlueTooth Interface 29
GND
AC97_MSTRCLK
GND
AC97_BITCLK 30 @22_0402
IAC_BITCLK <16,21,34>
2
BT_ON#
+3VALW +5VALW MDC@AMP 3-1473290-0 R325
Bluetooth Connector
2
15_0402
JP26 GREEN BLUE TOOTH
10K
B
<31,34> BT_DETACH BT_WAKE_UP 1 2 D28 R300
C391
<31,34> BT_WAKE_UP 3 4
10K
BT_ON# +5VALW
C
5 6 BT_ON# <31,34> 2 1 3 1 2 1
F L26 1 2 BT@FBM-11-160808-121 22PF_0402 F
<17,34> USBP3+ 7 8 BT_PRES# <31,34>
B T @1 2 -2 15 SYGC
E
<17,34> USBP3- 1 2
L27 BT@FBM-11-160808-121 9 10 Q33 BT@330_0402
11 12 C596 BT@DTA114EKA
<31,34> BT_RST# 13 14
1 2
15 16
17 18 BT/WL@.1UF_0402
19 20 Q78
1
1
C444 BT@AXK5S20035 C233 SW2
DTC144EKA
1 2 BT/WL_ON/OFF#
BT/WL_ON/OFF# <31> D45 R651
BT@.1UF_0402 BT@.1UF_0402
2
2
3 4 2 1 2 1 1 3
47K
BT/WL@HCH_PTS-05 1 2 -215 UYOC
47K
GREEN WIRELESS LAN WL@330_0402
E USB CONNECTOR 2 E
2
WL_ON <30,34>
USB_VCCB W=40mils R660
+5VS 1 2
1
C672 + C671 C673 New add 5/3 JOHNNY

.1UF_0402 100UF_16V_D2 1000PF_0402 10K_0402
2
L67 JP32
USB11@FBM-11-160808-121
USBP1- USB1D- 1
<17> USBP1- 1 2 2
USBP1+ 1 2 USB1D+
<17> USBP1+ USB11@FBM-11-160808-121 3
D L68 4 D
USB2_CONN
<26> USB1D-
1
<26> USB1D+ R560 R561
USB20@15K_0402 USB20@15K_0402
USB CONNECTOR 1
2
USB_VCCA W=40mils
C C
1
C394 + C396 C395
.1UF_0402 100UF_16V_D2 1000PF_0402

USB CONNECTOR 3
2
+5V USB_VCCC
USB_VCCC W=40mils
L35 JP12
USB11@FBM-11-160808-121
1
1
C756 U78 C742 + C741 C743 USBP0- 1 2 USB0D-

<17> USBP0- 2
USB11-3@1000PF_0402 USBP0+ 1 2 USB0D+
USB11-3@.1uF_0402 USB11-3@.1UF_0402 USB11-3@100UF_16V_D2 <17> USBP0+ USB11@FBM-11-160808-121 3
1 GND 8
2
OUT L34 4
2 IN 7
OUT USB1_CONN
3 IN 6
OUT
4 EN# 5 OVCUR#2 <17>
OC# L89
B JP37 B
USB11-3@FBM-11-160808-121
USB11-3@TPS2041 USBP2- USB2D- 1 <26> USB0D-
<17> USBP2- 1 2
USBP2+ USB2D+ 2
1 2
3
1
<17> USBP2+ USB11-3@FBM-11-160808-121 <26> USB0D+
L90 4 R562 R563
USB3_CONN
USB20@15K_0402 USB20@15K_0402
2
New add 5/3 JOHNNY
A
Title
401212
Custom
10 9 8 7 6 5 4 3 2 1
A B C D E F G H I J
Power ON Circuit Reset Button

+3VALW
+3VALW
1
+3VALW +3VALW C286 .01UF_0402
R447 1 2
1 R241 1
1 2 SW3 10K_0402
EC_RSMRST# <30>
5
U23
14
14
2
U12A U12B @0_0402 1 2 2
R271 74LVC14 74LVC14 R196 4 EC_RST#
2 1 1 2 RSM_RST# 3 4 1 2 RSMRST# 3 4 1
<30> EC_RST# RSMRST# <16,20>
1
200K_0402 0_0402 RESET BTN 7SH32FU
3
1
R184 C188 R203
7
R253
330K_0402 .1UF_0402 @100K_0402 1 2
2
<31> EC_GRST
2
2
10K_0402
2 Power BTN 1 2 2
+3VALW
D9 R47 100K_0402
1 ON /OFF# ON/OFF# <30>
DT : REMOVE <15> ON/OFFBTN# 3
+3VALW +3VALW 2 EC_PWR_ON# <37>
+3VALW
+3VALW DAN202U
R440 10K_0402
14
14
14
+3V 1 2
1
U21A
1
R665 10K_0402 R182 M@20K_0402 R51
1
ITP_PWROK C C68 D8
1
<43> VGATE 1 2 2 3 1 2 5 6 9 8
100K_0402
74LVC125 U12C U12D 1000PF_0402 RLZ20A
2
2
2
2
C186 74LVC14 74LVC14 EC_ON 1 2 2 22K
7
7
<30> EC_ON
1
C757 R52 B
1
3 D M@1UF_0805_X7R 0_0402 E 3
1
1000PF_0402 2 Q20 22K
2
<36> VR_ON#
G Q7
3
S @2N7002 DTC124EK
3 WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V
+3VS
R451 C610 @.01UF_0402 +5VS

1 2
+3VS
<30> VOL_IN_DN#
1
5
2
@240_0402 U14 R314 C398
<5> ITP_DBR# 1
4 PM_PWROK 220_0402 .1UF_0402
1
4 PM_PWROK <16> 4
2
1
ITP_PWROK 2
2
New update
1
SW1
a
GND
@7SH08 R418 5/16 JOHNNY
3
2
3
@10K_0402 D30 b
<30> EC_MUTEI# 4
c
5
2
d
2
6 7 -2 1SYGC C399 6
GREEN e
7
R422 M@0_0402 .1UF_0402 f
g
1
D Q36 HSS115A
8
R438 2
<22,31,35> EC_MUTEO
2 1 G
+3V
4
U21B S 2N7002
3
<30> VOL_IN_UP#
10K_0402
5 5
2
5 6 1 2 C401
ICH_VGATE <16>
R439 0_0402 CP6
74LVC125 1 2 .1UF_0402 KSI3 1 8
1
+3VS
R255 10K_0402 KSO5 2 7
KSO1 3 6
KSI0 4 5
CK408_PWRGD# <14>
1
R244 100K_0402 8P4C_100PF

1 2 2 Q31 CP7
3904 INT_KBD CONN. KSO2 1 8
2
C287 KSO4 2 7
3
KSI[0..7] KSO7 3 6
KSI[0..7] <15,30>
100PF_0402 KSO8 4 5
1
KSO[0..15] KSO[0..15] <30>

8P4C_100PF
6 JP5 6
CP4
KSI1 1 KSI1 1 8
RSM_RST# KSI7 1 KSI7
DT : INSTALL 2
2
2 7
KSI6 3 KSI6 3 6
KSO9 3 KSO9
4 4 5
+3VALW KSI4 4
5
C590 KSI5 5 8P4C_100PF
6
+5V +3V KSO0 6 CP5
2 1 7
C183 KSI2 7 KSI4
8 1 8
DT@.01UF_0402 KSI3 8 KSI5
1 2 9 2 7
9
1
KSO5 10 KSO0 3 6
R419 U13 KSO1 10 KSI2
11 4 5
11
5
DT@.1UF_0402 KSI0
14
12
DT@47K_0402 KSO2 12 8P4C_100PF
2 13
13
R416 4 KSO4 14
2
KSO7 14 CP8
7 1 2 11 10 1 15
15 7
KSO8 16 KSO6 1 8
16
1
DT@330K_0402 C533 U12E +3VS KSO6 17 KSO3 2 7

3
74LVC14 DT@7SH32FU C201 KSO3 17 KSO12

18 3 6
7
DT@.1UF_0402 KSO12 18 KSO13

1 2 19 4 5
2
KSO13 19
20
KSO14 20 8P4C_100PF
21
DT@.1UF_0402 KSO11 21 CP9
10
22
U21C KSO10 22 KSO14
23 23
1 8
1
U53 R213 DT@0_0402 KSO15 24 KSO11 2 7

PM_PWROK 24 KSO10
5 6 9 8 1 2 25 3 6
VCC
DT@.01UF_0402 MR# RST# 25 KSO15 4 5

1 2 3 74LVC125
+5VS PFI
1
INT_KB_CONN. 8P4C_100PF
1
R442 4 R212
GND
PFO#
1
DT@240K_0402 R445 C569 C567

8
DT@MAX6342
DT@10K_0402
Title
2
DT@100K_0402 SCHEMATIC, M/B LA-1381

2
DT@.1UF_0402 R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 2B
401212
Custom
A B C D E F G H I J
A B C D E F G H I J
1 1
Or use SI2305DS.
+3VALW Q28 +3VAUX

SI2301DS
D
3 1
1
C274
G
2
1
C275
1UF_0603
2
1UF_0603
2
2 +3VALW +5VALW 2
<30> EN_WOL#
1
C711 C712 LAN RESERVED JP24 LAN RESERVED

TIP RING
2
.1UF_0402 .1UF_0402
KEY KEY BT_WAKE_UP
3 4 L82 FBM-11-160808-121
+3VALW 3 4 BT_WAKE_UP <31,32>
5 5 6 6 2 1 USBP3+ <17,32>
+5VALW
<31,32> BT_PRES# 7 7 8 8 2 1 USBP3- <17,32>
BT_ON# 9 10
<31,32> BT_ON# 9 10 BT_RST# <31,32>
11 12 L83 FBM-11-160808-121
WL_ON 11 12
<30,32> WL_ON 13 13 14 14
<31,32> BT_DETACH 15 15 16 16
1 2 17 18 W=30mils
3 <16,18> PIRQD# 17 18 +5VS 3
+3VS 2 R425 1 +3VS_MINI_L W=40mils R427 0_0402 19 19 20 20 1 2
R231 0_0402 PIRQC# <16,18,26>
0_1206 <16,18> REQ#4 21 21 22 22 GNT#4 <16,18>
1
C551 23 24 W=40mils
CLK_PCI_MIN 23 24 +3VAUX
C548 25 26
<14> CLK_PCI_MIN 25 26 W=40mils +3VS_MINI_R PCIRST# <5,8,15,16,19,23,25,26,28> R234
1000PF_0402 100PF_0402 27 28 1 2
2
REQ#1 27 28 GNT#1 +3VS

<16,18> REQ#1 29 29 30 30 GNT#1 <16,18> 0_1206
1
31 32 C261 C262
31 32 MDM_PME#
<16,23,25,26> AD31 33 33 34 34 MDM_PME# <31>
35 36 LAN_PME# 100PF_04021000PF_0402
2
<16,23,25,26> AD29 35 36 LAN_PME# <31>
CLK_PCI_MIN 37 38
37 38 AD30 <16,23,25,26>
<16,23,25,26> AD27 39 39 40 40
1
<16,23,25,26> AD25 41 41 42 42 AD28 <16,23,25,26>

R428 AD22 1 2 43 44
IDSEL : AD22 R429 100_0402 43 44 AD26 <16,23,25,26>
<16,23,25,26> C/BE#3 45 45 46 46
@10_0402 AD18 AD24 <16,23,25,26>
<16,23,25,26> AD23 47 48 1 2
47 48 R236 100_0402 IDSEL : AD18 +5VS
49 50
1 2
4 51
49 50
52
4
<16,23,25,26> AD21 51 52 AD22 <16,23,25,26>
C550 53 54
<16,23,25,26> AD19 53 54 AD20 <16,23,25,26>
55 56
@15PF_0402 55 56 PAR <16,18,23,25,26>
57 58
2
<16,23,25,26> AD17 57 58 AD18 <16,23,25,26>
1
<16,23,25,26> C/BE#2 59 60 AD16 <16,23,25,26>
59 60
1
61 62 C549 C553 C554
<16,18,23,25,26> IR D Y#
63
61 62
64
+
63 64 FRAME# <16,18,23,25,26>
65 66 4.7UF_10V_0805 .1UF_0402 1000PF_0402
2
<16,18,23,25,28,30> PM_CLKRUN# 65 66 TRDY# <16,18,23,25,26>
<16,18,23,25> SERR# 67 68 STOP# <16,18,23,25,26>
67 68
69 70
69 70
<16,18,23,25> PERR# 71 72 DEVSEL# <16,18,23,25,26>
71 72
<16,23,25,26> C/BE#1 73 74
73 74
<16,23,25,26> AD14 75 76 AD15 <16,23,25,26>
75 76
77 78 AD13 <16,23,25,26>
77 78 +3VS
<16,23,25,26> AD12 79 80 AD11 <16,23,25,26>
79 80
5 <16,23,25,26> AD10 81 82 5
81 82
83 84 AD9 <16,23,25,26>
83 84
85 86 C/BE#0 <16,23,25,26>
<16,23,25,26> AD8 85 86
87 88
<16,23,25,26> AD7 87 88
1
89 90 AD6 <16,23,25,26>
89 90
1
91 92 C223 + C230 C231 C542 + C543
<16,23,25,26> AD5 91 92 AD4 <16,23,25,26>
93 94 AD2 <16,23,25,26>
93 94 4.7UF_10V_0805 .1UF_0402 .1UF_0402 1000PF_0402 4.7UF_10V_0805
95 96
2
<16,23,25,26> AD3 W=30mils 95 96 AD0 <16,23,25,26>
+5VS 97 98
97 98
99 100
<16,23,25,26> AD1 99 100
101 102
101 102
<16,21,32> IAC_SYNC 103 104
103 104
<16,32> SDATA_IN1 105 106 IAC_SDATAO <16,21,32>
IAC_BITCLK IAC_BITCLK 105 106 +3VAUX
<16,21,32> IAC_BITCLK 107 108 1 2
107 108 R510 10K_0402
109 110 AC97_RST# <16,21,32>
109 110
1
MD_MON 111 112

<21> MD_MON 111 112
6 R432 113 114 6
113 114 MD_SPK
115 116 MD_SPK <21,32>
<21,32> MD_MIC 115 116
1
@10_0402 117 118
117 118
1
119 120 C264 C263 C256
+
1 2
119 120
<29> MD_RI# 121 122
C552 W=30mils 121 122 W=40mils 4.7UF_10V_0805 .1UF_0402 1000PF_0402
123 124
2
+5VS 123 124 +3VAUX
1
@15PF_0402 127 128

2
C767 127 128 C768

Mini-PCI SLOT
2
1000PF_0402 1000PF_0402
7 7
8
Title
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Custom
A B C D E F G H I J
A B C D E F G H I J
1 1
R638 SUB@1K_0402 R639 SUB@1K_0402
MIX_OUT 1 2 1 2
+5V_AMP
+5V_AMP
1
C737
R641 SUB@100K_0402 SUB@@150PF_0402 R655
1
<21,22> RIGHT RIGHT 1 2 @39.2K_0402_1%
C738 R643 SUB@100K_0402 U75 C739 SUB@.1UF_0402
R642 SUB@100K_0402 1 2 1 8
LEFT MIX_IN 1OUT VDD+ LPF_OUT SUB_IN
<21,22> LEFT 1 2 2
1IN- 2OUT
7
SUB_VREF 3 6 R657
2
1IN+ 2IN- LPF_IN SUB_VREF SUB_VREF
4 5 1 2 +AUD_VREF
SUB@1UF_0402 GND 2IN+
1
SUB@TLV2462 C740 SUB@100PF_0402 SUB@0_0402
2 2
1
R656
2
C749 @39.2K_0402_1%
2
SUB@.1UF_0402
3 3
Layout note:
3
S
G
EC_MUTEO 2 Trace width=15 mils.
<22,31,33> EC_MUTEO
D Q80 1.SUBSPKFF-,SUBSPKFF+,SUBSPKF-,SUBSPKF+SUBSPK-,SUBSPK+
1
SUB@2N7002
4 4
R658
1 2 +12VALW
Q81 SUB@100K_0402
2
G
R659 SUB@2N7002 Q82
G
U73 SUB@2N7002 JP36
SUB@100K_0402 SUB_IN 1 8 SUBSPKFF- 3 1 SUBSPKF- 1 3 SUBSPK- 2
SUB_SD# IN VO- 2
D
1 2 2 7 1
S
+5VS SHUTDOWN# GND 1
3 6
+5V_AMP VDD SE/BTL SUBSPKFF+
4 5
BYPASS VO+ SUB@WOOFER CONN
1
SUB@TPA0211
1
D
SUBSPKF+ SUBSPK+
S
3 1 1 3
C750 C736 R637
Q83 Q84
5 5
2
SUB@.1UF_0402 SUB@.47UF_0402 SUB@100K_0402 G SUB@2N7002 SUB@2N7002
G
2
2
+ C745
SUB@10UF_16V_1206
16V
6 6
7 7
8
Title
401212
Custom
A B C D E F G H I J
A B C D E F G H I J
+CPU_CORE +1.25VS
+3VALW
+12VALW +12VALW
1
+5VALW to +5V Transfer R232 R235 R520
2
@100K_0402 470_0402
1
R363 @330
1 100K_0402 R424 1
1 2
D 10K_0402
2 +5VALW
1
D
+5V 2 SUSP
2
U44 VR_ON# 2 G
<33> VR_ON#
1
8 1 G S Q65 SUSP
3
D S <42> SUSP
1
1
D C491 Q26 2N7002
7 2 S
3
D S
1
SYSON# 2 R364 6 3 @2N7002
D S
1
G .01UF_0402 C484 R361 D
5 4 C487
2
D G
1
Q46 1M_0402 470_0805 D Q53
S 2
3
2
VR_ON 2 <21,30,42> SUSP#
2N7002 SI4800 10UF_10V_1206 .1UF_0402 G 2N7002
2
SUSON <30,43> VR_ON
G S
1 2
3
S Q25
3
D @2N7002
2 SYSON#
G
2 +5VALW +5VALW S 2
3
Q45 +12VALW To +12VS Transfer +2.5V To +2.5VS Transfer
2N7002 +1.5VALW to +1.5VS Transfer
1
+12VALW +2.5V
C493 1 + C490
+1.5VS
4.7UF_10V_0805 33UF_D2_16V C187 C405
2
2
1 2 1 2
Q16 Q39
@.1UF_25V_0805 SI3861 @.1UF_0402 SI3865
1
R177 R1 C424 C27
D
1 2 4 2 1 2 4 2 R214
.1UF_0402 470_0402
2
100K_0402 6 3 +12VS 100K_0402 6 3 22UF_10V_1206
G
+2.5VS
2
SUSP# 5 SUSP# 5
+3VALW to +3V Transfer
1
3 C193 Q22 3
1
R515 C413 + R516 D 2N7002
+12VALW 470_0402 470_0402 2 SUSP
1
+3VALW +3V 1UF_25V_0805 +2.5VS 4.7UF_10V_0805 G
2
S
1 2
1 2
3
1
1
U49 C184
1
R189 D R333 D
8 D S 1
7 2 1UF_25V_0805 2SUSP + C412 2 SUSP
2
D S
1
6 3 0_0402 G 0_0402 G
D S
1
5 4 C526 C538 R420 S Q63 4.7UF_10V_0805 S Q64
3
D G 470_0402 2N7002 2N7002
1
SI4800 10UF_10V_1206 .1UF_0402

2
2
1
+ C520 C527
2
33UF_D2_16V
10UF_6.3V_P +12VALW
2
D
4 2 SYSON# RTCPWR 4
SUSON G +1.8VALW +1.8VS BATT1
SUSON <26> +1.8VALW to +1.8VS Transfer
1
S Q50
- +
3
2N7002 U9 SI4800 2 1 RTCPWR R423

8 1 47K_0402
D S
1
7 2 C669
D S
1
6 3 C177 C179
2
D S R179 RTCBATT .1UF_0402
5 4
2
D G .1UF_0402 470_0402 SYSON#
2
<42> SYSON#
1
22UF_10V_1206
1
C195 D
1
10UF_6.3V_P 2 Q27
RTC Battery
2
<30> SYSON
Q18 D41 G 2N7002
+5VALW to +5VS Transfer
1
D 2N7002 S
3
+12VALW RU NON 2 SUSP
G +RTCVCC
5 5
S
2
1
+5VALW +5VS
R352 CHGRTC
100K_0402 U42 SI4800 HSM126S
8
D S 1 CF5 CF8 CF6 CF7 CF9 CF14 CF10 CF13 CF16 CF18 CF11 CF15 CF12 CF17 CF19 CF20 CF1 CF2
7
S 2
2
D
1
6
D S 3 R348
5
D G 4
1
C453 C459 470_0805

1
D C467 HOLEB HOLEB HOLEB HOLEB HOLEB HOLEB HOLEB HOLEB HOLEB HOLEB HOLEB HOLEB HOLEB HOLEB HOLEB HOLEB HOLEB HOLEB
SUSP 2 RU NON .1UF_0402 22UF_10V_1206
2
G R353
2
Q44 S 1M_0402 .01UF_0402

3
2N7002 Q43 H13 H11 H22 H21 H2 H19 H15 H23 H27 H18 H31 H32
1
D
6 SUSP
6
2
+5VALW +5VALW G
S
3
2N7002
1
1
1
C463 HOLER HOLES

+ C452
4.7UF_10V_0805 HOLEC HOLEC HOLEC HOLEC HOLEC HOLEC HOLEC HOLEC HOLEC HOLEC
2
100UF_D_16V
2
H5 H3 H12 H29 H7 H9 H10 H4 H1 H28 CF3 CF4
HOLEB HOLEB
7 7
1
1
+3VALW +3VS HOLEF
+3VALW to +3VS Transfer
U50 SI4800 HOLED HOLED HOLEL HOLEP HOLEE HOLEE HOLEE HOLEJ HOLEK H8 H30
8 1
D S H25 H24 H14 H16 H17 H20 H26
7 2
D S
1
6 3 C546 C531
D S R406 FD3 FD2 FD1 FD4 FD6 FD5
5 4
D G
1
.1UF_0402 82_0402
2
2
1
+ C530 22UF_10V_1206
1
100UF_D_16V C537
2
10UF_6.3V_P New update 5/20 Johnny HOLEG HOLEG HOLEG HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
2
Q49 HOLET HOLET

1
D 2N7002
RU NON 2 SUSP HOLEH HOLEH HOLEI HOLEI
G
8 S Compal Electronics, Inc. 8
3
Title
401212
Custom
A B C D E F G H I J
A B C D
Vin Detector
High 18.784 17.901 17.077 V

P1
PCN1
PL1
FBM-L18-453215-900LMA 90T_1812
VIN Low 17.877 17.043 16.195 V
3 1
3 1 1 2
4 2
1
1 1
PR1
4 2 1M_1%
PD1 1 2
EC10QS04 VIN VS
SIN-2DC-S726B201 PC1 PC2 PC3 PC4
2
1000PF_50V 100PF_50V 1000PF_50V 100PF_50V VS
1
1
PR2
1
PR3 PC5 10K PR4
84.5K_1% 0.1UF_50V 1K
1 2
2
PR5 ACIN <17,30,42>
8
22K
1 2 3 +
1
2 -
PACIN <40,41>
1
1
1
VIN PC6 PR6 PC7 PU1A
4
1000PF_50V 20K_1% 0.1UF_16V PZD1 PR7
PR8 1K_1206 LM393M RLZ4.3B 10K
B++
2
2 1 VIN+
2
PD2 PR10 1K_1206 2 1 RTCVREF
IN4148
PR9
10K
(3.3V)
PR11 1K_1206 ACIN
2 PR12 1K_1206 Precharge detector 2
VIN
VS
16.6 15.9 15.2
13.48 12.93 12.09
2
1
PD3 PR13
IN4148 10K_1%
PR14 BAT ONLY
1M_1%
1
2
* 2 1 B++
<41> VMB_A PD4
RB715F
Precharge detector
VIN++
1
3 8.597 8.247 7.904
1
2
PR15
<41> VMB_B * 499K_1%
PR16
6.310 6.101 5.683
VS
33_1206 PU1B
2
8
<5,42,43> MAINPWON LM393M
PZD2 PQ1 1 5
+
RLZ4.3B TP0610T 3 7
CHGRTCP 2 1 VS+ 3 1 2 6 2 1
-
1
<40,41> ACON
1
PR17 RTCVREF PR18
4
1
1
PD5 PC9 10K PC8
2
1
1
RB715F PZD3 1000PF_50V (3.3V) 499K_1% 1000PF_50V
2
PR19 PC10 PC11 RLZ6.2C PR20
2
1
100K 0.22UF_1206_25V 0.1UF_0805_25V 215K_1%
2
2
<33> EC_PWR_ON# PC12
2
0.1UF_16V
2
1 2
3 3
PR21
22K
1
PR22
47K
2 2 1 PACIN
PQ2
2N7002
1
CHGRTCP
RTCVREF 100K
PU2 PR23 2 +5VALWP
200_0805
S-81233SG(SOT-23-5)
PQ3 100K
CHGRTC 3.3V DTC115EUA
3
1 2 3 2 CHGRTCP+
3 2
1
PR24
1
200 PC13 PZD4

PC14 1UF_0805_25V RLZ16B
1
10UF_1206_10V
2
4 4
Title
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401212 2B
Date: 星期一, 十二月 30, 2002 Sheet 37 of 46
A B C D
A B C D
Iadp=0~4.5A 1
P2 P3 B+ B++
PQ4 PQ5 PR25 PL2 PQ6
SI4835DY SI4835DY 0.02_2512_1% FBM-L18-453215-900LMA 90T_1812 SI4835DY
VIN 8 1 1 8 2 1 1 2 1 8
7 2 2 7 2 7
1
6 3 3 6 PR30 PC15 PC16 PC17 3 6
5 5 0 5
1
1
1 2 10UF_1210_25V 0.1UF_0805_25V @1000PF_50V
2
4
4
PR26 PR27 L_2
10K 200K
PR29
2
2
L_1 47K
PR210 ACOFF# 1 2 1 2
0
VIN
1
2 1 PR28
PU3 MB3878 10K
PD6 PR31
<41> FSTCHG_EN#
1
1SS355 150K 1 24 D
ACOFF# -INC2 +INC2
1 2
ACOFF# <30> ADI_P * G
2
2
2 1 2 23 PC18 S
OUTC2 GND
3
0.022UF_25V
PR33 2.22V PR32 10K
PQ58
2N7002
1
3
2
1
1
10K D PQ8
<39,41> PACIN 3 +INE2 CS 22 1 2
1 2 2 2N7002
G
ACOFF <30>
1
S 4 21 L_3 1 2 4
3
-INE2 VCC(o) 100K

1
PR34 2
1
2 24K_1% PR36 10K PC19 PQ7 2
PC20 PR35 1 2 1 2 5 20 0.1UF_0805_25V C HR_G SI4835DY

<39,41> ACON 0.1UF_16V 19.1K_1% FB2 OUT PC22 100K PQ9
2
2
PC21 4700PF_50V 0.1UF_50V DTC115EKA
2
3
6 19 VH 1 2
5
6
7
8
VREF VH PC25
(5.0V)
1
PR37 10K 0.1UF_0805_25V
PC23 1 2 1 2 7 18 1 2
IREF=1.31 * Icharge 0.1UF_16V FB1 VCC
LXCHRG
2
PC24 2200PF_50V
IREF=0(0.73)~3.3V 8
-INE1 RT
17 1 2 CC=2.7A +-10%
PR39
140K_1% PR38 CV=12.6V(9 CELLS)
1 2 9 16 68K PL3
<30> IREF +INE1 -INE3 22UH_SPC_1205P_220A
PC26 1500PF_50V BATT+
PR41 10K 1 2 1 2
2 1 10
OUTC1 FB3
15 1 2 1 2
PR40
1
4.7UF_1210_25V
10UF_1210_25V
PC27 PR42 0.02_2512_1%
PR43 0.1UF_16V 11 14 47K 1 2 ACON
OUTD CTL
1
PC28
PC29
100K_1% PD8
2
1
PR203 1K EC31QS04
APL11 APL10 12 13 PR44
2
2
-INC1 +INC1
100K
2
PR35 19.1K_1% 12.7K_1%
3
+INE2 2.22V 1.73V 3
2 1 2 1
PR45 PR46
51K_1% (4.2V) 102K_1%
CHARGE <43>
VS
SDREF +2.5VP
1
PC30
0.1UF_50V
2
PR47
100K_0.5%
PU4A
8
PR48 LM358A
2
0 + 3 L_L19
1
1
- 2 PC31
1
PR49 0.1UF_16V
PC32 100K_0.5%
4
10UF_1206_10V
2
L_L18
4 4
PU4B
LM358A
+ 5
7
- 6
Title
A B C D
A B C D
VMB_A BATT+
VMB_A <39>
P5
PJP9 PJP10
PAD-OPEN 4x4m PAD-OPEN 4x4m
1 2 1 2
VMB_B
<39> VMB_B
1
PC34
PCN2 PC33 @1000PF_50V PCN3
1000PF_50V P4
PQ11
2
PQ10 PQ12 PQ13
PL4 PL5
FBM-L18-453215-900LMA 90T_1812 @FDS4435 @FDS4435 @FDS4435 @FDS4435 @FBM-L18-453215-900LMA 90T_1812
1 1 BAT_LA BAT_LB 1 1
2 1 8 1 1 8 8 1 1 8 2 1
2 ALI/NIMH# BLI/NIMH# 2
3 7 2 2 7 7 2 2 7 3
AB/I 6 3 3 6 6 3 3 6 BB/I
4 TS_A TS_B 4
5 5 5 5
5 5
1
6 6
1
PR50 PR51
4
7 7
1
1K PC35 PC36 @1K
8 8
1
0.01UF_50V PR52 PR53 @0.01UF_50V
2
9 PR54 PR55 @39K @39K PR56 PR57 9
2
100 100 @100 @100
2
L_4 L_5
* @BTD-09JR1
2
1 2 @BTD-09JR1
EC_SMD1 EC_SMD1 <15,30,31> 1 2 <5,30,35> EC_SMD2 EC_SMD2
PR58 @22K
1
EC_SMC1 PR59 @22K
1
EC_SMC1 <15,30,31> 2 <5,30,35> EC_SMC2 EC_SMC2
2
PD9 PD10 PQ14 PQ15
3
1
1
@BAS40-04 @BAS40-04 @HMBT2222A @HMBT2222A
3
2
1
PD12
PR60 PD11 PR61 PD13 PD14
@10K @IN4148 @10K @IN4148 @BAS40-04 @BAS40-04
3
1
2 1 2 1
3
1
1
PCN4 100K GB 100K
2 2
2 +5VALWP <43> GB 2
PQ16 PQ17 +5VALWP
2
100K @DTC115EKA 100K @DTC115EKA
1
3
2 PR62 PR63
3 @10K @10K
4
1
5 +3VALWP
6
7 PR64
8 25.5K_1%
9 TS_A
1 2
1
VS
1
PU5 VMB_B PR65
7
BTD-09JR1 @74HC253 VL 47K PR66

PD15 PD16 1K
1Y
2Y
GND
1
PC37 PR69 3 3
2
1
16 @0.01UF_50V PR67 1K
2
VL VCC ALI/NIMH#2
PR68 @1M_0.5% 1 1 1
2
PR72 @100K PU6A PR70
<39,40> ACON
1EN
2EN
1
8
1C0
1C1
1C2
1C3
2C0
2C1
2C2
2C3
1 2 @LM393M @100K_1% 2 2
S0
S1
2
PC38 + 3 1 2 <30> BATT_TEMPA
<30> ALI/NIMH#
2
@0.1UF_16V 1 2 1 @BAS40-04 @BAS40-04

2
6
5
4
3
10
11
12
13
14
2
1
15
1
270K - 2
1
PR71 @4.7K
PR73 PC39
4
@499K_1% @100PF_50V
<40> FSTCHG_EN#
2
2
S1 1 2
PQ18
1
DTC115EKA PR74 @5.6M

3
PR75 VL RTCVREF 3.3V 8 CELLS BATTERY UVP 3
@100K VMB_A
H 8.0V L 7.2V
1
<30> FSTCHG 100K 1 2
1
2 PR76
1
@10K PR77
PR78 @1M_0.5%
100K @100K PU6B PR80
1 2
2
@LM393M @100K_1%
3
PR79 + 5 2 1 2
2
@100K S0 1 2 7 +3VALWP PR83

1
- 6 @25.5K_1%
1
PR81 @4.7K 1 2 TS_B
PR82 PC40
1
@499K_1% @100PF_50V
2
1
1
1 2 PR85
2
@47K PR86
PR84 @5.6M PC41 PD17 PD18 @1K
2
@1000PF_50V PR87 3 3
2
100K
<30> A/B#USE 2 @1K
2
BLI/NIMH# 2 1 1 1
1
PQ19 100K 2 2
@DTC115EKA <30> BATT_TEMPB
<30> BLI/NIMH#
3
@BAS40-04 @BAS40-04
100K
2 2 1 PACIN <39,40>
PQ20
@DTC115EKA PR88
100K @47K
3
2 1 TRICKLE <30>
4 4
PD19
@IN4148
Title
A B C D
A B C D E
VS
PC42
2
4.7UF_1210_25V
PD40 12VDD 1 2
1SS355
1
470PF_0805_100V
2
PC44
PC43
DAP202U PD20
0.1UF_0805_25V PD21 PR89 EC11FS2
1
1 2 BST31 BST51 22_1206
2
B++
3
SNB 2 1 FLYBACK
2
10UF_1210_25V
1 1
VS_L+
0.1UF_0805_25V
2200PF_50V
PQ21
FDS6982S PR90 PC48
1
1
1
PC46 D1 0 0.1UF_0805_25V
PC47
PC45
5 4 D H3 1 2 VL VL 1 2
3
1G PT1
2
4.7UF_1206_16V
6 S1 3 LX3 B++ SDT-1205P-100
1
D2 PR91
PC49
7 2 DL3 10_1206 +12VALWP
10UF_1210_25V
0.1UF_0805_25V
G2
2200PF_50V
8 S2 1 D1
1
4 5
2
0.1UF_0805_25V
PC51
PC50
G1
PC52
S1
4.7UF_1210_25V
+3.3V Ipeak = 6.66A ~ 10A 3 6
2
1
PR92
1
PC53
0 D2
PC54
1
2 7
VS_L++
1
1
G2
2
2 PC55 1 S2 8
PL6 47PF_50V
SLF12565T_100M 1 2 D H5 PQ22
FDS6982S
PR93
2
1
0 PC56
22
21
LX5 47PF_50V
25 4
V+
VL
2
BST3 12OUT DL5
VDD 5
L_6 27 18 BST51+
DH3 BST5
1
16 L_51
PU7 DH5
PR95 26 17
LX3 LX5
1
PR94 1M 24 19
DL3 DL5
1
2 0.012_2512_1% 2
20
+3VALWP PGND
14 PR96 PR97
2
CSH3 CSH5 2M 0.012_2512_1%

1 CSH3 CSL5 13
2 12
2
CSL3 FB5
150UF_D_6.3V_FP
3 MAX1632 15
2
FB3 SEQ
150UF_D_6.3V_FP
<17,30,39> ACIN 1 2 10 SKIP# REF 9

2.5VREF
1
PD22 23 6 CSH5
SHDN# SYNC
1
1
PC57
3.57K_1%
PC58
+ + EP10QY03 PR98 11
RST#
1
10K 7
TIME/ON5
1
PR99
PC59 PC60
+5VALWP
2
47UF_D_6.3V_PC
33PF_50V 28 4.7UF_1206_16V
GND
2
RUN/ON3
150UF_D_6.3V_FP
PR100
2
1
FB3_L @300K PR101
1
2 10.5K_1% + +
8
2
PC64
PC63 33PF_50V
2
*
2
PR102
PC61
PC62
680PF_50V PD23
2
10K
EP10QY03
2
FB5_L
1
1
PR104
@0 PR103
10K
RUN
VS 2 1 VL
2
2 1 VL
1
PR106 PR105 1 2
+3VALWP 1 2 +3VALW (5A,200mils ,Via NO.= 10) 47K 47K
+5V Ipeak = 6.66A ~ 10A
PR107
PJP1 PAD-OPEN 4x4m 0
2
3 3
MAINPWON +1.5VS
PQ60
+5VALWP 1 2 +5VALW (5A,200mils ,Via NO.= 10) MAINPWON <5,39,43> SI3442DV_TSOP6 +1.25V+-5%
1
D
PJP4 PAD-OPEN 4x4m 6
S
PC66 5 4
2
+1.25VS_VGA
PC65 0.047UF_16V 2
2
+12VALWP 1 2 +12VALW (120mA,20mils ,Via NO.= 1) 0.047UF_50V 1

+5VALWP
4.7U_1206_16V
2
PJP6 JOPEN/2MMA
3
+ PC146
PR217
5.1K_0603_5%
PR216
PC147
PC149 0_0603_5%
+1.2VPP 1 2 +1.2VP (100mA,20mils ,Via NO.= 1)
.1U_0603_50V4Z
47U_6.3V_M
PJP8 JOPEN/2MMA
1
1
220P_0603_50V8J
PC148
2
PU17A
8
LM358AMX_SO8
+1.8VALWP 1 2 +1.8VALW (3A,120mils ,Via NO.= 6) + 3 2 1 VL
PU17B 1
PJP2 JOPEN/3MMA LM358AMX_SO8 - 2 PR218
97.6K_0603_1%
2
+ 5
1000P_0603_50V7K
+1.5VP 1 2 +1.5VS (3A,120mils ,Via NO.= 6) 7
- 6 PR219
PJP3 JOPEN/3MMA 33K_0603_1%
PC150
PC151
1
+2.5VP 1 2 +2.5V 68P_0603_50V8J
4
(3A,120mils ,Via NO.= 6) 4
PJP5 JOPEN/3MMA 1 2
M7C PR220 5.1K_0603_5%
+1.25VP 1 2 +1.25VS (3A,120mils ,Via NO.= 6) +1.25VS_VGA
PJP7 JOPEN/3MMA
+1.25VS Title
1 2 +1.25VS_VGA
(3A,120mils ,Via NO.= 6)
PJP11 JOPEN/3MMA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1381
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS B 2B
401212
A B C D E
A B C D
PTH1 under CPU botten side :

CPU thermal protection at 84(85)+-3 degree C
PTH2 near main Battery CONN :
Recovery at 36(37)+-3 degree C
BAT. thermal protection at 90(91)+-3 degree C
Recovery at 39(40)+-3 degree C
<5,39,42>
MAINPWON
1 1
3.3V
RTCVREF
<40>
CHARGE
PR108 RTCVREF
* 100K_1%
PC139 VS
0.1UF_50V PC67
0.1UF_16V VS
PTH1
MAINPWON
10K_1% PC68 PTH2
CPU 0.1UF_50V Battery 10K_1%
CHARGE
L_7
PR110 PR109
47K_1%
L_8
PR113 10K
PR112 47K_1%
PR111 10K
1
3.65K_1% PR114
PR115 3.65K_1%
1
1K_1%
L_L2 3 PD24 PQ23 PR116 1SS355
+ 100K
8
1 L_L3 2 1 OTP 2 DTC115EKA 1K_1% PD25
REV 2 -
L_L5 5 + 100K
PQ56
PU8A 7 L_L6 2 1 OTP 2 DTC115EKA
LM393M 1SS355 100K REV 6 -
4
L_L4
L_L1
PU8B
3
PR117 LM393M PZD6 100K
4
19.1K_1% RLZ3.6B
3
1
PR121 PR119 PC73 PR118
1
2 PC70 249K_1% 470K @1000PF_50V 18.2K_1% 2
0.1UF_16V PC71 PZD5 PC72
2
1000PF_50V RLZ3.6B 0.1UF_16V PR120 PC74
2
470K 0.1UF_16V
PC69
0.1UF_16V
APL10 PR117 18.7K

PTH1 under CPU botten side : Please refer to Page. 45
CPU thermal protection at 87(88)+-3 degree C
BATTERY Charger OVP : 13.56V Recovery at 37(38)+-3 degree C APL10 nonpop components for cpu_core
APL10 PR118 19.1K
PTH2 near main Battery CONN : PU15;PQ51;PQ52;PQ54;PQ55;PD39;PD38;PL14;PC130;
BAT. thermal protection at 84(85)+-3 degree C PC132;PC133;PC131;PC134;PC135;PC129;PC128;
VIN
Recovery at 36(37)+-3 degree C PR193;PR194;PR196;PR199;PR197;PR192;PR195;
ACOFF#
PR200;PR198,PR223
1
VS
3 2 BATT+ 3
PQ24
3
@2N7002 PR122 PC75

36K_1% 0.1UF_50V
APL11 nonpop components for mobile
2
PR123
1M_0.5%
<41> GB
8
PR125 PR124 0
1
309K 1% 3 L_L9 L_L10

2 L_L7 L_L8 1
+ PR171,PR172,PQ42,PR177,PQ43,PQ44,PR207,PR184,
2
PQ25
- 2.5VREF PQ49,PR204,PQ59,PR205,PQ50
3
@2N7002 PR126
4
PU11A 100K
LM393M PR127 PR128
PR129 PC76 @100K_0.5% 226K_1%
100K_1% 1UF_1206_25V PC77
1UF_0805_16V
4 4
Title
A B C D
A B C D
D
S
6
+5VALWP 4 5 PR131
2 PQ26 +2.5VP 10_1206
@SI3445DV
1 1 (+2.5V +-5%) +2.5VCC
G
2 1 1 2
PR132
3
+2.5VP PR130 PU10
0_1206
1
PL7 0_1206 CM8500IT
2
4.7UH SPC-1205P-4R7A PC78
D
2
1
LX2.5 +2.5VP 0.1UF_0805_25V PC79 1
S
6 2 1
2
2.5VDD 4 5 1 16
1
VCC1 VCC2 0.1UF_0805_25V
220UF_D_4V_FP
2 (+1.25V+-5%)
470PF_0805_100V
1
2
1
10UF_1210_25V
PD26 +1.25VP
1
RB751V PQ27 PR133 PR134 +2.5VDD 2 15
3
PVDD1 PVDD2
PC80
PC81
PQ28 SI3445DV @2M 191K_1% +
2
PL8
1
1
HMBT2222A PC83
2
1
5UH SPC-06704-5R0
PC82
PR135 PD27 4.7UF_1206_16V

1
2
1 2 2 10K EC31QS04 3 14 LX1.25 2 1
2
2
VL1 VL2
220UF_D_4V_FP
2
PR136
3
1
1
1K PC86
PC87
+
L_9
PC84 PC85 4 13 4.7UF_1206_16V
2200PF_50V @0.1UF_16V PGND1 PGND2
2
2
5 AGND1 AGND2 12
3
5 L_L12 PR139
+
PQ29 2 L_L11 7 2.5VREF 100K
2SA1036K - 6 L_L13 1 2 +2.5VP 1 2 6 11 2 1
PU9B SD VFB
1
1
LM393M PR137
PC88 47K VS PR138 100K 1 2 2 1
4700PF_50V 7 10 +2.5VP
2
VIN/2 VCCQ
1
1000PF_50V
PR140
1
PC89 1K
1
PR208 PC90 1000PF_50V
2
@47K 8 9 0.1UF_0805_25V
AGSEN AGND
1
SYSON# <38>
2
100K
@0
2 L_L14
2 2
PC91
100K
PR141
100K
* 2
2
3 PQ30
DTC115EKA <21,30,35,38> SUSP# 100K
3
PQ31
+3VALWP DTC115EUA Layout : "Compensation network close to FB pin"
1
PR142
0_1206
(+1.8V+-5%)
PQ32 +1.8VALWP
SI3445DV PL9
2
5UH SPC-06704-5R0
D
LX1.8
S
6 1 2
1.8VDD 4 5 +3VALWP
1
2
1
1
2
PR143
G
1
@2M PR144 + PC93
(+1.5V+-5%)
3
1
PD29 PQ33 191K_1% PC92 150UF_D_6.3V_FP PR145

2
PC94 RB751V HMBT2222A PD30 2200PF_50V 0_1206 PQ34 +1.5VP

2
2
1
10UF_1206_10V PR146 EC31QS04 SI3445DV PL10

2
1 2 2 10K 5UH SPC-06704-5R0
D
2
LX1.5
150UF_D_6.3V_FP
S
6 1 2
2
L_10
PR147 VS 1.5VDD 4 5
3
1
1
1K PC95 2
1
2200PF_50V
10UF_1206_10V
PC96 @0.1UF_16V PD31 1
2
1
PC97
PC98
2200PF_50V RB751V PR148
G
2
3 PR149 + 3
2
1
1
PC99 PQ35 @2M 191K_1%
2
PC100
0.1UF_50V HMBT2222A
2
2
1
PR150 PD32
2
8
1 2 2 10K EC31QS04
3
+ 3 L_L16
1
PQ36 2 L_L15 1 PR151
L_11
3
1
2SA1036K - 2 1.8V 1 2 2.5VREF 1K PC101
PU9A PC102 @0.1UF_16V
1
2
LM393M PR152 2200PF_50V
4
2
100K
2
0.01UF_50V
PR153
1
8
43K_1%
3
PC103
5 L_LTT
+
1
PQ37 2 L_L17 7 PR221

2
2SA1036K - 6 2 1 2.5VREF
1
4
PU11B 100K_1%
LM393M
2
0.01UF_50V
1
PC152
PR154 PR222
2
215K_1% 162K_1%
1
100K
SUSP 2
1
SUSP 100K
PQ61
3
4
DTC115EKA 4
Title
A B C D
A B C D E F G H
VID_VCC PR155
0 PU12 PL11
1.2VDD +1.2VPP CPU_B+ FBM-L18-453215-900LMA 90T_1812
4 VIN VOUT 5 *
1
+1.2VPP PC108 B++
+3VALWP PC104 2 6 10UF_1210_25V PC109 PC141 +5VALWP
4.7UF_1206_16V PC105 DELAY SENSE CPU_B+ 4.7UF_1210_25V @10UF_1210_25V
@100UF_EC_25V
@100UF_EC_25V
0.068UF_16V 7 1 PC106 PR156
ERROR CNOISE
1
1000PF_50V 0 PC107
PC136
PC137
8 3 PR157 4.7UF_1206_16V PC140 + + PU16
PC138 ON/OFF# GND @10K_1% @10UF_1210_25V PC145 MAX4322EUK-T_SOT23-5
2
@1000PF_50V SI91822DH-12-T1 0.1U PR211
*
2
5
6
7
8
5
6
7
8
5
499_0603_1%
+ 3 2 1 CM1+
CPU_ON 1 2 1
1 CPU_GH1 1
+5VALWP 4 4 - 4 2 1 +CPU_CORE
PR158
VR_ON 0 1 2 PR212 PR213
<30,38> VR_ON
2
2
PD33 PQ38 PQ39 0_0603_5% PR214 1K_0603_1%
2
PR159 0 1SS355 IR7811A IR7811A 2K_0603_1%
PR160 2 1
<16> SWC13V 20 PR162
3
2
1
3
2
1
PL12 0.002_2512_1% 2 1
1
PU13 MAX1718 SSC-1255-0R5
1
PR161 2 0 1 21 27 CPU_LX1 CM1+ 2 1 +CPU_CORE PR215
<7> CPU_VID4 D4 LX 2.2 1K_0603_1%
*
1
PR163 2 100K 1 22 28 L_12 1 2 +CPU_CORE 1K for MB P4 CPU.
<7> CPU_VID3 D3 DH
1
PR165
PR166 2 100K 1 23 26 L_19 PR164 PC110 68_0805 PD35 2K for DT P4 CPU.
<7> CPU_VID2 D2 BST
5
6
7
8
0.1UF_0805_25V PD34 EC31QS04
5
6
7
8
PR167 2 100K 1 24 16 EC31QS04 PR168
2
<7> CPU_VID1 D1 DL
1
CPU_B+ 2.8K_1%
2
PR169 2 100K 1 25 1 4
+3VALWP <7> CPU_VID0 D0 V+
4 PC111 PR171 PR172
2
<33> VGATE 14 9 CPUVCC 220PF_50V 49.9K_1% 68K_1%
PR170 0 VGATE VCC PC112 PQ40 PQ41
PR175 2 1 3 4 0.1UF_0805_25V SI4362DY SI4362DY
150K_1% TIME FB
1 2
CPU_ON PR173 120K 2 13 PQ42
3
2
1
SDN/SKIP POS
1
PC113 PR174 D 2N7002
3
2
1
CPUVDD 17 5 4.7UF_0805_10V 100 +5VALWP 2
VDD NEG PC114 G
PR176 PC115 47PF_50V 6 19 CPU_GL1 1000PF_50V S
3
180K_1% CC ZMODE
+2VREF
PC116 PC117 20 18 CPU_FB
1UF_0805 1UF_0805 OVP SUS PR177
+2VREF 11 8 POS 100K
+2VREF
2 REF S1 PQ43 2
1
ILIM D 2N7002
12 ILIM S0 7
PM_DPRSLPVR_R
* PR178 G
2
* 100K_1%
15 GND TON 10
S
3
PR179 PC142
48.7K_1% PR223 CPU_B+ @10UF_1210_25V
PR180 PC118
* 0@DT *
5
6
7
8
5
6
7
8
53.6K_1% 1000PF_50V PM_STPCPU# <14,16>
1
PC119 PC120 D
4.7UF_1210_25V 10UF_1210_25V 2 PQ44
CPU_GH2 4 4 G 2N7002
PR207 S
3
PC121 100K
PR181 0.1UF_0805_25V PQ45 PQ46
20K_1% IR7811A IR7811A
+5VALWP
PR201 PR182 33K_1% PR183
3
2
1
3
2
1
@0 L_13 ILIM PL13 0.002_2512_1%
SSC-1255-0R5
1 16 CPU_LX2 CM2+ 2 1 +CPU_CORE
ILIM LIMIT
1
PR185 PU14 PQ47 PQ48
5
6
7
8
5
6
7
8
1 200 2 2 MAX1887 15 SI4362DY SI4362DY PR184
TRIG V+ PR186 100K
PC122 3 14 L_14 68_0805 PD36
4700PF_50V CM+ BST EC31QS04
4 4
2
PR187 4 13 PC123 PR204
CM- LX
1
200 2 0.1UF_0805_25V 100K D
1
5 12 L_15 1 2 2 PQ49
CS- DH PC124 G
2
PR189 CPUVDD PR188 220PF_50V 2N7002
6 11 2 1 * <16> PM_GMUXSEL S
3
200 2 CS+ VDD PD37 2.2
1
3
2
1
3
2
1
3 CM1+ 1SS355 3
7 10
PC127 COMP DL PC126
4700PF_50V PC125 PR190 8 9 1UF_0805 CPU_GL2
PR191 470PF_50V 1K_1% GND PGND
1 200 2
PR202 0
PC128 PC129
1
CPU_B+ 4.7UF_1210_25V 10UF_1210_25V D PQ59
2 2N7002
5
6
7
8
5
6
7
8
PM_DPRSLPVR_R
PR193 1 16 L_16 ILIM PC143
* PC144
* G
200 2 ILIM PU15 LIMIT
1 S
3
2 MAX1887 15 PR192 33K_1% @10UF_1210_25V @10UF_1210_25V
TRIG V+
4 4
PC130 3 14 L_17
PR194 4700PF_50V CM+ BST PQ51 PQ52 PR205
*
1
200 2 PC131 PR195 IR7811A IR7811A 100K D
1 4 13
CM- LX 0.1UF_0805_25V 2.2 PM_DPRSLPVR
<16> PM_DPRSLPVR 2
PR196 5 12 L_18 2 1 G
200 2 CS- DH PQ50
1 S
3
2
1
3
2
1
3
6 11 CPUVDD 2 1 PL14 PR198 2N7002
CS+ VDD
1
PC132 PR197 1K_1% PD38 CPU_GH3 SSC-1255-0R5 0.002_2512_1% D
4700PF_50V CM1+ 7 10 1SS355 CPU_LX3 CM3+ 2 1 +CPU_CORE 2
PR199 COMP DL G
1
1 200 2 PC133 8 9 PC134 S
3
GND PGND
5
6
7
8
5
6
7
8
470PF_50V 1UF_0805 PR200 PQ53
68_0805 @2N7002
PD39
4 4 EC31QS04
2
1
PR206
1
PQ54 PQ55 @100K D
SI4362DY SI4362DY PC135 2
2 220PF_50V G
4 4
<7,31> NB/DT#_CPU S
3
PQ57
3
2
1
3
2
1
@2N7002
GMUXSEL STPCPU# DPRSLPVR VCORE' Offset VCORE CPU_GL3
PM 1 1 0 1.30V 0% 1.30V
PM D-S 1 0 0 4.62% 1.2309V Compal Electronics, Inc.
Title
BM 0 1 0 1.20V 2.0% 1.176V SCHEMATIC, M/B LA-1381
BM D-S 0 0 0 4.62% 1.144V AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R ev
Deeper X 0 1 1.0V 0% 1.0V MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401212 2B
A B C D E F G H
10 9 8 7 6 5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

H H
Item Fixed Issue Reason for change Rev. PG# Modify List B.Ver# Phase
G G
F F
E E
D D
C C
B B

A A
Title
401212
Custom
10 9 8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1

I tem Fixed Iss ue Rea son for change PA GE Mod ify List M. B. V er.
H H
1 Footprint error 4 Change R96 footprint to 0402 0 .2
5 Change RP6 footprint to 0402
7 Change RP8, RP86, RP87, R P89 and RP90 footprint to 0402
27 Change RP91 footprint to 0402
2 Power saving 6 Change C190. 1, R292. 2, R434. 2 and U 27. 8 connect from +12VALW to +12VS 0 .2
G G
Change D16. 1, D13. 1, Q 23. 1 and Q 24. 1 c onnect from +5VALW to +5VS
Change R433. 1 and R220. 1 connect from +3V to +3VS
3 No design requirement 7 Delete U 10 and C178 0 .2
17 Del ete RP7
F 21 Delete C62 1 and C623 F
22 Delete J8, C611, C612, L55 and L57
4 N o requirement for VGA board 15 Change JP3. 48 net fr om EC_PWR_ON# to N.C. 0 .2
5 Div ider c ir cuit for U62( AC97 CODEC ALC201 ) 21 A dd R503, R504, R507 a nd R508 6.8K 0 .2
6 Los t connected net for L59 22 Connec t L59. 2 to LINECL_OUT_L 0 .2

E E
7 Modify Bas e I / O A ddres s for U48( SUPER I/O SMsC LPC47N227 ) 27 Change R491 v alue from 10K_ 040 2 to @10K_0402 0 .2
Change R135 v alue from @ 10K_ 04 02 to 10K_0402
8 S olve Touch Pad no function issue 30 Change RP82. 3 net from TPA D _ON/OFF# to N.C. 0 .2
9 Prevent power leak age 30 Change RP80. 3 net from M _SEN# to N.C. 0 .2
D D
A dd R509 100K pull-hi gh to +3VS for M_SEN#
10 Modify b rig ht of D28 31 Change Q 33. 3 net from +3VALW to+5VALW 0 .2
11 S olve D28 can't work issue 31 Relayo ut for D28 0 .2
12 Solv e USB2 no function issue 31 Relay out for JP19 0 .2
C C
13 Solve power on fail issue 32 Delet e R183 0 .2
Change R271 from 0_ 0402 to 68K _0402
14 Modify net name for SW1 32 E xc hange V O L_IN_UP# and VOL_IN_DN# 0 .2
15 B I O S req u es t f or MDC 35 A dd R510 10K pull-d own to GND for JP24.108 0 .2
B 16 Modify U SB application 17 Change R157. 1 net fr om OVCUR#0 to OVCUR#5 0 .2 B

Change R160. 1 net fr om OVCUR#1 to OVCUR#3
Change R169. 1 net fr om OVCUR#2 to OVCUR#4
31 Change L26. 1 net from U SBP1+ to USBP3+

Change L27. 1 net from U SBP1- to USBP3-
A dd F5, C671, C672, C673, C674, R511, R51 2, L67, L68 and JP32
A
Title
401212
Custom
10 9 8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1

I tem Fixed Iss ue Rea son for change PA GE Mod ify List M. B. V er.
H H
17 For M. E . request 15 A dd JP33, R513, R514, D42 , D43 and Q62 0 .2
Change JP3. 8, JP3. 10, JP3. 9 4, JP3.96, JP2.84 and JP2.86 net to N.C.
Change JP3. 98 net f rom INVPWR_B+ to LVDS_BLON#
31 A dd JP34
32 Change JP5 for new connector

G G
18 Dis c h arge circuit for +12VS and +2.5VS 36 A dd R515, R516, Q 63 and Q64 0 .2
19 For USB2.0 can't fast speed 26 Change L73, L75, L76, L7 9 to 0_0603 0 .3
U 66 pin112 c onnec tor c ha nge to GNT#3,pin113 connector change to REQ#3
20 Signal H_ THE R MTRIP# Design change 5 A dd R632 and Q76 0 .3
Chan ge VL to +5VS
21 Remove serial port connector 28 A dd R633 and RP141 0 .3
29 Canc el U 4, C40, C1, C414, C415, C416, CP1, CP2 ,JP16
F 35 U pdate JP20 pin151, 152, 101, 102, 103, 104, 10 5,106 Name F
A dd net RIA0
22 C hange M_ SE N # R509 from 100K_ 0402 to 10K_ 0402 31 Change R509 from 100K_ 0402 to 10K_ 0402 0 .3
23 For s c he matic R568 711@ error 23 Change R568 711@ 0_ 0402 to 6912@ 0_ 04 02 0 .3
24 BT LE D SP EC update 32 Change D28 to new part 0 .3
A d d WL_LED
25 A d d sub-woofer soluction 22 A dd SUB@ 0 .3
26 A dd U SB1.1 port 32 A dd USB3 port 0 .3
27 A dd F an EMI soluction 6 A d d C 7 5 1 / C752/ C753/ C754/ C746/ C747/ C234 0 .3
E E
28 E C add MA IL_LED# 30 Change U 24_ pin162 to MAIL_LED# 0 .3
A dd U 24_ pin24 E C_ M UTEI#
29 Chang e audio amp power source 22 Change +5VALW to VDDA 0 .3
30 Change CD_ AGND connect to AGND 21 Change fr om GND to GNDA 0 .3
31 711 op tion cancel 23,27 Del 711@ 0 .4
32 A dd EMI request(FAN) 6 A dd C222/ C754/ C753/ C747 and c hange C746 to 220P 0 .4
33 A dd EMI request(HDD) 19 A dd R517/ R518/ C675/ C676 0 .4
34 SD c o ntrol vender recommend 27 R149 c hange to 1M/ A dd 4.7K pull-down 0 .4
D D
35 circuit update 30 JP27 pin10 c han ge to MAIL_LED# 0 .4
36 Add capacitance for audio noise 3 2 , 3 5, 36 A d d C 7 5 8 / C 7 5 9 / C760/ C761/ C762/ C763/ C764/ C765/ C766/ C767/ C768 0 .4
37 A dd POW E R VGATE recommend 33 A dd R665/ C7 57 0 .4
38 Change A CL201 to ACL202 21 Change CLK inpu t to 14MHZ 0 .4
39 A dd crystal for ALC202 21 A dd Y2, R475, C468, C469 Del R492,R480 0 .5
40 Power noise issue 30 Change C3 66 to @ 0 .5
41 Customer request 32 Chang e D45 to Green LED 0 .5
C C
B B
A
Title
401212
Custom
10 9 8 7 6 5 4 3 2 1
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Roverbook Voyager H570L Compal - La-1381 - r2b - Schematics

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Roverbook Voyager H570L Compal - La-1381 - r2b - Schematics

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A B C D E F G H I J

uFCBGA/uFCPGA Northwood with

1394@ SKU W/1394 controller 要打 TOP

Date: 星期一, 十二 ?30, 2002 Sheet 1 of 46

Mobile Northwood Thermal Sensor Clock Generator

LM75 thermal Memory

PCI BUS ICH3-M 3.3V 48MHz

Slot 0 IDE Connector AC97

BIOS PS/2 conn FIR FDD

Power Managment table

S5 S4/AC ON OFF OFF

A#32 D#29 HD#30

Place resistor <100mils from +1.2VP

ITP_TDI ITP_CLK0 H_VSSA +CPU_CORE

W =1 5mil Trace width>=7mila +5VS R171

C198 1K_0402 R176

10K_0402 <30> PROCHOT#

R199 R195 4/29 update

Address:1001_110X SCHEMATIC, M/B LA-1381

Layout note : +CPU_CORE

C123 C115 C159 C116 C448 New add

For Mobile CPU Mobil CPU Destop CPU

R390 DT : REMOVE 0.900V 1 0 0 1 1 X X X X X

NB/DT#_CPU <31,43> 0.850V 1 0 1 0 1 X X X X X

H_SWNG0 AA7 AC16 H_DSTBP#3 A3 J4 Layout note :

R68 C88 H_SWNG1 AD13 A7 J6 +1.8VS

HVREF0 VSS10 VSS40

HVREF1 49.9_1% Trace

BROOKDALE(MCH-M) R65 C102 C103 R_C

+1.5VS AGP_PIPE# 2 7 .01UF_0402

2 1 AGP_ADSTB0 2 1 AGP_ADSTB0# AGP_ST1

R41 8.2K_0402 R40 @8.2K_0402 1=System memory is SDR AGP_ST2 2 1

H10 AA4 DDR_SDQ43 E8 G18 DDR_SMA3

Layout note : DDR Memory interface

.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R

C114 C96 C105 C85 C97 C119

C126 C86 + C75

B C130 C127 C132 C133 B

8 PAD10 PAD11 PAD12

Place one cap close to every 2 pull up resistors termination to

C258 C257 C337 C321

1 +3VS L23 +3V_CLK 1

to CK_TITAN 14.318MHZ C93 C87

R129 +3VS R671 1 2 DT@1K_0402 R81 1 2 49.9_1%

R365 1 2 DT@1K_0402 R106 49.9_1%

Please closely pin42 23 CLK66_MCH R74 1 2 33.2_1%

5 R77 CLK_ICH48M CLKPCI_F2 5

PCICLK0 CLK_PCI_1394 <25>

C101 C112 C117

AGP 100X2 Pin connector JP33

C 46 C 35 C406 C129 C431 C432 C 22 C 65 C 64 Q42 Width=60 mils

TV_OUT CONNECTOR CRT CONNECTOR

S@75_0402 S@270PF_0402 S@330PF_0402 @470PF_0402

R385 10K_0402 AD10 L4 M1

C516 AD18 G4 Y6 +CPU_CORE

AD21 PCI_AD20 SMLINK1

C515 AD26 PCI_AD25

AD29 PCI_AD28 CPU_DPSLP# H_ F ERR#

PCI_REQ#1 HUB_PD7 H UB_PD8 3904

EEP_SHCLK <20> Close t o ICH3-M.

C566 C582 +1.8VS 1K_0402

1. Place R_G and R_H in middle of Bus. LAN_TXD2 <20>

301_1% Closely ICH3