LH53259 CMOS 256K (32K × 8) MROM

FEATURES PIN CONNECTIONS

• 32,768 words × 8 bit organization
28-PIN DIP TOP VIEW

• Access time: 150 ns (MAX.)

28-PIN SOP

• Low-power consumption: NC 1 28 VCC

A12 2 27 A14
Operating: 137.5 mW (MAX.)
A7 3 26 A13
Standby: 550 µW (MAX.)
A6 4 25 A8
• Programmable output enable A5 5 24 A9
A4 6 23 A11
• Static operation A3 7 22 OE/OE

• TTL compatible I/O A2 8 21 A10

A1 9 20 CE
• Three-state outputs A0 10 19 D7
D0 11 18 D6
• Single +5 V power supply
D1 12 17 D5
• Packages: D2 13 16 D4
GND 14 15 D3
28-pin, 600-mil DIP
28-pin, 450-mil SOP
53259-1
28-pin, 8 × 13.4 mm2 TSOP (Type I)
Figure 1. Pin Connections for DIP and
• JEDEC standard EPROM pinout (DIP) SOP Packages

DESCRIPTION 28-PIN TSOP (Type I) TOP VIEW

The LH53259 is a mask-programmable ROM organ-
ized as 32,768 × 8 bits. It is fabricated using silicon-gate OE/OE 1 28 A10
CMOS process technology. A11 2 27 CE
A9 3 26 D7
A8 4 25 D6
A13 5 24 D5
A14 6 23 D4
VCC 7 22 D3
NC 8 21 GND
A12 9 20 D2
A7 10 19 D1
A6 11 18 D0
A5 12 17 A0
A4 13 16 A1
A3 14 15 A2

53259-7

Figure 2. Pin Connections for TSOP Package

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LH53259 CMOS 256K MROM

A14 27
A13 26
A12 2 MEMORY
A11 23 MATRIX
A10 21 (32,768 x 8)

ADDRESS DECODER
ADDRESS BUFFER
A9 24
A8 25
A7 3
A6 4
A5 5
COLUMN SELECTOR
A4 6
A3 7
A2 8
A1 9
A0 10
SENSE AMPLIFIER

CE
CE 20 BUFFER TIMING
GENERATOR

OUTPUT BUFFER

OE
OE/OE 22 BUFFER

28 14 11 12 13 15 16 17 18 19
VCC GND D0 D1 D2 D3 D4 D5 D6 D7

NOTE: Pin numbers apply to the 28-pin DIP or SOP.

53259-2

Figure 3. LH53259 Block Diagram

PIN DESCRIPTION
SIGNAL PIN NAME NOTE SIGNAL PIN NAME NOTE
A0 – A14 Address input VCC Power supply (+5 V)
D0 – D7 Data output GND Ground
CE Chip enable input NC No connection
OE/OE Output enable input 1
NOTE:
1. The active level of OE/OE is mask-programmable.

TRUTH TABLE
CE OE/OE MODE D0 - D7 SUPPLY CURRENT NOTE
H X Standby 1
Non selected High-Z
L/H
L Operating
H/L Selected DOUT
NOTE:
1. X = H or L ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Supply voltage VCC –0.3 to +7.0 V

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CMOS 256K MROM LH53259

Input voltage VIN –0.3 to VCC +0.3 V

Output voltage VOUT –0.3 to VCC +0.3 V
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +150 °C

RECOMMENDED OPERATING CONDI-

TIONS (TA = 0 to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage VCC 4.5 5.0 5.5 V

DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C)

PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Input ‘Low’ voltage VIL –0.3 0.8 V
Input ‘High’ voltage VIH 2.2 VCC + 0.3 V
Output ‘Low’ voltage VOL I OL = 1.6 mA 0.4 V
Output ‘High’ voltage VOH I OH = –400 µA 2.4 V
Input leakage current | ILI | V IN = 0 V to VCC 10 µA
Output leakage current | ILO | V OUT = 0 V to VCC 10 µA 1
ICC1 t RC = 150 ns 25
mA 2
ICC2 t RC = 1 µs 20
Operating current
ICC3 t RC = 150 ns 20
mA 3
ICC4 t RC = 1 µs 15
ISB1 CE = V IH 2 mA
Standby current
ISB2 CE = V CC – 0.2 V 100 µA
Input capacitance CIN f = 1 MHz 10 pF
Output capacitance COUT T A = 25°C 10 pF
NOTES:
1. CE/OE = VIH or OE = VIL
2. VIN = VIH/VIL, CE = VIL, outputs open
3. VIN = (VCC – 0.2 V) or 0.2 V, CE = 0.2 V, outputs open

AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Read cycle time tRC 150 ns
Address access time tAA 150 ns
Chip enable access time tACE 150 ns
Output enable time tOE 10 80 ns
Output hold time tOH 5 ns
CE to output in High-Z tCHZ 70 ns
1
OE to output in High-Z tOHZ 70 ns
NOTE:
1. This is the time required for the output to become high impedance.

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LH53259 CMOS 256K MROM

AC TEST CONDITIONS
PARAMETER RATING

Input voltage amplitude 0.6 V to 2.4 V

Input rise/fall time 10 ns
Input reference level 1.5 V
Output reference level 0.8 V and 2.2 V
Output load condition 1TTL + 100 pF

tRC

A0 - A14

tAA (NOTE)

CE
tACE (NOTE) tCHZ

OE
OE
tOE (NOTE) tOHZ

tOH

D0 - D7 DATA VALID

NOTE: Data becomes valid after the intervals tAA, tACE, and tOE from address
inputs, chip enable and output enable, respectively have been met.
53259-3

Figure 4. Timing Diagram

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CMOS 256K MROM LH53259

PACKAGE DIAGRAMS

28DIP (DIP028-P-0600)

28 15

DETAIL

13.45 [0.530]
12.95 [0.510]

1 14 0° TO 15°
0.30 [0.012]
36.30 [1.429]
0.20 [0.008]
35.70 [1.406]

15.24 [0.600]
4.50 [0.177] TYP.
4.00 [0.157]

5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]

0.51 [0.020] MIN.

2.54 [0.100] 0.60 [0.024]
TYP. 0.40 [0.016]

MAXIMUM LIMIT
DIMENSIONS IN MM [INCHES]
MINIMUM LIMIT 28DIP-2

28-pin, 600-mil DIP

28SOP (SOP028-P-0450)

1.27 [0.050]
0.50 [0.020] TYP.
0.30 [0.012]
1.70 [0.067]

28 15

8.80 [0.346] 12.40 [0.488]

10.60 [0.417]
8.40 [0.331] 11.60 [0.457]

1 14
1.70 [0.067]
18.20 [0.717] 0.20 [0.008]
17.80 [0.701] 0.10 [0.004]

0.15 [0.006]

1.025 [0.040]

2.40 [0.094]
2.00 [0.079]

0.20 [0.008]
0.00 [0.000]
1.025 [0.040]

MAXIMUM LIMIT
DIMENSIONS IN MM [INCHES]
MINIMUM LIMIT
28SOP

28-pin, 450-mil SOP

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LH53259 CMOS 256K MROM

28TSOP (TSOP028-P-0813)

0.28 [0.011] 0.55 [0.022]

0.12 [0.005] TYP.

28 15

12.00 [0.472] 13.70 [0.539] 12.60 [0.496]

11.60 [0.457] 13.10 [0.516] 12.20 [0.480]

1 14

8.20 [0.323]
7.80 [0.307] 0.20 [0.008]
0.10 [0.004]
0.15 [0.006]
1.10 [0.043] DETAIL
0.90 [0.035]

1.20 [0.047] 0 - 10°

MAX.

0.425 [0.017] 0.425 [0.017]

0.20 [0.008]
1.10 [0.043]
0.00 [0.000]
0.90 [0.035]

MAXIMUM LIMIT 0.20 [0.008]

DIMENSIONS IN MM [INCHES] 0.00 [0.000]
MINIMUM LIMIT 28TSOP

28-pin, 8 × 13.4 mm2 TSOP (Type I)

ORDERING INFORMATION

LH53259 X
Device Type Package

D 28-pin, 600-mil DIP (DIP028-P-0600)

N 28-pin, 450-mil SOP (SOP028-P-0450)
T 28-pin, 8 x 13.4 mm2 TSOP (Type I) (TSOP028-P-0813)

CMOS 256K (32K x 8) Mask Programmable ROM

Example: LH53259D (CMOS 256K (32K x 8) Mask Programmable ROM, 28-pin, 600-mil DIP)
53259-6

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