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fully edited. Content may change prior to final publication. Citation information: DOI
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A Near-State Three-Dimensional Space Vector

Modulation for a Three-Phase Four-Leg Voltage
Source Inverter
Min Zhang, David Atkinson, Bing Ji, Member, IEEE, Matthew Armstrong, and Mingyao Ma,
Member, IEEE

 distributed generation systems are required to sometimes

Abstract—A near-state three-dimensional space vector
modulation (NS 3-D SVM) switching scheme, which aims to
reduce the common-mode noise in a three-phase four-leg voltage
source inverter, is proposed. The impact of common-mode noise,
which is related to EMI issues for a high-voltage level four-leg
system, is investigated first. Identification of the section in a 3-D
space, selection of the near-state switching vectors and sequence
of the selected switching vectors are then introduced in steps to
describe the proposed switching scheme. The proposed switching
scheme is based on classical 3-D SVM, producing higher DC link
utilization, less harmonic content and reduced switching loss
compared to sinusoidal PWM. Theory, simulation and
experimental results show that the near-state 3-D SVM can work
under both balanced and unbalanced load conditions.
Index Terms—Common-mode voltage (CMV), electromagnetic
interference (EMI), near-state three-dimensional space vector
modulation (NS 3-D SVM), classical three-dimensional space
vector modulation (3-D SVM), three-phase four-leg voltage
source inverter (VSI).
I. INTRODUCTION
T HREE-PHASEfour-leg voltage source inverters (VSIs)
are widely used in distributed power generation
applications, three-phase UPS systems and islanded operation
of a three-phase system where the balanced three-phase
voltage output is required when the loads are unbalanced [1-
9]. There are a number of power converter applications where
an unbalanced load needs to be catered for. These include
three-phase converter systems for uninterruptable power
supplies (UPS). There are also cases where grid-connected
This paper was submitted in Jan, 2014.
Min Zhang was with the School of EEE, Newcastle University, UK
(zhangmin@hotmail.co.uk).
David Atkinson is with the School of EEE, Newcastle University, UK
(dave.atkinson@ncl.ac.uk).
Bing Ji is with the School of EEE, Newcastle University, UK
(bing.ji@ncl.ac.uk).
Matthew Armstrong is with the School of EEE, Newcastle University, UK
(matthew.armstrong@ncl.ac.uk).
Mngyao Ma is with the School of EEE, Newcastle University, UK
(mingyao.ma@ncl.ac.uk).
operate in islanded mode to supply local loads when the grid
supply is temporarily lost. Systems of this nature are based on
gas-turbines or renewable energy sources such as PV. To
correctly supply the unbalanced load there must be a neutral
connection back to the power converter. It is possible to
connect the neutral to the centre of a split dc link capacitor
bank. This approach requires a very large dc link capacitance
values to handle the line frequency neutral current. An
alternative approach is to connect the neutral to a fourth
inverter leg. The fourth-leg solution of a three-phase inverter
is especially suited for systems with zero-sequence current
path since negative-sequence current paths can be controlled
by dual current controllers[10]. A three-dimensional space
vector modulation (3-D SVM) switching scheme for a four-leg
VSI, has the advantage of higher DC link utilization, less
harmonic content and less switching loss compared with
sinusoidal PWM[1]. The only drawback of 3-D SVM is that it
requires complex procedures to calculate the duty ratios for
each leg and could become a computational burden [11-13].
Other switching schemes, which aim to simplify the 3-D SVM
either uses space vector method [14-16] or carrier based scalar
method [11, 12, 17, 18]. These schemes have the same output
performance as the 3-D SVM based on the fact the duty ratio
waveforms are the same as 3-D SVM.
The effect of common-mode voltage (CMV) noise, which is
related to the EMI problems for a high voltage level power
system has been investigated extensively for a three-phase
variable speed drive (VSD) and methods to mitigate the noise
have been introduced in [19-22]. However, the impact of 3-D
SVM on common-mode noise problems has rarely be seen in
the literature survey [23], therefore it draws the attention of
research.
The high repetition of the common-mode voltage due to the
fast switching transitions of the modern power devices,
through parasitic capacitance, creates a common-mode current
path [21] as shown in Fig. 1. On this path, the gate driver
circuit, DSP interface board and sensor circuit are all EMI
sensitive [24] and the vicinity of the system could be affected
by the EMI noise[25]. The impact of CMV can be reduced by
implementation of passive or active filter component[26]; this
means the increase of size and cost of the system [20].

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Fig. 1 Common-mode current path and EMI issues in a three-phase four-leg voltage source inverter

TABLE I COMMON-MODE VOLTAGE LEVEL WITH DIFFERENT SWITCHING STATES

pppp nnnp pnnp ppnp npnp nppp nnpp pnpp
Vao VDC/2 -VDC/2 VDC/2 VDC/2 -VDC/2 -VDC/2 -VDC/2 VDC/2
Vbo VDC/2 -VDC/2 -VDC/2 VDC/2 VDC/2 VDC/2 -VDC/2 -VDC/2
Vco VDC/2 -VDC/2 -VDC/2 -VDC/2 -VDC/2 VDC/2 VDC/2 VDC/2
Vfo VDC/2 VDC/2 VDC/2 VDC/2 VDC/2 VDC/2 VDC/2 VDC/2
Vno VDC/2 -VDC/4 0 VDC/4 0 VDC/4 0 VDC/4
pppn nnnn pnnn ppnn npnn nppn nnpn pnpn
Vao VDC/2 -VDC/2 VDC/2 VDC/2 -VDC/2 -VDC/2 -VDC/2 VDC/2
Vbo VDC/2 -VDC/2 -VDC/2 VDC/2 VDC/2 VDC/2 -VDC/2 -VDC/2
Vco VDC/2 -VDC/2 -VDC/2 -VDC/2 -VDC/2 VDC/2 VDC/2 VDC/2
Vfo -VDC/2 -VDC/2 -VDC/2 -VDC/2 -VDC/2 -VDC/2 -VDC/2 -VDC/2
Vno VDC/4 -VDC/2 -VDC/4 0 -VDC/4 0 -VDC/4 0

Industrial solutions often include proper grounding and
shielding for a very wide range of frequencies [21].
Alternatively certain PWM switching schemes can be
implemented to reduce the CMV for a three-phase VSD
system and this approach has been proved to be the most
economical [19, 20, 23] since there’s no extra hardware
components required. However, the CMV reducing PWM
requires complex switching algorithm and sometimes have
their limiting operational range as it will be seen in the
following parts of the paper.
For a three-phase four-leg VSI, the CMV is defined as the
potential difference of the star point of the load with respect to
the midpoint of the DC link capacitors Vno as shown in Fig. 1.
This is based on the assumption that Vogis small and varying
slowly [20, 22]. Therefore the relation between the CMV and
the phase voltage can be defined as follows[27]:
vao  vbo  vco  vfo
vno  (1)
4
Depending on the switching states of the VSI, Vao, Vbo, Vco
and Vfo have ±VDC/2 voltage levels. Therefore for a four-leg
VSI, the existing voltage levels of the common-mode voltage
will show ±VDC/2, ±VDC/4 and 0 depending on the 16
switching states of the inverter. The details of the CMV
according to different switching states are shown in Table I.
During the transient between the switching states, the CMV
changes by ±VDC/4. The switching schemes for the four-leg
inverter, either 3-D SVM or carrier-based PWM, exhibit high
CMV that poses problems in the high power application.
In [23, 28], a common-mode voltage mitigation method was
proposed by only utilizing the six switching states that have
zero CMV. However, this switching scheme cannot work
properly under unbalanced load condition and simultaneous
switching actions between different phases are required,
therefore it cannot be implemented in a practical system[20].
References [20, 25] suggest that by avoiding utilizing the
two zero switching states pppp and nnnn, the CMV level
should be limited to ±VDC/4. Unlike the three-leg inverter
which only has 8 switching states, the four-leg VSI has 16
switching states; this makes the selection of the non-zero
switching vectors more difficult. Therefore the steps that are
required to synthesize the rotating reference vector are
different with the classical 3-D SVM.
This paper proposes a near-state three-dimensional space
vector modulation (NS 3-D SVM) switching scheme for a
three-phase four-leg VSI. The proposed switching scheme
reduces the CMV level of the inverter to be ±VDC/4 while
maintaining the merit of classical 3-D SVM. The technique of
implementation of the proposed switching scheme in a real-

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time DSP system has been introduced. Simulation and pppn

experimental results validate the effectiveness of the NS 3-D
pnpn npnx ppnx
SVM. Analysis for a four-leg VSI based on space vector ppnn
method verifies and compares the performance of both NS 3- ⃗ ref
D SVM and the classical 3-D SVM. pnnn pnnx
B1

II. NEAR-STATE THREE-DIMENSIONAL SPACE VECTOR nppx

MODULATION
nnpx pnpx β
According to [1], the switching vectors in the α-β-γ pnpp ppnp
coordinate can be calculated based on the Clarke α
transformation shown in Eq.(2) γ

2 1 1  pnnp
 X    3  3  3  X a 
-β α
nnnp
   1  1  X  Section I Sector B1
X    0  b (2)
3   
Fig. 3 Definition of Section I in a 3-D space and its projection on α-β
 X   3 coordinate
  1 1 1  X c 
 3 3 3 
ppnn ppnn
Based on (2), the switching vectors can be obtained in a pnpn pnpn
three-dimensional space. The theory of the switching vectors
pnnn pnnn
in a 3-D α-β-γ coordinate has already been introduced in [1, pnnn pnnn
2], therefore in this paper, the definition of 3-D space vectors
will not be covered.
pnpp pnpp ppnp ppnp
pppn pppn pppn

pnnp pnnp pnnp

pnpn ppnn ppnn nppn pnnp
ppnn Section I Set B
Section I Set A
pnnn pnnn npnn
npnn
ppnn ppnn ppnn
pnnn ppnn
npnn npnn pnnn

pnpp ppnp
ppnp nppp
ppnp ppnp
ppnp ppnp ppnp
pnnp pnnp pnnp npnp
npnp npnp
pnnp npnp
nnnp nnnp Section II Set A Section II Set B
nnnp
Section II Section III
Section I
Fig. 4. Selection of the near-state switching vectors in Set A, Set B
pppn pppn pppn of Section I and II

pnpn Instead of having prism and tetrahedron identification,

nppn nppn pnpn
unique section identification is required and therefore the
npnn nnpp nnpn nnpn pnnn selected adjacent switching vectors and the duration of each
applied switching vector are different with those of classical 3-
D SVM. Sequencing of the selected switching vectors follows
different rules. Synthesis of the reference vector takes the
following steps: (1) section identification; (2) selection of
nppp near-state switching vectors; (3) projection of the reference
nppp pnpp vector; (4) sequencing of the selected switching vectors. The
nnpp details are given in the following sections.
npnp pnpp nnpp pnnp
nnpp
nnnp nnnp nnnp A. Section Identification
Section IV Section V Section VI Just as the six prisms defined in the classical 3-D SVM, six
Fig. 2. Definition of section identification of near-state 3-D SVM sections can be identified. They are numbered Section I
through Section VI, as shown in Fig. 2. Half of the two
adjacent prisms form the complete defined section. For

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instance, Section I consists half of Prism VI and half of Prism

I. Still based on the projection of the reference switching
vector on the α-β coordinate, the projection of Section I lies in
Sector B1 which is between 330° and 30° on α-β plane as
shown in Fig. 3. Therefore, the criteria to determine in which
section the reference vector lies relies on the projection of the
reference vector in α-β coordinate.
B. Selection of Near-state Switching Vectors
When the reference switching vector is located in Section I,
i.e. the projection of the reference vector is within sector B1,
four non-zero switching vectors are needed to synthesize the
reference vector. In order to minimize the circulating energy,
therefore reducing the current ripple and harmonic contents, Fig. 6 Comparison of harmonic contents based on the output voltages of
switching vectors adjacent to the reference vector should be Schem1 and 3; zoomed in version showing harmonic contents at 3rd-9th
selected. In this case, the adjacent switching vectors are called
TABLE II SET SELECTION TABLE
near-state switching vectors[20] and there are altogether eight
Section
switching vectors that are adjacent to the reference vector, I II III IV V VI
Set selection
four of which will be chosen. Selection of the switching
Scheme 1 Set A Set A Set A Set A Set A Set A
vectors must be based on the following rules:
 Reduced common-mode voltage level Scheme 2 Set B Set B Set B Set B Set B Set B

 Simultaneous switching between the phases must be Scheme 3 Set A Set B Set A Set B Set A Set B
avoided Scheme 4 Set B Set A Set B Set A Set B Set A
 Minimum switching loss
 High DC link utilization
 Work under both balanced and unbalanced load The principle behind the selection is that simultaneous
conditions switching actions between phases should be avoided. Here we
name the switching vector of pnpx (where x=p or n) as ⃗ 1, the
Based on these rules, only two sets of four switching
switching vector of pnnx as ⃗ 2 and ⃗ 3 and the switching vector
vectors can be selected to synthesize the reference vector in
each section. Fig. 4 shows the two sets of switching vectors in of ppnx as ⃗ 4.Hence the duration times of the applied
Section I and Section II. As it can be seen, each set consists of switching vectors are named as d1, d2, d3 and d4.
two tetrahedrons that lie in two prisms. Therefore the reference switching vector can be represented
In Section I, for Set A, switching vectors of pnpp, pnnp, as
    
pnnn and ppnn are selected while for Set B, switching states of Vref  d1V 1  d 2V 2  d 3V 3  d 4V 4 (3)
pnpn, pnnn, pnnp and ppnp are selected. It can be seen that the
switching states pnnn and pnnp are selected in both cases When sequencing these two sets in Section I, it has been
since these two switching vectors are the closest to the found that the switching patterns for the first three phases are
reference vector. One of the two switching states of pnpp and exactly the same while for the fourth leg, the switching
pnpn is selected, and the fourth switching state will then be patterns show opposite polarity as it can be seen in Fig. 5. The
decided based on the third switching state that has been just effect of both sets therefore is the same. So for each section,
selected. one set of switching vectors will be used to synthesize the
reference switching vector. The choice of sets in each section
will lead to different levels of harmonic content and ripple in
the output voltage and will be discussed later. It is also noted
in Fig. 5 that one of the phases is not switched during one
VDC/2
PWM cycle, which indicates a third of the switching loss has
been saved. There is no simultaneous switching action
-VDC/2
between the phases. Also it is shown clearly that the CMV
VDC/2
-VDC/2 level has been reduced to ±VDC/4 as expected.
VDC/2 There are four schemes in terms of set selection in each
-VDC/2 section as shown in Table II. In effect, Scheme 1 and 2 belong
VDC/2 to the same class since they choose either Set A or B to
-VDC/2 sequence the selected switching vectors. As a result they have
VDC/4
-VDC/4
the same output voltage waveform while Scheme 3and
Scheme 4 chose Set A and B alternatively, so they have
Fig. 5 Switch pulse pattern and CMV, near state 3-D SVM
different output features compared to Scheme 1 and 2. It has

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been found that the harmonic content and the voltage ripple of Phase A
the output voltage of Scheme 1 or 2 are slightly higher than
that of Scheme 3 or 4 as it can be seen in the FFT analysis Phase B

Duty ratio
(Fig. 6) based on the output voltages of both schemes.
Therefore, Scheme 3 is selected in the proposed 4th leg
implementation as shown in Fig. 7.
Phase C
C. Projection of the Reference Vector
The duration of each applied switching vector can be
computed by projecting the reference rotating vector onto the Fig. 8 Simulated duty ratio waveform of the proposed near-state 3-D
switching vectors, which is similar to the classical 3-D SVM. SVM with one carrier waveform (Mi=0.84)
The difference in this case is that instead of utilizing the zero
switching vectors ( ⃗ Z= pppp or nnnn or both), four non-zero When the reference vector is located in the sets of other
switching vectors are utilized; therefore a 4×4 matrix is given sections, the only feature that needs to be changed is the
as below (Assuming the reference vector lies in Set A of matrix in (3). The corresponding near-state switching vectors
Section I) : for all the sets in different sections are shown in Appendix A
 3  and the matrices that are needed to compute the duty ratios for
3
  0 1 each phase are shown in Appendix B.
 d1   2 2  V 
 1 3   _ ref D. Sequencing of the Selected Switching Vectors
d 
1  2  1 0  V 
 2 2   _ ref  The classical 3-D SVM has many sequencing schemes with
 d 3  V DC  5 3

V  (4) the option of choosing either one or two ZSVs. Unlike the
    1  1   _ ref 
d 4   2 2   V DC 
classical 3-D SVM, the sequencing of the near state 3-D SVM
 3 3  is straight forward with the constraints of minimum switching
 0 1 actions, no simultaneous switching actions between the
 2 2  phases, and reduced CMV. The symmetrical aligned scheme is
chosen for the reason that it has less harmonic distortion
compared with falling-edge or rising edge scheme[1].
ppnn ppnn
Therefore there is only one sequence in terms of sequencing of
pnnn pnnn the selected switching vectors, and it is ⃗ 1- ⃗ 2- ⃗ 3- ⃗ 4- ⃗ 3- ⃗ 2-
⃗ 1.The switching states related to the switching vectors are
shown in Appendix C.
pnpp
ppnp E. Duty Ratio Waveform of Near-state 3-D SVM
npnp A simulation model has been built in Matlab/Simulink and
pnnp
Matlab/Simpower, with the switching algorithm written in a S-
Section I Set A Section II Set B
function block. A balanced linear load is used to show the
nppn nppn effect of the duty ratio waveforms on each phase. In order to
obtain a balanced three-phase output voltage, a rotating
npnn npnn
reference vector on the α-β coordinate has to be supplied. The
following reference voltages represent the reference switching
vector[1]
ppnp
nppp V _ ref  cos(t ) 
 
  Mi
nnpp
V _ ref  VDC  sin( t )  (5)
3  
npnp V _ ref   0 
Section III Set A Section IV Set B  

pnpn pnpn where Mi is the modulation index value and is given by

nnpn nnpn
Vˆll
Mi  (6)
VDC

nppp
where ̂ is the peak-to-peak value of the line-to-line voltage
pnpp of the converter output, VDC is the DC link voltage of the
pnnp converter.
nnpp The duty ratio waveform of the near state 3-D SVM over
Section V Set A Section VI Set B one power cycle is then plotted in Matlab. It should be noted
Fig. 7 Scheme 3 has been selected to implement the proposed switching
that the waveforms that are drawn in Fig. 8 indicates that only
scheme
one carrier waveform (internal generation of firings from duty

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cycles) is utilized, which is the same case as the experimental Sa+

implementation. If two carrier waveforms were utilized, then
the plotted duty ratios would be the same as those of classical Sb+
3-D SVM. It can be seen from Fig. 8 that the features of
Sc+
classical 3-D SVM such as higher DC link utilization, lower
switching loss has been maintained. Sf+
F. Linear Operating Range of Near-state 3-D SVM -30° 30° 90° 150° 210° 270° 330°
Section I Section II Section III Section IV Section V Section VI
As with the NSPWM method for a three-phase three-leg
VSI, the proposed near state 3-D SVM has its linear operation Fig. 9 Switching pulse pattern of near-state 3-D SVM within six sections
range, according to the matrix shown in Appendix B. It has over one power cycle
been found that when Mi<0.666, d 2 and d3 both become
negative, resulting even higher CMV level. Therefore the
linear operating range of the proposed near state 3-D SVM is
within [0.666 1]. In variable speed drives which must maintain
a constant ratio of voltage to frequency, it is therefore
important that the PWM scheme can operate over its full
modulation range of 0 pu to 1 pu. In distributed power
generation applications however, the inverter frequency is
most of the time at line frequency and hence the output
Section II-III Section I, IV-VI
voltage range is restricted. Still, the limited linear range could ↑Action qualifier control register is set high
be a short coming in the presence of voltage dip and ride- ↓Action qualifier control register is set low
through compliance according to the grid codes (in the Fig. 10. DSP implementation of near-state 3-D SVM (Phase A)
presence of a gird fault, the dc link voltage could be much high
greater than the peak-to-peak grid voltage).
G. Implementation of Near-state 3-D SVM
VAG VBG VCG
Fig. 9 shows the switching pulse patterns of four legs within
six sections over one power cycle. As it can be seen, for each
Voltage (V)

phase except the fourth leg, over one power cycle, there are
two sections in which the pulse patterns show the opposite
switching actions compared to the others. For instance, for
phase A, it is clearly shown that Section II and Section III
have opposite switching patterns with other sections. Here we
assume that when the duty ratio value is bigger than carrier
wave value, the gate drive signal is active high, hence in this
time (second)
convention the gate drive signals in Section II and III are (a)
defined as the opposite. The switch pulse patterns of the fourth
leg have to change polarity every section. This unique
characteristic of the proposed switching scheme requires VAG VBG VCG
special techniques when it comes to real time implementation.
A scalar implementation of NSPWM is proposed in [20, 25],
Voltage (V)

in which two carrier waveforms for each phase are utilized.

The implementation is possible with DSPs that have two
individual PWM comparator registers per phase.
In this research a Texas Instrument F28335 eZdsp with 150
MHz operating speed is used for the real-time implementation.
It may be worth mentioning here that an FPGA could be used
to implement the scheme in a commercial system. A general
interface board which has features such as 6 gate-drive
interface, 10 sensor interface, 4 DAC output, etc has been time (second)
designed to serve as an interface between the microprocessor (b)
and the power stage. Instead of using two carrier waveforms, Fig. 11 Simulated three-phase line to neutral voltages the common-mode
voltage under balanced linear load,(a) NS 3-D SVM; (b) classical 3-D SVM;
here only one carrier waveform is utilized. The choice of the Mi=0.84
switching actions is section dependent and can be realized
with the use of the flexible configurability provided by the the interrupt service routine (ISR) where the action qualifier
action qualifier sub-module of the ePWM module in the control register changes the PWM switching pattern for the
DSP[29, 30]. The additional code that is required is placed in next PWM cycle. This is illustrated with phase A in Fig. 10.

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A
B

Ia Ib Ic
Phase Current (A)

Gate driver Fault

In

C D
Interface RS232

eZdsp
time (second)
USB
(a) (a)
A B

Ia Ib Ic
Phase Current (A)

In
C

D
time (second)
(b) (b)
Fig. 12. Simulated three-phase output inductor currents and the neutral Fig. 13. A laboratory test bench for the proposed switching scheme; A. a
current under balanced linear load, (a) NS 3-D SVM; (d) classical 3-D SVM; three-phase four-leg VSI; B. filter and load; C. a general DSP interface
Mi=0.84 board; D. a Labview based control panel and Codecomposer studio

TABLE III DESIGN SPECIFICATIONS OF THE FOUR-LEG VSI

Maximum output power:
Output phase voltage: 200V/50Hz
Output voltage THD:
≤ 3%(Balanced load condition)
≤ 5%(Unbalanced load condition)
TABLE IV POWER STAGE PARAMETERS OF THE 5KW TEST BENCH
DC link voltage
DC link capacitor
AC filter inductor for each phase
AC filter capacitor for each phase
Switching frequency
Dead time delay for gate drivers
Load for testing purpose
III. SIMULATION RESULTS
A balanced linear load is used for open loop simulation to
test the NS 3-D SVM switching scheme. The simulation
parameters are set the same as the laboratory test bench and
can be seen in Table IV. The three-phase output line to neutral
voltages; load currents and the common-mode voltage are
shown in Fig. 11(a). As it can be seen, the common-mode
voltage level has been successfully reduced to 150V, which is
1/4of the DC link voltage. In comparison, the results of the
classical 3-D SVM are also shown in Fig. 11 (b). The three-
phase inductor currents and the neutral current under NS 3-D
SVM are shown in Fig. 12(a). Compared with the results of
classical 3-D SVM, the phase current ripples shown in the Fig.
5kW
12 (a) indicate higher current harmonic contents of the
Load power factor range: proposed switching scheme. In spite of the current ripple, the
0.8 lagging to 0.8 leading average neutral current with linear balanced load is shown as
zero.
600V
IV. EXPERIMENTAL RESULTS
1100μF
The design targets of the four-leg inverter are shown in
10mH
Table III and a laboratory test bench has been set to test the
10μF proposed switching scheme experimentally. The circuit layout
5kHz of a digital controller implementation is shown in Fig. 13(a)
3.4μs and the laboratory test bench was set up as shown in Fig.
Three-phase variable resistors 13(b). SKM 50GB123D IGBT modules and SKHI 22A hybrid
dual IGBT drivers are selected as the switching devices. The
current rating of the IGBTs in the fourth leg is based on the
maximum neutral current which itself is dependent on the
degree of imbalance in the load. For manufacturing
simplicity, it is desirable to use the same rating for the IGBTs
in the 4th leg as is used for the other three legs. The only
significant implication for the digital controller (or DSP) is
that enough PWM output channels are available to switch the
fourth leg. This would require extra 2 PWN channels. Most
modern DSP/microcontrollers have sufficient PWM outputs.
The communication between the PC and the DSP is through

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VAG100V/Div
VCG100V/Div
50Hz/282V

Magnitude (Abs)
VAG100V/Div VCG100V/Div
V

3rd/7.5V fsw-f/2.23V
VBG100V/Div
VCMV 500V/Div 5th/1.9V fsw+f/2.12V
9th/0.9V VBG100V/Div

VCMV 500V/Div
Zoomed in CMV waveform Harmonic order
(a) (a) (a)
VBG100V/Div
50Hz/282V ILA 5A/Div

Magnitude (Abs)
V ILB 5A/Div
VAG100V/Div ILC5A/Div

VCG100V/Div 3rd/6.8V fsw-f/1.3V

VCMV 500V/Div 5th/2.35V fsw+f/1.28V
9th/0.72V
In20A/Div

Zoomed in CMV waveform
(b)
Fig. 14. (a)Experimental results showing three-
phase line to neutral voltages and the common-
mode voltage; (b) Experimental results showing
line to neutral and common-mode voltage under
classical 3-D SVM
Harmonic order
(b) (b)
Fig. 15. FFT analysis based on two switching Fig. 16. (a) Experimental results showing three-
schemes; (a) NS-3D SVM; (b) Classical 3-D SVM phase line to neutral voltage and the common-
mode voltage under unbalanced load condition;
(b) Experimental results showing three-phase
load currents and the neutral current under
unbalanced load condition

an RS232 channel, and a Labview based control panel serves specification.

as a graphical user interface (GUI). The key parameters of the
test bench are shown in Table IV.
A. Balanced Load Conditions
The experimental test rig has been tested open loop up to
4kW. The three-phase output voltage waveforms and the
common-mode voltage waveform were measured over one
power cycle are shown in Fig. 14 (a). As it can be seen, the
peak phase voltage reaches 282V. With Mi=0.84, this
demonstrates the 15% more dc link utilization compared to
sinusoidal PWM. The common-mode voltage level shows the
same feature as it was in the simulation. As a comparison, the
output voltage and the CMV of the classical 3-D SVM is also
shown in Fig. 14(b), the reduction of the CMV level of the
proposed NS 3-D SVM can easily be seen.
The output voltage frequency spectrums of both schemes
are shown in Fig. 15. From the frequency spectrum analysis, it
can be seen that there are two distinct harmonic 3 rd and 5th
harmonics, and two harmonics around the switching frequency
fsw-f and fsw+f. It should be noted that the 3rd harmonics are
due to the zero-sequence current present in the system. Since
the system is an open-loop system, there’re still small amount
of negative-sequence and zero-sequence currents circulating.
The 3.4 μs dead time delay at 5 kHz switching frequency also
leads to some lower harmonics like the 3rd and 5th. The
harmonics contents around the switching frequency are due to
the scalar implementation of the proposed switching method.
The output voltage THD of NS 3-D SVM (Fig. 15 (a)) is
calculated to be 2.97%, though slightly higher than that of
classical 3-D SVM (2.62%), still satisfies the design
B. Unbalanced Load Conditions
In this test, the three-phase four-leg VSI is tested under two
unbalanced load conditions. In the first test, an open loop
system for an unbalanced load is built with three-phase load as
RA=30Ω, RB =45Ω, and RC=60Ω. This results in an
unbalanced three-phase load current as ILA=6.67/_0°A,
ILB=4.4/_-120°A, and ILC=3.3/_-240°A. The neutral current In
in this case is 4.17A. The reference switching vector has been
pre-calculated for the switching scheme algorithm. The three-
phase output line to neutral voltages and the common mode
voltage are shown in Fig. 16(a). The three-phase load currents
and the neutral current are shown in Fig. 16(b). It can be seen
that the three-phase output voltages maintain balanced under
unbalanced load condition. It is also important to notice that
the common mode voltage level is still reduced, proving that
the proposed switching scheme works under unbalanced load
condition as well.
In the second test a heavily unbalanced linear load is used.
Phase A and B are connected to 30 Ω resistors while Phase C
has no load. The DC link voltage is still 600V. The three-
phase output voltages remain the rated value shown in Fig. 17
(a), which gives 6.67A load currents for Phase A and B. Phase
C current is zero since it is not loaded. It is shown in Fig. 17
(b) that the magnitude of the neutral current is equal to the
value of phase A and B load current value, with large
switching ripple on the current waveform. With the proposed
switching scheme, a balanced three-phase output voltage is
obtained. The THD is 3.8%. Considering the load unbalance
percentage in this case, with Unbal_N%= Unbal_0%=50%,

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the quality of the output voltage is high. In comparison, the

VCG 100V/Div
results under the same load condition by using classical 3-D
VAG 100V/Div SVM are shown in Fig. 18. Compared with the results in
Fig.18 (a), the common-mode voltage shows a reduced level
VBG 100V/Div in Fig. 17 (a), which validates the proposed switching scheme.

VCMV500V/Div V. CONCLUSION
In this paper, a near-state 3-D SVM (NS 3-D SVM) has
been proposed to reduce the common-mode voltage for a
three-phase four-leg voltage source inverter. The impact of
common-mode noise which is related to EMI issues for a high
Zoomed in CMV waveform voltage level four-leg inverter has been investigated and the
(a) proposed switching scheme is introduced. The scheme
proposed in this paper would be useful for commercial
ILA 5A/Div ILB 5A/Div applications where the power converter has to supply a
potential unbalanced load at a close to nominal output voltage
ILC 5A/Div such as a UPS or embedded generator.
The distribution of switching vectors is studied before a
comprehensive procedure for the NS 3-D SVM is given,
which consists of section identification, selection of near-state
switching vectors, projection of the reference vector and
In20A/Div sequencing of the selected switching vectors. Implementation
technique with a DSP has also been introduced.
(b) The proposed near-state 3-D SVM can reduce the common-
Fig. 17. (a) Experimental results showing three-phase line to neutral mode voltage for a four-leg inverter while inheriting the merits
voltage and the common-mode voltage when phase C is unloaded;(b)
Experimental results showing three-phase load currents and the neutral of classical 3-D SVM. The implementation of the switching
current when Phase C is unloaded; NS 3-D SVM is used scheme is compatible with a real-time DSP based control
system.
Simulation and experimental results validate the proposed
VCG 100V/Div
switching scheme under both balanced and unbalanced load
condition. The proposed switching scheme reduces the
VAG 100V/Div common-mode voltage level, while the drawbacks of it
include higher voltage and current harmonic contents
VBG 100V/Div compared with classical 3-D SVM.
Appendix A
VCMV500V/Div
Eq. (1) shown in the paper is deduced based on a three-
phase balanced load condition. For simplicity and
demonstration purposes, the load condition is assumed
balanced. Later it is found by both simulation and
experimental results that under unbalanced load condition, the
Zoomed in CMV waveform
proposed switching scheme still works. The following shows
(a)
the deduction based on Fig.1
ILB 5A/Div van  vao  vno
ILA 5A/Div
vbn  vbo  vno
ILC 5A/Div
vcn  vco  vno
vfn  vfo  vno

Adding the four equations together, one obtains

van  vbn  vcn  vfn  (vao  vbo  vco  vfo)  4vno
In10A/Div
(b) Under balanced load condition, one has
Fig. 18. (a) Experimental results showing three-phase line to neutral voltage van  vbn  vcn  0
and the common-mode voltage when phase C is unloaded ;(b) Experimental
results showing three-phase load currents and the neutral current when
Also, vfn is assumed to be small compared to the phase
Phase C is unloaded; Classical 3-D SVM is used voltage, hence one obtains (1).

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APPENDIX B

TABLE MATRIX FOR SWITCHING VECTOR DUTY RATIO COMPUTATION

Section I II

Set A B A B

 3 3 
 3    1
0  0 1
3
  0 1
 2 2   0  3 0 1  3 0
 2 2     
Matrix of  1   5 3   1 3
duration of 
3
1 0   2 1  1  1 3 3
 1  1 1 0
 2 2  2  2 2   2 2 
each    2
 5 3 
 1 3  1 0 1 0 3  1  1
1 0 
switching  1  1
 2   3   
vector  2   2  3
 3 3
  1
2 1
 3  3 
0  0
0 1 
3
3  2 2   2 2 
 2 2   0 1
 2 2 
Section III IV

Set A A A B

 3 3   3 3 
 3 3  3 3   0 1  0 1
  0 1   0 1  2 2   2 2 
Matrix of  2 2   2 2   5 3   1 3 
duration of  1 0 1 0 
 2 3 1  1  2 
2
 1  1  2 
2
1 0
each  1 3 3  1     
switching  2 2
1  1

3
1 0   1 3
1 0  5 3
 1  1
vector    2 2   2 2   2 2 
 0  3 0 1  3   3 
 0  3 0 1  3 3
  0 1   0 1
 2 2   2 2 
Section V VI

Set A B A B

 0 3 0 1  0 1  3 
 
3 0 3  3 3 
1 3    0 1  0 1
Matrix of   1 0   1 
3 3
1  1  2 2 
 2   2 2 
duration of 2  2 2   2  3  1  1  1 0 1 0
each  2  3 1  1  1 0 1 0   1 
  3  1 3 3 
switching  3 3    1 0  2   1  1
vector  3 3
1  0 1  2  2
0 2  
 2 2   2 2   0 3 0 1   0 3 0 1

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Min Zhang received his M.Sc. and
Ph.D. degrees in electrical and electronic
engineering from Newcastle University,
Newcastle upon Tyne, UK, in 2009 and
2013, respectively. His research
interests are mainly focused on control
of power electronics, permanent magnet
brushless DC machine drive and
sensorless control.
David J. Atkinson received the B.Sc.
degree in electrical and electronic
engineering from Sunderland Polytechnic,
Sunderland, U.K., in 1978, and the Ph.D.
degree from Newcastle University,
Newcastle upon Tyne, U.K., in 1991. In
1987, he joined Newcastle University
after 17 years in industry with NEI
Reyrolle Ltd. and British Gas
Corporation. He is currently a Senior Lecturer with the Power
Electronics, Drives and Machines Research Group, School of
Electrical and Electronic Engineering, Newcastle University.
His research interests are mainly focused on the control of
power electronic systems including electric drives and
converters. Dr. Atkinson is a Chartered Electrical Engineer in
the U.K.
Bing Ji (M’13) received his M.Sc. and
Ph.D. degrees in electrical and electronic
engineering from Newcastle University,
England, in 2007 and 2012, respectively.
He was a power electronics engineer with
a UK low carbon vehicle company from
2012, where he works on powertrain
development and battery management
system for hybrid electric vehicles. Since
2013, he has been an EPSRC Postdoctoral Researcher at
Newcastle University,where he is involved in accurate power
loss measurement for high efficiency power converters and
motors with calorimetric methods.His research interests
include reliability study of power semiconductor devices,
batteries and power electronics converters, function
integration of gate drivers, electro-thermal modelling, thermal
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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management and high power-density converter integration for

electric vehicle applications. He is a member of the IEEE and
IEEE PELS societies.

Matthew Armstrong received the M.Eng.

degree from Newcastle University,
Newcastle Upon Tyne, U.K., in 1998. He
is currently a Lecturer in control of
electrical power at Newcastle University.
Prior to his university lectureship, he spent
eight years as a Research Associate with
the Newcastle University Power
Electronics, Drives and Machines Group.
His current research interests include real-time control of
electrical drive systems and power electronics, power
electronic hardware-in-the-loop systems, and grid connected
renewable energy systems.

Mingyao Ma received the B.Sc. and

Ph.D. degrees in applied power
electronics and electrical engineering
from Zhejiang University, Hangzhou,
China, in 2004 and 2010,
respectively.From October 2008 to
October 2009, she was a visiting PhD
postgraduate research student in the
University of Strathclyde, Glasgow,
U.K., and in 2010, she joined Zhejiang
University as a Post-Doctoral Research
Fellow. In 2011, she worked for the University of Central
Florida, Orlando, US, as the visiting scholar. From April 2012,
she joined the Newcastle University, Newcastle, UK, as the
research associate. Her research interests include multilevel
converters, distributed control of PEBB-based converters,
software design using FPGA and DSP, and SR motor control.

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