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Ate Lab5
Ate Lab5
EXPERIMENT 6
AIM
To test by Boundary Scan testing method using QT 2251..
APPARATUS REQUIRED
1. QT-2251 Testing Equipment
2. JTAG interface
3. PCB with the SMTs under test
4. Power cable for QT-2251
5. Interactive Software and a PC
DESCRIPTION
• Using QT2251, one can perform all types of testing such as; OCFT, ICFT, QSMVI and
boundary scan.
• Boundary scan is used when the PCB is complex and on cannot test all the ICs separately.
Hence all the interconnects are tested. It is checked if the signals are passed properly or not.
• Unlike OCFT, ICFT, and QSMVI which uses Dual-in-Package (DIP) ICs which have limited
number of pins, and can be tested using a clip by making a contact; in boundary scan where
surface mount technology-based ICs such as processors are used, the number of pins increase
and performs complex function.
• The ICs can have a range up to 100 pins and manufactured uniquely. So, in this case boundary
scan is used because taking signal from each and every pin is not possible.
• In such cases, SMTs (maximum 5-6) that are placed on a PCB are configured on boundary scan
kits.
• The boundary scan kit has Vcc, gnd, TDI, TDO, TCK, TMS and TRST. Using these boundary
scan pins; the data is fetched from the SMTs while testing.
• The issues with interconnects can be identified. Moreover, the number of nets can be identified.
• Not necessary to test each SMT separately but interconnects can be tested for proper working.
• First Board (Demo board):
SMTs --> BSD1 & BSD2 --> PASS
• Second Board (FPGA):
Spartan 3E kit
XE3S500E (family name)
FG-320 (package) --> fauty board --> to identify shorts or
open circuits and identify the number of nets.
OUTPUT
--> Demo board
1. QT 2251
2. JTAG interface
4. Interactive software
8. Learning characteristics
9. Contact check
1. Spartan 3E kit
2. JTAG
4. Number of nets
5. System learnt
6. Verifying
7. Test status