A 2nd order Σ-Δ Modulator as Readout

Circuit for SOI MEMS Accelerometers

 
 
By

Lujun Ji

March 2009

KTH Examiner Industrial Supervisor

Asso. Prof. Svante Signell Dr. Ir. Geert Langereis

ECS/ICT/KTH Research/Corporate I&T
Royal Institute of Technology NXP Semiconductors
Stockholm, Sweden Eindhoven, the Netherlands

 
 
  
 
Abstract 
Recently, there has been an increasing demand for low-power MEMS accelerometers
for a variety of applications ranging from inertial navigation to automotive stability
systems, geographical sensing and biomedical applications. A MEMS accelerometer
consists of a sensing element and an electrical readout circuit.

This thesis project presents the design and development of a fully-differential 2nd
order switched-capacitor sigma-delta modulator as interface circuit for the open-loop
integrated capacitive accelerometers. The surface-micromachined accelerometers are
designed in thin silicon-on-insulator (SOI) substrate. The interface IC provides 1-bit
digital output stream and operates at a sampling frequency of 2.5 MHz. The
influences induced by circuit non-idealities such as integrator leakage, distortion and
noise on the overall A/D converter has been studied and verified by system-level
modeling and simulations in MATLAB.

The interface IC is designed in the ABCD-3 process with 1μm 5V SOI-CMOS

provided by NXP Semiconductors. This includes implementation of the integrators,
op-amps, comparator, bandgap reference, clock generator and layout. The modulator
has a good performance in the simulation in a 5 kHz bandwidth from -40ºC to +150
ºC, and has a peak SNDR of 70dB which corresponds to 11-bit resolution and
minimum capacitance resolution of 15 aF. The chip area is 1.32 mm2 with power
consumption of 5 mW.

Keywords: accelerometer, MEMS, readout, sigma-delta converter, SNDR, SOI.

i 
 
 ii 
 
Acknowledgments 
I would like to express my sincerest gratitude to my mentor Dr. Geert Langereis for
his great guidance, support and encouragement. I am grateful for his offering me such
an opportunity to conduct my master thesis project at NXP Semiconductors. I have
been enormously honored to work under his supervision and learn from his advice
and useful insights throughout my internship.

This research would not have been enabled without any single help and support that I
had received from many employees of NXP Semiconductors. My special thanks to Dr.
Jan Jaap Koning, Dr. Marius Rolsma and Ir. Peter Prieshof for their kindest support in
Cadence installation and configuration, Dr. Lucien Breems for the discussion of my
ideas and answering my questions, Ir. Jin Chen for his invaluable suggestions in
solving the convergence problem encountered in AC analysis of op-amp with
SC-CMFB, and Ir. Stefan Butschelaar for his kind advices on layout. Thanks to all my
colleagues at NXP for enjoying the coffee break with me.

I would like to thank my thesis examiner at KTH, Dr. Svante Signell, for giving me
many suggestions and revising of this report.

Finally, I want to thank my parents for raising me in an educational and supportive

environment where I always have had the opportunity to share my ideas and thoughts
with them.

iii 
 
 iv 
 
Table of Contents 
1.  Introduction ...................................................................................................................... 1 
1.1.  Overview ....................................................................................................................... 1 
1.2.  Motivation ..................................................................................................................... 2 
 
2.  Sensing Element Design ..................................................................................................... 5 
2.1.  Overview ....................................................................................................................... 5 
2.2.  System Architecture ...................................................................................................... 9 
2.2.1.  Open‐Loop System ........................................................................................... 9 
2.2.2.  Closed‐Loop System ....................................................................................... 10 
2.2.3.  Architecture Selection .................................................................................... 11 
2.3.  System Specifications .................................................................................................. 11 
2.4.  Summary ..................................................................................................................... 12 
 
3.  Design of a 2nd Order Sigma‐Delta Modulator .................................................................. 13 
3.1.  Overview ..................................................................................................................... 13 
3.2.  The 1st Integrator ......................................................................................................... 14 
3.2.1.  Integrator Structure ....................................................................................... 15 
3.2.2.  Design of the Feedback DAC .......................................................................... 18 
3.3.  Noise Analysis .............................................................................................................. 19 
3.3.1.  Brownian Noise .............................................................................................. 19 
3.3.2.  Quantization Noise ......................................................................................... 20 
3.3.3.  Switch (kT/C) Noise ........................................................................................ 20 
3.3.4.  Op‐Amp Thermal Noise and DC Offset ........................................................... 21 
3.3.5.  Flicker (1/f) Noise............................................................................................ 23 
3.4.  Application of Auto‐zeroing ........................................................................................ 24 
3.5.  The 2nd Integrator and Comparator ............................................................................. 25 
3.6.  System‐Level Modeling of Circuit Non‐idealities ......................................................... 26 
3.6.1.  Clock Jitter ...................................................................................................... 26 
3.6.2.  Switch Thermal Noise ..................................................................................... 27 
3.6.3.  Operational Amplifier Noise ........................................................................... 28 
3.6.4.  Finite DC Gain ................................................................................................. 28 
3.6.5.  Bandwidth and Slew Rate .............................................................................. 29 
3.6.6.  Saturation ....................................................................................................... 30 
3.7.  Summary ..................................................................................................................... 33 
 
4.  Electrical Interface Circuitry Design.................................................................................. 35 
4.1.  Integrators ................................................................................................................... 35 
4.1.1.  The 1st Integrator ............................................................................................ 36 
4.1.2.  The 2nd Integrator ........................................................................................... 38 
4.2.  Operational Amplifiers ................................................................................................ 39 
4.2.1.  The 1st Op‐Amp ............................................................................................... 42 

v 
 
 4.2.2.  The 2nd Op‐Amp .............................................................................................. 45 
4.3.  Comparator ................................................................................................................. 45 
4.4.  Bandgap Reference ..................................................................................................... 47 
4.5.  On‐Chip Clock Generator ............................................................................................ 50 
4.6.  Simulation Results ....................................................................................................... 52 
4.7.  Layout .......................................................................................................................... 56 
4.8.  Summary ..................................................................................................................... 57 
 
5.  Conclusions and Future Work .......................................................................................... 59 
5.1.  Conclusions ................................................................................................................. 59 
5.2.  Future Directions ......................................................................................................... 59 
 
6.  References ...................................................................................................................... 61 
 
Appendix A. Acronyms ............................................................................................................ 64 
 
Appendix B. Study on Sensing Capacitances ............................................................................ 65 
 
Appendix C. Transfer Function of Σ‐Δ Modulator ..................................................................... 67 
 
Appendix D. Simulation Method of Op‐Amp with SC‐CMFB ..................................................... 69 
 
Appendix E. Verilog‐A and MATLAB Codes .............................................................................. 71 
 
Appendix F. Test Setup ............................................................................................................ 75 
 

vi 
 
Index of Figures 
Fig 1.1: An unstable car that is running on the road. ........................................................................ 2 
Fig 1.2: An architecture that clusters inertial MEMS sensors in the automotive. ............................. 2 
Fig 2.1: Schematic of a fully‐differential capacitive accelerometer. .................................................. 5 
Fig 2.2: SEM image of the sensor element........................................................................................ 6 
Fig 2.3: Schematic of an open‐loop system. ..................................................................................... 9 
Fig 2.4: Schematic of a closed‐loop system. .................................................................................... 10 
Fig 3.1: A conventional 2nd order Σ‐Δ modulator. ............................................................................ 13 
Fig 3.2: A 2nd order Σ‐Δ modulator as the interface circuit (where the 1st integrator is also a C/V 
converter). ....................................................................................................................................... 14 
Fig 3.3: Schematic of a fully‐differential SC charge integrator. ....................................................... 15 
Fig 3.4: Schematic of the 1st integrator with 1‐bit DAC. .................................................................. 18 
Fig 3.5: Periodically sampled capacitor. .......................................................................................... 20 
Fig 3.6: Half circuit of the 1st integrator during P1. ......................................................................... 22 
Fig 3.7: The 1st integrator with auto‐zeroing. .................................................................................. 24 
Fig 3.8: The 2nd integrator and comparator. .................................................................................... 25 
Fig 3.9: Model of a random sampling jitter. .................................................................................... 27 
Fig 3.10: Modeling switch thermal noise (kT/C block). ................................................................... 27 
Fig 3.11: Op‐amp noise block. ......................................................................................................... 28 
Fig 3.12: Model of a real integrator. ................................................................................................ 29 
Fig 3.13: Single‐ended SC integrator. .............................................................................................. 29 
Fig 3.14: Schematic of a 2nd order SC Σ‐Δ modulator (non‐ideal model). ....................................... 30 
Fig 3.15: PSD of the ideal 2nd order SC Σ‐Δ modulator. ................................................................... 31 
Fig 3.16: PSD of the 2nd order SC Σ‐Δ modulator with kT/C noise (CS = 0.335 pF). .......................... 32 
Fig 3.17: PSD of the 2nd order SC Σ‐Δ modulator with all the above non‐idealities. ....................... 32 
Fig 4.1: The 2nd order SC Σ‐Δ ADC as interface circuit. .................................................................... 35 
Fig 4.2: Clock phases of the modulator. .......................................................................................... 36 
Fig 4.3: Schematic of the 1st integrator. .......................................................................................... 36 
Fig 4.4 (a): A single‐transistor NMOS switch; (b): A low signal feed‐through NMOS switch. .......... 37 
Fig 4.5: Schematic of an integrating capacitor. ............................................................................... 38 
Fig 4.6: Schematic of the 2nd integrator. ......................................................................................... 38 
Fig 4.7: Folded‐cascode op‐amp with biasing circuits (PMOS input differential pair). ................... 39 
Fig 4.8: Conventional SC‐CMFB circuit. ........................................................................................... 41 
Fig 4.9: SC‐CMFB configuration with symmetric loading of the DM loop. ...................................... 42 
Fig 4.10: Amplitude and phase responses of the op‐amp. ............................................................. 43 
Fig 4.11: Results from transient simulation. ................................................................................... 44 
Fig 4.12: Results from noise analysis. .............................................................................................. 44 
Fig 4.13: Individual contributors from noise summary. .................................................................. 45 
Fig 4.14: Schematic of the dynamic comparator (with CLK controlled by P1d). ............................. 46 
Fig 4.15: Schematic of the SR latch and buffers. ............................................................................. 47 
Fig 4.16: Schematic of the bandgap reference circuit. .................................................................... 48 
Fig 4.17: Bandgap reference with voltage buffer and external capacitor. ...................................... 50 
Fig 4.18: Simulation results of the bandgap reference circuit. ....................................................... 50 
vii 
 
Fig 4.19: Schematic of the clock generator. .................................................................................... 51 
Fig 4.20: Simulation results of clock generator. .............................................................................. 51 
Fig 4.21: Simulation results of clock generator (zoomed‐in version). ............................................. 52 
Fig 4.22: Output swings of the 1st integrator (middle) and the 2nd integrator (bottom). ............... 52 
Fig 4.23: Output single‐bit stream of the modulator and input sinusoidal signal. ......................... 53 
Fig 4.24: Output spectrum of the modulator (without DC offset), SNDR = 77.49 dB. .................... 55 
Fig 4.25: Output spectrum of the modulator (with DC offset), SNDR = 70.16 dB. .......................... 56 
Fig 4.26: Layout of the interface circuit. ......................................................................................... 57 
Fig B.1: Schematic of simplified accelerometer model. ................................................................. .65 
Fig C.1: Block diagram of the 2nd order single‐loop feedback Σ‐∆ modulator. ................................ 67 
Fig D.1: Ideal CMFB circuit. ............................................................................................................. 69 
Fig D.2: Configurations in the Select Initial Condition Set window. ................................................ 69 
Fig D.3: Configurations in the Choosing Analyses window. ............................................................. 70 
Fig D.4: Configurations in the AC Options window. ......................................................................... 70 
Fig  F.1:  Two  equivalent  circuits:  (a)  Varying  capacitors  and  constant  voltage;  (b)  Constant 
capacitors and varying voltages. ..................................................................................................... 75 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

viii 
 
Index of Tables 
Table 2.1: Specifications of the developed SOI accelerometer. ...................................................... 12 
Table 2.2: Expected performance summary of the interface circuitry. ........................................... 12 
Table 3.1: Charges on CS1‐4 during P1 and P2 (right plate as positive). ........................................... 17 
Table 3.2: SNDR and resolution of a 2nd order Σ‐Δ modulator as interface circuit. ......................... 33 
Table 4.1: Capacitor sizes in the 1st integrator. ................................................................................ 37 
Table 4.2: Switch sizes in the 1st integrator. .................................................................................... 37 
Table 4.3: Capacitor sizes in the 2nd integrator. ............................................................................... 38 
Table 4.4: Switch sizes in the 2nd integrator. .................................................................................... 38 
Table 4.5: Transistor sizes in the 1st op‐amp. .................................................................................. 42 
Table 4.6: Capacitor sizes in the CMFB circuit. ................................................................................ 42 
Table 4.7: Switch sizes in the CMFB circuit. ..................................................................................... 43 
Table 4.8: Performance of the 1st op‐amp. ..................................................................................... 45 
Table 4.9: Floor‐planning of the layout. .......................................................................................... 56 
Table 4.10: Pin list of the chip. ........................................................................................................ 57 
Table 4.11: Summary of the accelerometer performance. ............................................................. 58 
Table F.1: Charges on the sensing capacitors. ................................................................................. 75 
Table F.2: Charges on the differential inputs of the 1st integrator. .................................................. 75 
Table F.3: Charges on the sensing capacitors. ................................................................................. 76 
Table F.4: Charges on the differential inputs of the 1st integrator. .................................................. 76 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
ix 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

x 
 
1. Introduction 
1.1. Overview 

Micro-Electro-Mechanical Systems (MEMS) are small integrated devices which are

usually fabricated on a silicon substrate and able to combine electrical and mechanical
elements for sensing or actuating purposes [1]. Examples of MEMS components
include accelerometers, RF MEMS switches, microphones, and micro-resonators.
Other new applications are rising as existing technologies are applied to miniaturize
and integrate conventional devices.

With the fast development of MEMS technology, the MEMS accelerometers, as the
most mature MEMS-based inertial sensor application, have seen significant progress
over the past decades. The advantages such as low-cost, low-power, small size, batch
fabrication make MEMS accelerometers have a wide range of applications such as
automotive safety and stability, biomedical applications, oil and gas exploration, and
computer accessories [2]. Current MEMS accelerometers have the highest degree of
integration, with sensing elements and electronic interface circuitry integrated on a
single chip [3].

Capacitive MEMS accelerometers have been implemented using various surface and
bulk micromachining technologies. Unlike bulk micromachining, which defines
structures by selectively etching inside a substrate (wafer), surface micromachining
creates structures on top of a substrate by using a succession of thin film deposition
and selective etching [4]. In surface micromachined devices, the thickness of the
deposited layer and hence the proof mass is small, resulting in limitations on the
performance of the accelerometers. Typically, the resolution of the commercial
surface micromachined accelerometers is in the milli-gravity (mg) range [5]. On the
other hand, bulk micromachining features larger proof mass and larger capacitive area
that leads to higher sensitivity and higher resolution approaching micro-gravity (μg).

MEMS accelerometers are available in a wide variety of ranges up to thousands of g’s.

Single-axis, dual-axis, and three-axis models are available. In our case, it will be used
in automotive stability systems as shown in Fig 1.1 and Fig 1.2 [6] which only require
low g’s.

Currently, high performance mixed-signal interface circuits have received growing

attention towards high-level of integration, power reduction and noise cancellation
(improved resolution). The new generation of accelerometer interface architectures
should have the versatility of interfacing with sensors of various sensitivities while
maintaining low power consumption, small drift, increased functionality, and large
dynamic range.

1 
 
  
Fig 1.1: An unstable car that is running on the road.

 
Fig 1.2: An architecture that clusters inertial MEMS sensors in the automotive. 

Silicon-on-insulator (SOI) technology has been widely applied to automotive industry.

One of the most obvious advantages of SOI is the reduction of parasitic capacitances
compared with conventional silicon (bulk CMOS) due to isolation from the bulk
silicon, which improves power consumption at matched performance. In addition,
SOI provides resistance to latch-up due to complete isolation of the n and p well
structures [7]. Therefore, power consumption is reduced, and faster operation can be
achieved.

1.2. Motivation 

The objective of this thesis is to design and implement a 2nd order Σ-Δ modulator to
readout a surface-micromachined SOI accelerometer. Conventionally, an electronic
front-end circuit is needed to convert the sensed signal to a voltage signal, and an
analog-to-digital converter (ADC) can be added after the front-end to obtain digital
output. Alternatively, the sensor can be incorporated into the ADC in order to improve
the performance and simplify the complexity of the interface circuitry [8].
2 
 
Sigma-delta modulators are often used as interface circuit due to its wide dynamic
range, inherent linearity and relaxed accuracy requirements on the analog circuits.

The accelerometer described in this report is designed with the SOI technology
developed by NXP Semiconductors. And, a fully differential 2nd order switched
capacitor Σ-Δ modulator as interface circuit is implemented in the ABCD-3 process
with 1µm 5V SOI-CMOS provided by NXP Semiconductors. The modulator performs
well in simulation. The peak SNDR is 70 dB (minimum capacitance resolution of 15
aF) in a 5 kHz signal bandwidth from -40ºC to +150ºC. The chip area is 1.32 mm2
with power dissipation of 5 mW at 2.5 MS/s. The Cadence software environment is
used for all design, simulation and layout.

This report is organized in five chapters. Chapter 1 briefly introduces the MEMS
accelerometers and the motivation behind the work. Chapter 2 discusses the
accelerometer’s principle of operation and determines the technological requirements
for improving the resolution and stability of the sensor. Chapter 3 proposes the
modulator architecture, investigates the noise effects on the accelerometer
performance, and introduces the system-level modeling and simulation of the 2nd
order switched-capacitor sigma-delta ADC. Chapter 4 presents a low-power
high-performance SC interface circuit to readout the SOI accelerometer, gives the
experimental results and comments on these results. Chapter 5 briefly summarizes
the research contributions and gives recommendations to implement lower-power
interface circuit as well as the closed-loop SOI accelerometers as the future directions.

3 
 
 4 
 
2. Sensing Element Design 
This chapter gives a brief introduction to accelerometer systems. An
electro-mechanical model of accelerometers is presented first. The accelerometer
systems are classified into two categories, open-loop and closed-loop, depending on
whether a force-feedback loop is applied to the sensor. The chapter concludes with the
specifications of accelerometers and interface circuitry.

2.1. Overview 

For acceleration, a mechanical sensing element converts the unknown quantity into a
displacement that is then detected and converted to an electrical signal.

CS3 = (CS − ΔCS ) / 4 CS1 = (CS + ΔCS ) / 4

CS 2 = (CS − ΔCS ) / 4 CS 4 = (CS + ΔCS ) / 4

Fig 2.1: Schematic of a fully-differential capacitive accelerometer.

The simplified schematic of a fully-differential capacitive MEMS accelerometer is

depicted in Fig 2.1 [9]. The central part of the accelerometer is a micromechanical
proof mass M suspended to a supporting frame by mechanical springs with effective
spring constant K, which acts as the sensing element. The squeezed film damping D is
imposed by the surrounding air on the structure. The accelerometer has a fully
differential sense topology; it means that four sense electrodes with one common node
at the proof mass are devised in the fabricated MEMS accelerometers. CS1, CS2, CS3,
and CS4 are sensing capacitors between the proof mass fingers and the four sense
electrodes, respectively.

C S 1, 2 = (C S ± ΔC S ) / 4 (2.1)

Where, CS is the rest capacitance and ΔCS is the capacitance variation of the sensor.

When an external acceleration aext is applied, the proof mass will move in the sensing
axis with respect to the moving frame of reference (X = Y - Z), causing a change in
distance between it and the adjacent fixed electrodes. The displacement of the proof
mass can be measured as a very small change in capacitance between it and the fixed
5 
 
electrodes. Fig 2.2 [10] shows a scanning electron microscope (SEM) image of how
this is implemented in silicon. By integrating the interface circuit on the same chip as
the sensor, extremely small changes in capacitance and, accordingly, small
accelerations can be detected.

 
Fig 2.2: SEM image of the sensor element.

The schematic as shown in Fig 2.1 shows the mechanical parameters for the sensing
element. According to Newton’s law, the differential equation for the displacement x
as a function of external acceleration aext is that of a second-order
mass-spring-damper system [1]:

d 2x dx
M 2
+ D + K eff x = Fext = Maext (2.2)
dt dt

Where, D and Keff are the damping coefficient and spring constant, respectively, and
linear relations are assumed. Taking Laplace transform of (2.2) yields the second-
order equation:

(Ms 2
)
+ Ds + K eff ⋅ X (s ) = M ⋅ A(s ) (2.3)

Solving for X(s) gives the transfer function:

X (s ) 1 1
= = (2.4)
A(s ) D K eff ωr
s + s+
2
s +
2
s +ω 2
r
M M Q

with the resonant angular frequency ω r = K eff / M = 2πf r and quality factor

Q = K eff M / D . At frequencies well below resonance (ω<<ωr), the displacement

6 
 
 x ≈ a / ωr2 , which leads to the sensitivity S:

x 1
≈ (2.5)
a ω r2

This relationship indicates a trade-off between sensitivity and bandwidth of the sensor:
low resonant frequency results in large displacements and hence, high resolution
restricts the bandwidth of the sensor. But actually, the lower limit of resonant
frequency is bounded by many factors such as the mechanical shock resistance, the
achievable lowest spring constant, the highest possible effective mass, and
manufacturability.

The effective spring constant (K) of the accelerometer is expressed by [11]:

K eff = K mechanical − K electrical [N/m] (2.6)

The mechanical and electrical stiffness of the structure are given by [12]:

3
⎛ w⎞
K mechanical = 6 E x h⎜ ⎟ [N/m] (2.7 )
⎝l ⎠

V2
K electrical = C S [N/m] (2.8)
2d 2

Where Ex is the Young’s modulus of silicon in the sense direction; h, w, and l are the
thickness, width and length of the springs, respectively; CS is the rest (initial)
capacitance between the proof mass fingers and the sense electrodes with an initial
gap spacing of d. The voltage applied to the sensing capacitor is V. The accelerometer
is designed such that Kelectrical << Kmechanical.

The Brownian noise equivalent acceleration (BNEA) is expressed by [13]:

a2 4kbTD 4 k b Tω r ⎡ m/s 2 ⎤
BNEA = = = ⎢ ⎥ (2.9)
Δf M MQ ⎣ Hz ⎦

The air-damping coefficient D is formulated as [14]:

3
⎛h ⎞
D = nμ eff le ⎜ e ⎟ [N ⋅ s/m] (2.10)
⎝d⎠

7 
 
Where, n is the total number of fingers that form each sense electrode, μeff is the
effective viscosity of air, and he and le are the height and length of the electrode
respectively.

Another limiting factor is the circuit noise equivalent acceleration (CNEA) that
depends on the capacitive resolution of the interface circuit (ΔCmin) and the capacitive
sensitivity (S) of the accelerometer (S = ΔCS/aext) given in (2.16):

ΔC min ⎡ m/s 2 ⎤
CNEA = ⎢ ⎥ (2.11)
S ⎣ Hz ⎦

For amax = 5 g, and the maximum displacement xmass, max = 50 nm (10% of a capacitive
gap spacing of 0.5 µm), we find a resonance frequency fr = 5 kHz according to (2.4).
Subsequently, the values for M and Keff are calculated when fr is fixed, M =
9.011×10-10 kg, Keff = 0.889 N/m, and D = 28.287×10-6 N·s/m. So, Q = 0.92.

If aext = 0, the sensing capacitors are:

C S 1 = C S 2 = C S 3 = C S 4 = Aε r ε 0 / d = C S / 4 (2.12)

Where, A is the area of the sensing electrode made up of interdigitated fingers.

If aext ≠ 0 and Δd << d, the variation of the sensing capacitance is:

⎛ 1 1 ⎞ Δd
ΔC S = C S 1 + C S 4 − C S 2 − C S 3 = 2 Aε r ε 0 ⎜ − ⎟ ≈ CS (2.13)
⎝ d − Δd d + Δd ⎠ d

And, the sensor capacitors are:

C S 1 = C S 4 = (C S + ΔC S ) / 4 (2.14)
C S 2 = C S 3 = (C S − ΔC S ) / 4 (2.15)

From (2.2) and (2.13), the sensitivity of the accelerometer is:

ΔC S C S M C S 1 ⎡ F ⎤
S= = = ⎢⎣ m/s 2 ⎥⎦ (2.16)
aext d K d ω02

Finally, the total noise equivalent acceleration (TNEA) of the accelerometer is

8 
 
expressed as:

⎡ m/s 2 ⎤
TNEA = BNEA 2 + CNEA 2 ⎢ ⎥ (2.17 )  
⎣ Hz ⎦

2.2. System Architecture 

The operation of an accelerometer system can be classified into two categories,

open-loop and closed-loop, depending on whether a force-feedback loop is applied to
the sensor.

2.2.1. Open­Loop System 

An open-loop system is depicted in Fig 2.3, which consists of a sensor functioning as

the acceleration-to-displacement (capacitance) converter, and a position readout
circuit generating the output voltage.

1
Ms + Ds + K
2

 
Fig 2.3: Schematic of an open-loop system.

From (2.2), the mechanical bandwidth (i.e., the -3dB cut-off frequency) is:

1 1
ω −3dB = ω0 1 − 2
+ 2
1 − 4Q 2 + 8Q 4 (2.18)
2Q 2Q

The sensitivity of the system is:

Vout K v ⎡ F ⎤
S= = 2 ⎢⎣ m/s 2 ⎥⎦ (2.19)
a ω0

The minimum detectable acceleration amin is determined by the total input-referred

noise of the accelerometer, including mechanical noise BNEA from sensor given by
(2.9) and electronic noise CNEA from interface circuit given by (2.11).

The maximum detectable acceleration amax is determined by Δdmax,

9 
 
 ⎡ m/s 2 ⎤
a max = Δd max ⋅ ω 02 ⎢ ⎥ (2.20)
⎣ Hz ⎦

From (2.13), the nonlinear capacitance change due to displacement can be calculated
as:
⎛ ⎞ Δd
CS ⋅
CS ⎜ 1 ⎟
d ≅ C ⎡ Δd + ⎛⎜ Δd ⎞⎟ ⎤
3
1
ΔC S = ⎜ − ⎟= S⎢ ⎥ (2.21)
2 ⎜ 1 − Δd 1 + Δd ⎟ ⎛ Δd ⎞
2
⎢
⎣ d ⎝ d ⎠ ⎦⎥
⎜ ⎟ 1− ⎜ ⎟
⎝ d d ⎠ ⎝ d ⎠

From (2.21), if Δdmax = d/10, the third harmonic distortion (THD) is:

2
1 ⎛ Δd ⎞
THD ≅ ⎜ max ⎟ ≈ −52 dB (2.22)
4⎝ d ⎠

2.2.2. Closed­Loop System 

Fig 2.4 illustrates an acceleration sensor embedded in a feedback loop. The negative
feedback loop measures the deviations of the proof mass and applies a force to oppose
displacements of the proof mass from its nominal position. The output voltage is
taken as the force needed to null the position.

Sensor Position
readout
Fext 1 d
aext M Kv Vout
+ Ms + Ds + K
2
-
Ffb
Kf
Electrostatic feedback
 
Fig 2.4: Schematic of a closed-loop system.

Electrostatic actuation is the simplest means for generating the feedback force in a
micromechanical sensor. When a voltage V is applied to the electrodes of a parallel
plate capacitor C with gap d, the electrodes are attracted with a force [15]:

1C 2
F= V (2.23)
2d

One-bit forcing can be achieved by applying a feedback voltage Vfb across one half of
the sensing capacitance, while applying zero potential difference across the other half
10 
 
[15]. The full-scale feedback acceleration in g’s is:

1 T f ⎛ 1 CS / 2 2 ⎞
a fs = ⎜ V fb ⎟ (2.24)
9 .8 ⋅ M T ⎝ 2 d ⎠

Where, Tf/T is the fraction of the period when feedback is applied. If M = 9.011×10-10
kg, CS = 0.67 pF, d = 0.5 μm, Vfb = 5 V, Tf/T = 0.25, the full-scale feedback
acceleration is ±237.39 g.

Feedback can be used to improve many important characteristics of a sensor,

including bandwidth, dynamic range and linearity. Increasing the bandwidth is
particularly important in accelerometers due to the trade-off between sensitivity and
bandwidth imposed by the sensing element. Feedback increases the useful bandwidth
by a factor of loop gain, which can be made large by using electronic circuitry [16].
Thus, the resonant frequency of the sensing element can be optimized for sensitivity
alone, regardless of the desired sensor bandwidth.

Because of the quadratic dependence of the force on voltage, electrostatic actuators

cannot be used directly, but must be combined with some means of linearization. A
general and accurate solution is sigma-delta modulation that generates pulse
modulated digital feedback signal [16].

2.2.3. Architecture Selection 

Although closed-loop systems have higher linearity and wider bandwidth than
open-loop systems, an open-loop system is adopted in this project for the following
reasons:

a) Open-loop system has inherent high resolution and stability, and relaxes the
circuit complexity. By contrast, closed-loop system is complex, noisy and
unstable [15], because the proof-mass is a 2nd order filter.
b) Open-loop system consumes less power.
c) The application of MEMS accelerometer into automotive stability systems
does not impose requirements on the linearity and bandwidth, thus an
open-loop system is enough.
d) Under shock conditions, it is impossible to balance high-G acceleration with
electrostatic actuation according to (2.25).

2.3. System Specifications 

The proposed specifications of SOI accelerometer are listed in Table 2.1. The
expected performance summary of the interface circuitry is given in Table 2.2.

11 
 
 Table 2.1: Specifications of the developed SOI accelerometer.
Proof mass dimensions (L × W × T) 0.5 mm × 0.6 mm × 1.5 µm
Proof mass M 9.011 × 10-10 kg
Rest capacitance Cs 0.67 pF
Full scale ΔCsmax 0.039 pF
Full scale amax 5G
Capacitive sensitivity S 7.8 fF/G
Mechanical noise floor 77.53 µG/√Hz
Capacitive gaps dnarrow/dwide 0.5 µm/1 µm
Quality factor Q 0.92
Resonance frequency fr 5 kHz
Mechanical bandwidth f-3dB 4.6 kHz

Table 2.2: Expected performance summary of the interface circuitry.

Rest capacitance Cs 0.67 pF
Full scale ΔCsmax 0.039 pF
Signal bandwidth fB DC to 5 kHz
Oversampling ratio R 250
Sampling frequency fs 2.5 MHz
Peak SNDR 70 dB
Power dissipation Pd 5 mW
Temperature range -40ºC to +150ºC
Supply voltage 5V
Technology process 1 µm SOI-CMOS

2.4. Summary 

This chapter provides a brief introduction to accelerometer system. An

electro-mechanical model of accelerometer is presented, which shows that such
sensors can be seen as acceleration-to-capacitance converters.

The operation of an accelerometer system can be classified into two categories,

open-loop and closed-loop, depending on whether a force-feedback loop is applied to
the sensor. An open-loop system is used in this design, as it is simple and fits into
automotive stability system applications. The specifications of the developed SOI
accelerometer are proposed and the expected performance summary of the interface
circuit is also given. The following chapter will discuss the design issues of a Σ-Δ
modulator as an interface circuit for SOI accelerometers in detail.

12 
 
3. Design of a 2nd Order Sigma­Delta Modulator 
This chapter presents the architecture and circuit specifications of a 2nd order
sigma-delta modulator as readout circuitry for MEMS accelerometers. The 1st
integrator, acting as a capacitance-to-voltage converter, is proposed. The circuit noise
contributors are analyzed, and auto-zeroing technology is discussed in order to reduce
the flicker noise and DC offset. The architecture of the 2nd integrator and comparator
is given. Finally, system-level simulations are performed to figure out the design
specifications of the Σ-Δ modulator, as it is necessary to estimate the modulator
performance at system-level before starting the circuit-level design.

3.1. Overview 

Sigma-delta (Σ-Δ) analog-to-digital (A/D) converters are the most suitable converters
for low-frequency high-resolution applications. Σ-Δ modulators are based on trading
accuracy with speed to avoid the difficulty of implementing complex precision analog
circuits [17].

A conventional 2nd order Σ-Δ modulator is depicted in Fig 3.1. In the time domain, the
integrator integrates the difference between the input signal X and the fedback output
signal of the Σ-Δ modulator. The feedback DAC and the 1st feedback coefficient force
the average value of 0.5·Y to track X.

 
nd
Fig 3.1: A conventional 2 order Σ-Δ modulator.

The z-domain output function is derived in Appendix C:

Y (z ) =
0.335
X (z ) + 2
(z − 1)
2
E (z ) (3.1)
z − 1.75 z + 0.9175
2
z − 1.75 z + 0.9175

Where E is the quantization noise.

It can be seen from (3.1) that, the quantization noise E is pushed to the high
frequencies outside the signal bandwidth by a 2nd order noise shaping, and will be
13 
 
removed by the low pass filter following the modulator.

The theoretical signal-to-noise ratio (SNR) of a 2nd order Σ-Δ modulator is defined as
the power ratio of a full-scale input signal and the base-band quantization noise. It is
given by the following formula [18]:

SNRQ [dB] = 6.02 N + 1.76 − 12.9 + 50 log(OSR ) (3.2)

Where N is the number of bits of the quantizer, OSR = fS/(2fB) is the over-sampling
ratio, fS is the sampling frequency and fB is the signal bandwidth.

From (3.2), it can be seen that doubling the OSR results in about 2.5 bits of additional
resolution. To obtain a SNRQ higher than 80 dB, for a quantizer with N = 1, OSR ≥
50.4 is needed. But, it is preferable to use a power of 2 for OSR as it will simplify the
subsequent decimation to Nyquist sampling rate. Then OSR = 64 is tried, but with this
value, SNRQ = 85.2 dB, which is not enough to tolerate base-band noise due to circuit
non-idealities. Finally OSR = 256 is chosen, thus SNRQ = 115.3 dB, to leave a safe
margin for the non-idealities. With this OSR, the sampling frequency is fS = 2.5 MHz,
for a signal bandwidth of 5 kHz.

The architecture of a 2nd order Σ-Δ modulator as an interface circuit for

accelerometers is shown in Fig 3.2. The 1st integrator also acts as a
capacitance-to-voltage (C/V) converter for the accelerometer. The design of Σ-Δ
modulator depicted in Fig 3.2 will be discussed in the following sections in detail.

 
Fig 3.2: A 2nd order Σ-Δ modulator as the interface circuit (where the 1st integrator is
also a C/V converter).

3.2. The 1st Integrator 

The 1st integrator is the most important component of the modulator. It interfaces the
sensor as a capacitance-to-voltage converter. On the other hand, its noise and
distortion have a predominant impact the noise performance of the modulator. The
noise and distortion from the 2nd integrator and comparator will be attenuated by the
14 
 
high DC gain of the 1st integrator.

3.2.1. Integrator Structure 

Fig 3.3 depicts a fully-differential SC charge integrator, which consists of sensing

capacitors Cs1-4, integrating capacitors Cint1-2, and an op-amp. The common-electrode
of Cs1-4, which is the proof mass, is connected to DC voltage 0.5Vref [19].

The integrator has two non-overlapping clock phases: the pre-charge phase P1 and the
charge-integration phase P2. During P1, the right electrodes of Cs1-4 track Vref, ground,
Vref and ground, respectively. During P2, the right electrodes of Cs1-4 connect to the
op-amp input. The operation is explained in detail as follows.

Under external acceleration, the sensing capacitors are:

C S1 = C S 4 = (CS + ΔC S ) / 4 (3.3)  
C S 2 = C S 3 = (CS − ΔC S ) / 4 (3.4)  

During P1, the voltages over Cs1-4 are 0.5Vref, -0.5Vref, 0.5Vref and -0.5Vref (take right
side as positive) respectively. During P2, if the input common-mode voltage of the
op-amp is VICM, the voltages over Cs1-4 are all VICM－0.5Vref.

 
Fig 3.3: Schematic of a fully-differential SC charge integrator.

Since the charge on a capacitor Q is equal to the capacitance value C times the voltage
V over it (Q = CV), during P1, the sum of charge on Cs1 and Cs2 is:

15 
 
 Q1 = 0.5Vref ⋅ (C S + ΔC S ) / 4 + (− 0.5Vref ) ⋅ (C S − ΔC S ) / 4
= 0.25 ⋅ Vref ⋅ ΔC S (3.5)

and the sum of charge on Cs3 and Cs4 is:

Q2 = 0.5Vref ⋅ (C S − ΔC S ) / 4 + (− 0.5Vref ) ⋅ (CS + ΔC S ) / 4

= −0.25 ⋅ Vref ⋅ ΔC S (3.6)

During P2 (when stable), the sum of charge on Cs1 and Cs2 is:

Q1′ = (VICM − 0.5Vref ) ⋅ [(C S + ΔC S ) / 4 + (CS − ΔC S ) / 4]

= 0.5 ⋅ (VICM − 0.5Vref ) ⋅ CS (3.7 )

and the sum of charge on Cs3 and Cs4 is:

Q2′ = (VICM − 0.5Vref ) ⋅ [(CS − ΔC S ) / 4 + (C S + ΔC S ) / 4]

= 0.5 ⋅ (VICM − 0.5Vref ) ⋅ CS (3.8)

Therefore, during P2, the net charge that is transferred from Cs1 and Cs2 to Cint1 is:

ΔQ1 = Q1 − Q1′ = 0.25 ⋅ Vref ⋅ ΔC S − 0.5 ⋅ (VICM − 0.5 ⋅ Vref ) ⋅ CS (3.9)  

 
Similarly, the net charge that is transferred from Cs3 and Cs4 to Cint2 is:

ΔQ2 = Q2 − Q2′ = −0.25 ⋅ Vref ⋅ ΔC S − 0.5 ⋅ (VICM − 0.5 ⋅ Vref ) ⋅ CS (3.10)

It can be seen from (3.9) and (3.10) that, ΔQ1 and ΔQ2 consist of a common-mode
charge Qcm, and a differential-mode charge Qdm:

Qcm = −0.5 ⋅ (VICM − 0.5 ⋅ Vref ) ⋅ CS (3.11)

Qdm = 0.25 ⋅ Vref ⋅ ΔC S (3.12)

Because the output common-mode voltage VOCM is controlled by the common-mode

feedback of the op-amp, VICM is changed by Qcm by:

ΔVICM = Qcm / C int = −0.5 ⋅ (VICM − 0.5 ⋅ Vref ) ⋅ CS / C int 1, 2 (3.13)  

16 
 
Taking the z-transform of (3.13), we have:

0.5 ⋅ Vref
Vicm ( z ) = (3.14)
1 + 2 ⋅ (1 − z ) ⋅ C int1,2 / CS

At DC (i.e., when z = 1),

VICM = 0.5 ⋅ Vref (3.15)  

From (3.11) and (3.15),

Qcm = 0 (3.16)

From (3.15) and (3.16), it can be seen that, during P2, the common-mode charges Qcm
from Cs1-4 cancel each other, which not only set the input common-mode voltage of
the op-amp to 0.5Vref, but also relax the requirement for common-mode rejection ratio
(CMRR) of the op-amp. And the differential charges ΔQ1,2 from Cs1-4, due to the
change of capacitance ΔCS, are transferred to the integrator output and change the
output voltages.

The charges on Cs1-4 during P1 and P2 are summarized in Table 3.1.

Table 3.1: Charges on CS1-4 during P1 and P2 (right plate as positive).

Sensing Capacitor P1 P2
CS1 0.5Vref·CS1 0
CS2 -0.5Vref·CS2 0
CS3 0.5Vref·CS3 0
CS4 -0.5Vref·CS4 0

Over one clock period, the differential output voltage of the integrator changes by:

ΔVout =
ΔQ V (C − CS 2 ) − (CS 3 − CS 4 ) = Vref ⋅ ΔCS
= ref ⋅ S 1 (3.17 )
C int 1, 2 2 C int 1, 2 2 C int 1, 2

Taking the z-transform of (3.17), we have:

Vout ( z ) Vref
H (z ) = = (3.18)
ΔC S ( z ) 2 ⋅ (1 − z ) ⋅ C int1,2

17 
 
3.2.2. Design of the Feedback DAC 

The 1st integrator with a 1-bit DAC [20] is shown in Fig 3.4, which consists of
feedback capacitors Cfb1,2 and several switches. The left electrodes of Cfb1,2 are
connected to DC voltage source 0.5Vref.

 
st
Fig 3.4: Schematic of the 1 integrator with 1-bit DAC.

During P1, the right electrodes of Cfb1,2 track Vref and ground respectively. During P2,
the right electrodes of Cfb1,2 connect to the op-amp inputs, the common voltage of
which is 0.5Vref. Thus, the differential reference charges ( ± 0.5Vref·Cfb1,2) are
transferred from Cfb1,2. The comparator outputs Y+ and Y- (in Fig 2.10) decide
whether Cint1 and Cint2 receive a positive or negative reference charge. If Y+ is logic
high (and Y- is logic low), Cint1 receives a positive reference charge while Cint2
receives a negative charge. If Y+ is logic low, the charge delivery is reversed.

An important advantage of this circuit topology is that the current drawn from the
reference voltage Vref does not depend on the signal. Otherwise some non-linear
version of the signal may distort the reference voltage. An external decoupling
capacitor will be added between Vref and ground to smooth out the current pulses from
CS1-4 and Cfb1-2.

Since the average of reference charges from Cfb1-2 balances the signal charge from
18 
 
CS1-4, the single-bit stream Y+ and Y- is proportional to the ratio of ΔCS and Cfb1-2.
Thus Cfb1-2 uses mechanical capacitor similar to CS1-4, except that Cfb1-2 is fixed while
CS1-4 is variable by using mechanical springs.

3.3. Noise Analysis 

There are several noise sources in the accelerometer system. In the mechanical
domain, the sensor presents Brownian noise to the system; in the electrical domain,
the interface circuit introduces quantization noise, switch noise, op-amp thermal noise
and DC offset, and flicker noise.

3.3.1. Brownian Noise 

In the system, the fundamental sense limit is set by the Brownian noise equivalent
acceleration (BNEA) of the suspended mass. Brownian noise is induced by random
collision of air molecules with the sensor. This acceleration is expressed as [21] [22]:

a2 4kbTD 4 k b Tω r ⎡ m/s 2 ⎤
BNEA = = = ⎢ ⎥ (3.19)
Δf M MQ ⎣ Hz ⎦

Where kb is Boltzmann’s constant (1.38×10-23 J/K), T is the absolute temperature (300

K), ωr is the resonant angular frequency in rad/sec, M is the effective mass of the
proof mass, and Q is the mechanical quality factor.

From (3.19), Brownian noise can be reduced by either increasing effective mass or
reducing air damping, or equivalently increasing quality factor. However, reducing the
damping increases the possibility of resonant behavior (high-Q) and sensitivity to
higher order mode shapes that are not desirable. Another limiting factor is the circuit
noise equivalent acceleration (CNEA) that depends on the capacitive resolution of the
interface circuit (∆CMIN) and the capacitive sensitivity (S) of the accelerometer (S =
∆C/gravity):

ΔC MIN ⎡ m/s 2 ⎤
CNEA = ⎢ ⎥ (3.20)
S ⎣ Hz ⎦

Substituting all the parameters into (3.19), we have 77.53 µG/√Hz for the mechanical
noise floor. For many commercial applications (e.g., in the automotive sector), this
noise level is acceptable. Low noise can be achieved by either increasing the effective
mass or increasing the quality factor Q by reducing the damping coefficient of the
sensing element.

Since Q = 0.92, fr = 5 kHz, the mechanical bandwidth is f-3dB ≈ fr · Q = 4.6 kHz.

19 
 
If purely dominated by mechanical noise, the dynamic range is:

amax 5
DR = = = 59.56 dB
amin 77.53 ⋅ 10 −6 ⋅ 4600

3.3.2. Quantization Noise 

In Fig 3.5, over a clock period, the reference charge from Cfb1-2 changes the
differential output voltage of the integrator by:

ΔVoutref = Qref / C int 1, 2 = Vref ⋅ Cfb1,2 / C int 1, 2 (3.21)

Referring to (3.17), the variation of sensing capacitance that it can balance is:

ΔCsref = 2 ⋅ Cfb1,2 (3.22)

This is the reference level (0 dBr) of the modulator.

Since the dynamic range of a sigma-delta modulator is SNRQ relative to the reference
level as shown in (3.2), the quantization-noise equivalent resolution is:

ΔCsn = 2 ⋅ Cfb1,2 / SNRQ (3.23)

3.3.3. Switch (kT/C) Noise 

If a capacitor C is in series with a switch (with on-resistance Ron) that periodically

opens as shown in Fig 3.5 [23], the on-resistance introduces thermal noise at the
output and, when the switch turns off, this noise is stored on the capacitor along with
the instantaneous value of the input voltage. The noise power that is sampled onto the
capacitor is:
∞
4kTRon
PSC ,noise = ∫ df = kT / C (3.24)
0 1 + (2πRon C )
2

 
Fig 3.5: Periodically sampled capacitor.
20 
 
The resistor’s thermal noise spread over the band from 0 to fS/2 according to
Nyquist-Shannon sampling theorem. With an oversampling ratio of OSR, the rms
voltage of the sampled noise inside the signal bandwidth fB is:

PSC ,noise kT
Vn = ⋅ fB = (3.25)
fS / 2 C ⋅ OSR

Therefore, the noise charge on the capacitor is:

Qn = C ⋅ Vn = kTC / OSR (3.26)

In Fig 3.4, during P1, the switch noise is sampled onto CS1-4 and Cfb1-2 respectively,
resulting in noise charge on each capacitor as (3.26). During P2, the noise charge is
transferred to the integrator output and changes the output voltage by ΔVoutn =
Qn/Cint1-2 respectively. And, during P2, assuming the op-amp is ideal and the op-amp
input is virtual ground, the closed switches induce again similar noise as those during
P1.

Due to the uncorrelation between all the noise sources, their powers can be summed
together, and over a clock cycle the differential output voltage of the integrator is
changed by [24]:

ΔVout ,n = 8 ⋅ QnCs
2
1− 4 + 4 ⋅ QnCfb1− 2 / C int 1, 2 =
2 2kT
(CS + 2C fb1,2 ) / Cint1,2 (3.27 )
OSR

From (3.17) and (3.27), the switch noise equivalent resolution is:

ΔC S ,n =
8kT
(CS + 2C fb1,2 ) / Vref (3.28)
OSR

3.3.4. Op­Amp Thermal Noise and DC Offset 

In principle, all noise sources except the input referred thermal noise Vn2 from the
amplifier are negligible. Due to the effective channel resistance, in an appropriately
designed amplifier, the input MOS transistor is the dominant noise contributor, and
the op-amp input-referred thermal noise power per unit bandwidth is (assuming a
differential input):

21 
 
 2
S ( f ) ≈ 8kT (3.29)
3g m

Apparently, the noise can be reduced by increasing the trans-conductance gm.

And the closed-loop bandwidth is:

gm
f cl = (3.30)
2πCcl

Where Ccl denotes the closed-loop load capacitance of the op-amp.

Cfb1

CS1 Cint1

CS2
Opamp1

Cl
Vn

0 0 0 0
 
st
Fig 3.6: Half circuit of the 1 integrator during P1.

According to sampling, the op-amp thermal noise spreads over the band from 0 to fS/2.
With an over-sampling ratio of OSR, the noise voltage inside the signal bandwidth fB
is:

π S ( f ) ⋅ f cl 4kT
Vtherm,n = ⋅ = (3.31)
2 OSR 3 ⋅ OSR ⋅ Ccl

Due to the charge integration by CS1-4 and Cfb1-2 during P2, Vn changes the op-amp
output voltage by:

ΔVout ,n = Vtherm,n ⋅ (0.5C S + C fb1, 2 ) / Cint 1, 2 (3.32)

Therefore, the loss of the sensing precision that is caused by the op-amp thermal noise

22 
 
is:

C S + 2C fb1, 2
ΔC S ,n = Vtherm ,n (3.33)
Vref

The closed-loop load capacitance Ccl of the op-amp is the open-loop capacitive load
Col divided by the loop transfer factor fint, which is given by [25]:

Cint 1, 2 (0.5C S + C fb1, 2 )

Cl +
Col Cint 1, 2 + 0.5C S + C fb1, 2 Cl (0.5C S + C fb1, 2 )
Ccl = =
Cint 1, 2
= 0.5C S + C fb1, 2 + Cl + (3.34)
f int Cint 1, 2
Cint 1, 2 + 0.5C S + C fb1, 2

If CS1-4 = Cfb1-2 = 0.17 pF, Cint1-2 = 0.51 pF, and Cl ≈ 0.25Cint1-2 (including the parasitic
capacitance of Cint1-2), then Ccl = 0.765 pF. Taking into account the thermal noise
contribution from other transistors of the op-amp, the op-amp thermal noise in (3.33)
is doubled and approximately equal to the switch noise in (3.28).

From (3.34), the noise contribution of op-amp DC offset can also be figured out.
Given CS = 4Cfb1,2 and Vref = 2.5 V, an DC offset of 20 mV is equivalent to 1.2%·CS
that is comparable to the inherent mismatch of the sensing capacitors (mechanical
offset).

3.3.5. Flicker (1/f) Noise 

Similar to the modeling method used in calculating op-amp thermal noise and DC
offset as described above, the op-amp flicker noise (1/f noise) can also be modeled as
a noise voltage Vn in series with the op-amp input terminals as shown in Fig 3.6.

For a one-stage differential op-amp with a large input trans-conductance, the input
transistors dominate the noise performance of the op-amp. The input-referred 1/f noise
power per unit bandwidth is:

K 1
S fl ,n ( f ) = 2 ⋅ ⋅ (3.35)
WL f

Where, K is the flicker noise coefficient. The in-band flicker noise voltage is:

fB
K
V fl , n = ∫ S ( f )df
1
fl , n = 2⋅
WL
⋅ ln ( f B ) (3.36)

23 
 
From (3.36) and (3.17), the flicker noise equivalent resolution is:

CS + 2C fb1, 2
ΔCS , n = V fl , n (3.37)
Vref

Compared with other noise sources, the flicker noise dominates at low frequency
within the signal bandwidth, thus it cannot be reduced by increasing the
over-sampling ratio. For every doubling of the transistor gate area, there is a 3 dB
improvement, which results in a significantly large gate area. If Vn = 10 μV, then
W·L > 4920 μm2, resulting in an enormously large area. However, a far more efficient
method to reduce 1/f noise, is to apply auto-zeroing technique into the 1st integrator as
explained in section 3.4.

3.4. Application of Auto­zeroing 

Auto-zeroing (AZ) is a widely accepted technique aiming at reducing the effect of

low-frequency noise, finite DC gain and offset of CMOS amplifiers used in
switched-capacitor (SC) circuits. The basic idea of AZ is sampling the unwanted
quantity (noise and offset) and then subtracting it from the instantaneous value of the
contaminated signal either at the input or the output of the op-amp [26].

 
Fig 3.7: The 1st integrator with auto-zeroing.

Fig 3.7 depicts the schematic of the 1st integrator with auto-zeroing using
offset-storage capacitors Ch1 and Ch2. The 1-bit DAC is not shown for clarity. The
principle of AZ is described considering not only the input-referred DC offset voltage
Vos but also the input-referred 1/f noise voltage Vfln.

24 
 
The AZ process has two phases: a sampling phase (P1) when the 1/f noise voltage Vfln
and the offset voltage Vos are sampled and stored, and a signal-processing phase (P2)
when the offset-free operation is available [26]. In Fig 3.7, during P1, the op-amp is
disconnected from the signal path, and CS1-4 and Cfb1-2 are pre-charging. The left
electrodes of Ch1-2 are connected to DC voltage Vref/2. The sum of the 1/f noise
voltage and offset voltage, Vfln+Vos, is stored onto Ch1-2 since the op-amp input
voltage is ideally zero due to negative feedback. During P2, by subtracting from the
time-varying noise a recent sample of the same noise which results in a cancellation,
the noise voltage at the left electrode of Ch1-2 is approximately zero. This indicates
that AZ effectively acts as a high-pass filter for DC and low-frequency noise.

3.5. The 2nd Integrator and Comparator 

The 2nd integrator and comparator are shown in Fig 3.8. During P1, the output voltage
Vo1-2 from the 1st integrator is sampled onto CS5-6. During P2, the voltage over CS5-6 is
zero, so the net charge transferred from CS5-6 to Cint3-4 is (Vo1 - Vo2)·CS5,6.

 
Fig 3.8: The 2nd integrator and comparator.

The operation of the 2nd DAC is explained as follows. During P1, the left electrodes
of Cfb3-4 track Vref and GND respectively and the right electrodes are connected to Vref.
During P2, the left electrodes of Cfb3-4 track GND and Vref respectively and the right
electrodes are connected to the op-amp input nodes with common-mode voltage Vref.
Therefore, the differential reference charges ±Vref·Cfb3,4 are transferred from Cfb3-4 to
Cint3-4.

At the rising edge of P1, the comparator makes decision which controls the feedback
25 
 
DACs.

3.6. System­Level Modeling of Circuit Non­idealities 

System-level modeling quickly establishes circuit block specifications, and easily

validates any changes on the system level. It can simplify the work on transistor-level
design as it can predict the performance of the system on a higher level. In this section,
the Σ-∆ ADC design in CMOS technology is introduced at the system level, most of
the sigma-delta modulator non-idealities, such as sampling jitter, kT/C noise and
operational amplifier parameters (noise, finite gain, finite bandwidth, slew rate and
saturation voltages).

System-level modeling and simulation are done by using Matlab/Simulink.

3.6.1. Clock Jitter 

The operation of a SC circuit depends on complete charge transfers during each of the
clock phases [27]. Once the sampling of analog input signal is finished, the SC circuit
is a sampled-data system where variations of the clock cycle have no impact on the
circuit performance. Therefore, the effect of clock jitter on an SC circuit is simply
described by computing its effect on the sampling of the input signal, which also
means that the effect of clock jitter on Σ-∆ modulator is independent of the structure or
order of the modulator.

Sampling clock jitter results in non-uniform sampling time sequence, and increases
the total error power at the quantizer output. The magnitude of this error is determined
by both the statistical properties of the jitter and the input signal to the modulator. The
error introduced when a sinusoidal signal with amplitude A and frequency fin is
sampled at an instant with offset δ is given by

d
x(t + δ ) − x(t ) ≈ 2πfinδA cos(2πfint ) = δ x(t ) (3.38)
dt

The model depicted in Fig 3.9, implements (3.38) and can be used to simulate the jitter
effect. Both the input signal x(t) and its derivative dx(t)/dt are continuous-time signals,
which are sampled with sampling period TS by a zero-order hold. In the model, the
sampling uncertainty δ is assumed to be a Gaussian random process n(t) with standard
deviation Δτ. The signal n(t) is implemented by a sequence of random numbers with
Gaussian distribution, zero mean, and unity standard deviation. Assuming a white
jitter, the error has uniform power spectrum density (PSD) from 0 to fs/2, with a total
power of (2πfin·Δτ·A)2/2. Thus, the total error power will be reduced by the
over-sampling ratio [28].

26 
 
  
Fig 3.9: Model of a random sampling jitter.

3.6.2. Switch Thermal Noise 

The most important noise sources affecting the operation of a SC modulator are the
thermal noise due to the sampling switches and the intrinsic noise of the operational
amplifiers.

The switch thermal noise voltage eT (eT2 = kT/CS as given in (3.24)), is superimposed
to the input voltage x(t) leading to [29]
⎡ kT ⎤
y (t ) = [x(t ) + eT (t )] b = ⎢ x(t ) + n(t )⎥ b
⎣ CS ⎦
⎡ kT ⎤
= ⎢ x(t ) + n(t )⎥ b (3.39)
⎢⎣ bC f ⎥⎦

Where n(t) represents a Gaussian random process with unity standard deviation, b
denotes the integrator gain CS/Cf (Cf is the integrating capacitor). The model
described by (3.39) is shown in Fig 3.10 [29].

The integrator in Fig 3.14 includes two SC input branches, one carrying the signal and
the other providing the feedback from the modulator output. Each branch has to be
modeled with a separate kT/C noise block, including the proper coefficient b.

 
Fig 3.10: Modeling switch thermal noise (kT/C block).
27 
 
3.6.3. Operational Amplifier Noise 

The model used to simulate the effect of the operational amplifier noise is shown in
Fig 3.11 [29], where Vn indicates the total rms noise voltage of the operational
amplifier referred to the integrator input. The op-amp noise consists of 1/f noise, DC
offset and wide-band thermal noise. In this project, since low-pass Σ-Δ modulator is to
be developed, flicker noise and DC offset are typically canceled by means of
auto-zeroing.

 
Fig 3.11: Op-amp noise block.

3.6.4. Finite DC Gain 

For an ideal integrator, the transfer function is:

z −1
H (z ) = (3.40)
1 − z −1

The DC gain of the integrator described by (3.40) is infinite. However, the actual gain
is limited by circuit constraints and particularly by the op-amp open loop gain A0.
With low op-amp open-loop gain, only a fraction α of the previous output of the
integrator is added to each new input sample (as shown in Fig 3.12). This loss of
charge is sometimes referred to as integrator leakage. The consequence of this
integrator “leakage” is that the in-band noise is increased.

The transfer function of the integrator with leakage becomes:

z −1
H (z ) = (3.41)
1 − αz −1

So, the DC gain of the integrator H0 is:

1
H 0 = H (1) = (3.42)
1−α

28 
 
  
Fig 3.12: Model of a real integrator.

3.6.5. Bandwidth and Slew Rate 

The finite bandwidth and the slew rate of the op-amp are modeled as a building block
placed in front of the integrator as shown in Fig 3.12 [29]. In switched-capacitor
circuits, finite BW and SR lead to a non-ideal transient response within each clock
cycle, thus resulting in an incomplete or inaccurate charge transfer to the output at the
end of the integration period.

 
Fig 3.13: Single-ended SC integrator.

Referring to the single-ended SC integrator shown in Fig 3.13, the change of output
voltage during the nth integration period (when Φ2 is on, between nTS –TS/2 and nTS)
is [29]:

⎛ −
t
⎞ T
v0 (t ) = v0 (nTS − TS ) + αVS ⎜⎜1 − e τ ⎟, 0 < t < S
⎟ (3.43)
⎝ ⎠ 2

Where, VS = Vin(nTS-TS/2), α is the integrator leakage (which accounts for the op-amp
finite dc gain A0) and τ = 1/(2π·GBW) is the time constant of the integrator and GBW
is the unity gain frequency of the integrator loop gain during the considered clock
phase. The slope of this curve reaches its maximum value when t = 0, resulting in:

d V
v0 (t ) = α S (3.44)
dt max τ

29 
 
Two separate cases as follows should be taken into account.

1) The value given by (3.44) is lower than the op-amp SR. In this case, there is no
slew-rate limitation and the evolution of v0 is described by (3.43) during the whole
clock period (until t = TS/2).
2) The value given by (3.44) is higher than SR. In this case, the op-amp is in slewing,
thus the first part of the transient of v0 (t < t0) is linear with slope SR. The
following equations hold (assuming t0 < TS/2):

t ≤ t0： v0 (t ) = v0 (nTS − TS ) + SR ⋅ t (3.45)

⎛ − 0 ⎞
t −t
t > t 0： v0 (t ) = v0 (t 0 ) + (αVS − SR ⋅ t0 )⎜⎜1 − e τ ⎟⎟ (3.46)
⎝ ⎠
To have a continuity of the derivatives of (3.45) and (3.46) in t0, we get

αVS
t0 = −τ (3.47 )
SR

If t0 ≥ TS/2, equation (3.45) holds for the whole clock period.

The above equations are implemented by the MATLAB function block in Fig 3.12 to
calculate the value of v0(t) at time TS, which will be different from VS because of the
DC gain, BW and SR limitations of the op-amp. Since harmonic distortion is induced
by the SR and BW limitations, the total SNDR of the Σ-Δ modulator is reduced.

3.6.6. Saturation 

Since the dynamic of signals in Σ-Δ modulator is of great concern. Therefore, it is

crucial to consider the saturation voltages of the op-amp used. This can simply be
done in SIMULINK using the saturation block inside the feedback of the integrator,
as shown in Fig 3.12.

 
Fig 3.14: Schematic of a 2nd order SC Σ-Δ modulator (non-ideal model).
30 
 
As shown in Fig 3.14 [29], issues like clock jitter, kT/C noise, op-amp noise,
sensitivity to amplifier DC gain, slew rate and settling time constant of op-amps,
integrator swings, have been analyzed.

The power spectral density (PSD) of the ideal modulator (quantization noise included
only) is shown in Fig 3.15. The input sinusoidal signal has a half-peak amplitude of
0.1455 V, which corresponds to -24.7 dB with a reference voltage of 2.5 V.

Power Spectral Density

0

-20

-40

-60
PSD [dB]

-80

-100

-120 SNDR = 82.1 dB

ENOB = 13.35 bits
-140

-160
3 4 5 6
10 10 10 10
Frequency [Hz]  
nd
Fig 3.15: PSD of the ideal 2 order SC Σ-Δ modulator.

The PSD of the modulator with quantization noise and kT/C noise is shown in Fig
3.16. And, the PSD with all the non-idealities that have been taken into account is
shown in Fig 3.17.

31 
 
 Power Spectral Density
0

-20

-40

-60
PSD [dB]

-80

-100

-120 SNDR = 72.7 dB

ENOB = 11.79 bits
-140

-160
3 4 5 6
10 10 10 10
Frequency [Hz]  
nd
Fig 3.16: PSD of the 2 order SC Σ-Δ modulator with kT/C noise (CS = 0.335 pF).

Power Spectral Density

0

-20

-40

-60
PSD [dB]

-80

-100

-120 SNDR = 71.7 dB

ENOB = 11.61 bits
-140

-160
3 4 5 6
10 10 10 10
Frequency [Hz]  
nd
Fig 3.17: PSD of the 2 order SC Σ-Δ modulator with all the above non-idealities.

Table 3.2 compares the SNDR obtained with an input signal of -24.7 dB (SNDR-24.7dB)
with respect to full-scale and the corresponding equivalent resolution in bits of the

32 
 
ideal modulator, which are the maximum obtainable with the architecture and
parameters used, with those achieved with the same architecture when one single
non-ideality at a time is introduced. Finally, the modulator is simulated with all of the
above non-idealities. It can be seen from Table 3.2 that, the kT/C noise is a dominant
noise contributor.

Table 3.2: SNDR and resolution of a 2nd order Σ-Δ modulator as interface circuit.
SNDR-24.7dB Resolution
Σ-Δ Modulator Parameter
[dB] [bits]
Ideal modulator 82.1 13.35
Sampling jitter (Δτ = 8 ns) 80.3 13.04
Switches (kT/C) noise (Csampling = 0.335 pF) 72.7 11.79
Input-referred operational amplifier noise 74.0 11.99
(Vn = 50 μVrms)
Finite DC gain (A0 = 50 dB) 80.7 13.11
Finite bandwidth (GBW = 20 MHz) 80.3 13.04
Slew-rate (SR = 4 V/μs) 80.9 13.15
Saturation voltages (Vmax = ± 0.95 V) 82.1 13.35
Modulators simulated including all the above 71.7 11.61

3.7. Summary 

This chapter discusses the circuit structure, analyzes the noise contributors,
investigates the system-level model of circuit non-idealities, and determines the
circuit parameters for a Σ-Δ modulator as an interface circuit for SOI accelerometers.
Due to the wide dynamic range and simplicity for implementation, a 2nd order Σ-Δ
modulator is chosen. The 1st integrator, acting as a capacitance-to-voltage converter, is
proposed in this design. Based on noise analysis, auto-zeroing technique is adopted to
reduce the flicker noise and DC offset. The architecture of the 2nd integrator and
comparator is presented. Finally, most of the Σ-Δ modulator non-idealities, such as
sampling jitter, kT/C noise and operational amplifier parameters (noise, finite DC gain,
finite bandwidth and slew rate, and saturation voltages), are modeled and simulated
on the system-level. Thus the specifications on circuit blocks are easily established.
The next chapter will illustrate the transistor-level implementation of an experimental
Σ-Δ modulator that fulfills these specifications.

33 
 
 34 
 
4. Electrical Interface Circuitry Design 
After system-level simulations are performed, enough parameters are available for
transistor-level implementation. This chapter illustrates the implementation of the Σ-Δ
ADC in the ABCD-3 process with 1μm 5V SOI-CMOS technology provided by NXP
Semiconductors. The integrators are presented first, and all required modules
including op-amps, comparator, band-gap reference and clock generator are designed,
and simulated. Finally, the layout is carried out.

The Σ-Δ modulator as interface circuit is shown in Fig 4.1 [24].

Cfb1 P2d&Y+

P2d&Y-
P1

Vref P1d Cfb3

Y+
Cfb2 P2d&Y-
Y-
P2d
P2d&Y+
P1
GND
Vref
P2d Cfb4
GND Y-
GND
CS1 Y+
P1d
P2d
GND
P1

CS2 Vref Vref Vref

Cint1 Cint3
P2 P1
P2d
P2d C P1
S5
P1 P1d P1d P2 0
Ch1 0 0
Y+
GND 0.5Vref Opamp1 Opamp2 P1d
Ch2 Y-
0.5Vref 0 0

P1 P1d P1d P2
CS4 CS6 Comparator
GND P2d P1
P2d
P2 P1
Cint2 Cint4
Vref Vref Vref

P1
CS3
P2d

 
nd
Fig 4.1: The 2 order SC Σ-Δ ADC as interface circuit.

4.1. Integrators 

The integrators have a significant impact on the performance of the Σ-Δ ADC.
According to the system-level simulations in section 3.6, some safety margins are
taken in the implementation of Σ-Δ modulator to assure integrator performance.

The two integrators and the comparator used in the modulator depicted in Fig 4.1 are
controlled by two-phase non-overlapping clocks P1 and P2, delayed phases P1d and
P2d and complements of the delayed phases P1d_m and P2d_m, as shown in Fig 4.2.

35 
 
  
Fig 4.2: Clock phases of the modulator.

4.1.1. The 1st Integrator 

The 1st integrator is shown in Fig 4.3. The operation has been explained in section 3.2
and 3.4.

 
st
Fig 4.3: Schematic of the 1 integrator.

The specifications of the capacitors in the 1st integrator are given in Table 4.1. In this
project, all the capacitors (except decoupling capacitors) are High Voltage oxide
(HV-stack) capacitors because of their linearity.
36 
 
 Table 4.1: Capacitor sizes in the 1st integrator.
Capacitor Size
Sensing capacitor CS1-4 0.17 pF each
Feedback capacitor Cfb1-2 0.17 pF each
Hold capacitor Ch1-2 1 pF each
Integrating capacitor Cint1-2 0.51 pF each

Table 4.2: Switch sizes in the 1st integrator.

Switch Type Size (μm)
S1, S3, S6 Single-transistor NMOS switch: NMOS: 6/1 each
Drain connected to Vref
S2, S4, S5 Single-transistor NMOS switch: NMOS: 3/1 each
Source connected to GND
S7 to S14 Low signal feed-through NMOS switch NMOS: 6/1 each
S15, S16, S19, S20 Low signal feed-through NMOS switch NMOS: 3/1 each
S17, S18 Low signal feed-through NMOS switch NMOS: 6/1 each

The sizes of the switches in the 1st integrator are shown in Table 4.2. All the switches
are implemented with minimum-length Low Voltage NMOS (LV-NMOS) transistors.
As depicted in Fig 4.4 (a), in a single-transistor switch, there is a parasitic diode
between source and drain when the switch is off. Due to the SOI technology, the
source of a transistor is connected to its bulk and there is a p-n junction between bulk
and drain, which can introduce voltage feed-through of large signal. In Fig 4.4 (b), a
more complex switch is used to tackle this problem. If the switch is off (when CLK is
low), these two parasitic diodes in opposite directions can effectively suppress the
signal feed-through. The same technique is applied to PMOS switches.

 
Fig 4.4 (a): A single-transistor NMOS switch; (b): A low signal feed-through NMOS
switch.

Theoretically, the op-amp input capacitance degrades both the speed and resolution of
the integrator. Since the bottom plate of a capacitor suffers more from parasitic
capacitance than its top plate, in this design the bottom plate of a capacitor is usually
driven by the input or the output of the integrator, while the top plate is connected to
the input terminals of op-amp to minimize the parasitic capacitance at the op-amp
input. For instance, in Fig 4.5, the bottom plate of Cint1 should be connected to the

37 
 
integrator output. This technique is applied to all the capacitors.

 
Fig 4.5: Schematic of an integrating capacitor.

4.1.2. The 2nd Integrator 

The 2nd integrator is depicted in Fig 4.6. Its operation has been explained in section
3.5. The capacitor and switch sizes are given in Table 4.3 and Table 4.4 respectively.

 
Fig 4.6: Schematic of the 2nd integrator.

Table 4.3: Capacitor sizes in the 2nd integrator.

Capacitor Size
Sampling capacitor CS5-6 0.4 pF each
Feedback capacitor Cfb3-4 0.2 pF each
Integrating capacitor Cint3-4 0.8 pF each

Table 4.4: Switch sizes in the 2nd integrator.

Switch Type Size (μm)
S1, S3 Single-transistor NMOS switch NMOS: 3/1 each
38 
 
 (Drain connected to Vref)
S2, S4 Single-transistor NMOS switch NMOS: 3/1 each
(Source connected to gnd)
S5, S6, S8, S9, S10 Low signal feed-through NMOS switch NMOS: 3/1 each
S7 Low signal feed-through CMOS switch NMOS: 3/1 each
PMOS: 9/1.2 each

4.2. Operational Amplifiers 

The operational amplifier used in integrators is the most important component of the
modulator. In order to suppress the distortion, the op-amps should have enough DC
gain. Besides, they should have sufficient slew-rate and large bandwidth to allow fast
settling response within the available period.

The performance of op-amp is less influenced by low-frequency noise, because the

op-amp thermal noise can be suppressed by increasing OSR, and the flicker noise can
be suppressed by applying auto-zeroing technique.

 
Fig 4.7: Folded-cascode op-amp with biasing circuits (PMOS input differential pair).

The need for high speed, coupled with a relatively modest gain requirement of 70 dB
to suppress harmonic distortion, encouraged the use of the fully-differential
folded-cascode op-amp as shown in Fig 4.7 [23]. Compared with telescopic cascode
op-amp, it has a larger output voltage swing. PMOS transistors P1-2 are used for input
differential pair because of the low input common-mode voltage (1.25 V) in the 1st
integrator. P3-4 and N3-4 are the current mirrors, and P5-6 and N1-2 are the cascode
transistors. Other transistors in the op-amp make up the biasing circuit. All the
39 
 
transistors work in the saturation region.

System-level simulation with non-idealities indicates that a DC gain of 70 dB,

slew-rate of 100 V/μs, GBW of 100 MHz is sufficient to fulfill system objectives.
Since the comparator can be designed to be quite fast, the settling speed of the
integrator becomes a key factor on limiting the achievable sampling rate of the
modulator.

With proper choice of Vb1 and Vb2, the lower limit of the swing is given by
VodN1+VodN3, and the upper limit by Vdd-(|VodP3|+|VodP5|). Thus, the peak-to-peak swing
on each cascode branch is equal to Vdd-(VodN1+VodN3+|VodP3|+|VodP5|), and the
differential peak-to-peak swing is 2·[Vdd-(VodN1+VodN3+|VodP3|+|VodP5|)], where Vod =
Vgs-Vth denotes the overdrive voltage. The op-amp output voltage swing should satisfy
the following inequality:

2[Vdd − (VodN 1 + VodN 3 + VodP 3 + VodP 5 )] ≥ 3 V (4.1)

And, the small signal voltage gain of the folded-cascode op-amp is [23]:

Av = g mP1 Rout ≈ g mP1 { [( g mN 1 + g mbN 1 )roN 1 (roP1 || roN 3 )] || [( g mP 5 + g mbP 5 )roP 5 roP 3 ] } (4.2)

Where, ro ≈ 1 / λI D ∝ L / I D and g m = 2 β I DW / L = 2 I D / Vod . Doubling the length

and width of a transistor will double its gm·ro, since gm remains constant while ro
doubles.

The dominant pole is at the op-amp output determined by the output impedance ro and
the load capacitance CL. The unity-gain frequency of the op-amp is:

ω0 = g mP1 / C L (4.3)

P1-4 and N3-4 are the noise sources, and the input-referred noise power per unit
bandwidth is [23]:

⎛ 4 4 g 3 4 g mN 3 ⎞ 2K p 2 K p ⋅ g mP
2
2 K n ⋅ g mN
2
Vn2 = 4kT ⎜⎜ 2 + mP + ⎟
⎟ + +
3
+ 3
(4.4)
⎝ 3 g mP1 3g mP1 3 g mP1 ⎠ (WL )P1 f (WL )P 3 f ⋅ g mP1 (WL )N 3 f ⋅ g mP1
2 2 2 2

Where, Kp and Kn are the flicker noise coefficients of PMOS and NMOS transistors
respectively.

40 
 
In order to have a maximum output voltage swing, the drains of N3-4 and P3-4 are
biased almost at the minimum voltage required to remain in saturation, for example,
the drain source voltage of P3-4 is VdsP3-4 = 1.5·Vdsat0 to keep P3-4 in saturation with
some margins.

An improved version of the switched-capacitor common-mode feedback (SC-CMFB)

circuit for the op-amp in Fig 4.7 is depicted in Fig 4.9 [30]. Vbias is the bias voltage for
the current sources N3-4. Vref is the desired output common-mode voltage of the
op-amp. Due to the symmetry of the SC-CMFB, only half of the circuit needs to be
analyzed. Referring to the right half (equivalently the circuit in Fig 4.8), during clock
phase P2d, C1+ and C1－ are connected to C2+ and C2－, respectively. The dc voltage
across C2+ and C2－ is set by C1+ and C1－ respectively, and is refreshed in every P2d.
During clock phase P1d, C1+ and C1－ are charged to Vref-Vbias and capacitors C2+ and
C2－ generate the control voltage Vctrl, level-shifting the average output voltage by
Vref-Vbias. The CM is controlled by the negative feedback of the CM loop, once the
CM voltage is defined at the output nodes after startup. Any CM variation at the
output nodes (outp and outn) is coupled at node Vctrl via C2+ and C2－. As Vctrl changes,
the gate-source voltage of transistors N3 and N4 changes, which in turn, changes the
current sunk by these transistors, cancelling the variation of the output CM. Therefore,
as long as the CM loop gain is large enough and has enough bandwidth to stabilize
fast CM variations, the CM output voltage is always maintained at the reference CM
value.

Different from the conventional SC-CMFB circuit shown in Fig 4.8, in this circuit, an
extra set of capacitors C1 and an extra set of switches are used. Compared to the
switches on the right side, switches on the left side of axis of symmetry through outp
and outn node, operate with opposite clock phase. Therefore, during every clock
phase, the total loading on the differential loop is CT = C1 + C2. The value of C2 can
be determined by making the CM loop bandwidth comparable to that of the DM loop,
thus C1 can be designed 5−10 times that of C2 for faster DC settling, lower
steady-state errors, leakage errors and charge injection errors [30]. Therefore, better
performance of SC-CMFB can be achieved using the circuit in Fig 4.9, for the same
total capacitance loading of the DM loop, at the cost of additional chip area.
 

 
Fig 4.8: Conventional SC-CMFB circuit.
 

41 
 
  
Fig 4.9: SC-CMFB configuration with symmetric loading of the DM loop.

4.2.1. The 1st Op­Amp 

The 1st op-amp shown in Fig 4.7 and Fig 4.9 should fulfill the requirements in Table
3.2.

The temperature-independent tail current of the input differential pair P1-2 is set to 100
μA, providing a safe margin. To meet the requirement on output voltage swing, the
output CM voltage is Vref = 2.5 V and the overdrive voltages Vod of transistors (N1-4
and P3-6) are set to 0.3 V at 27°C. The overdrive voltages of the input differential pair
are set to 0.2 V at 27°C to have a large input trans-conductance (note that it will range
from approximately 0.15 V at −40°C to 0.3 V at +150°C). Thus the W/L ratio of all
transistors can be determined from Id = (β/2)·(W/L)·Vod2. The lengths of the input pair
are set to 1.5 μm regarding the trade-off among high dc gain, low flicker noise and
small input capacitance. And, the lengths of the transistors on cascode branches are
set to 2 μm for high dc gain and low flicker noise.

Table 4.5: Transistor sizes in the 1st op-amp.

Transistor Size Transistor Size
P1, P2 (10 μm/1.5 μm)·15 P3-6 (10 μm/2 μm)·10
P7, P8 (10 μm/2 μm)·20 P9, P10 (10 μm/2 μm)·8
P11, P14 (10 μm/2 μm)·1 P12, P13 (10 μm/2 μm)·4
N1, N2 (10 μm/2 μm)·5 N3, N4 (10 μm/2 μm)·10
N5, N8 (10 μm/2 μm)·1 N6, N7 (10 μm/2 μm)·4

The transistor sizes are illustrated in Table 4.5. Unit transistor is used for matching.
The current feed into the op-amp is 20 μA and the total current consumption is 275
μA.

Table 4.6 and Table 4.7 illustrate the capacitor values and switch sizes in the
SC-CMFB circuit in Fig 4.9, respectively.

Table 4.6: Capacitor sizes in the CMFB circuit.

Capacitor Value
C1 200 fF
42 
 
 C2 40 fF

Table 4.7: Switch sizes in the CMFB circuit.

Switch Type Size (μm)
Switches connected Low signal feed-through CMOS NMOS: 1.5/1 each
to outp and outn switch PMOS: 4.5/1.2 each
Other switches Low signal feed-through NMOS NMOS: 1.5/1 each
switch

Fig 4.10 illustrates the amplitude and phase responses of the op-amp.

 
Fig 4.10: Amplitude and phase responses of the op-amp.

Fig 4.11 shows the simulation results from transient analysis.

43 
 
  
Fig 4.11: Results from transient simulation.

In Fig 4.12, it can be seen that the flicker noise dominates in the low-frequency
component. At dc, the noise power is approximately 110×10-9 V2, while at 5 kHz, it is
2.234×10-11 V2.

 
Fig 4.12: Results from noise analysis.

The noise summary for individual contributors is shown in Fig 4.13, where Sfl means
flicker (1/f) noise, and Sth means channel thermal noise. It can be seen clearly that the

44 
 
NMOS transistors for the current sources contribute most of the flicker noise. The
total summarized noise is 5.42×10-7 V2, and the total input-referred noise is 6.94×10-10
V2. Thus, the in-band flicker noise specified as a spectral density in rms volts per root
Hertz is about 10.1 μV/√Hz.

 
Fig 4.13: Individual contributors from noise summary.

The performance of the 1st op-amp in simulation is given illustrated in Table 4.8.

Table 4.8: Performance of the 1st op-amp.

Parameters Value
Supply voltage Vdd 5V
DC open-loop gain Adc 73.8 dB
Unity-gain frequency (CL = 1pF) 89.4 MHz (at 27°C)
Phase margin (CL = 1pF) 57.6°
Output voltage swing > ±3 V (−40°C to +150°C)
In-band flicker noise 10.1 μV/√Hz
Input capacitance of P1 and P2 254 fF
Current consumption 275 μA

4.2.2. The 2nd Op­Amp 

The 2nd op-amp is also a folded cascode op-amp. It is the same as the 1st op-amp in
Fig 4.7. The CMFB circuit is the same as that in Table 4.6 and Table 4.7.

4.3. Comparator 

The second major component of the modulator is the quantizer. The one-bit quantizer
is realized with a dynamic comparator and a SR latch as shown in Fig 4.14 [31] and
Fig 4.15 respectively. The function of the comparator in a sigma-delta modulator is to
quantize a signal in the loop and provide the digital output of the modulator. The
structure and operation are explained as follows.
45 
 
  
Fig 4.14: Schematic of the dynamic comparator (with CLK controlled by P1d).

Transistors M1a and M1b constitute an NMOS differential pair. NMOS transistors
M2a and M2b are controlled by the clock and act as cascode devices. Since the design
does not use a separate pre-amplifier, these cascode transistors (also called isolation
transistors) help to minimize the kickback noise by separating the drain nodes of the
input differential pair from the regeneration nodes during the regeneration process.
NMOS transistors M3a and M3b, together with PMOS transistors M4a and M4b,
form a regeneration circuit. The regeneration is done by two cross-coupled CMOS
inverters. During the regeneration process, their current increases momentarily to
charge the output nodes faster [32]. PMOS transistors M5a and M5b implement the
switching transistors.

While clock CLK is low, the transistor M5a and M5b reset the output node P and Q to
AVDD. M2a and M2b are off and no supply current exists. When CLK goes high, the
reset transistors M5a/M5b are opened, and the pre-charged parasitic capacitances of
node P and Q are discharged by transistor M1a and M1b respectively. The discharge
rate of each cross-coupled inverter (M3a/M4a or M3b/M4b) depends on the input
voltage. When the voltage of node P and Q drops to the threshold voltage of the latch
formed by two cross-coupled inverters, the regeneration process starts [33]. Finally,
the voltage of node P and Q reaches the rail voltage according to the decision made.
The following SR latch shown in Fig 4.15 then latches the result. The whole
comparator is a purely dynamic circuit, which is quite power efficient.

For a single-bit Σ-Δ modulator, the requirement for the quantizer is quite relaxed as
non-idealities such as the comparator offset and hysteresis in this stage can be largely
suppressed in the baseband by the second-order noise shaping.

46 
 
  
Fig 4.15: Schematic of the SR latch and buffers.

The comparator outputs are buffered by digital inverters (CNIV) and then recorded by
off-chip data acquisition system for testing. All the transistors are of the size 10 μm/2
μm.

4.4. Bandgap Reference 

The bandgap reference generates both the reference voltages and temperature
independent bias currents for the modulator. In Fig 4.16, the pre-regulated circuit is
introduced to supply a relatively stable voltage for the reference, which is also a
proportional to absolute temperature (PTAT) current source [34]. In this pre-regulator,
the drain voltage of MP6 can be seen as a pseudo-supply whose fluctuations are much
smaller than those of AVDD.

In Fig 4.16, the start-up circuit consists of MP0, Q1, Q2 and R1. As soon as the
steady-state current is established in the current loop, the voltage drop over R1 and R2
is large enough to turn off Q2 and then disconnect the start-up circuit from the bias
circuit. In order to turn off Q2 quickly, a W/L ratio of MP0 much less than unity is
chosen and R1 should be large enough.

After start-up, for the base-emitter loop composed of Q3,4,5,6 and R2, a KVL
equation is given as:

VBE 3 + VBE 6 = VBE 4 + VBE 5 + I1 R2 (4.5)

Assuming that the transistors work in the forward-active region, the base-emitter
voltage VBE is:
⎛I ⎞
VBE = VT ln⎜⎜ C ⎟⎟ (4.6)
⎝ IS ⎠

47 
 
Where, VT = kT/q is the thermal voltage, and IS is the reverse saturation current which
is proportional to the emitter area. Substituting (4.6) into (4.5) gives:

⎛I ⎞ ⎛I ⎞ ⎛I ⎞ ⎛I ⎞
VT ln⎜⎜ C 3 ⎟⎟ + VT ln⎜⎜ C 6 ⎟⎟ = VT ln⎜⎜ C 4 ⎟⎟ + VT ln⎜⎜ C 5 ⎟⎟ + I1 R2 (4.7 )
⎝ IS ⎠ ⎝ IS ⎠ ⎝ IS ⎠ ⎝ mI S ⎠

Assuming the MOS transistors MP1,2,3,4 have the same aspect ratio, neglecting the
base current, thus

I C 3 = I C 6 = I C 4 = I C 5 = I1 = I 2 = I (4.8)

Simplification gives:

VT ln m kT ln m
I= = (4.9)
R2 qR2

Where, I is a PTAT current, and m is the emitter ratio of Q5 and Q6. Substituting k =
1.38×10-23 J/K, T = 300 K, and q = 1.6×10-19 C into (4.9), when the desired current I
= 10 μA, m is chosen to be 6, we have R2 = 4.64 kΩ. In practice, R2 is tuned to 4.77
kΩ in order to ensure that I is as close as possible to 10 μA.

 
Fig 4.16: Schematic of the bandgap reference circuit.

Neglecting the temperature dependence of R3, I3 is a PTAT current since it is mirrored

from I1 and I3 = b·I1 = b·I.

48 
 
For R3/R2 = n, Q7 and Q8 are identical (thus VBE7 = VBE8), the reference voltage Vref is:

VT ln m
Vref = 2VBE 7 + b ⋅ I ⋅ R3 = 2VBE 7 + b ⋅ ⋅ R3
R2
= 2VBE 7 + b ⋅ n ⋅ VT ln m (4.10)

where, VBE7 has a negative temperature coefficient (TC) of approximately -1.8 mV/°C
at 27°C, and VT has a positive TC of +0.086 mV/°C. Theoretically, to obtain a
temperature-independent voltage Vref, it should be ensured

∂Vref ∂VBE 7 ∂V R
=2 + b ⋅ T ⋅ 3 ⋅ ln m
∂T ∂T ∂T R2
= −3.6 + 0.086 ⋅ b ⋅ n ⋅ ln m (4.11)
=0

Since m = 6, b is set to 5 to get a 2.5 V reference voltage, we have n = 4.67 and thus
R3 = 21.68 kΩ.

In equation (4.11), the required value of ∂Vref / ∂T is tuned to get the zero TC.

Trimming on R3 can be done to achieve a best TC, and R3 is tuned to 20 kΩ in the

circuit. In the same way, R4 is calculated to be 18.07 kΩ and tuned to 17.5 kΩ.

The bandgap reference is followed by an op-amp as voltage buffer, providing low

output impedance Rout. In the layout of the circuit, a large external capacitor needs to
be placed between the buffer output and ground as shown in Fig 4.17 [20], which
yields averaging of current spikes taken from the buffer because they are fed from Cext.
Then the total switched-capacitor load CSCLoad of Vref can be modeled as a resistor of
value 1/(fs·Cext). In Fig 4.1, CSCLoad is:

C SCLoad = C fb1, 2 / 2 + (C S1 + C S 4 ) / 2 + 2 ⋅ C fb 3, 4 = 0.655 pF (4.12)

This will attenuate Vref to a degree determined by Rout. The average current taken from
the buffer is:

I bf = Vref ⋅ f s C SCLoad ≈ 4.1 μA (4.13)  

 
The current consumption of the bandgap reference circuit and op-amp as buffer is 110
μA and 320 μA respectively.

49 
 
  
Fig 4.17: Bandgap reference with voltage buffer and external capacitor.

It can be measured from the simulation results depicted in Fig 4.18 that, the maximum
variation of Vrefout over the temperature range from −40°C to +150°C is approximately
6.22 mV, and 7.87 mV for 0.5Vrefout.

 
Fig 4.18: Simulation results of the bandgap reference circuit.

4.5. On­Chip Clock Generator 

The on-chip clock generator is shown in Fig 4.19. The external clock input signal is
buffered by the SR NAND latch, and then two main non-overlapping clock signals
(P1 and P2) are generated. To avoid signal dependent charge injection, two delayed
clock phases (P1d and P2d) are generated to drive different switches. Their inverse
versions (P1d_m and P2d_m), are also generated in the latch loop by inverters. The
master clock input CLK, with 50% duty cycles and period of 400 ns (corresponds to fs
50 
 
= 2.5 MHz), is supplied from off-chip circuit.

Since the delay of each inverter is about 0.2 ns, chains of inverters are used in the
latch loop so as to introduce enough delay. From Fig 4.21, it can be figured out that
the delay of P1d/P1d_m from P1 is 2 ns and the separation between P1d/P1d_m and
P2 is 6 ns; the delay of P2d/P2d_m from P2 is 2 ns and the separation between
P2d/P2d_m and P1 is also 2 ns at 27°C.

 
Fig 4.19: Schematic of the clock generator.

 
Fig 4.20: Simulation results of clock generator.

51 
 
  
Fig 4.21: Simulation results of clock generator (zoomed-in version).

4.6. Simulation Results 

The modulator depicted in Fig 4.1 is simulated using transistor-level models to

evaluate the performance on signal transfer function, quantization noise shaping and
distortion, etc. The input signal is ΔCsmax = 0.039 pF at 1.6785 kHz.

 
st nd
Fig 4.22: Output swings of the 1 integrator (middle) and the 2 integrator (bottom).

52 
 
The output signal swings of the 1st integrator and the 2nd integrator are depicted in Fig
4.22. Their envelopes follow ΔCsmax. They are both within ±2V, which fits the op-amp
output range (±3V) without significant harmonic distortions.

Fig 4.23 shows the two-level digital single-bit stream at the output of the modulator in
time domain. The duty cycle of the output pulses follows the input signal ΔCs.

 
Fig 4.23: Output single-bit stream of the modulator and input sinusoidal signal.

Then the output single-bit stream is windowed by a Hanning window and FFT is used
in calculating the PSD of the bit-stream.

In order to increase the spectral resolution of a Fast Fourier Transform (FFT),

coherent sampling technology is used which is one of the most useful techniques for
evaluating the dynamic performance of high-speed ADCs. Coherent sampling
describes the sampling of a periodic signal, where an integer number of cycles fit into
a predefined sampling window [35]. Mathematically, this can be expressed as:

N window
f in = f sample (4.14)
N record

Where, fin is the periodic input signal frequency, fsample is the sampling frequency,
Nwindow is the integer number of cycles within the sampling window (must be an odd
or prime number), and Nrecord is the number of data points in the sampling window or
FFT (must be a power of 2).

The conditions for coherent sampling are met by choosing fin = 1.7548 kHz, fs = 2.5

53 
 
MHz, Nwindow = 23, and Nrecord = 215. Therefore, a modulator with OSR = 250 and 66
in-band FFT bins requires 32768 sample points. Note that a Hanning window of
length N is:

⎛ ⎛ 2π ⋅ (0 : N − 1) ⎞ ⎞
whn = 0.5⎜⎜1 − cos⎜ ⎟ ⎟⎟ (4.15)
⎝ ⎝ N ⎠⎠

which does not smear tones located exactly in a bin.

When Vrefa,b = 2.5±0.1455·sin(2πfin·t) V, it is not so clear to tell the digital high level
(5 V) and the digital low level (0 V) from the output of Σ-Δ modulator as shown in
Fig 4.23.

The simulation time is about 20 hours, which can be reduced to approximately 6.5
hours by excluding the bandgap reference and clock generator in simulating the
modulator. They are only modeled as a voltage source with certain output impedance.
A DC offset of 10 mV is added at the input of the 1st op-amp to introduce some input
transistor pair mismatch.

Fig 4.24 and Fig 4.25 illustrate the output spectrum of the modulator in frequency
domain without (Fig 4.24) or with (Fig 4.25) DC offset in the 1st op-amp respectively.
Some comments on the simulation results are:

a) Since the device models used in transient analysis are noiseless, the output
power spectrums in Fig 4.24 and Fig 4.25 do not include the contributions of
switch noise, op-amp thermal noise and flicker noise, but only contain
quantization noise, harmonic distortions and numerical errors due to accuracy
of finite in-band FFT bins, simulator algorithm and device models, etc.
b) Both figures show the 2nd order quantization noise shaping of 40 dB/decade,
and most of the quantization noise moves to higher frequencies outside the
signal bandwidth.
c) In both figures, significant harmonic distortion is not observed within the
signal bandwidth of 5 kHz. Therefore, it can be inferred that the
implementation of the op-amps, the capacitors, the switches and the DACs
have sufficient linearity.
d) In Fig 4.24, the signal to noise-and-distortion ratio (SNDR) is 77.49 dB when
DC offset is not introduced, and it is 70.16 dB in Fig 4.25 when DC offset is
added. Compared to the result from system-level simulation as shown in
Table 3.1, which is 82.1 dB for the ideal modulator, one reason is the finite
DC gain of op-amps degrades the attenuation of quantization noise in the
signal bandwidth. The other reason is the limited accuracy of the simulator.
e) In Fig 4.25, the FFT bin at the lowest frequency is corresponding to
frequency smearing of DC offset by Hanning window, and its power is

54 
 
 -73dBr. The auto-zeroing technology effectively reduces the op-amp DC
offset together with the flicker noise.

A best-case estimation of the trade-off between bandwidth, resolution and power can
be derived from the Figure-Of-Merit (FOM) [36]:

Pd
FOM = [pJ/conversion ] (4.16)
2 ⋅ fN
N

Where Pd is the power dissipation, N is the effective number of bits and fN is the
Nyquist sampling frequency. In the modulator, Pd = 5 mW, N = 11 related to the
full-scale, and fN = 10 kHz. Substituting these values into (4.16), we get FOM = 244
pJ per conversion step.

PSD of output signal from ADC, with Hanning window, N=32768

0

-20

-40
Normalized power

40 dB/decade
-60

-80

-100

5 kHz Bandwidth
SINAD=77.494
-120
1 2 3 4 5 6 7
10 10 10 10 10 10 10
Frequency  
Fig 4.24: Output spectrum of the modulator (without DC offset), SNDR = 77.49 dB.

55 
 
 PSD of output signal from ADC, with Hanning window, N=32768
0

-20

-40
Normalized power

40 dB/decade
-60

-80

-100

-120
5 kHz Bandwidth
SINAD=70.1603
-140
1 2 3 4 5 6 7
10 10 10 10 10 10 10
Frequency  
Fig 4.25: Output spectrum of the modulator (with DC offset), SNDR = 70.16 dB.

4.7. Layout 

The layout of the interface circuit is depicted in Fig 4.26. The total chip area is 1.2
mm×1.1 mm. The blank region is filled by decoupling capacitors for supply voltage
and reference voltages, which is not shown for clarity. Separate bond-pads for analog
and digital supply voltage are added. On-chip sampling and feedback capacitors CS1-4
and Cfb1-2 (0.17 pF each) in the 1st integrator, together with their enable/disable pins,
are implemented to make it possible to test the modulator without or with an
accelerometer. The test setup is given in detail in Appendix F. The floor-planning and
the pin-list of the chip layout are explained in Table 4.9 and Table 4.10 respectively.

Table 4.9: Floor-planning of the layout.

1 Switches in the 1st integrator 7 Op-amp in the 2nd integrator
2 Op-amp in the 1st integrator 8 Sampling, feedback and integrating
capacitors in the 2nd integrator
3 Integrating capacitors Cint1-2 in the 9 Comparator
st
1 integrator
4 Offset-storage capacitors Ch1-2 in 10 Bandgap reference
st
the 1 integrator
5 On-chip sampling and feedback 11 Op-amp as buffer for reference
st
capacitors CS1-4 and Cfb1-2 in the 1 voltages
integrator
56 
 
 6 Switches in the 2nd integrator 12 Clock generator

 
Fig 4.26: Layout of the interface circuit.

Table 4.10: Pin list of the chip.

B1 B11 Digital ground
B2 Interfacing off-chip accelerometer B12 Digital supply voltage
B3 CS1-4, respectively B13 Master clock
B4 B14 Output single-bit stream of the
B5 Interfacing off-chip mechanical B15 modulator
B6 capacitors Cfb1-2, respectively B16 Enable/disable on-chip
reference voltage
B7 Off-chip Vref/2, for stand-alone test B17 Enable/disable on-chip Cfb1-2
B8 Output current of the bandgap B18 Enable/disable on-chip CS1-4
reference circuit (10 μA) B19 Off-chip Vref, Vrefa, Vrefb
B9 Analog supply voltage B20 respectively, for testing the
B10 Analog ground B21 stand-alone modulator

4.8. Summary 

This chapter illustrates the transistor-level implementation of the Σ-Δ modulator as

interface circuit, including the design of the integrators, op-amps, comparator,
bandgap reference, clock generator and layout. The modulator has satisfactory
performance over supply voltage ranging from 4.75 V to 5.25 V, and under

57 
 
temperature ranging from -40ºC to +150ºC.

Table 4.11 summarizes the accelerometer performance.

Table 4.11: Summary of the accelerometer performance.

Rest capacitance Cs 0.67 pF
Full scale ΔCsmax 0.039 pF
Signal bandwidth DC to 5 kHz
Oversampling ratio OSR 250
Sampling frequency fs 2.5 MHz
Peak SNDR 70 dB
Resolution ΔCsmin 15 aF
Supply voltage 5V
Power consumption 5 mW
Chip area 1.32 mm2
Temperature range -40ºC to +150ºC
Technology process 1 µm SOI-CMOS

58 
 
5. Conclusions and Future Work 

5.1. Conclusions 

Micromachined accelerometers, one of the most important classes of MEMS devices,

are widely used in applications ranging from automotive safety and stability systems
to biomedical applications, oil and gas exploration, computer accessories, etc. The
objective of this design project is to design an interface circuit for SOI accelerometers
in automotive stability systems. This work has focused on two topics: the analysis of
accelerometer system and the design of a low-power high-resolution interface circuit
in top-down methodology.

The principle of the accelerometer model indicates that sensor capacitance changes in
response to external acceleration. Accelerometer systems are classified into open-loop
and closed-loop systems, depending on whether a force feedback loop is applied to
the sensor. In this design, open-loop structure is used as it is simple and effective for
the application. The specifications of SOI accelerometers and its readout circuitry
have been proposed. A fully differential sigma-delta modulator is adopted in this
project due to its wide dynamic range, inherent linearity and relaxed accuracy
requirements on the analog circuit.

The 1st integrator is a crucial component in the design of a 2nd order sigma-delta
modulator. It acts as a capacitance-to-voltage converter and determines the noise and
distortion performance of the modulator. Based on noise analysis, auto-zeroing
technique is applied to reduce flicker noise and DC offset, achieving high resolution.
The specifications on circuit blocks are easily established by modeling and simulating
non-idealities of the Σ-Δ modulator, such as sampling jitter, kT/C noise and
operational amplifier parameters (noise, finite DC gain, finite bandwidth and slew rate,
and saturation voltages) on the system-level in MATLAB.

An experimental Σ-Δ modulator that fulfills these specifications is implemented in the

ABCD-3 process with 1μm 5V SOI-CMOS technology provided by NXP
Semiconductors. This includes implementation of the integrators, op-amps,
comparator, bandgap reference, clock generator and layout. In the simulation, the
modulator performs well in a 5 kHz bandwidth from -40 ºC to +150 ºC, and has a
peak SNDR of 70 dB which corresponds to 11-bit resolution and minimum
capacitance resolution of 15 aF. The chip area is 1.32 mm2 with power consumption
of 5 mW.

5.2. Future Directions 

This design work may be extended to lower voltage operation (i.e., 3.3 V) despite the
large threshold voltage of transistors (approximately 1 V). The reference voltage can
59 
 
be tied to supply voltage for better resolution.

Some trade-offs can be made between the power dissipation and resolution, to allow
the use of other ADCs such as successive approximation registers (SAR) as interface
circuit for accelerometers.

This work has been verified by CADENCE which is a mixed-mode simulation tool.
The transistor-level simulation is very time consuming. In recent years, the
mixed-signal circuit design is more and more popular. In order to speed up the period
of design flow path, using other modeling level simulation tool such as Verilog-A is
an important method. Besides, demonstrating the operation and performance metrics
of the designed interface circuit by taping out and measuring is another important
process in the future.

The next research interest would be to employ a closed-loop system. Force-feedback

may improve many characteristics of a sensor including bandwidth, dynamic range
and linearity. The most popular approach is to pulse-modulate the force-feedback
signal [15]. High-order closed-loop system (i.e., 2nd order sensor element and 2nd
order electronic filter [37]) may result in low quantization noise.

60 
 
6. References 
[1] B. V. Amini, A Mixed-Signal Low-Noise Sigma-Delta Interface IC for
Integrated Sub-Micro-Gravity Capacitive SOI Accelerometers, Doctoral Thesis,
Georgia Institute of Technology, May 2006.

[2] G. Zhang, Design and Simulation of A CMOS-MEMS Accelerometer, Master

Thesis, Carnegie Mellon University, May 1998.

[3] W. Yun, A surface micromachined accelerometer with integrated CMOS

detection circuitry, Doctoral Thesis, U.C. Berkeley, 1992.

[4] http://en.wikipedia.org/wiki/Bulk_micromachining

[5] B. V. Amini and F. Ayazi, “A 2.5-V 14-bit ΣΔ CMOS SOI Capacitive

Accelerometer”, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2467–2476, Dec.
2004.

[6] http://www.sensorsmag.com/sensors/article/articleDetail.jsp?id=361648

[7] http://en.wikipedia.org/wiki/Silicon_on_insulator

[8] V. P. Petrov, High-Order Sigma-Delta Interface for Micromachined Inertial

Sensors, Doctoral Thesis, U.C. Berkeley, 2004.

[9] B. V. Amini and F. Ayazi, “Micro-gravity Capacitive Silicon-on-Insulator

Accelerometers”, J. Micromech. Microeng., vol. 15, pp. 2113-2120, Sep. 2005.

[10] http://www.micromagazine.com

[11] S. D. Senturia, Microsystem Design, Kluwer Academic Publishers, 2001.

[12] A. M. Lemkin, Micro accelerometer design with digital feedback control,

Doctoral Thesis, U. C. Berkeley, 1997.

[13] T. B. Gabrielson, “Mechanical-thermal noise in micromachined acoustic and

vibration sensors”, IEEE Trans. Electron Devices, vol. 40, no. 5, pp. 903 – 909, May
1993.

[14] A. Selvakumar, A multifunctional silicon micromachining technology for

high performance microsensors and microactuators, Doctoral Thesis, U. Michigan,
1997.

[15] A. M. Lemkin, B. E. Boser, “A three-axis micromachined accelerometer with

61 
 
a CMOS position-sense interface and digital offset-trim electronics”, IEEE J.
Solid-State Circuits, vol. 34, no. 4, Apr. 1999.

[16] B. E. Boser and R. T. Howe, “Surface Micromachined Accelerometers”,

IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 366-375, Mar. 1996.

[17] V. Peluso, M. Steyaert, and W. Sansen, Design of Low-Voltage Low-Power

CMOS Delta-Sigma Converters, Kluwer Academic Publishers, 1999.

[18] D. A. Johns, K. Martin, Analog Integrated Circuit Design, John Wiley & Sons
Inc, 1997.

[19] B. V. Amini, S. Pourkamali, M. Zaman, and F. Ayazi, “A new input switching

scheme for a capacitive micro-g accelerometer”, Tech. Dig. 2004 Symposium on VLSI
Circuits, pp. 310-313, Jun. 2004.

[20] S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data

Converters: Theory, Design and Simulation, IEEE Press, 1997.

[21] T. B. Gabrielson, “Mechanical-thermal noise in micromachined acoustic and

vibration sensors”, IEEE Trans. Electron Devices, vol. 40, no. 5, pp. 903 – 909, May
1993.

[22] J. Bernstein, R. Miller, W. Kelley, and P. Ward, “Low noise MEMS

vibration sensor for geophysical applications”, in Proc. Solid-State Sensor and
Actuator Workshop 1998, pp. 55 – 58.

[23] B. Razavi, “Design of Analog CMOS Integrated Circuits”, McGraw-Hill,

2001.

[24] Y. Yu, A Sigma-delta ADC as Interface Circuit for SOI Accelerometers,

Master Thesis, TU Delft, 2005.

[25] O. Bajdechi, Systematic design of sigma-delta analog-to-digital converters,

Doctoral Thesis, TU Delft, 2003.

[26] C. C. Enz, G. C. Temes, “Circuit techniques for reducing the effects of

op-amp imperfections: Autozeroing, Correlated Double Sampling, and Chopper
Stabilization”, in Proc. of the IEEE, vol. 84, no. 11, pp. 1584 – 1614, Nov. 1996.

[27] H. Hai Tao, L. Toth, and J. M. Khoury, “Analysis of timing jitter in bandpass
sigma–delta modulators”, IEEE Trans. Circuits Syst. II, vol. 46, pp. 991–1001, Aug.
1999.

62 
 
[28] B. E. Boser and B. A. Wooley, “The design of sigma-delta modulation
analog-to-digital converters”, IEEE J. Solid-State Circuits, vol. 23, no. 6, pp.
1298–1308, Dec. 1988.

[29] P. Malcovati, et al, “Behavioral modeling of switched-capacitor sigma-delta

modulators”, IEEE Trans. Circuits Syst. I, vol. 50, no. 3, pp. 352-364, Mar. 2003.

[30] O. Choksi and L. R. Carley, “Analysis of switched-capacitor common-mode

feedback circuit”, IEEE Trans. Circuits Syst. II, vol. 50, no. 12, pp. 906-917, Dec.
2003.

[31] T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D

converter”, IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166–172, Mar. 1995.

[32] P. M. Figueiredo and J. C. Vital, “Kickback noise reduction techniques for

CMOS latched comparators”, IEEE Trans. Circuits Syst. II, vol. 53, no. 7, pp.
541–545, Jul. 2006.

[33] L. Yao, M. Steyaert, and W. Sansen, Low-Power Low-Voltage Sigma-Delta

Modulators in Nanometer CMOS, Springer, 2006.

[34] S. Gu, X. Wu and X. Yan, “A high precision bandgap reference used in power
management ICs”, Engineering Letters, 14:1, EL_14_1_9, Feb. 2007.

[35] http://www.maxim-ic.com/appnotes.cfm/an_pk/1040/, “Coherent Sampling

vs. Window Sampling”, Application Note 1040, Maxim-IC, Mar. 2002.

[36] F. Gerfers, K. Min Soh, M. Ortmanns, and Y. Manoli, “Figure of merit based
design strategy for low-power continuous-time Σ-Δ modulators”, IEEE ISCAS, vol. 4,
pp. 233-236, 2002.

[37] V. P. Petrov and B. E. Boser, “A fourth-order sigma-delta interface for

micromachined inertial sensors”, ISSCC 2004, pp. 320-329, 15-19 Feb. 2004.

63 
 
Appendix A. Acronyms 

ABCD Advanced Bipolar-CMOS-DMOS

AC Alternating Current
ADC Analog-to-Digital Converter
AZ Auto-Zeroing
BNEA Brownian Noise Equivalent Acceleration
CDS Correlated Double Sampling
CM Common-Mode
CMFB Common-Mode-Feed-Back
CMOS Complementary-Metal-Oxide-Semiconductor
CMRR Common-Mode-Rejection-Ratio
CNEA Circuit Noise Equivalent Acceleration
DAC Digital-to-Analog Converter
dBr dB relative
DC Direct Current
DM Differential-Mode
DR Dynamic Range
ENOB Effective-Number-Of-Bits
FFT Fast Fourier Transform
FOM Figure-Of-Merit
GBW Gain-Band-Width-Product
KVL Kirchhoff’s Voltage Law
MEMS Micro-Electro-Mechanical Systems
MOS Metal-Oxide-Semiconductor
NMOS N-type Metal-Oxide-Semiconductor
OSR Over-Sampling-Ratio
PMOS P-type Metal-Oxide-Semiconductor
PSD Power Spectral Density
PSRR Power-Supply-Rejection-Ratio
PTAT Proportional-To-Absolute-Temperature
SC Switched-Capacitor
SEM Scanning Electron Microscope
SNDR Signal-to-Noise-plus-Distortion-Ratio
SNR Signal-to-Noise-Ratio
SOI Silicon-On-Insulator
SR Slew-Rate
TC Temperature Coefficient
THD Third Harmonic Distortion
TNEA Total Noise Equivalent Acceleration
VCVS Voltage-Controlled-Voltage-Source

64 
 
Appendix B. Study on Sensing Capacitances 

Since the four sensing capacitors form a full bridge, our analysis only needs to cover
two of them, and CS1 = CS4.

Proof Mass

CS1 CS2 CS3 CS4

c c

Sense 1 Sense 2 Sense 3 Sense 4  

Fig B.1: Schematic of simplified accelerometer model.

Referring to the schematic of simplified accelerometer model as shown in Fig B.1,

a) When aext = 0,

⎛ Aε ε Aε 0ε r ⎞ ⎛1 1 ⎞
C S1 = N (C S11 + C S 12 ) = N ⎜⎜ 0 r + ⎟⎟ = NAε 0ε r ⎜⎜ + ⎟⎟ (B.1)
⎝ d1 d2 ⎠ ⎝ d1 d 2 ⎠

⎛ Aε ε Aε 0ε r ⎞ ⎛1 1 ⎞
C S 2 = N (C S 21 + C S 22 ) = N ⎜⎜ 0 r + ⎟⎟ = NAε 0ε r ⎜⎜ + ⎟⎟ (B.2)
⎝ d2 d1 ⎠ ⎝ d1 d 2 ⎠

b) When aext ≠ 0,

i. If the proof mass is moving to the right hand side, i.e., when the acceleration
is to the left,

⎛ Aε 0ε r Aε 0ε r ⎞ d1 + d 2
C S′ 1 = N ⎜⎜ + ⎟⎟ = NAε 0ε r
⎝ d1 − Δd d 2 + Δd ⎠ (d1 − Δd )(d 2 + Δd )
⎛1 1 ⎞ 1
= NAε 0ε r ⎜⎜ + ⎟⎟
⎝ d1 d 2 ⎠ (1 − Δd / d1 )(1 + Δd / d 2 )
CS1
= (B.3)
(1 − Δd / d1 )(1 + Δd / d 2 )

65 
 
 and,

⎛ Aε 0ε r Aε 0ε r ⎞ d1 + d 2
C S′ 2 = N ⎜⎜ + ⎟⎟ = NAε 0ε r
⎝ d1 + Δd d 2 − Δd ⎠ (d1 + Δd )(d 2 − Δd )
⎛1 1 ⎞ 1
= NAε 0ε r ⎜⎜ + ⎟⎟
⎝ d1 d 2 ⎠ (1 + Δd / d1 )(1 − Δd / d 2 )
CS 2
= (B.4)
(1 + Δd / d1 )(1 − Δd / d 2 )

ii. If the proof mass is moving to the left hand side, i.e., when the acceleration is
to the right, due to symmetry, Δd can be substituted by -Δd. Therefore,

C S1
C S′′1 = (B.5)
(1 + Δd / d1 )(1 − Δd / d 2 )
CS 2
C S′′2 = (B.6)
(1 − Δd / d1 )(1 + Δd / d 2 )

66 
 
Appendix C. Transfer Function of Σ­Δ Modulator 

Derivations of the STF (Signal Transfer Function) and NTF (Noise Transfer
Function):

Fig C.1: Block diagram of the 2nd order single-loop feedback Σ-∆ modulator.

[( X (z ) − c1Y (z )) ⋅ b1 ⋅ I (z ) − c2Y (z )]⋅ b2 ⋅ I (z ) + E (z ) = Y (z ) (C.1)

Simplify the above equation, we get

(1 + b c ⋅ I (z ) + b b c ⋅ I (z ))⋅ Y (z ) = b b
2 2 1 2 1
2
1 2 ⋅ I 2 (z ) ⋅ X (z ) + E (z ) (C.2)

Further simplification yields

b1b2 ⋅ I 2 ( z ) 1
Y (z ) = X (z ) + E (z ) (C.3)
1 + b2 c2 ⋅ I (z ) + b1b2 c1 ⋅ I ( z )
2
1 + b2 c2 ⋅ I ( z ) + b1b2 c1 ⋅ I 2 ( z )

z −1
Substituting I (z ) = into the above equation, we get
1 − z −1

b1b2 z −2
Y (z ) = X (z )
(1 + b1b2 c1 − b2 c2 )z −2 + (b2 c2 − 2)z −1 + 1
+
(1 − z )
−1 2
E (z ) (C.4)
(1 + b1b2 c1 − b2 c2 )z −2 + (b2 c2 − 2)z −1 + 1

Therefore, the signal transfer function (STF) and the quantization noise transfer
function (NTF) of the 2nd order full feedback Σ-∆ modulator are calculated as below:

b1b2 z −2
STF (z )＝ (C.5)
(1 + b1b2 c1 − b2 c2 )z −2 + (b2 c2 − 2)z −1 + 1

67 
 
 NTF ( z )＝
(1 − z ) −1 2
(C.6)
(1 + b1b2 c1 − b2 c2 )z −2 + (b2 c2 − 2)z −1 + 1

since b1 = 0.67, b2 = 0.5, c1 = 0.5, c2 = 0.5, then

0.335 z −2 0.335
STF (z )＝ −2 −1
= 2 (C.7 )
0.9175 z − 1.75 z + 1 z − 1.75 z + 0.9175

and,

NTF (z )＝
(1 − z )
−1 2
=
(z − 1)2 (C.8)
0.9175 z −2 − 1.75 z −1 + 1 z 2 − 1.75 z + 0.9175

68 
 
Appendix D. Simulation Method of Op­Amp with SC­CMFB 

The ideal CMFB circuit consists of a VCVS (Voltage-Controlled-Voltage-Source)

with a gain of 1, which is shown in Fig D.1.

 
Fig D.1: Ideal CMFB circuit.

AC analysis with the SC-CMFB was unable to perform because the tool acquired a
false DC analysis. Thanks to the suggestions from Jin Chen, I set the initial voltages
of both the output nodes (outp and outn) to 2.5V in detail as follows.

In Cadence ADE, go to Simulation -> Convergence Aids -> Initial Condition, then the
following window pops out. Set the initial voltage, and select the corresponding node.

 
Fig D.2: Configurations in the Select Initial Condition Set window.

After doing this, in the AC analysis window depicted in Fig D.3, click the “Options”
button, the window in Fig D.4 pops out and choose “node” for “force”.

69 
 
  
Fig D.3: Configurations in the Choosing Analyses window.

 
Fig D.4: Configurations in the AC Options window.

70 
 
Appendix E. Verilog­A and MATLAB Codes   

// Based on the OVI Verilog-A Language Reference Manual, version 1.0 1996

`define PI 3.14159265358979323846264338327950288419716939937511

//--------------------

// opamp

//

// - operational amplifier

//

// vin_p,vin_n: differential input voltage [V,A]

// vout: output voltage [V,A]

// vref: reference voltage [V,A]

// vspply_p: positive supply voltage [V,A]

// vspply_n: negative supply voltage [V,A]

//

// INSTANCE parameters

// gain = gain []

// freq_unitygain = unity gain frequency [Hz]

// rin = input resistance [Ohms]

// vin_offset = input offset voltage referred to negative [V]

// ibias = input current [A]

// iin_max = maximum current [A]

// slew_rate = slew rate [A/F]

// rout = output resistance [Ohms]

// vsoft = soft output limiting value [V]

//

// MODEL parameters

// {none}

//

module opamp(vout, vref, vin_p, vin_n, vspply_p, vspply_n);

input vref, vspply_p, vspply_n;

inout vout, vin_p, vin_n;

electrical vout, vref, vin_p, vin_n, vspply_p, vspply_n;

parameter real gain = 835e3;

parameter real freq_unitygain = 1.0e6;

parameter real rin = 1e6;

parameter real vin_offset = 0.0;

parameter real ibias = 0.0;

parameter real iin_max = 100e-6;

parameter real slew_rate = 0.5e6;

parameter real rout = 80;

parameter real vsoft = 0.5;

71 
 
 real c1;

real gm_nom;

real r1;

real vmax_in;

real vin_val;

electrical cout;

analog begin

@ ( initial_step or initial_step("dc") ) begin

c1 = iin_max/(slew_rate);

gm_nom = 2 * `PI * freq_unitygain * c1;

r1 = gain/gm_nom;

vmax_in = iin_max/gm_nom;

end

vin_val = V(vin_p,vin_n) + vin_offset;

//

// Input stage.

//

I(vin_p, vin_n) <+ (V(vin_p, vin_n) + vin_offset)/ rin;

I(vref, vin_p) <+ ibias;

I(vref, vin_n) <+ ibias;

//

// GM stage with slewing

//

I(vref, cout) <+ V(vref, cout)/100e6;

if (vin_val > vmax_in)

I(vref, cout) <+ iin_max;

else if (vin_val < -vmax_in)

I(vref, cout) <+ -iin_max;

else

I(vref, cout) <+ gm_nom*vin_val ;

//

// Dominant Pole.

//

I(cout, vref) <+ ddt(c1*V(cout, vref));

I(cout, vref) <+ V(cout, vref)/r1;

72 
 
 //

// Output Stage.

//

I(vref, vout) <+ V(cout, vref)/rout;

I(vout, vref) <+ V(vout, vref)/rout;

//

// Soft Output Limiting.

//

if (V(vout) > (V(vspply_p) - vsoft))

I(cout, vref) <+ gm_nom*(V(vout, vspply_p)+vsoft);

else if (V(vout) < (V(vspply_n) + vsoft))

I(cout, vref) <+ gm_nom*(V(vout, vspply_n)-vsoft);

end

endmodule

// MATLAB code for plotting PSD of ADC output and calculating SNDR

clc; clear all; close all;

junk = dlmread('C:\Matlab 2007b\work\SD output data\SD_y_plus_0918_ADCtest_transistor_1.csv', '\n');

adc_out = junk(:,:);

length(adc_out)

% Variable definitions

fb = 5e3; % input signal bandwidth

OSR = 250; % oversampling ratio

f_s = 2.5e6; % sampling frequency

nr_periods = 23; % number of periods (should be an odd number)

nr_points = 2^15; % number of sample points (should be a power of 2)

len = nr_points;

adc_out = adc_out(end-nr_points+1:end); % discard the transient points

% Coherent Sampling

sig_freq = nr_periods*f_s/nr_points; % calculate the test tone

w = linspace(-f_s/2,f_s/2,len)'; % Linear scale

fres = f_s/nr_points; % frequency resolution

bw_limit = ceil(fb/fres) % find the in-band limit

% Remove the DC component

adc_out = adc_out - mean(adc_out);

% Multiply with hanning window, and calcualte FFT

YWw = fftshift(fft(adc_out.*hanning(len),len));

73 
 
% Plot the normalized power spectrum with frequency in logarithmic scale

figure;

semilogx(w(len/2:len),20*log10(abs(YWw(len/2:len))/max(abs(YWw))));

% Format figure with title and so on

title(strcat('PSD of output signal from ADC, with Hanning window, N=',num2str(len)));

ylabel('Normalized power');

xlabel('Frequency');

% Find maximum index for SINAD evaluation.

max_index = find(abs(YWw(len/2+1:len/2+bw_limit)) == max(abs(YWw(len/2+1:len/2+bw_limit)))) % locates the

maximum index within bandwidth

% Calculate the SINAD. Sum the fundamental tone signal power, and divide by the in-band noise power.

SINAD =

10*log10(sum(abs(YWw(len/2+max_index-4:len/2+max_index+4)).^2)./(sum(abs(YWw(len/2:len/2+max_index-5)).^2)+sum(a

bs(YWw(len/2+max_index+5:len/2+max_index+5+bw_limit)).^2)));

% Insert the calculated SINAD into the figure.

legend(strcat('SINAD=',num2str(SINAD)),'Location','SouthEast');

grid on;

74 
 
Appendix F. Test Setup 

It is possible to test the standalone modulator either with or without the accelerometer.
Fig F.1 describes the idea. In Fig F.1 (a), Cs1-4 = Cs (1 ± β)/4 and Vref is constant.
Where, β is the percentage of the capacitance variation, and the full-scale βmax =
ΔCs,max/Cs = 0.039 pF/0.67 pF = 0.0582. In Fig F.1 (b), Cs1-4 = Cs/4 is constant and
Vrefa,b = Vref (1 ± β). With equal β, the net charges transferred to the 1st integrator
output are equal in a clock cycle. The following derivation proves that the two circuits
are equivalent.

Fig F.1: Two equivalent circuits: (a) Varying capacitors and constant voltage; (b)
Constant capacitors and varying voltages. 

1. When sensing capacitors are varying, while voltages are constant:

Table F.1: Charges on the sensing capacitors.

Charge variation on Cs1 Vref/2·Cs(1 + β)/4
Charge variation on Cs2 -Vref/2·Cs(1 − β)/4
Charge variation on Cs3 Vref/2·Cs(1 − β)/4
Charge variation on Cs4 -Vref/2·Cs(1 + β)/4

So, the sum of charge at the differential inputs of the 1st integrator is as follows:

Table F.2: Charges on the differential inputs of the 1st integrator.

Charge at differential input inn βVref·Cs/4
Charge at differential input inp -βVref·Cs/4
Difference of charges above Vref/2·ΔCs

75 
 
2. When sensing capacitors are constant, while voltages are varying:

Table F.3: Charges on the sensing capacitors.

Charge variation on Cs1 Vref(1 + 2β)/2·Cs/4
Charge variation on Cs2 -Vref/2·Cs/4
Charge variation on Cs3 Vref(1 − 2β)/2·Cs/4
Charge variation on Cs4 -Vref/2·Cs/4

So, the sum of charge at the differential inputs of the 1st integrator is as follows:

Table F.4: Charges on the differential inputs of the 1st integrator.

Charge at differential input inn βVref·Cs/4
Charge at differential input inp -βVref·Cs/4
Difference of charges above Vref/2·ΔCs

By comparing the results in Table F.2 and Table F.4, it can be seen that, the two
circuits are functionally equivalent.

If testing of the standalone modulator is conducted in the way as depicted in Fig F.1
(b), bond-pads B17 and B18 should be set to logic-high (to enable on-chip Cfb1-2 and
Cs1-4) and B16 should be set to logic-low (to disable on-chip reference voltage). An
external differential sine-wave generator will supply the input to B20 and B21. Its
common- mode voltage (Vref = 2.5 V) is the input to B19 and half of its
common-mode voltage (0.5Vref = 1.25 V) is the input to B7. DC power supply
generates separate supply voltages for both the analog and digital portions. A pulse
generator will generate the master clock input to B13. The two output single-bit
streams (B14 and B15) of the modulator will be fed into a serial-to-parallel converter
and then stored in a Digital Analysis System, which is subsequently downloaded to a
workstation for processing.

If interfacing an accelerometer is presented as in Fig F.1 (a), B17 and B18 should be
set to logic-low (to disable on-chip Cfb1-2 and Cs1-4) and Cs1-4 and Cfb1-2 in the
accelerometer should be connected to B1-6 respectively. Depending on whether
on-chip or off-chip reference voltage is desired, B16 should be set to logic-high or
logic-low respectively. If off-chip Cfb1-2 is not available, on-chip Cfb1-2 can be used
with B17 set to logic-high. The rest of test setup is the same as that used for the
standalone modulator as mentioned above.

76