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VO (i ) 1 e1 VO (i 1) 0.5 1 e2 {Vin (i ) VDAC (i )} (7) if the second or higher order error terms such as e1e2 and
e12 are ignored and where N i 3 D(i ) . It is also
M
where,e1 and e2 are
e1 (e fg 2 e fg ) / (1 e fg ) e fg 2 e fg and expressed as
e2 (em e fg ) / (1 e fg ) em e fg , respectively. 0.5(1 EG ) M X Y ( M ) 0.5N E 1 E2 (15)
2.3 Overall Error of the RDSM M 1
In order to build an error correction model for the RDSM where EG e2 e1 (16)
in digital domain, the Eq. (1) is writen as 2
Y (i) Y (i 1) 0.5{X (i ) D(i )} is the overall gain error, and
(8) M
where E1 0.5e1 ( M i ) D(i ) (17)
Y (i) V0 (i) / VR , i 3
M
INL 2
i (19)
where N D(i ) is the counter output code. Equation
N i 1
(a)
(b)
Fig. 7. Simulated non-linearity plots for the 12-bit RDSM
after calibration with optimized value of error coefficients. (a)
DNL (b) INL.
The differential nonlinearity (DNL) and integral
nonlinearity (INL) of the ADC before error correction is
shown in Fig. 5. These linearity data are obtained by the
counter output as a coarse ADC code (Fig. 4(b)) and the
(a) analog output shown in Fig. 4(a) which is assumed to be
digitized by an ideal 11-bit ADC. The DNL and INL are
evaluated at 12-bit resolution and the horizontal axis of Fig. 5
is expressed as 12-bit code range. The maximum DNL and
INL at 12bits before error correction are +5.75/-0.18[LSB12]
and +4.52/-4.58[LSB12], respectively, where LSB12 is one LSB
at 12-bit resolution.
Because of the influence of many different analog
(b) imperfections, the best coefficients to minimize the non-
Fig. 5. Simulated non-linearity plots for the 12-bit RDSM before linearity errors estimated by the optimization using the cost
calibration. (a) DNL (b) INL. function calculated with the INL curve given by Eq. (19).
Figure 6 shows a plot of the cost by the INL of the designed
ADC with error corrections as a function of the applied error
coefficients of e1 and e2. The minimum of the cost function is
found at e1 and e2 of 0.22% and -1.25%, respectively, which
are close to the error coefficients with theoretical equations of
Eq. (6) considering capacitor mismatch and finite gain error
only. The DNL and INL plots after the error correction using
these coefficients are shown in Fig. 7(a) and Fig. 7(b),
respectively. The maximum DNL and INL are reduced to
+0.53/-0.49 [LSB12] and +0.30/-0.45[LSB12] respectively.
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