Processing Unit: Control Path: - Module 3

Processing Unit : Control Path
- Module 3
Road Map
 Machine instructions
 Operands
 Addressing modes
 Instruction formats
 Instruction set architectures
 CISC and RISC architectures
 Instruction Cycle :– Fetch – Decode - Execute
 Control Unit
 Organization of a control unit
 Operations of a control unit
 Hardwired control unit
 Micro-programmed control unit
Prof. Shanmugasundaram | SENSE | VIT 2

Structure of von Neumann machine
3
Structure of
IAS –
detail
4
IAS Instruction Set

Notations
• A = Content of an address field in the instruction
• R = Content of an address field in the instruction that
refers to register
• EA = Effective Address of location containing the
referenced operand
• X = Contents of memory location X or register X

Addressing Modes
• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement (Indexed)
• Stack

Immediate Addressing
• Operand is part of instruction
• Operand = A
• Used to define constants, initial values of variables
• e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast
• Limited range
Immediate Addressing Diagram
Instruction
Opcode Operand
LOAD 55 ; ACC  55
ADD 55 ; ACC  ACC + 55

Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective
address
• Limited address space

Direct Addressing Diagram
Instruction
Opcode Address A
Memory
Operand
LOAD M[55] ; ACC  [55]
ADD M[55] ; ACC  ACC + [55]

Indirect Addressing
• Memory cell pointed to by address field contains
the address of (pointer to) the operand
• EA = (A)
– Look in A, find address (A) and look there for
operand
• e.g. ADD (A)
– Add contents of cell pointed to by contents of A to
accumulator

Indirect Addressing
• Large address space
• 2n where n = word length
• May be nested, multilevel, cascaded
– e.g. EA = (((A)))
• Draw the diagram yourself
• Multiple memory accesses to find operand
• Hence slower

Indirect Addressing Diagram
Instruction
Opcode Address A
Memory
Pointer to
operand
Operand
LOAD [M[55]] ;
ADD [M[55]] ;

Register Addressing
• Operand is held in register named in address
filed
• EA = R
• Limited number of registers
• Very small address field needed
– Shorter instructions
– Faster instruction fetch

Register Addressing …
• No memory access
• Very fast execution
• Very limited address space
• Multiple registers helps performance
– Requires good assembly programming or compiler
writing
– C programming
• register int a;
• c.f. Direct addressing
Register Addressing Diagram
Instruction
Opcode Register Address R
Registers
Operand
 LOAD MQ ; ACC  MQ

Register Indirect Addressing
• C.f. indirect addressing
• EA = (R)
• Operand is in memory cell pointed to by
contents of register R
• Large address space (2n)
• One fewer memory access than indirect
addressing

Register Indirect Addressing Diagram
Instruction
Opcode Register Address R
Memory
Registers
Pointer to Operand Operand
 LOAD [MQ] ; ACC  [MQ]

Displacement Addressing
• EA = A + (R)
• Address field hold two values
– A = base value
– R = register that holds displacement
– or vice versa

Displacement Addressing Diagram
 LOAD [MQ] [05] ;
Instruction
Opcode Register R Address A
Memory
Registers
Pointer to Operand Operand

+

Relative Addressing
• A version of displacement addressing
• R = Program counter, PC
• EA = A + (PC)
• i.e. get operand from A cells from current
location pointed to by PC
• c.f locality of reference & cache usage

Base-Register Addressing
• A holds displacement
• R holds pointer to base address
• R may be explicit or implicit
• e.g. segment registers in 80x86

Indexed Addressing
• A = base
• R = displacement
• EA = A + R
• Good for accessing arrays
– EA = A + R ( Auto indexing)
– R++

Combinations
• Post-index
– EA = (A) + (R)
• Pre-index
– EA = (A+(R))

Stack Addressing
• Operand is (implicitly) on top of stack
• e.g.
– Push
– Pop

Instruction Formats
• Layout of bits in an instruction
• Includes opcode.
• Includes (implicit or explicit) operand(s)
• Usually more than one instruction format in an
instruction set

RISC and CISC Instruction Sets
• Nature of instructions distinguishes computer
• Two fundamentally different approaches
• Reduced Instruction Set Computers (RISC) have one-
word instructions and require arithmetic operands to be
in registers
• Complex Instruction Set Computers (CISC)
have multi-word instructions and allow operands
directly from memory

RISC Instruction Sets
• Focus on RISC first because it is simpler
• RISC instructions each occupy a single word
• A load/store architecture is used, meaning:
– only Load and Store instructions are used
to access memory operands
– operands for arithmetic/logic instructions
must be in registers, or one of them
may be given explicitly in instruction word

RISC Instruction Sets
• Instructions/data are stored in the memory
• Processor register contents are initially invalid
• Because RISC requires register operands,
data transfers are required before arithmetic
• The Load instruction is used for this purpose:
Load procr_register, mem_location
• Addressing mode specifies memory location;

RISC Instruction Sets …
• Consider high-level language statement:
C=A+B
• A, B, and C correspond to memory locations
• Steps: fetch contents of locations A and B,
compute sum, and transfer result to location C

RISC Instruction Sets …
• Sequence of simple RISC instructions for task:
Load R2, A
Load R3, B
Add R4, R2, R3
Store R4, C
• Load instruction transfers data to register
• Store instruction transfers data to the memory
• Destination differs with same operand order

A Program in the Memory
• Consider the preceding 4-instruction program
• How is it stored in the memory?
(32-bit word length, byte-addressable)
• Place first RISC instruction word at address i
• Remaining instructions are at i + 4, i + 8, i + 12
• For now, assume that Load/Store instructions
specify desired operand address directly;
this issue is discussed in detail later
Instruction Execution/Sequencing
• How is the program executed?
• Processor has program counter (PC) register
• Address i for first instruction placed in PC
• Control circuits fetch and execute instructions,
one after another : straight-line sequencing
• During execution of each instruction,
PC register is incremented by 4
• PC contents are i + 16 after Store is executed
Details of Instruction Execution
• Two-phase procedure: fetch and execute
• Fetch involves Read operation using PC value
• Data placed in Instruction Register (IR)
• To complete execution, control circuits
examine encoded machine instruction in IR
• Specified operation is performed in steps,
e.g., transfer operands, perform arithmetic
• Also, PC is incremented, ready for next fetch
Branching
• We can illustrate the concept of branching with
a program that adds a list of numbers
• Same operations performed repeatedly,
so the program contains a loop
• Loop body is straight-line instruction sequence
• It must determine address of next number,
load value from the memory, and add to sum
• Branch instruction causes repetition of body
Branching …
• Assume that size of list, n, stored at location N
• Use register R2 as a counter, initialized to N
• Body of loop includes the instruction
Subtract R2, R2, #1
to decrement counter in each loop pass
• Branch_if_[R2]> 0 goes to branch target
LOOP as long as contents of R2 are greater
than zero
• Therefore, this is a conditional branch
Branching …
• Branches that test a condition are used in loops
and various other programming tasks
• One way to implement conditional branches
is to compare contents of two registers, e.g.,
Branch_if_[R4]>[R5] LOOP
• In generic assembly language with mnemonics
the same instruction might actually appear as
BGT R4, R5, LOOP

Constants
• Assume constant 200 is added to a variable
• Immediate mode enables use of constants
in assembly-language instructions
• One approach for specification:
Add R4, R6, 200immediate
• Not practical to use subscripts in this manner
• Alternative approach uses special character:
Add R4, R6, #200
Assembly Language
• Mnemonics (LD/ADD instead of Load/Add)
used when programming specific computers
• The mnemonics represent the OP codes
• Assembly language is the set of mnemonics and
rules for using them to write programs
• The rules constitute the language syntax
• Example: suffix „I‟ to specify immediate mode
ADDI R2, R3, 5 (instead of #5)
Assembler Directives
• Other information also needed to translate source
program to object program
• How should symbolic names be interpreted?
• Where should instructions/data be placed?
• Assembler directives provide this information
• ORIGIN defines instruction/data start position
• RESERVE and DATAWORD define data storage
• EQU associates a name with a constant value

Program Assembly & Execution
• From source program, assembler generates machine-
language object program
• Assembler uses ORIGIN and other directives
to determine address locations for code/data
• For branches, assembler computes ±offset
from present address (in PC) to branch target
• Loader places object program in memory
• Debugger can be used to trace execution

Number Notation
• Decimal numbers used as immediate values:
ADDI R2, R3, 93
• Assembler translates to binary representation
• Programmer may also specify binary numbers:
ADDI R2, R3, %01011101
• Hexadecimal specification is also possible:
ADDI R2, R3, 0x5D
• Note that 93  10111012  5D16
Stacks
• A stack is a list of data elements where
elements are added/removed at top end only
• Also known as pushup/down stack or
last-in-first-out (LIFO) stack
• We push a new element on the stack top
or pop the top element from the stack
• Programmer can create a stack in the memory
• There is often a special processor stack as well
Processor Stack
• Processor has stack pointer (SP) register
that points to top of the processor stack
• Push operation involves two instructions:
Add SP, SP, #4
Store Rj, (SP)
Pop operation also involves two instructions:
Load Rj, (SP)
Subtract SP, SP, #4
Subroutines
• In a given program, a particular task may be
executed many times using different data
• Examples: mathematical function, list sorting
• Implement task in one block of instructions
• This is called a subroutine
• Rather than reproduce entire subroutine block in each
part of program, use a subroutine call
• Special type of branch with Call instruction

Subroutines …
• Branching to same block of instructions
saves space in memory, but must branch back
• The subroutine must return to calling program
after executing last instruction in subroutine
• This branch is done with a Return instruction
• Subroutine can be called from different places
• How can return be done to correct place?
• This is the issue of subroutine linkage

Subroutine Linkage
• During execution of Call instruction,
PC will be updated to point to instruction after Call
• Save this address for Return instruction to use
• Simplest method: place address in link register
• Call instruction performs two operations:
store updated PC contents in link register,
then branch to target (subroutine) address
• Return just branches to address in link register

Logic Instructions
• AND, OR, and NOT operations on single bits
are basic building blocks of digital circuits
• Similar operations in software on multiple bits
• Using RISC-style instructions, all operands are
in registers or specified as immediate values:
OR R4, R2, R3
AND R5, R6, #0xFF
• 16-bit immediate is zero-extended to 32 bits

Shift and Rotate Instructions
• Shifting binary value left/right = mult/div by 2
• Arithmetic shift preserves sign in MS bit
• Rotate copies bits from one end to other end
• Shift amount in register or given as immediate
• Carry flag (discussed later) may be involved
• Examples:
LShiftL R3, R3, #2 (mult by 4)
RotateL R3, R3, #2 (MS bits to LS bits)

Multiplication and Division
• Signed integer multiplication of n-bit numbers
produces a product with as many as 2n bits
• Processor truncates product to fit in a register:
Multiply Rk, Ri, Rj (Rk  [Ri]  [Rj])
• For general case, 2 registers may hold result
• Integer division produces quotient as result:
Divide Rk, Ri, Rj (Rk  [Ri] / [Rj])
• Remainder is discarded or placed in a register
CISC Instruction Sets
• Not constrained to load/store architecture
• Instructions may be larger than one word
• Typically use two-operand instruction format,
with at least one operand in a register
• Implementation of C  A  B using CISC:
Move Ri, A
Add Ri, B
Move C, Ri

CISC Instruction Sets …
• Move instruction equivalent to Load/Store
• But also can transfer immediate values
and possibly between two memory locations
• Arithmetic instructions may employ addressing modes
for operands in memory:
Subtract LOC, Ri
Add Rj, 16(Rk)

Additional Addressing Modes
• CISC style has other modes not usual for RISC
• Autoincrement mode: effective address given by
register contents; after accessing operand,
register contents incremented to point to next
• Useful for adjusting pointers in loop body:
Add SUM, (Ri)
MoveByte (Rj), Rk
• Increment by 4 for words, and by 1 for bytes
Additional Addressing Modes
• Autodecrement mode: before accessing operand,
register contents are decremented, then new
contents provide effective address
• Notation in assembly language:
Add Rj, (Ri)
• Use autoinc. & autodec. for stack operations:
Move (SP), NEWITEM (push)
Move ITEM, (SP) (pop)

Condition Codes
• Processor can maintain information on results
to affect subsequent conditional branches
• Results from arithmetic/comparison & Move
• Condition code flags in a status register:
N (negative) 1 if result negative, else 0
Z (zero) 1 if result zero, else 0
V (overflow) 1 if overflow occurs, else 0
C (carry) 1 if carry-out occurs, else 0

Branches using Condition Codes
• CISC branches check condition code flags
• For example, decrementing a register causes N
and Z flags to be cleared if result is not zero
• A branch to check logic condition N  Z  0:
Branch > 0 LOOP
• Other branches test conditions for , , , , 
• Also Branch_if_overflow and Branch_if_carry
• Consider CISC-style list-summing program
RISC and CISC Styles
• RISC characteristics include:
– simple addressing modes
– all instructions fitting in a single word
– arithmetic/logic operations on registers
– load/store architecture for data transfers
• Simpler instructions make it easier to
design faster hardware (e.g., use of pipelining)

RISC and CISC Styles
• CISC characteristics include:
– more complex addressing modes instructions
– spanning more than one word more instructions
– arithmetic/logic operations on memory memory-to-
memory data transfers
• Complexity makes it somewhat more difficult
to design fast hardware, but still possible.

Processing Unit: Data path &
Control Path
Module 3
BASIC ARCHITECTURE
• Control unit and data- Processor
path Control unit Datapath
– Note similarity to single- ALU

Controller
purpose processor Control
/Status
• Key differences
Registers
– Data-path is general
– Control unit doesn‟t
store the algorithm – the PC IR
algorithm is
“programmed” into the
memory I/O
Memory

Datapath Operations
• Load Processor
– Read memory location Control unit Datapath
into register
ALU
• ALU operation Controller Control
/Status
+1
– Input certain registers

through ALU, store Registers
back in register
• Store 10 11
– Write register to PC IR
memory location
I/O
Memory
...
10
11
...

Control Unit
• Control unit: configures the data-path
operations Processor
– Sequence of desired operations Control unit Datapath
(“instructions”) stored in memory –
“program” ALU
Controller Control
• Instruction cycle – broken into several /Status
sub-operations, each one clock cycle,
e.g.: Registers
– Fetch: Get next instruction into IR
– Decode: Determine what the
instruction means
– Fetch operands: Move data from PC IR R0 R1
memory to data-path register
– Execute: Move data through the ALU
– Store results: Write data from register I/O
to memory 100 load R0, M[500] Memory
...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...

Control Unit Sub-Operations
• Fetch Processor
– Get next
Control unit Datapath
ALU
instruction into IR Controller Control
/Status
– PC: program
counter, always
Registers
points to next
instruction PC 100 IR
load R0, M[500] R0 R1
– IR: holds the

fetched instruction 100 load R0, M[500] Memory
I/O
...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...

• Decode Processor
– Determine what ALU
the instruction Controller Control

/Status
means
Registers
PC 100 IR R0 R1
load R0, M[500]
I/O
100 load R0, M[500] Memory

...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...

• Fetch operands Processor
– Move data from ALU
memory to Controller Control

/Status
datapath register
Registers
10
PC 100 IR R0 R1
load R0, M[500]
I/O

...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...

• Execute Processor
– Move data ALU
through the ALU Controller Control

/Status
– This particular
Registers
instruction does
nothing during 10
this sub-operation PC 100 IR
load R0, M[500] R0 R1
I/O

...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...

• Store results Processor
– Write data from ALU
register to Controller Control

/Status
memory
Registers
– This particular
instruction does 10
nothing during PC 100 IR
load R0, M[500] R0 R1
this sub-operation
I/O

...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...

Instruction Cycles
PC=100 Processor
Fetch Decode Fetch Exec. Store Control unit Datapath

ops results ALU
clk Controller Control
/Status
Registers
10
PC 100 IR R0 R1
load R0, M[500]
I/O

...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...

Instruction Cycles
PC=100 Processor

ops results ALU
clk Controller Control +1
/Status
PC=101
Registers
Fetch Decode Fetch Exec. Store
ops results
clk
10 11
PC 101 IR R0 R1
inc R1, R0
I/O

...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...

Instruction Cycles
PC=100 Processor

ops results ALU
clk Controller Control
/Status
PC=101
Registers
Fetch Decode Fetch Exec. Store
ops results
clk
10 11
PC 102 IR R0 R1
store M[501], R1
PC=102
Fetch Decode Fetch Exec. Store I/O
ops results ...
clk 500 10
101 inc R1, R0 501 11
102 store M[501], R1 ...

Stages of a Data paths
• Problem: a single, atomic block which “executes an
instruction” (performs all necessary operations beginning with
fetching the instruction) would be too bulky and inefficient.
• Solution: break up the process of “executing an instruction”
into stages, and then connect the stages to create the whole
data path.
– Smaller stages are easier to design.
– Easy to optimize (change) one stage without touching the others.

• There is a wide variety of MIPS instructions: so what
general steps do they have in common?
• Stages
1. Instruction Fetch
2. Instruction Decode
3. ALU
4. Memory Access
5. Register Write

• Stage 1: Instruction Fetch.
– No matter what the instruction is, the 32-bit
instruction word must first be fetched from
memory (the cache-memory hierarchy).
– Also, this is where we increment PC (that is, PC
= PC + 4, to point to the next instruction; byte
addressing so + 4).

Fetch Processor
– Get next Control unit Datapath
instruction into IR Controller Control

ALU
– PC: program /Status
counter, always Registers
points to next
instruction
PC 100 IR R0 R1
load R0, M[500]
– IR: holds the
fetched I/O
instruction 100 load R0, M[500] Memory
...
500 10
104 inc R1, R0 501
108 store M[501], R1 ...

• Stage 2: Instruction Decode
– Upon fetching the instruction, we next gather data
from the fields (decode all necessary instruction data).
– First, read the opcode to determine instruction
type and field lengths.
– Second, read in data from all necessary registers.
• For add, read two registers.
• For addi, read one register.

• Stage 3: ALU (Arithmetic-Logic Unit)
– The real work of most instructions is done here:
arithmetic (+, -, *, /), shifting, logic (&, |),
comparisons (slt).
– What about loads and stores?
• lw $t0, 40($t1)
• The address we are accessing in memory = the value in
$t1 plus the value 40.
• We do this addition at this stage.

• Stage 4: Memory Access
– Actually only the load and store instructions do
anything during this stage; for the other
instructions, they remain idle during this stage.
– Since these instructions have a unique step, we
need this extra stage to account for them.
– As a result of the cache system, this stage is
expected to be just as fast (on average) as the
others.

• Stage 5: Register Write
– Most instructions write the result of some
computation into a register.
– Examples: arithmetic, logical, shifts, loads
– What about stores, branches, jumps?
– They do not write anything into a register at the
end.
– These remain idle during this fifth stage.

Data path: Generic Steps

Data path Walkthroughs: add
• add r3,r1,r2 ; r3 = r1+r2
– Stage 1: Fetch this instruction, increment PC.
– Stage 2: Decode to find that it is an add
instruction, then read registers r1 and r2.
– Stage 3: Add the two values retrieved in stage 2.
– Stage 4: Idle (nothing to write to memory).
– Stage 5: Write result of stage 3 into register r3.

Data path Walkthroughs: add (2)

CONTROL UNIT
Micro programmed and Hardwired
Module 3
Introduction
• In the Previous lecture, we focused on machine instructions and the
operations performed by the processor to execute each instruction.
• What was left out of this discussion is exactly how each individual
operation is caused to happen. This is the job of the control unit.
• The control unit is
– that portion of the processor that actually causes things to happen.
– issues control signals external to the processor to cause data exchange with
memory and I/O modules.
– issues control signals internal to the processor
• to move data between registers,
• to cause the ALU to perform a specified function, and
• to regulate other internal operations.
• Input to the control unit consists of the instruction register, flags, and
control signals from external sources (e.g., interrupt signals).
Road Map
In this topic we are going to discuss
 How processor functions are performed or, more specifically,
how the various elements of the processor are controlled to
provide these functions, by means of the control unit.
 It is shown that each instruction cycle is made up of a set of
micro-operations that generate control signals.
 Execution is accomplished by the effect of these control
signals, emanating from the control unit to the ALU, registers,
and system interconnection structure.
 Finally, an approach to the implementation of the control unit,
referred to as hardwired implementation, is presented.

Key points
• Execution of instruction  execution of sequence of sub steps 
cycles.
• Each cycle  made of sequence of more fundamental operations
(micro-operations).
• A single micro-operations involves transfer of data
– Between register
– Between register and external bus
– ALU operation
• Tasks of Control Unit:
1. causes processor to step through series of micro-operations in proper
sequence based on program execution.
2. Generate the control signal  to cause micro-program execution.
• Control signals  cause opening and closing of logic gates  result in

transfer of data among registers and ALU operation.

Micro operations
• Execution of program  consists of sequence of instruction
cycle.
• Sequence of instruction not necessary to follow written
sequence.  branch instruction.
• Instruction cycle  combination of number of smaller units.
– Fetch, Indirect, Execute, Interrupt
• Further more division of these instruction cycle  micro
operation.
– Functional
– Atomic
– Involved with registers
– Operations of processor.

Program Execution(constituent Elements)
 Performance of each sub cycle involves one or more shorter operations, that
is, micro – operations.
 Micro – operations are the functional, or atomic, operations of a processor.

Fetch Cycle

Micro operation of Fetch Cycle

Micro operation of Indirect Cycle
Consider the instruction SUB R1, X, which subtracts the contents
of location X from the contents of register R1, and places the
result in R1.
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: MBR ← Complement(MBR)
t4: MBR ← Increment(MBR)
t5: R1 ← (R1) + (MBR)

Micro operation of Interrupt cycle

The Instruction Cycle
• To complete the picture, we need to tie sequences of micro-
operations together.
• We assume a new 2-bit register called the instruction cycle code
(ICC).
• The ICC designates the state of the processor in terms of which portion
of the cycle it is in:
00: Fetch
01: Indirect
10: Execute
11: Interrupt

What & Why Micro operations?
• The behavior of processor is decomposed in to elementary
operations – Micro operations.
• By doing this we are able to define the functional requirements

for the control unit.

Characterization of Control Unit
1. Define the basic elements of processor.
2. Describe the micro-operation that processor performs.
3. Determine the functions that the control unit must perform to
cause the micro operations to be performed.

What Control Unit is doing?
• Sequencing: The control unit causes the processor to step
through the series of micro-operations in the proper sequence ,
based on the program being executed.
• Execution: The control unit causes each micro-operations to be
performed.

Control Unit Model

Example
Memory

Hard wired control Unit
• In this, for each control signal a Boolean expression is
derived as a function of input of that signal
• Let P &Q are two signal defined as
00 – Fetch cycle
01 - Indirect cycle
10 - Execute cycle
11 – Interrupt cycle
Then Boolean expression for a Control signal C5(for
example) then from the previous table

Then Boolean expression for a Control signal C5(for
example) then from the previous table
ICC
Cycle
P Q
0 0 Fetch
0 1 Indirect
1 0 Execute
1 1 Interrupt

• LOAD AC:
t2: MBR ← Memory
t3: AC ← (MBR)
• STORE AC
t2: MBR ← (AC)
t3: Memory ← (MBR)
• ADD AC
t2: MBR ← Memory
t3: AC ← (AC) + (MBR)

• LOAD AC:
t1: MAR ← (IR(address)) C8
t2: MBR ← Memory C5,CR
t3: AC ← (MBR) C10
• STORE AC
t2: MBR ← (AC) C11
t3: Memory ← (MBR) C12,CW
• ADD AC
t2: MBR ← Memory C5,CR
t3: AC ← (AC) + (MBR) CALU,C7,C9

Problems with Hardwired Control Unit
• Sequencing & micro-operation logic gets complex
• Difficult to design, prototype, and test
• Resultant design is inflexible, and difficult to build upon
(Pipeline, multiple computation units, etc.)
• Adding new instructions requires major design and adds
complexity quickly

Hard wired and Micro programmed
Control Units
• In H/wired, control signals are generated by a micro
instructions are used to cause register transfers and
ALU operations.
• In Micro programmed control unit, the control unit is

specified by a micro program

Basic Idea
• For each micro operation control unit has to generate set of
control signals and each control line is either ON or OFF
• We can assume each control line by a binary digit.
• A Control word is then formed by these bits

Basic idea…
• Then each micro operation would be represented by a
different patterns of 1‟s and 0‟s in the control word
• Then each control word are saved in memory with
unique address. Also add an address field to indicate the
location of next control word to be executed (also add
few bits about the conditions)


Processing Unit: Control Path: - Module 3

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Processing Unit : Control Path

Prof. Shanmugasundaram | SENSE | VIT 2

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Pointer to Operand Operand

 LOAD [MQ] ; ACC  [MQ]

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Pointer to Operand Operand

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– Note similarity to single- ALU

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– Input certain registers

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– IR: holds the

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the instruction Controller Control

100 load R0, M[500] Memory

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memory to Controller Control

100 load R0, M[500] Memory

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through the ALU Controller Control

100 load R0, M[500] Memory

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register to Controller Control

100 load R0, M[500] Memory