Module 3

Processing Unit : Control Path

IAS Instruction Set

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 Notations
• A = Content of an address field in the
instruction
• R = Content of an address field in the
instruction that refers to register
• EA = Effective Address of location
containing the referenced operand
• X = Contents of memory location X or
register X
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 Addressing Modes
• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement (Indexed)
• Stack

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 Immediate Addressing
• Operand is part of instruction
• Operand = A
• Used to define constants, initial values of variables
• e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast
• Limited range
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Immediate Addressing Diagram

Instruction
Opcode Operand

LOAD 55 ; ACC  55
ADD 55 ; ACC  ACC + 55

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 Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective
address
• Limited address space

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 Direct Addressing Diagram

Instruction
Opcode Address A
Memory

Operand
LOAD M[55] ; ACC  [55]
ADD M[55] ; ACC  ACC + [55]

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 Indirect Addressing
• Memory cell pointed to by address field contains
the address of (pointer to) the operand
• EA = (A)
– Look in A, find address (A) and look there for
operand
• e.g. ADD (A)
– Add contents of cell pointed to by contents of A to
accumulator

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 Indirect Addressing
• Large address space
• 2n where n = word length
• May be nested, multilevel, cascaded
– e.g. EA = (((A)))
• Draw the diagram yourself
• Multiple memory accesses to find operand
• Hence slower

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 Indirect Addressing Diagram
Instruction
Opcode Address A
Memory

Pointer to
operand

Operand

LOAD [M[55]] ;
ADD [M[55]] ;

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 Register Addressing
• Operand is held in register named in address
filed
• EA = R
• Limited number of registers
• Very small address field needed
– Shorter instructions
– Faster instruction fetch

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 Register Addressing
• No memory access
• Very fast execution
• Very limited address space
• Multiple registers helps performance
– Requires good assembly programming or compiler
writing
– C programming
• register int a;
• c.f. Direct addressing
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 Register Addressing Diagram
Instruction
Opcode Register Address R
Registers

Operand

 LOAD MQ ; ACC  MQ

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 Register Indirect Addressing
• C.f. indirect addressing
• EA = (R)
• Operand is in memory cell pointed to by
contents of register R
• Large address space (2n)
• One fewer memory access than indirect
addressing

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Register Indirect Addressing Diagram

Instruction
Opcode Register Address R
Memory

Registers

Pointer to Operand Operand

 LOAD [MQ] ; ACC  [MQ]

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 Displacement Addressing
• EA = A + (R)
• Address field hold two values
– A = base value
– R = register that holds displacement
– or vice versa

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Displacement Addressing Diagram
 LOAD [MQ] [05] ;

Instruction
Opcode Register R Address A
Memory

Registers

Pointer to Operand Operand

+

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 Relative Addressing
• A version of displacement addressing
• R = Program counter, PC
• EA = A + (PC)
• i.e. get operand from A cells from current
location pointed to by PC
• c.f locality of reference & cache usage

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 Base-Register Addressing
• A holds displacement
• R holds pointer to base address
• R may be explicit or implicit
• e.g. segment registers in 80x86

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 Indexed Addressing
• A = base
• R = displacement
• EA = A + R
• Good for accessing arrays
– EA = A + R ( Auto indexing)
– R++

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 Combinations
• Post-index
– EA = (A) + (R)

• Pre-index
– EA = (A+(R))

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 Stack Addressing
• Operand is (implicitly) on top of stack
• e.g.
– Push
– Pop

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 RISC Instruction Sets
• Focus on RISC first because it is simpler
• RISC instructions each occupy a single word
• A load/store architecture is used, meaning:
– only Load and Store instructions are used
to access memory operands
– operands for arithmetic/logic instructions
must be in registers, or one of them
may be given explicitly in instruction word

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 RISC Instruction Sets
• Instructions/data are stored in the memory
• Processor register contents are initially invalid
• Because RISC requires register operands,
data transfers are required before arithmetic
• The Load instruction is used for this purpose:
Load procr_register, mem_location
• Addressing mode specifies memory location;
different modes are discussed later

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 RISC Instruction Sets
• Consider high-level language statement:
C=A+B
• A, B, and C correspond to memory locations
• RTN specification with these symbolic names:
C ← [A] + [B]
• Steps: fetch contents of locations A and B,
compute sum, and transfer result to location C

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 RISC Instruction Sets
• Sequence of simple RISC instructions for task:
Load R2, A
Load R3, B
Add R4, R2, R3
Store R4, C
• Load instruction transfers data to register
• Store instruction transfers data to the memory
• Destination differs with same operand order

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Data path

Module 3
 BASIC ARCHITECTURE
• Control unit and data- Processor
path Control unit Datapath

– Note similarity to single- ALU

Controller
purpose processor Control
/Status

• Key differences
Registers
– Data-path is general
– Control unit doesn’t
store the algorithm – the PC IR
algorithm is
“programmed” into the
memory I/O
Memory

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 Datapath Operations
• Load Processor
– Read memory location Control unit Datapath
into register
ALU
• ALU operation Controller Control
/Status
+1

– Input certain registers

through ALU, store Registers
back in register
• Store 10 11
– Write register to PC IR

memory location
I/O
Memory
...
10
11
...

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 Control Unit
• Control unit: configures the datapath
operations Processor
– Sequence of desired operations Control unit Datapath
(“instructions”) stored in memory –
“program” ALU
Controller Control
• Instruction cycle – broken into several /Status
sub-operations, each one clock cycle,
e.g.: Registers
– Fetch: Get next instruction into IR
– Decode: Determine what the
instruction means
– Fetch operands: Move data from PC IR R0 R1
memory to datapath register
– Execute: Move data through the ALU
– Store results: Write data from register I/O
to memory 100 load R0, M[500] Memory
...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...

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 Control Unit Sub-Operations
• Fetch Processor

– Get next
Control unit Datapath

ALU
instruction into IR Controller Control
/Status
– PC: program
counter, always
Registers

points to next
instruction PC 100 IR
load R0, M[500] R0 R1

– IR: holds the

fetched instruction 100 load R0, M[500] Memory
I/O
...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...

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 Control Unit Sub-Operations
• Decode Processor
Control unit Datapath
– Determine what ALU

the instruction Controller Control

/Status

means
Registers

PC 100 IR R0 R1
load R0, M[500]

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...

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 Control Unit Sub-Operations
• Fetch operands Processor
Control unit Datapath
– Move data from ALU

memory to Controller Control

/Status

datapath register
Registers

10
PC 100 IR R0 R1
load R0, M[500]

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...

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 Control Unit Sub-Operations
• Execute Processor
Control unit Datapath
– Move data ALU

through the ALU Controller Control

/Status

– This particular Registers

instruction does
nothing during PC 100 IR R0
10
R1
this sub- load R0, M[500]

operation I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...

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 Control Unit Sub-Operations
• Store results Processor
Control unit Datapath
– Write data from ALU

register to Controller Control

/Status

memory
Registers

– This particular
instruction does PC 100 IR R0
10
R1
nothing during load R0, M[500]

this sub- I/O

operation 100 load R0, M[500] Memory

...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...

Prof. Shanmugasundaram | SENSE | VIT 37