REGISTER

NO NAME
PATNALA SAI RAMESH
20BIT0022 KRISHNA
20BIT0030 ASMITA UPADHYAY
20BIT0038 RIDDHI DHAWAN
20BIT0040 PATIL ANUSHKA BIPIN
20BIT0047 AGRAWAL RISHABH
20BIT0049 ASWIN M M
20BIT0053 YASH BHAVIN JASANI
20BIT0054 ARPIT GOYAL
20BIT0057 PENDHARI SANIYA SWAPNIL
20BIT0070 SYED ARSAL ABBAS
20BIT0074 AGRAWAL ADWIT

1. a. Design a sequential circuit for the following state diagram using JK Flip Flop.

b. Design a circuit that has a 4-bit binary input and has the following three outputs and
defined as follows.

 If the lower order 2 bits are 00, then the output will be addition of the higher order 2
bits.
 If the lower order 2 bits are 11, then the output will be the AND operation of the
higher order 2 bits.

----------------------------------------------------------------------------------------------------------------

20BIT0094 UNDRE PRANAV NARAYAN

20BIT0102 HITESH DAGA
20BIT0103 AKSHIT JAIN
20BIT0117 SAUDAMINI SHAIL
20BIT0120 ASHI RATHI
20BIT0121 SHRIA SANNUTHI
20BIT0123 TEJAS GUPTA
AAZIM AJMAL
20BIT0125 SHAUKATHALI P
20BIT0128 VINAY RAVINDRA MASKE
20BIT0130 GARV TANDON
 20BIT0131 ANIKET ACHARYA
20BIT0132 VANSH BAJAJ
20BIT0134 ABHISHEK RAJ

2. a. Design a sequential circuit using T Flip Flop for the following state diagram.

b. Design a combinational circuit which has 4 inputs A, B, C and D representing the month of the year
such that January is 0000. The outputs are the binary representation of number of days in a month.

---------------------------------------------------------------------------------------------------------------------

THUMMAPUDI LAKSHMI
20BIT0135 SRAVANI
20BIT0136 ANUJ PATEL
20BIT0137 SWARNAMEENA V
20BIT0144 SHREYA BASU
20BIT0146 SURBHIT AGRAWAL
20BIT0153 HANEET ARYA
NEKKALAPU SRI ANJAN
20BIT0157 KUMAR
20BIT0159 ADITYA SHARMA
20BIT0161 HARSH JAIN
20BIT0167 PRANAV S DESAI
20BIT0172 SESHADRI SRIYA
NANDINI
20BIT0173 DHAKSHINAMURTHY
3. a. Design a sequential circuit for the following state diagram using SR Flip flop

b. Design a circuit that takes 4 inputs I4, I3, I2 and I1 where I4 is the MSB and I1 is the
LSB. The outputs are defined as follows.

 If the input has even number of 1’s, then add 2 to the number of 1’s in the input.
 If the input has odd number of 1’s, then find 1’s complement of the input.
 If the input doesn’t fall under any of these two conditions, then assume as “Don’t
cares”

---------------------------------------------------------------------------------------------------------------------

20BIT0179 ISHAAN CHHIPA

20BIT0180 YASHASHVI KALA
20BIT0183 KAUSHAL AGRAWAL
DHAKSHANA MOORTHI
20BIT0193 G
20BIT0202 SHREYAS CHITRANSH
20BIT0214 SANCHIT SAH
KARNAM CHANDU
20BIT0217 KUMAR
20BIT0226 KUNCHAKURI RITHESH
20BIT0236 AANCHAL PATEL
20BIT0239 C DHANUSH
20BIT0265 GANDLA SASANK
20BIT0270 NIMISH JAIN
20BIT0277 VANSH MAKADIA

4. a. Design a sequential circuit using T Flip Flop for the following state diagram.
 b. Design a combinational circuit, which takes a 4 bit binary number ABCD as input and the
output is defined as follows.
i. If the higher order 2 bits are greater than the lower order 2 bits, then the
output is the 1’s complement of the higher order bits.
ii. If the higher order 2 bits are lesser than the lower order 2 bits, then the output
is the EXOR of higher order bits.
iii. If the higher order 2 bits are equal to the lower order 2 bits, then the output
is the OR operation of the lower order bits.
---------------------------------------------------------------------------------------------------------------

20BIT0280 SIDDHANT ANCHAL

20BIT0290 TONY BIJU ANTONY
20BIT0292 UDITH SHYAMSUKHA
20BIT0296 AMBARAPU RAHITYA TEJA
20BIT0307 PRIYADHARSHINI R
20BIT0324 NIMESH THAKUR
20BIT0342 VINEET JAIN
20BIT0343 ANISH MITTAL
20BIT0352 HARISH EDISON
20BIT0353 SHRIYANSH SINHA
20BIT0356 SHIVANSH PANDIT
20BIT0361 ANKIT YADAV
20BIT0365 SHREYAS SRIVASTAVA
20BIT0368 ELAGANDULA NEHA
PONNAPATI MANISH KUMAR
20BIT0393 REDDY

5. a. Design a sequential circuit for the following state diagram using JK Flip flop
b. Design a combinational circuit which takes 2 data inputs D1 and D2, 2 control inputs C1
and C2. The 2 outputs are defined as follows.
 The outputs should be the remainder after dividing the control input from data input.
 If divide by zero error occurs, assume the output as “Don’t Cares”

------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------