Ada4077-1 Ada4077-2 Ada4077-4: 4 MHZ, 7 NV/ HZ, Low Offset and Drift, High Precision Amplifiers

4 MHz, 7 nV/√Hz, Low Offset and
Drift, High Precision Amplifiers

Data Sheet ADA4077-1/ADA4077-2/ADA4077-4
FEATURES PIN CONNECTION DIAGRAMS
Offset voltage: NIC 1 8 NIC
25 μV maximum at 25°C (B grade, 8-lead SOIC, single/ dual) –IN 2 ADA4077-1 7 V+
50 μV maximum at 25°C (A grade, 8-lead SOIC, single/ dual) +IN 3 TOP VIEW 6 OUT
V– 4 (Not to Scale) 5 NIC
50 μV maximum at 25°C (A grade, 14-lead SOIC, quad)
10238-101
Offset voltage drift: NIC = NOT INTERNALLY CONNECTED.
0.25 μV/°C maximum (B grade, 8-lead SOIC, single/dual) Figure 1. ADA4077-1, 8-Lead SOIC and 8-Lead MSOP
0.55 μV/°C maximum (A grade, 8-lead SOIC, single/dual)
OUT A 1 8 V+
0.75 μV/°C maximum (A grade, 14-lead SOIC, quad)
–IN A 2 ADA4077-2 7 OUT B
MSL1 rated TOP VIEW
+IN A 3 (Not to Scale)
6 –IN B
10238-001
Low input bias current: 1 nA maximum at TA = 25°C
V– 4 5 +IN B
Low voltage noise density: 6.9 nV/√Hz typical at f = 1000 Hz
CMRR, PSRR, and AV > 120 dB minimum Figure 2. ADA4077-2, 8-Lead MSOP and 8-Lead SOIC
Low supply current: 400 μA per amplifier typical
OUT A 1 14 OUT D
Wide gain bandwidth product: 3.9 MHz at ±5 V
–IN A 2 13 –IN D
Dual-supply operation:
+IN A 3 ADA4077-4 12 +IN D
Specified at ±5 V to ±15 V TOP VIEW
V+ 4
(Not to Scale)
11 V–
Operates at ±2.5 V to ±15 V
+IN B 5 10 +IN C
Unity gain stable 6
–IN B 9 –IN C
No phase reversal
10238-202
OUT B 7 8 OUT C
Long-term offset voltage drift (10,000 hours): 0.5 μV typical
Temperature hysteresis: 1 μV typical Figure 3. ADA4077-4, 14-Lead TSSOP and 14-Lead SOIC
APPLICATIONS The ADA4077-1 and ADA4077-2 are available in an 8-lead SOIC
Process control front-end amplifiers package, including the B grade, and in an 8-lead MSOP (A grade
Optical network control circuits only). The ADA4077-4 is offered in a 14-lead TSSOP and a 14-lead
Instrumentation SOIC package.
Precision sensors and controls 200
VSY = ±5V
Precision filters 180 SOIC
GENERAL DESCRIPTION 160
NUMBER OF AMPLIFIERS
The single ADA4077-1, dual ADA4077-2, and quad ADA4077-4 140

amplifiers feature extremely low offset voltage and drift, and low 120
input bias current, noise, and power consumption. Outputs are
100
stable with capacitive loads of more than 1000 pF with no
80
external compensation.
60
Applications for this amplifier include sensor signal conditioning
(such as thermocouples, resistance temperature detectors (RTDs), 40
strain gages), process control front-end amplifiers, and precision 20
diode power measurement in optical and wireless transmission 0

MORE
0
5
50
–5
10
15
20
25
30
35
40
45
–50
–45
–40
–35
–30
–25
–20
–15
–10
systems. The ADA4077-1/ADA4077-2/ADA4077-4 are useful in

10238-103
line powered and portable instrumentation, precision filters, VOS (µV)
and voltage or current measurement and level setting. Figure 4. Offset Voltage Distribution
Unlike other amplifiers, the ADA4077-1/ADA4077-2/ Table 1. Evolution of Precision Devices by Generation
ADA4077-4 have an MSL1 rating that is compliant with the most Op Amp First Second Third Fourth Fifth Sixth
stringent of assembly processes, and they are specified over the Single OP07 OP77 OP177 OP1177 AD8677 ADA4077-1
extended industrial temperature range from −40°C to +125°C for Dual OP2177 ADA4077-2
Quad OP4177 ADA4077-4
the most demanding operating environments.
Rev. E Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012–2017 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 11
Applications ....................................................................................... 1 Test Circuit ...................................................................................... 21
General Description ......................................................................... 1 Theory of Operation ...................................................................... 22
Pin Connection Diagrams ............................................................... 1 Applications Information .............................................................. 23
Revision History ............................................................................... 2 Output Phase Reversal ............................................................... 23
Specifications..................................................................................... 3 Low Power Linearized RTD ...................................................... 23
Electrical Characteristics, ±5 V .................................................. 3 Proper Board Layout .................................................................. 23
Electrical Characteristics, ±15 V ................................................ 5 Long-Term Drift ......................................................................... 24
Absolute Maximum Ratings ....................................................... 7 Temperature Hysteresis ............................................................. 24
Thermal Resistance ...................................................................... 7 Outline Dimensions ....................................................................... 25
ESD Caution .................................................................................. 7 Ordering Guide .......................................................................... 27
Pin Configurations and Function Descriptions ........................... 8
REVISION HISTORY
5/2017—Rev. D to Rev. E 1/2014—Rev. A to Rev. B
Changes to Features Section, Applications Section, and Figure 1 ... 1 Added ADA4077-1 ............................................................. Universal
Added Maximum Reflow Temperature (MSL1 Rating) Changes to Features Section ............................................................1
Parameter and Note 2,Table 4; Renumbered Sequentially .......... 7 Added Figure 1; Renumbered Sequentially ...................................1
Changes to Figure 5, Figure 6, and Table 6 ................................... 8 Changes to Table 2.............................................................................3
Changes to Figure 24 and Figure 27 ............................................. 13 Changes to Table 3.............................................................................4
Changes to Figure 29, Figure 30, Figure 31, Figure 32, Figure 33, Added Figure 5, Figure 6, and Table 6; Renumbered
and Figure 34 ................................................................................... 14 Sequentially ........................................................................................7
Changes to Figure 66 ...................................................................... 20 Changes to Figure 17, Figure 20, and Figure 21 ......................... 11
Added Test Circuit Section and Figure 69; Renumbered Changes to Figure 65...................................................................... 19
Sequentially ..................................................................................... 22 Added Figure 67 and Figure 68 .................................................... 19
Added Long-Term Drift Section, Temperature Hysteresis Section, Changes to Output Phase Reversal Section and Figure 70 ....... 21
Figure 72, Figure 73, and Figure 74 ................................................. 24 Changes to Ordering Guide .......................................................... 24
Changes to Ordering Guide .......................................................... 27
10/2013—Rev. 0 to Rev. A
10/2016—Rev. C to Rev. D Added ADA4077-4 ............................................................. Universal
Changes to Table 2 ............................................................................ 3 Changes to Features, General Description, and Figure 1 .............1
Changes to Table 3 ............................................................................ 5 Deleted Figure 2; Renumbered Sequentially .................................1
Changes to Figure 19 ...................................................................... 12 Added Figure 2...................................................................................1
Changes to Figure 23 and Figure 26 ............................................. 13 Changes to Table 2.............................................................................3
Changes to Figure 29, Figure 30, Figure 32, and Figure 33 ....... 14 Changes to Table 3.............................................................................4
Changes to Table 4.............................................................................6
6/2015—Rev. B to Rev. C Added Figure 6, Figure 7, and Table 7; Renumbered
Change to Figure 63 ....................................................................... 18 Sequentially ........................................................................................8
Changes to Typical Performance Characteristics Section ...........9
Changes to Figure 65...................................................................... 20
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 23
10/2012—Revision 0: Initial Version
Rev. E | Page 2 of 27
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS, ±5 V
VSY = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS
ADA4077-1/ADA4077-2
B Grade, SOIC 10 25 µV
−40°C < TA < +125°C 65 µV
A Grade, SOIC 15 50 µV
−40°C < TA < +125°C 105 µV
A Grade, MSOP 50 90 µV
−40°C < TA < +125°C 220 µV
ADA4077-4
−40°C < TA < +125°C 105 µV
A Grade, TSSOP 15 120 µV
−40°C < TA < +125°C 220 µV
Offset Voltage Drift ∆VOS/∆T −40°C < TA < +125°C
ADA4077-1/ADA4077-2
B Grade, SOIC 0.1 0.25 µV/°C
A Grade, SOIC 0.25 0.55 µV/°C
A Grade, MSOP 0.5 1.2 µV/°C
ADA4077-4
A Grade, SOIC 0.4 0.75 µV/°C
A Grade, TSSOP 0.5 1.2 µV/°C
Input Bias Current IB −1 −0.4 +1 nA
−40°C < TA < +125°C −1.5 +1.5 nA
Input Offset Current IOS −0.5 +0.1 +0.5 nA
−40°C < TA < +125°C −1 +1 nA
Input Voltage Range −3.8 +3 V
Common-Mode Rejection Ratio CMRR VCM = −3.8 V to +3 V 122 140 dB
VCM = −3.8 V to +3 V, −40°C < TA < +85°C 120 dB
VCM = −3.8 V to +2.8 V, 85°C < TA < 125°C 120 dB
Large Signal Voltage Gain Av RL = 2 kΩ, VO = −3.0 V to +3.0 V 121 130 dB
−40°C < TA < +125°C 120 dB
Input Capacitance CINCM Common mode 5 pF
Input Resistance RIN Common mode 70 GΩ
OUTPUT CHARACTERISTICS
Output Voltage High VOH IL = 1 mA 3.8 V
−40°C < TA < +125°C 3.7 V
Output Voltage Low VOL IL = 1 mA −3.8 V
−40°C < TA < +125°C −3.7 V
Output Current IOUT VDROPOUT < 1.6 V ±10 mA
Short-Circuit Current ISC TA = 25°C 22 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = +1 0.05 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±2.5 V to ±18 V 123 128 dB
−40°C < TA < +125°C 120 dB
Supply Current per Amplifier ISY VO = 0 V 400 450 µA
−40°C < TA < +125°C 650 µA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 1.2 V/µs
Settling Time to 0.1% tS VIN = 1 V step, RL = 2 kΩ, AV = −1 3 µs
Gain Bandwidth Product GBP VIN = 10 mV p-p, RL = 2 kΩ, AV = +100 3.9 MHz
Unity-Gain Crossover UGC VIN = 10 mV p-p, RL = 2 kΩ, AV = +1 3.9 MHz
−3 dB Closed-Loop Bandwidth −3 dB AV = +1, VIN = 10 mV p-p, RL = 2 kΩ 5.9 MHz
Phase Margin ΦM VIN = 10 mV p-p, RL = 2 kΩ, AV = +1 55 Degrees
Total Harmonic Distortion Plus Noise THD + N VIN = 1 V rms, AV = +1, RL = 2 kΩ, f = 1 kHz 0.004 %
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.25 µV p-p
Voltage Noise Density en f = 1 Hz 13 nV/√Hz
f = 100 Hz 7 nV/√Hz
f = 1000 Hz 6.9 nV/√Hz
Current Noise Density in f = 1 kHz 0.2 pA/√Hz
MULTIPLE AMPLIFIERS CHANNEL SEPARATION CS f = 1 kHz, RL = 10 kΩ −125 dB
ELECTRICAL CHARACTERISTICS, ±15 V
VSY = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 3.
INPUT CHARACTERISTICS
Offset Voltage VOS
ADA4077-1/ADA4077-2
B Grade, SOIC 10 35 µV
−40°C < TA < +125°C 65 µV
−40°C < TA < +125°C 105 µV
A Grade, MSOP 50 90 µV
−40°C < TA < +125°C 220 µV
ADA4077-4
−40°C < TA < +125°C 105 µV
A Grade, TSSOP 15 120 µV
−40°C < TA < +125°C 220 µV
Offset Voltage Drift ∆VOS/∆T
ADA4077-1/ADA4077-2
B Grade, SOIC −40°C < TA < +125°C 0.1 0.25 µV/°C
A Grade, SOIC −40°C < TA < +125°C 0.25 0.55 µV/°C
A Grade, MSOP −40°C < TA < +125°C 0.5 1.2 µV/°C
ADA4077-4
A Grade, SOIC −40°C < TA < +125°C 0.4 0.75 µV/°C
A Grade, TSSOP −40°C < TA < +125°C 0.5 1.2 µV/°C
Input Bias Current IB −1 −0.4 +1 nA
−40°C < TA < +125°C −1.5 +1.5 nA
Input Offset Current IOS −0.5 +0.1 +0.5 nA
−40°C < TA < +125°C −1 +1 nA
Input Voltage Range −13.8 +13 V
Common-Mode Rejection Ratio CMRR VCM = −13.8 V to +13 V 132 150 dB
−40°C < TA < +125°C 130 dB
Large Signal Voltage Gain Av
ADA4077-1/ADA4077-2 (SOIC, MSOP) RL = 2 kΩ, VO = −13.0 V to +13.0 V 125 130 dB
−40°C < TA < +125°C 120 dB
ADA4077-4 (SOIC, TSSOP) RL = 2 kΩ, VO = −13.0 V to +13.0 V 122 130 dB
−40°C < TA < +125°C 120 dB
Input Capacitance CINDM Differential mode 3 pF
CINCM Common mode 5 pF
Input Resistance RIN Common mode 70 GΩ
OUTPUT CHARACTERISTICS
Output Voltage High VOH IL = 1 mA 13.8 V
−40°C < TA < +125°C 13.7 V
Output Voltage Low VOL IL = 1 mA −13.8 V
−40°C < TA < +125°C −13.7 V
Output Current IOUT VDROPOUT < 1.2 V ±10 mA
Short-Circuit Current ISC TA = 25°C 22 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = +1 0.05 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±2.5 V to ±18 V 123 128 dB
−40°C < TA < +125°C 120 dB
Supply Current per Amplifier ISY VO = 0 V 400 500 µA
−40°C < TA < +125°C 650 µA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 1.2 V/µs
Settling Time to 0.01% ts VIN = 10 V p-p, RL = 2 kΩ, AV = −1 16 µs
Settling Time to 0.1% ts VIN = 10 V p-p, RL = 2 kΩ, AV = −1 10 µs
Gain Bandwidth Product GBP VIN = 10 mV p-p, RL = 2 kΩ, AV = +100 3.6 MHz
Unity-Gain Crossover UGC VIN = 10 mV p-p, RL = 2 kΩ, AV = +1 3.9 MHz
−3 dB Closed-Loop Bandwidth −3 dB AV = +1, VIN = 10 mV p-p, RL = 2 kΩ 5.5 MHz
Phase Margin ΦM VIN = 10 mV p-p, RL = 2 kΩ, AV = +1 58 Degrees
Total Harmonic Distortion Plus Noise THD + N VIN = 1 V rms, AV = +1, RL = 2 kΩ, 0.004 %
f = 1 kHz
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.25 µV p-p
Voltage Noise Density en f = 1 Hz 13 nV/√Hz
f = 100 Hz 7 nV/√Hz
f = 1000 Hz 6.9 nV/√Hz
Current Noise Density in f = 1 kHz 0.2 pA/√Hz
MULTIPLE AMPLIFIERS CHANNEL SEPARATION CS f = 1 kHz, RL = 10 kΩ −125 dB
ABSOLUTE MAXIMUM RATINGS
Table 4. THERMAL RESISTANCE
Parameter Rating θJA is specified for the worst case conditions, that is, a device
Supply Voltage 36 V soldered in a circuit board for surface-mount packages.
Input Voltage ±VSY
Table 5. Thermal Resistance
Input Current1 ±10 mA
Differential Input Voltage ±VSY Package Type θJA θJC Unit
Output Short-Circuit Duration to GND Indefinite 8-Lead MSOP 190 44 °C/W
Storage Temperature Range −65°C to +150°C 8-Lead SOIC 158 43 °C/W
Operating Temperature Range −40°C to +125°C 14-Lead TSSOP 240 43 °C/W
Junction Temperature Range −65°C to +150°C 14-Lead SOIC 115 36 °C/W
Maximum Reflow Temperature (MSL1 Rating)2 260°C
Lead Temperature, Soldering (10 sec) 300°C
ESD CAUTION
Electrostatic Discharge (ESD)
Human Body Model (HBM)3 6 kV
Field Induced Charge Device Model (FICDM)4 1.25 kV
1
The input pins have clamp diodes to the power supply pins and to each
other. Limit the input current to 10 mA or less whenever input signals
exceed the power supply rail by 0.3 V.
2
IPC/JEDEC J-STD-020 applicable standard.
3
ESDA/JEDEC JS-001-2011 applicable standard.
4
JESD22-C101 (ESD FICDM standard of JEDEC) applicable standard.
Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NIC 1 8 NIC NIC 1 8 NIC
–IN 2 ADA4077-1 7 V+ –IN 2 ADA4077-1 7 V+
+IN 3 TOP VIEW 6 OUT +IN 3 TOP VIEW 6 OUT
V– 4 (Not to Scale) 5 NIC (Not to Scale)
V– 4 5 NIC
10238-205
10238-105
NIC = NOT INTERNALLY CONNECTED. NIC = NOT INTERNALLY CONNECTED.
Figure 5. ADA4077-1 Pin Configuration, 8-Lead MSOP (RM-8) Figure 6. ADA4077-1 Pin Configuration, 8-Lead SOIC (R-8)
Table 6. ADA4077-1 Pin Function Descriptions, 8-Lead MSOP and 8-Lead SOIC
Pin No. Mnemonic Description
1, 5, 8 NIC Not internally connected.
2 −IN Inverting Input.
3 +IN Noninverting Input.
4 V− Negative Supply Voltage.
6 OUT Output.
7 V+ Positive Supply Voltage.
OUT A 1 8 V+ OUT A 1 8 V+
–IN A 2 ADA4077-2 7 OUT B –IN A 2 ADA4077-2 7 OUT B
TOP VIEW
+IN A 3 (Not to Scale) 6 –IN B +IN A 3 TOP VIEW 6 –IN B
10238-004
10238-005
V– 4 5 +IN B (Not to Scale)
V– 4 5 +IN B
Figure 7. ADA4077-2 Pin Configuration, 8-Lead MSOP Figure 8. ADA4077-2 Pin Configuration, 8-Lead SOIC
Table 7. ADA4077-2 Pin Function Descriptions, 8-Lead MSOP and 8-Lead SOIC
1 OUT A Output Channel A.
2 −IN A Inverting Input Channel A.
3 +IN A Noninverting Input Channel A.
5 +IN B Noninverting Input Channel B.
6 −IN B Inverting Input Channel B.
7 OUT B Output Channel B.
OUT A 1 14 OUT D OUT A 1 14 OUT D

–IN A 2 13 –IN D
–IN A 2 13 –IN D
+IN A 3 ADA4077-4 12 +IN D
+IN A 3 ADA4077-4 12 +IN D
TOP VIEW V+ 4 TOP VIEW 11 V–

V+ 4
(Not to Scale)
11 V– (Not to Scale)
+IN B 5 10 +IN C
+IN B 5 10 +IN C –IN B 6 9 –IN C
10238-207
–IN B 6 9 –IN C OUT B 7 8 OUT C
10238-206
OUT B 7 8 OUT C
Figure 9. ADA4077-4 Pin Configuration, 14-Lead TSSOP Figure 10. ADA4077-4 Pin Configuration, 14-Lead SOIC
Table 8. ADA4077-4 Pin Function Descriptions, 14-Lead TSSOP and 14-Lead SOIC
1 OUT A Output Channel A.
2 −IN A Negative Input Channel A.
3 +IN A Positive Input Channel A.
5 +IN B Positive Input Channel B.
6 −IN B Negative Input Channel B.
7 OUT B Output Channel B.
8 OUT C Output Channel C.
9 −IN C Negative Input Channel C.
10 +IN C Positive Input Channel C.
12 +IN D Positive Input Channel D.
13 −IN D Negative Input Channel D.
14 OUT D Output Channel D.
TYPICAL PERFORMANCE CHARACTERISTICS

120 140
VSY = ±5V
VSY = ±15V
MSOP
120 MSOP
100
100
80
80
60
60
40
40
20
20
0 0
MORE
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5
–5
10
15
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25
30
35
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50
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50
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–45
–40
–35
–30
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–20
–15
–10
10238-006
10238-003
VOS (µV) VOS (µV)
Figure 11. ADA4077-2 Offset Voltage (VOS) Distribution, VSY = ±5 V Figure 14. ADA4077-2 Offset Voltage (VOS) Distribution, VSY = ±15 V
200 200
VSY = ±5V VSY = ±15V
180 SOIC 180 SOIC
160 NUMBER OF AMPLIFIERS 160

140 140
120 120
100 100
80 80
60 60
40 40
20 20
0 0
0
5
MORE
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10
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20
25
30
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30
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50
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–10
10238-009
10238-144
VOS (µV) VOS (µV)
Figure 12. Offset Voltage (VOS) Distribution, VSY = ±5 V Figure 15. Offset Voltage (VOS) Distribution, VSY = ±15 V
20 15
15 10
10 5
VOS (µV)
VOS (µV)
5 0
0 –5
–5 –10
–10 –15
10238-213
10238-210
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125

TEMPERATURE (°C) TEMPERATURE (°C)
Figure 13. Offset Voltage (VOS) vs. Temperature, VSY = ±5 V Figure 16. Offset Voltage (VOS) vs. Temperature, VSY = ±15 V
50 70
VSY = ±15V, ±5V
VSY = ±15V, ±5V SOIC, A GRADE
45
TSSOP AND MSOP, A GRADE 60
40
35 50
30
40
25
30
20
15 20
10
10
5
0 0
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
10238-008
10238-130
TCVOS (µV/°C)
TCVOS (µV/°C)
Figure 17. TCVOS Distribution ([TSSOP and MSOP, A Grade) Figure 20. TCVOS Distribution (SOIC, A Grade)
10 140
VSY = ±15V, ±5V
SOIC, B GRADE
120
5
100
VOS (µV)
80
0
60
–5 40
20
–10
10238-134
0
0 5 10 15 20 25 30 35
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
10238-308
VSY (V)
TCVOS (µV/°C)
Figure 18. Offset Voltage (VOS) vs. Power Supply Voltage (VSY) Figure 21. TCVOS Distribution (SOIC, B Grade)
100 0.6
VS = ±15V
80 –15V ≤ V CM ≤ +15V
60
40
0.4
20
VOS (µV)
ISY (mA)
–20
0.2
–40
–40°C VO = 0V
–60 +25°C
+85°C
AVERAGE +125°C
–80 AVERAGE +3σ
AVERAGE –3σ
–100 0
10238-218
10238-419
–15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38

VCM (V) VSY (V)
Figure 19. Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = ±15 V Figure 22. Supply Current per Amplifier (ISY) vs. Power Supply Voltage (VSY)
4.15 14.15
VOH = 1mA VOH = 1mA
VOL = 1mA VOL = 1mA
4.10 14.10
OUTPUT VOLTAGE SWING (V)
OUTPUT VOLTAGE SWING (V)

4.05 14.05
4.00 14.00
3.95 13.95
3.90 13.90
3.85 13.85
3.80 13.80
VS = ±5V VS = ±15V
3.75 13.75
10238-423
10238-426
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
Figure 23. Output Voltage Swing vs. Temperature, VSY = ±5 V Figure 26. Output Voltage Swing vs. Temperature, VSY = ±15 V
350 400
300 350
300
250
250
200
200
150
150
100
100
50 50
0 0
0
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
–1
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
10238-013
10238-016
INPUT BIAS CURRENT (nA) INPUT BIAS CURRENT (nA)
Figure 24. Input Bias Current Distribution, VSY = ±5 V Figure 27. Input Bias Current Distribution, VSY = ±15 V
0 0
–0.1 –0.1
–0.2 –0.2
–IB +IB
–IB
–0.3 –0.3
IB (nA)
IB (nA)
–0.4 –0.4
+IB
–0.5 –0.5
–0.6 –0.6
–0.7 –0.7
10238-014
10238-017
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125

Figure 25. Input Bias Current (IB) vs. Temperature, VSY = ±5 V Figure 28. Input Bias Current (IB) vs. Temperature, VSY = ±15 V
10k 100k
ISINK = –40°C ISINK = –40°C
ISINK = +25°C ISINK = +25°C
OUTPUT DROPOUT VOLTAGE (mV)

10k
1k
1k

–40°C ≤ T ≤ +125°C –40°C ≤ T ≤ +125°C
100 100
10238-432
10238-429
0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100
ILOAD (mA) ILOAD (mA)
Figure 29. Output Dropout Voltage vs. ILOAD, Sink Current, VSY = ±5 V Figure 32. Output Dropout Voltage vs. ILOAD, Sink Current, VSY = ±15 V
10k 100k
ISOURCE = –40°C ISOURCE = –40°C
ISOURCE = +25°C ISOURCE = +25°C
ISOURCE = +85°C ISOURCE = +85°C
ISOURCE = +125°C

ISOURCE = +125°C
10k
1k
1k
VSY = ±5V
VSY = ±15V
–40°C ≤ T ≤ +125°C
100 –40°C ≤ T ≤ +125°C
100
10238-430
0.001 0.01 0.1 1 10 100
10238-433
0.001 0.01 0.1 1 10 100
ILOAD (mA) ILOAD (mA)
Figure 30. Output Dropout Voltage vs. ILOAD, Source Current, VSY = ±5 V Figure 33. Output Dropout Voltage vs. ILOAD, Source Current, VSY = ±15 V
150 150 150 150

GAIN = 0pF GAIN = 100pF GAIN = 200pF GAIN = 0pF GAIN = 100pF GAIN = 200pF
PHASE = 0pF PHASE = 100pF PHASE = 200pF PHASE = 0pF PHASE = 100pF PHASE = 200pF
100 100 100 100
PHASE MARGIN (Degrees)
PHASE MARGIN (Degrees)

OPEN-LOOP GAIN (dB)
OPEN-LOOP GAIN (dB)
50 50 50 50
0 0 0 0

–50 AV = –1 –50 –50 AV = –1 –50
RL = 2kΩ RL = 2kΩ
–100 –100 –100 –100
–150 –150 –150 –150

10238-227
10238-230
10k 100k 1M 10M 100M 10k 100k 1M 10M 100M

FREQUENCY (Hz) FREQUENCY (Hz)
Figure 31. Open-Loop Gain and Phase Margin vs. Frequency, VSY = ±5 V Figure 34. Open-Loop Gain and Phase Margin vs. Frequency, VSY = ±15 V
133 140
VSY = ±5V TO ±15V VSY = ±15V
VSY = ±5V
132
120
131
100
130
CMRR (dB)
PSRR (dB)
80
129
128 60
127
40
126
20
125
124 0
10238-029
10238-035
100 1k 10k 100k 1M 10M
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C) FREQUENCY (Hz)
Figure 35. PSRR vs. Temperature, VSY = ±5 V to ±15 V Figure 38. CMRR vs. Frequency, VSY = ±5 V and VSY = ±15 V
120 120
100 100
80 80
PSRR (dB)
60 PSRR (dB) 60 PSRR–
40 PSRR– 40
PSRR+
PSRR+
20 20
0 0
–20 –20
10238-034
10238-037
100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
Figure 36. PSRR vs. Frequency, VSY = ±5 V Figure 39. PSRR vs. Frequency, VSY = ±15 V
152 159
151 VSY = ±5V VSY = ±15V
150 158
149
157
148
CMRR (dB)
CMRR (dB)
147
156
146
145
155
144
143 154
142
141 153
10238-030
10238-033
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125

Figure 37. CMRR vs. Temperature, VSY = ±5 V Figure 40. CMRR vs. Temperature, VSY = ±15 V
50 50
G = 100 VSY = ±5V G = 100 VSY = ±15V
40 40
30 30
G = 10 G = 10
CLOSED-LOOP GAIN (dB)

CLOSED-LOOP GAIN (dB)
20 20
10 10
G=1 G=1
0 0
–10 –10
–20 –20
–30 –30
–40 –40
–50 –50
10238-028
10238-031
1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
Figure 41. Closed-Loop Gain vs. Frequency, VSY = ±5 V Figure 44. Closed-Loop Gain vs. Frequency, VSY = ±15 V
1k 1k

100 100
AV = +100 AV = +100
10 AV = +10 10 AV = +10
ZOUT (Ω)
ZOUT (Ω)
1 AV = +1 1 AV = +1
0.1 0.1
0.01 0.01
0.001 0.001
10238-039
10238-036
100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M

Figure 42. Output Impedance (ZOUT) vs. Frequency, VSY = ±5 V Figure 45. Output Impedance (ZOUT) vs. Frequency, VSY = ±15 V

VOLTAGE (0.2V/DIV)
VOLTAGE (1V/DIV)
VIN = 1V p-p VIN = 4V p-p

AV = +1 AV = +1
0V CL = 300pF 0V CL = 300pF
10238-040
10238-043
TIME (100µs/DIV) TIME (100µs/DIV)

Figure 43. Large Signal Transient Response, VSY = ±5 V Figure 46. Large Signal Transient Response, VSY = ±15 V
0.20 0.20
0.15 0.15
0.10 0.10
0.05 0.05
VOLTAGE (V)
VOLTAGE (V)
0 0
–0.05 –0.05
–0.10 VIN = 100mV p-p –0.10 VIN = 100mV p-p
AV = +1 AV = +1
LOAD = 2kΩ||1000pF LOAD = 2kΩ||1000pF
–0.15 –0.15
–0.20 –0.20
10238-344
10238-247
–0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
TIME (ms) TIME (ms)
Figure 47. Small Signal Transient Response, VSY = ±5 V Figure 50. Small Signal Transient Response, VSY = ±15 V
INPUT VOLTAGE (V)
0.5 0.5 35
INPUT 0 30
0
–0.5 25
–0.5 VSY = ±5V
–1.0 20
OUTPUT (V)
AV = –100
INPUT (V)
VIN = 200mV VSY = ±15V
RL = 10kΩ 5 –1.5 VIN = 200mV p-p 15
AV = –100
OUTPUT VOLTAGE (V)
LOAD = 10kΩ
–2.0 10
3
–2.5 5
OUTPUT 1
–3.0 0
10238-046
–1 –3.5 –5
10238-248
TIME (10µs/DIV) –10 0 10 20 30 40 50 60 70 80 90
TIME (µs)
Figure 48. Positive Overload Recovery, VSY = ±5 V Figure 51. Positive Overload Recovery, VSY = ±15 V
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
0.5 0.5
INPUT INPUT
0 0
–0.5 –0.5
OUTPUT
1 0
OUTPUT
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
–1 –5
AV = –100 AV = –100
VIN = 200mV –3 VIN = 200mV –10
10238-047
10238-051
–5 –15
Figure 49. Negative Overload Recovery, VSY = ±5 V Figure 52. Negative Overload Recovery, VSY = ±15 V
40 40
35 RL = 2kΩ 35 RL = 2kΩ
30 30
OVERSHOOT (%)
OVERSHOOT (%)
25 25
20 20
15 15
OS+ OS+
OS– OS–
10 10
5 5
0 0
10238-250
10238-253
1p 10p 100p 1n 10n 1p 10p 100p 1n 10n
LOAD CAPACITANCE (F) LOAD CAPACITANCE (F)
Figure 53. Small Signal Overshoot vs. Load Capacitance, VSY = ±5 V Figure 56. Small Signal Overshoot vs. Load Capacitance, VSY = ±15 V
0.05 0.25
0.04 0.20
0.03 0.15
VSY = ±5V
VIN = 1V p-p 0.02 0.10
OUTPUT (V)
OUTPUT (V)
RL = 2kΩ
INPUT (V)
INPUT (V)
0.01 0.05
0 0
–0.01 VSY = ±15V –0.05

VIN = 10V p-p
RL = 2kΩ
–0.02 –0.10
10238-251
10238-254
–0.03 –0.15
Figure 54. Positive 0.1% Settling Time, VSY = ±5 V Figure 57. Positive 0.1% Settling Time, VSY = ±15 V
0.05 0.25
0.04 0.20
VIN = 1V p-p 0.03 VIN = 10V p-p 0.15
0.02 0.10
OUTPUT (V)
OUTPUT (V)
INPUT (V)
INPUT (V)
0.01 0.05
0 0
–0.01 –0.05
–0.02 –0.10
10238-252
10238-255
–0.03 –0.15
Figure 55. Negative 0.1% Settling Time, VSY = ±5 V Figure 58. Negative 0.1% Settling Time, VSY = ±15 V
1k 100
VSY = ±15V
VSY = ±5V 90 VSY = ±5V
AV = +1 VSY = ±15V
VOLTAGE NOISE DENSITY (nV/√Hz)
VOLTAGE NOISE CORNER (nV/√Hz)

80
70
100
60
50
40
10
30
20
10
1 0
10238-153
10238-053
10 100 1k 10k 100k 1M 10M 0 0.5 1.0 1.5 2.0 2.5 3.0
Figure 59. Voltage Noise Density vs. Frequency, VSY = ±5 V and VSY = ±15 V Figure 62. Voltage Noise Corner vs. Frequency, VSY = ±15 V and VSY = ±5 V
1 100
10
0.1
1 BANDWIDTH = 80kHz
THD + NOISE (%)
THD + NOISE (%)

BANDWIDTH = 500kHz
BANDWIDTH = 80kHz
BANDWIDTH = 500kHz
0.01 0.1
0.01
0.001
0.001
0.0001 0.0001
10238-158
10238-155
10 100 1k 10k 100k 10 100 1k 10k 100k

Figure 60. THD + Noise vs. Frequency, VSY = ±5 V Figure 63. THD + Noise vs. Frequency, VSY = ±15 V

INPUT VOLTAGE (50nV/DIV)
INPUT VOLTAGE (50nV/DIV)

10238-054
10238-058
TIME (1s/DIV) TIME (1s/DIV)
Figure 61. 0.1 Hz to 10 Hz Noise, VSY = ±5 V Figure 64. 0.1 Hz to 10 Hz Noise, VSY = ±15 V
200 100
VSY = ±15V VSY = ±15V
100
–15V ≤ VCM ≤ +15V
CURRENT NOISE DENSITY (pA/√Hz)

0 TA = 25°C
–100
–200 10
–300
IB (pA)
–400
–500
–600 1
–700
–800 MEAN +3σ
MEAN
–900 MEAN –3σ
–1000 0.1
10238-219
10238-267
–20 –15 –10 –5 0 5 10 15 20 1 10 100 1k 10k 100k
VCM (V) FREQUENCY (Hz)
Figure 65. Input Bias Current (IB) vs. Common-Mode Voltage (VCM) Figure 67. Current Noise Density, VSY = ±15 V
0 100
VSY = ±5V
–20
CURRENT NOISE DENSITY (pA/√Hz)

CHANNEL SEPARATION (dB)
–40
10
–60
–80
–100
1
–120
VSY = ±15V
VIN = 10V p-p
–140 AV = +1
RL = 10kΩ
–160 0.1
10238-244
10238-268
100 1k 10k 100k 1M 1 10 100 1k 10k 100k
Figure 66. Channel Separation, VSY = ±15 V (See Figure 69) Figure 68. Current Noise Density, VSY = ±5 V
TEST CIRCUIT
10kΩ
VCC VCC
1kΩ
– –
+ +
VEE VEE
VIN 2kΩ 2kΩ
10238-469
CH A CH B,
CH C,
CH D
Figure 69 Test Circuit for Channel Separation vs. Frequency
THEORY OF OPERATION
The ADA4077-1/ADA4077-2/ADA4077-4 are the sixth generation The ADA4077-1/ADA4077-2/ADA4077-4 have an operating
of the Analog Devices, Inc., industry-standard OP07 amplifier temperature range of −40°C to +125°C with an MSL1 rating, which
family. The ADA4077-1/ADA4077-2/ADA4077-4 are high pre- is as wide as any similar device in a plastic surface-mount package.
cision, low noise operational amplifiers with a combination of This MSL1 rating is increasingly important as printed circuit
extremely low offset voltage and very low input bias currents. board (PCB) and overall system sizes continue to shrink, causing
Unlike JFET amplifiers, the low bias and offset currents are internal system temperatures to rise.
relatively insensitive to ambient temperatures, even up to 125°C. In the ADA4077-1/ADA4077-2/ADA4077-4, the power con-
The Analog Devices proprietary process technology and linear sumption is reduced by a factor of four compared to the OP177,
design expertise have produced high voltage amplifiers with and the bandwidth and slew rate are both increased by a factor
superior performance to the OP07/OP77/OP177/OP1177 in of six. The low power dissipation and very stable performance
tiny, 8-lead SOIC and 8-lead MSOP packages (ADA4077-1 and vs. temperature also reduce warmup drift errors to insignificant
ADA4077-2) and 14-lead TSSOP and 14-lead SOIC packages levels.
(ADA4077-4). Despite their small size, the ADA4077-1/ Inputs are protected internally from overvoltage conditions
ADA4077-2/ADA4077-4 offer numerous improvements, referenced to either supply rail. Like any high performance
including low wideband noise, wide bandwidth, lower offset and amplifier, maximum performance is achieved by following
offset drift, lower input bias current, and complete freedom from appropriate circuit and PCB guidelines.
phase inversion.
APPLICATIONS INFORMATION
OUTPUT PHASE REVERSAL +15V
500Ω
FULL-SCALE ADJ
Phase reversal is defined as a change of polarity in the amplifier 0.1µF

ADR4525
transfer function. Many operational amplifiers exhibit phase 0.1µF
4.12kΩ 4.37kΩ 200Ω
reversal when the voltage applied to the input is greater than the
maximum common-mode voltage. In some instances, this phase 6
4.12kΩ
reversal can cause permanent damage to the amplifier. In feedback 100Ω
1/2
ADA4077-2
7
VOUT
loops, it can result in system lockups or equipment damage. The 5
ADA4077-1/ADA4077-2/ADA4077-4 are immune to phase 100Ω 20Ω

RP,
reversal problems even at input voltages beyond the power ZERO ADJ 5kΩ
LINEARITY
supply settings. 49.9kΩ ADJ
100Ω V+
RTD
2 8
1/2 1
ADA4077-2
3
10238-064
4
V–
2 1
Figure 71. Low Power Linearized RTD Circuit
PROPER BOARD LAYOUT

The ADA4077-1/ADA4077-2/ADA4077-4 are high precision
devices. To ensure optimum performance at the PCB level, care
must be taken in the design of the board layout.
10238-063
CH1 5.00V CH2 5.00V M10.0ms A CH1 300mV To avoid leakage currents, maintain a clean and moisture free
T 0.000%
board surface. Coating the surface creates a barrier to moisture
Figure 70. No Phase Reversal
accumulation, and reduces parasitic resistance on the board.
LOW POWER LINEARIZED RTD Keeping supply traces short and properly bypassing the power
A common application for a single element varying bridge is an supplies minimizes the power supply disturbances caused by
RTD thermometer amplifier, as shown in Figure 71. The excitation the output current variation, such as when driving an ac signal
is delivered to the bridge by a 2.5 V reference applied at the top into a heavy load. Connect bypass capacitors as closely as possible
of the bridge. to the device supply pins. Stray capacitances are a concern at the
RTDs can have a thermal resistance as high as 0.5°C/mW to outputs and the inputs of the amplifier. It is recommended that
0.8°C/mW. To minimize errors due to resistor drift, keep the the signal traces be kept at least 5 mm from supply lines to
current low through each leg of the bridge. In this circuit, the minimize coupling.
amplifier supply current flows through the bridge. However, at a A variation in temperature across the PCB can cause a mismatch
maximum supply current of 500 µA for the ADA4077-2, the RTD in the Seebeck voltages at solder joints and other points where
dissipates less than 0.1 mW of power, even at the highest dissimilar metals are in contact, resulting in thermal voltage errors.
resistance. Therefore, errors due to power dissipation in the To minimize these thermocouple effects, orient resistors so that
bridge are kept under 0.1°C. heat sources warm both ends equally. Ensure, where possible, that
Calibration of the bridge is made at the minimum value of the input signal paths contain matching numbers and types of
temperature to be measured by adjusting RP until the output is components, to match the number and type of thermocouple
zero. junctions. For example, dummy components such as zero value
resistors can be used to match real resistors in the opposite input
To calibrate the output span, set the full-scale and linearity path. Place matching components in close proximity to each other,
potentiometers to midpoint, and apply a 500°C temperature to and orient them in the same manner. Ensure that leads are of equal
the sensor, or substitute the equivalent 500°C RTD resistance. length so that thermal conduction is in equilibrium. Keep heat
Adjust the full-scale potentiometer for a 5 V output. Finally, sources on the PCB as far away from amplifier input circuitry as
apply 250°C or the equivalent RTD resistance, and adjust the is practical.
linearity potentiometer for a 2.5 V output. The circuit achieves The use of a ground plane is highly recommended. A ground
higher than ±0.5°C accuracy after adjustment. plane reduces electromagnetic interference (EMI) noise and
maintains a constant temperature across the circuit board.
LONG-TERM DRIFT TEMPERATURE HYSTERESIS
The stability of a precision signal path over its lifetime or between In addition to stability over time as described in the Long-Term
calibration procedures is dependent on the long-term stability Drift section, it is useful to know the temperature hysteresis,
of the analog components in the path, such as op amps, references, that is, the stability vs. cycling of temperature. Hysteresis is an
and data converters. To help system designers predict the long- important parameter because it tells the system designer how
term drift of circuits that use the ADA4077-1/ADA4077-2/ closely the signal returns to its starting amplitude after the
ADA4077-4, Analog Devices measured the offset voltage of ambient temperature changes and subsequent return to room
multiple units for 10,000 hours (more than 13 months) using a temperature. Figure 73 shows the change in input offset voltage
high precision measurement system, including an ultrastable oil as the temperature cycles three times from room temperature to
bath. To replicate real-world system performance, the devices 125°C to −40°C and back to room temperature. The dotted line
under test (DUTs) were soldered onto an FR4 PCB using a is an initial preconditioning cycle to eliminate the original
standard reflow profile (as defined in the JEDEC J-STD-020D temperature-induced offset shift from exposure to production
standard), as opposed to testing them in sockets. This manner solder reflow temperatures. In the three full cycles, the offset
of testing is important because expansion and contraction of the hysteresis is typically only 1 µV, or 1.5% of its 65 µV maximum
PCB can apply stress to the integrated circuit (IC) package and offset voltage over the full operating temperature range. The
contribute to shifts in the offset voltage. histogram in Figure 74 shows that the hysteresis is larger when
The ADA4077-1/ADA4077-2/ADA4077-4 have extremely low the device is cycled through only a half cycle, from room
long-term drift (LTD). Figure 72 shows the LTD of the temperature to 125°C and back to room temperature.
ADA4077-1 (SOIC package). The red, blue, and green traces 30
VSY = 10V
show sample units. Note that the mean drift over 10,000 hours PRECONDITION
CYCLE 1
CHANGE IN OFFSET VOLTAGE (µV) 20
is less than 0.5 µV, or less than 2% of their maximum specified CYCLE 2
CYCLE 3
offset voltage of 25 µV at room temperature.
10
10
MEAN
8 MEAN PLUS ONE STANDARD DEVIATION 0
MEAN MINUS ONE STANDARD DEVIATION
CHANGE IN OFFSET VOLTAGE (µV)
4 –10
2
–20
0
–2
–30
10238-072
–40 –20 0 20 40 60 80 100 120
–4
TEMPERATURE (°C)
–6
SAMPLE 1 VSY = 10V Figure 73. Change in Offset Voltage over Three Full Temperature Cycles
–8 SAMPLE 2 27 UNITS
SAMPLE 3 TA = 25°C 40
VSY = 10V HALF CYCLE
–10 35 27 UNITS × 3 CYCLES FULL CYCLE
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
HALF CYCLE = +26°C, +125°C, +26°C

10,000
30 FULL CYCLE = +26°C, +125°C, +26°C, –40°C, +26°C

25
10238-071
20
TIME (Hours)
NUMBER OF DEVICES
15
Figure 72. Measured Long-Term Drift of the ADA4077-1/ADA4077-2/ 10
ADA4077-4 Offset Voltage over 10,000 Hours 5
0
40
35
30
25
20
15
10
5
0
10238-073
–12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12
OFFSET VOLTAGE HYSTERESIS (µV)
Figure 74. Histogram Showing the Temperature Hysteresis of the Offset

Voltage over Three Full Cycles and over Three Half Cycles
OUTLINE DIMENSIONS
3.20
3.00
2.80
8 5 5.15
3.20 4.90
3.00 4.65
2.80 1
4
PIN 1
IDENTIFIER
0.65 BSC
0.95 15° MAX

0.85 1.10 MAX
0.75
0.80
0.15 6° 0.23
0.40 0.55
0.05 0° 0.09 0.40
COPLANARITY 0.25
10-07-2009-B
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 75. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284)
4
1.27 (0.0500) 0.50 (0.0196)

BSC 45°
1.75 (0.0688) 0.25 (0.0099)
0.25 (0.0098) 1.35 (0.0532)
8°
0.10 (0.0040) 0°
COPLANARITY 0.51 (0.0201)
0.10 1.27 (0.0500)
0.31 (0.0122) 0.25 (0.0098)
SEATING 0.40 (0.0157)
PLANE 0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
012407-A
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 76. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
5.10
5.00
4.90
14 8
4.50
4.40 6.40
BSC
4.30
1
7
PIN 1
0.65 BSC
1.05
1.00 1.20
MAX 0.20
0.80 0.09 0.75
0.15 8° 0.60
SEATING 0°
0.05 0.30 PLANE 0.45
COPLANARITY 0.19
0.10
061908-A
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 77. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)
Dimensions shown in millimeters
8.75 (0.3445)
8.55 (0.3366)
14 8
4.00 (0.1575) 6.20 (0.2441)
1
3.80 (0.1496) 7 5.80 (0.2283)
1.27 (0.0500) 0.50 (0.0197)

BSC 45°
1.75 (0.0689) 0.25 (0.0098)
0.25 (0.0098) 8°
1.35 (0.0531)
0.10 (0.0039) 0°
COPLANARITY SEATING
0.10 0.51 (0.0201) 0.25 (0.0098) 1.27 (0.0500)
PLANE
0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AB

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
060606-A
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 78. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model 1 Temperature Range MSL Rating 2 Package Description Package Option Branding
ADA4077-1ARMZ −40°C to +125°C MSL1 8-Lead MSOP RM-8 A35
ADA4077-1ARMZ-R7 −40°C to +125°C MSL1 8-Lead MSOP RM-8 A35
ADA4077-1ARMZ-RL −40°C to +125°C MSL1 8-Lead MSOP RM-8 A35
ADA4077-1ARZ −40°C to +125°C MSL1 8-Lead SOIC_N R-8
ADA4077-1ARZ-R7 −40°C to +125°C MSL1 8-Lead SOIC_N R-8
ADA4077-1ARZ-RL −40°C to +125°C MSL1 8-Lead SOIC_N R-8
ADA4077-1BRZ −40°C to +125°C MSL1 8-Lead SOIC_N R-8
ADA4077-1BRZ-R7 −40°C to +125°C MSL1 8-Lead SOIC_N R-8
ADA4077-1BRZ-RL −40°C to +125°C MSL1 8-Lead SOIC_N R-8
ADA4077-2ARMZ −40°C to +125°C MSL1 8-Lead MSOP RM-8 A2X
ADA4077-2ARMZ-R7 −40°C to +125°C MSL1 8-Lead MSOP RM-8 A2X
ADA4077-2ARMZ-RL −40°C to +125°C MSL1 8-Lead MSOP RM-8 A2X
ADA4077-2BRZ −40°C to +125°C MSL1 8-Lead SOIC_N R-8
ADA4077-2BRZ-R7 −40°C to +125°C MSL1 8-Lead SOIC_N R-8
ADA4077-2BRZ-RL −40°C to +125°C MSL1 8-Lead SOIC_N R-8
ADA4077-4ARUZ −40°C to +125°C MSL1 14-Lead TSSOP RU-14
ADA4077-4ARUZ-R7 −40°C to +125°C MSL1 14-Lead TSSOP RU-14
ADA4077-4ARUZ-RL −40°C to +125°C MSL1 14-Lead TSSOP RU-14
1
Z = RoHS Compliant Part.
2
See the Absolute Maximum Ratings section.
©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D10238-0-5/17(E)

Ada4077-1 Ada4077-2 Ada4077-4: 4 MHZ, 7 NV/ HZ, Low Offset and Drift, High Precision Amplifiers

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Ada4077-1 Ada4077-2 Ada4077-4: 4 MHZ, 7 NV/ HZ, Low Offset and Drift, High Precision Amplifiers

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4 MHz, 7 nV/√Hz, Low Offset and

Drift, High Precision Amplifiers

The single ADA4077-1, dual ADA4077-2, and quad ADA4077-4 140

strain gages), process control front-end amplifiers, and precision 20

diode power measurement in optical and wireless transmission 0

systems. The ADA4077-1/ADA4077-2/ADA4077-4 are useful in

line powered and portable instrumentation, precision filters, VOS (µV)

10/2012—Revision 0: Initial Version

Stresses at or above those listed under Absolute Maximum

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

OUT A 1 14 OUT D OUT A 1 14 OUT D

TOP VIEW V+ 4 TOP VIEW 11 V–

TYPICAL PERFORMANCE CHARACTERISTICS

160 NUMBER OF AMPLIFIERS 160

VOS (µV) VOS (µV)

VSY = ±5V VSY = ±15V

–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125

–15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38

OUTPUT VOLTAGE SWING (V)

–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125

OUTPUT DROPOUT VOLTAGE (mV)

VSY = ±5V VSY = ±15V

OUTPUT DROPOUT VOLTAGE (mV)

0.001 0.01 0.1 1 10 100

150 150 150 150

PHASE MARGIN (Degrees)

OPEN-LOOP GAIN (dB)

VSY = ±5V VSY = ±15V

–100 –100 –100 –100

–150 –150 –150 –150

10k 100k 1M 10M 100M 10k 100k 1M 10M 100M

60 PSRR (dB) 60 PSRR–

151 VSY = ±5V VSY = ±15V

–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125

CLOSED-LOOP GAIN (dB)

VSY = ±5V VSY = ±15V

100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M

VSY = ±5V VSY = ±15V

VIN = 1V p-p VIN = 4V p-p

TIME (100µs/DIV) TIME (100µs/DIV)

INPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

–0.01 VSY = ±15V –0.05

VOLTAGE NOISE CORNER (nV/√Hz)

THD + NOISE (%)

10 100 1k 10k 100k 10 100 1k 10k 100k

VSY = ±5V VSY = ±15V

INPUT VOLTAGE (50nV/DIV)

TIME (1s/DIV) TIME (1s/DIV)

CURRENT NOISE DENSITY (pA/√Hz)

CURRENT NOISE DENSITY (pA/√Hz)

Figure 69 Test Circuit for Channel Separation vs. Frequency

Phase reversal is defined as a change of polarity in the amplifier 0.1µF

loops, it can result in system lockups or equipment damage. The 5

ADA4077-1/ADA4077-2/ADA4077-4 are immune to phase 100Ω 20Ω

PROPER BOARD LAYOUT

HALF CYCLE = +26°C, +125°C, +26°C

30 FULL CYCLE = +26°C, +125°C, +26°C, –40°C, +26°C

Figure 74. Histogram Showing the Temperature Hysteresis of the Offset

0.95 15° MAX

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 75. 8-Lead Mini Small Outline Package [MSOP]

1.27 (0.0500) 0.50 (0.0196)