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    The document is a midterm exam from Vemu Institute of Technology for an Embedded Systems course. It contains 3 questions worth 10 marks each: 1) Explain the Altera MAX macrocell and illustrate the architectures of several different product families. 2) What are the various approaches to memory synthesis? Explain memory synthesis in Verilog and VHDL with coding. 3) Explain the switch level simulation of True Single –Phase Flip-Flop with circuit schematic.

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    The document is a midterm exam from Vemu Institute of Technology for an Embedded Systems course. It contains 3 questions worth 10 marks each: 1) Explain the Altera MAX macrocell and illustrate the architectures of several different product families. 2) What are the various approaches to memory synthesis? Explain memory synthesis in Verilog and VHDL with coding. 3) Explain the switch level simulation of True Single –Phase Flip-Flop with circuit schematic.

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    © All Rights Reserved
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    29 views1 page

    ASIC Design-Mid-2 Questions

    Uploaded by

    Elaiyarja
    The document is a midterm exam from Vemu Institute of Technology for an Embedded Systems course. It contains 3 questions worth 10 marks each: 1) Explain the Altera MAX macrocell and illustrate the architectures of several different product families. 2) What are the various approaches to memory synthesis? Explain memory synthesis in Verilog and VHDL with coding. 3) Explain the switch level simulation of True Single –Phase Flip-Flop with circuit schematic.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    VEMU INSTITUTE OF TECHNOLOGY SUB: 17D5526- ASIC

    P.KOTHAKOTA, PUTHALAPATTU (M), CHITTOOR DIST – 517 112 Design


    I M.Tech II SEM MID-I EXAMINATIONS-October-2020
    Branch: Embedded Systems
    Time: 1Hr 30Min Max.Marks:30

    SET-1
    PART-A
    Answer all questions.

    Explain the Altera MAX macrocell and illustrate the architectures of several different
    1 10M
    product families.
    What are the various approaches to memory synthesis? Explain the memory synthesis in
    2 10M
    Verilog and VHDL with coding.
    3 Explain the switch level simulation of True Single –Phase Flip-Flop with circuit schematic . 10M

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