Deberjeet Usham 2K21/VLS/05 EXP No.

10

Exp. No.: 10
To design, synthesize, and simulate 74381 TTL 4-bit ALU
using Verilog.

AIM:

To design, simulate and implement 74381 TTL 4-bit ALU Verilog HDL.

APPARATUS REQUIRED:

 PC with Windows OS
 XILINX Vivado

THEORY:

The 74F381 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional
select input codes force the function outputs LOW or HIGH.
Features:-
1 Low input loading minimizes drive requirements
2 Performs six arithmetic and logic functions
3 Selectable LOW (clear) and HIGH (preset) functions
4 Carry generate and propagate outputs for use with carry lookahead generator.
Signals applied to the Select inputs S0–S2 determine the mode of operation, as indicated in the Function Select
Table. An extensive listing of input and output levels is shown in the Truth Table. The circuit performs the arith-
metic functions for either active HIGH or active LOW operands, with output levels in the same convention. In
the Subtract operating modes, it is necessary to force a carry (HIGH for active HIGH operands, LOW for active
LOW (operands) into the Cn input of the least significant package.

Function Table:

Verilog Code:

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SIMULATION WAVEFORM:

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RTL SCHEMATIC:

SYNTHESIS SCHEMATIC:

RESULT:

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Deberjeet Usham 2K21/VLS/05 EXP No. 10

The 4 bit ALU was implemented sucessfully.

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