Chapter 6: Interrupts and Resets: Fundamental Concepts of Interrupts

The HCS12/MC9S12 Microcontroller
Chapter 6: Interrupts and Resets
The HCS12 Microcontroller
Han-Way Huang
Minnesota State University, Mankato
September 2009
Copyright © 2010 Delmar Cengage Learning H. Huang Transparency No.6-1
Fundamental Concepts of Interrupts

What is an interrupt?
 A special event that requires the CPU to stop normal program execution and
perform some service related to the event.
 Examples of interrupts include I/O completion, timer time-out, illegal opcodes,
arithmetic overflow, divide-by-0, etc.
Functions of Interrupts
 Coordinating I/O activities and preventing CPU from being tied up

 Providing a graceful way to exit from errors
 Reminding the CPU to perform routine tasks
Interrupt Maskability
 Interrupts that can be ignored by the CPU are called maskable interrupts.
 A maskable interrupt must be enabled before it can interrupt the CPU.
 An interrupt is enabled by setting an enable flag.
 Interrupts that can’t be ignored by the CPU are called non-maskable interrupts.
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Interrupt priority
 Allow multiple pending interrupt requests
 Resolve the order of service for multiple pending interrupts
Interrupt Service
 CPU executes a program called the interrupt service routine.

 A complete interrupt service cycle includes
1. Saving the program counter value in the stack

2. Saving the CPU status (including the CPU status register and some other
registers) in the stack
3. Identifying the cause of interrupt
4. Resolving the starting address of the corresponding interrupt service routine
5. Executing the interrupt service routine
6. Restoring the CPU status and the program counter from the stack
7. Restarting the interrupted program
Interrupt Vector
Starting address of the interrupt service routine
Interrupt Vector Table

A table where all interrupt vectors are stored.
Methods of Determining Interrupt Vectors
1. Predefined locations (Microchip PIC18, 8051 variants)

2. Fetching the vector from a predefined memory location (HCS12, Atmel avr)
3. Executing an interrupt acknowledge cycle to fetch a vector number in order to
locate the interrupt vector (68000 and x86 families)
Steps of Interrupt Programming

Step 1. Initializing the interrupt vector table
Step 2. Writing the interrupt service routine
Step 3. Enabling the interrupt
2
The Overhead of Interrupts
 Saving and restoring of CPU status and other registers. (HCS12 needs to save all
CPU registers).
 Execution time of instructions of the interrupt service routine.
 The execution of the RTI instruction that will restore all the CPU registers.
Resets
 The initial values of some CPU registers, flip-flops, and the control registers in I/O
interface chips must be established in order for the computer to function properly.
 The reset mechanism establishes these initial conditions for the computer system.
 There are at least two types of resets: power-on reset and manual reset.
 The power-on reset establishes the initial values of registers and I/O control registers.
 The manual reset without power-down allows the computer to get out of most error
conditions if hardware doesn’t fail.
 A reset is non-maskable.
3
HCS12 Exceptions
 Maskable interrupts: including IRQ pin and all peripheral function interrupts.
 Nonmaskable interrupts: including XIRQ pin, SWI interrupt, and unimplemented opcode
trap.
 Resets: including the power-on reset, reset pin manual reset, the COP reset (computer
operate properly), and clock monitor reset.
Maskable Interrupts
 Different HCS12 members implement different number and types of peripheral functions,
and hence may have different number of maskable interrupts.
 One of the maskable interrupts can be raised to the highest priority among the maskable
interrupt group and receive quicker service. This is achieved by programming the
HPRIO register.
4
 The priority and vector addresses of all HCS12 exceptions are listed in Table 6.1.
 To raise a maskable interrupt source to the highest priority, write the low byte of the
vector address of this interrupt to the HPRIO register.
 In Table 6.1, exceptions that have higher vector addresses are at higher priorities.
 Not all the exceptions are available in all HCS12 members.
IRQ Pin Interrupt

 The only external maskable interrupt for the HCS12.
 IRQ interrupt can be edge-triggered or level-triggered.
 IRQ interrupt has a local enable mask in the IRQCR register.
 The IRQ interrupt is configured by programming the IRQCR register.
 The contents of the IRQCR register are shown in Figure 6.2.
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5
11
This register is also called INTCR
The bit 1 of port E is connected to the IRQ pin of the

HCS12. The IRQ pin is connected to the header pin
marked 55.
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6
Making IRQ Level-Sensitive

Pros:
Multiple interrupt sources can be tied to this pin.
Cons:
Need to make sure that the IRQ signal has become inactive before the IRQ service routine
is complete if there is only one interrupt request pending.
Making IRQ Edge-Sensitive

Pros:
No need to control the duration of the IRQ pulse.
Cons:
Not suitable for noisy environment because every falling edge caused by noise will be
recognized as an interrupt.
When does the MCU recognize interrupt requests?

The MCU recognizes the interrupt request when it completes the execution of the current
instruction unless the current instruction is a fuzzy logic instruction. For fuzzy logic
instructions, the HCS12 recognizes the interrupt immediately.
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The Stack Order on Entry of an Interrupt From Datasheet:
 The HCS12 saves all CPU registers on an interrupt.

 The order of saving CPU registers is shown in Figure 6.3. e.g.
The RTI Instruction

 RTI is used to terminate interrupt service routines.
 RTI will restore CPU registers from the stack.
 The HCS12 will continue to execute the interrupted
program unless there is another
pending interrupt.
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7
Non-maskable Interrupts
 XIRQ pin, SWI instruction, & unimplemented instruction opcode trap.
XIRQ Pin Interrupt
 XIRQ interrupt is disabled during a system reset and upon entering the service routine of
another XIRQ interrupt.
 After minimal system initialization, software can clear the X bit of the CCR register to
enable the (using the andcc #$BF instruction) XIRQ interrupt. Software cannot reset the X
bit once it has been set.
 When a non-maskable interrupt is recognized, both the X and I bits are set after CPU
registers are saved.
 The execution of an RTI instruction at the end of the XIRQ service routine will restore the
X and I bits to the pre-interrupt request state.
Unimplemented Opcode Trap
 There are 202 unimplemented opcode on page 2 (16-bit opcode).
 These unimplemented opcode share the same vector $FFF8:$FFF9.
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Software Interrupt Instruction (SWI)

 Execution of the SWI instruction causes an interrupt without an interrupt request signal.
 The SWI instruction is commonly used in the debug monitor to implement breakpoints
and to transfer control from a user program to the debug monitor.
 A breakpoint in a user program is a memory location where we want program execution
to be stopped and information about instruction execution (in the form of register
contents) to be displayed.
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8
Setting Up the Interrupt Vector
 Assume that the label (or name) of the IRQ interrupt service routine is irqISR.
In assembly language,
For miniIDE (D-Bug12 monitor), the interrupt vector must be stored in SRAM
movw #irqISR,UserIRQ ; store the vector at the designated address
For CodeWarrior (the serial monitor or BDM debug adapter), the interrupt vector must be
stored at the default address (for example, IRQ interrupt at $FFF2).
org $FFF2 ; set up interrupt vector for IRQ under CodeWarrior

dc.w irqISR ; “
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In C langauge
CodeWarrior Template for Interrupt Service Routine in CodeWarrior
void interrupt 6 handler(){

… // statements to service the interrupt
}
Interrupt void ISR_name (void)

{
… // statements to service the interrupt
}
The number 6 is the vector number for the IRQ interrupt, this number can be found in the
vector table.
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9
Example 6.1 The IRQ pin of the HCS12DP256 is connected to a 1-Hz digital
waveform and port B is connected to eight LEDs. Write a program to configure port B for
output and enable the IRQ interrupt and also write the service routine for the IRQ interrupt.
The service routine for the IRQ interrupt simply increments a counter and outputs it to
port B. The assembly language version is to be assembled miniIDE whereas the C language
version of the program is to be compiled by GNU C compiler.
Solution:
The assembly and C language versions of the program are in the following two
pages.
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#include "c:\miniide\hcs12.inc"
org $1000
count ds.b 1 ; reserve one byte for count
org $1500
lds #$1500 ; set up the stack pointer
movw #IRQISR,UserIRQ ; set up interrupt vector in SRAM
clr count
movb #$FF,DDRB ; configure port B for output
bset DDRJ,$02 ; configure PJ1 pin for output (required in Dragon12)
bclr PTJ,$02 ; enable LEDs to light (required in Dragon12)
movb count,PTB ; display the count value on LEDs
movb #$C0,IRQCR ; enable IRQ pin interrupt, select edge-triggering
cli ;"
forever nop
bra forever ; wait for IRQ pin interrupt
; ****************************************************************************
; This is the IRQ service routine.
; ****************************************************************************
IRQISR inc count ; increment count
movb count,PTB ; and display count on LEDs
rti
end
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10
#include "c:\egnu\include\hcs12.h"
#include "c:\egnu\include\vectors12.h"
#define INTERRUPT __attribute__((interrupt))
void INTERRUPT IRQISR(void);
unsigned char cnt;
void main(void)
{
UserIRQ = (unsigned short)&IRQISR;
DDRB = 0xFF;
cnt = 0;
DDRJ |= BIT1; // configure PJ1 pin for output
PTJ &= ~BIT1; // enable LEDs to light
IRQCR = 0xC0; // enable IRQ interrupt on falling edge
asm("cli"); // enable interrupt globally
while(1); // wait for interrupt forever
}
void INTERRUPT IRQISR(void)
{
cnt++;
PTB = cnt;
}
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Clock and Reset Generation Block (CRG)
 CRG generates the clock signals required by the HCS12 instruction execution and all
peripheral operations.
 The clock signal has the form of square waveform.
 Crystal oscillators are often used to generate clock signals.
 The crystal oscillator output is a sinusoidal wave and must be converted to square wave
before it can be used.
 The HCS12 has internal circuit to do this square up operation.
 The CRG block also has a PLL circuit that can multiply the frequency of the incoming
clock signal.
 The block diagram is shown in Figure 6.4.
 The CRG can also accept oscillator output (square waveform) directly.
 The XCLKS signal must be tied low (for MC9S12DP256B) in order to use external
clock signal.
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11
Clock oscillator types
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24
12
Choice of Clock Source
 The user can choose between using the external crystal or oscillator to produce the clock
signal.
 The external crystal is connected between the EXTAL and XTAL pins and needs an
on-chip oscillator circuitry to square it up.
 The external clock source provided by the oscillator is connected to the EXTAL pin and
have a 2.5V peak to peak magnitude for D family.
 The XCLKS signal must be grounded to select the external clock signal.
 The output from the OSC module in Figure 6.4 may bypass or go through the PLL circuit.
 The PLL circuit has the capability to multiply incoming signal frequency and stabilize
its output signal frequency.
 Either the OSCCLK or the PLLCLK can be chosen as the SYSCLK which will be
divided by 2 to derive the bus clock to control the instruction execution and peripheral
operation.
 The HCS12 clock generation circuit is shown in Figure 6.15.
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26
13
Phase Locked Loop
 The frequency of the PLLCLK is controlled by registers SYNR and REFDY using the
following equation:
(SYNR + 1)
PLLCLK = 2  OSCCLK  ------------------- (6.1)
(REFDV + 1)
7 6 5 4 3 2 1 0
0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
reset: 0 0 0 0 0 0 0 0
Figure 6.8 The CRG synthesizer register (SYNR)
7 6 5 4 3 2 1 0
0 0 0 0 REFDV3 REFDV2 REFDV1 REFDV0
reset: 0 0 0 0 0 0 0 0
Figure 6.9 The CRG reference divider register (REFDV)
Selection of PLL for clock generation is controlled by the CRGSEL register.
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•Operating frequency :50MHz equivalent to 25MHz Bus Speed for single chip
The HCS12 family has a highest bus clock frequency of 32 MHz.
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14
PLL circuit is also controlled by the PLLCTL register.
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30
15
Also called:
CLKSEL
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Example 6.2 There is a system that derives its bus clock from the PLL circuit and an
crystal oscillator of 8 MHz is selected. The desired bus clock is 24 MHz. Write an assembly
routine and a C function to perform the configuration.
Solution:
 The SYSCLK frequency is 48 MHz and the frequency of OSCCLK is 8 MHz.
48 MHz = 2  8 MHz  [SYNR + 1] /[REFDV + 1]
One solution is to set SYNR and REFDV to 2 and 0, respectively.

SetClk8 movb #02,SYNR
movb #0,REFDV
movb #$60,PLLCTL ; disable clock monitor, enable PLL
brclr CRGFLG,LOCK,* ; wait until PLL locks into the target frequency
movb #$80,CLKSEL ; use PLL to generate system clock
rts
void SetClk8(void)
{
SYNR = 0x02; // use PLL and 8-MHz crystal to generate 24-MHz E clock
REFDV= 0; // “
PLLCTL= 0x60; // enable PLL
while(!(CRGFLG & 0x08); // wait until PLL locks into the target frequency
CLKSEL |= PLLSEL; // clock derived from PLL
}
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16
Clock Monitor
 The clock monitor is based on an RC circuit.

 If no OSCCLK edges are detected within the RC time delay, the clock monitor may
reset the MCU if the CME bit in the PLLCTL register is set to 1.
 The SCME bit of the PLLCTL register must be cleared to 0 for clock monitor to
work.
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Real Time Interrupt
- Main function is to generate periodic interrupt to the MCU.

- The RTI interrupt is enabled by the CRGINT register (shown in Figure 6.11)
- The interrupt interval of RTI is selected by the RTICTL register (shown in Figure 6.16).
- The actual available interrupt periods for RTI are listed in Table 6.4.
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17
35
Table 6.4 RTI interrupt period (in units of OSCCLK cycle)

RTR[3:0] RTR[6:4]
000 001 010 011 100 101 110 111
(off) (210 ) (211 ) (212 ) (213 ) (214 ) (215 ) (216 )
0000 (1) off* 210 211 2 12 213 214 215 2 16
0001(2) off* 2210 2211 2212 22 13 2214 2215 22 16
0010 (3) off* 3210 3211 3212 32 13 3214 3215 32 16
0011 (4) off* 4210 4211 4212 42 13 4214 4215 42 16
0100 (5) off* 5210 5211 5212 52 13 5214 5215 52 16
0101 (6) off* 6210 6211 6212 62 13 6214 6215 62 16
0110 (7) off* 7210 7211 7212 72 13 7214 7215 72 16
0111 (8) off* 8210 8211 8212 82 13 8214 8215 82 16
1000 (9) off* 9210 9211 9212 92 13 9214 9215 92 16
1001 (10) off* 10210 102 11 102 12 10213 10214 102 15 102 16
1010 (11) off* 11210 112 11 112 12 11213 11214 112 15 112 16
1011 (12) off* 12210 122 11 122 12 12213 12214 122 15 122 16
1100 (13) off* 13210 132 11 132 12 13213 13214 132 15 132 16
1101 (14) off* 14210 142 11 142 12 14213 14214 142 15 142 16
1110 (15) off* 15210 152 11 152 12 15213 15214 152 15 152 16
1111 (16) off* 16210 162 11 162 12 16213 16214 162 15 162 16
OSCCLK == 16MHZ for the minidragon board e.g. RTICTL=0x50; // 2^14 =>
e.g. RTICTL=0x59; // 10 x 2^14 => 163840 16384
 163840/16MHz = 10.24 ms  16384/16MHz = 1.024 ms
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How do we do it in code warrior?
1. Set the RTICTL register to select the required time period

2. Set the CRGINT to enable RTI
3. Write your interrupt service routine
4. Inside the interrupt service routine : clear the RTI flag in the CRGFLG register.
37
Example 6.5 Write a C program to use the RTI interrupt to time-multiplex four seven
segment displays using the circuit shown in Figure 4.18 and shift the seven-segment
display pattern as described in Example 5.9. Turn on one display at a time and light each
display for about 1 ms then switch to the next display. Use display #0 to display #3. Use
CodeWarrior and a demo board programmed with serial monitor to implement the circuit.
Solution:
Arangememt
 Place the segment patterns in one array segPat[].
 Place digit select values in the array digit[].
 Use the variable seq as index to the segment array that identifies the first digit of the
current sequence.
 Use the variable ix as an index to the digits within one sequence (ix = 0..3).
 Use the variable count to specify the repetition count of a sequence
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19
#include "c:\cwHCS12\include\hcs12.h"
#include "c:\cwHCS12\include\SetClk.h"
int seq; // start index to segPat[] of a sequence of digits (0 to 9)
int ix; // index of digits of a sequence (0 to 3)
int count; // repetition count of a sequence
char segPat[13] = {0x06,0x5B,0x4F,0x66,0x6D,0x7D,0x07,0x7F,0x67,0x3F,0x06,
0x5B,0x4F};
char digit[4] = {0xFE,0xFD,0xFB,0xF7};
void main (void) {

seq = 0; // initialize the start index to segPat[] for the display sequence
ix = 0; // initialize the index of a new sequence
count = 400; // initialize the RTI interrupt count of a sequence
SetClk8(); // set E clock to 24 MHz from an 8-MHz crystal oscillator
RTICTL = 0x40; // RTI interrupt interval set to 2**10 OSCCLK cycles
DDRB = 0xFF; // configure Port B for output
DDRP = 0xFF; // configure Port P for output
CRGINT|= RTIE; // enable RTI interrupt
asm("CLI"); // enable interrupt globally
while(1);
}
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// RTI interrupt service routine

interrupt void rtiISR(void) {
CRGFLG = 0x80; // clear RTIF bit
PTB = segPat[seq+ix]; // send out digit segment pattern
PTP = digit[ix]; // turn on the display
ix++; // increment the index to digits of a sequence
if (ix == 4) // make sure the index to digits of a sequence is from 0 to 3
ix = 0; // “
count--;
if(count == 0){ // is time for the current sequence expired?
seq++; // change to a new sequence of digits
count = 400; // reset repetition count
}
if(seq == 10) // is this the last sequence?
seq = 0; // reset start index of a sequence
}
This project also contains the vectors.c file.
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20
extern void near rtiISR(void);

#pragma CODE_SEG __NEAR_SEG NON_BANKED
#pragma CODE_SEG DEFAULT // Change code section to DEFAULT.
typedef void (*near tIsrFunc)(void);

const tIsrFunc _vect[] @0xFFF0 = {
rtiISR
};
Example 6.6 Modify the C program in Example 6.5 so that it can be compiled using the
ICC12 C compiler and run in a demo board programmed with the D-Bug12 monitor.
Solution:
#include "c:\cwHCS12\include\hcs12.h"
#include "c:\cwHCS12\include\SetClk.h"
void rtiISR(void);
int seq,ix,count;
char segPat[13] = {0x06,0x5B,0x4F,0x66,0x6D,0x7D,0x07,0x7F,0x67,0x3F,0x06,0x5B,0x4F};
char digit[4] = {0xFE,0xFD,0xFB,0xF7};
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void main (void) {

asm("ldd #_rtiISR");// set up RTI interrupt vector by calling SetUserVector
asm("pshd"); // function using in-line assembly instructions
asm("ldd #56"); // “
asm("ldx $EEA4"); // “
asm("jsr 0,x"); // “
seq = 0;
ix = 0;
count = 400;
SetClk8();
RTICTL = 0x40; // RTI interrupt interval set to 2**10 OSCCLK cycles
DDRB = 0xFF; // configure Port B for output
DDRP = 0xFF; // configure Port P for output
CRGINT |= RTIE; // enable RTI interrupt
asm("CLI"); // enable interrupt globally
while(1);
}
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#pragma interrupt_handler rtiISR

void rtiISR(void) {
CRGFLG = 0x80; // clear RTIF bit
PTB = segPat[seq+ix]; // output the segment pattern
PTP = digit[ix]; // output digit select value
ix++; // increment digit index within a sequence
if (ix == 4)
ix = 0;
count--; // decrement repetition count
if(count == 0){ // if repetition count is 0, then change to the next sequence
seq++;
count = 400;
}
if(seq == 10) // Reach the last sequence?
seq = 0;
}
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The HCS12/MC9S12 Microcontroller