Compal Confidential: G400S/G500S UMA M/В Schematics Document

Compal Confidential
G400S/G500S UMA M/В Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
LA-9902P
2013-05-06
REV:1.0
C o m p a l S e c re t D ata C o m p a l E le c tro n ic s , In c.
Issued Date 2011/06/15 f D e c ip h e re d Date | 2012/07/11 Title
SCHEMATIC M/В LA-9902
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R |sOust.
n Document Number *ev
в
" 4019N1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
W ednesdav.Mav08.2013 ISheet 1 of 52
C __________________________ 1_______________________________ Ū___________________________ _ L _ E
Voltage Rails BOARD ID Table ~ -- — __ __
STATE
SIGNAL
-- ----- SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Board ID PCB Revision Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+5VS
0 1.0 SI (Power On Suspend,) LOW HIGH HIGH HIGH ON ON ON LOW
+3VS
1 0.3
2 0.2 S3 (S u s p e n d t o R A M ) LOW LOW HIGH HIGH ON ON OFF OFF
+ 1 . 5 VS
+ V 1 . 05S_VCCP
3 0.1 S4 (Suspend to D i s k ) LOW LOW LOW HIGH ON OFF OFF OFF
+V C C _C O R E
4
+V G A _C O R E
5 S5 ( S o f t OFF ) LOW LOW LOW LOW ON OFF OFF OFF
+VCC_G FXCO RE_AXG

6
+ 1 . 8VS
7
+ 0 .7 5 V S
Board !D table for AD channel
+ 1 . 0 5 VS
Vcc 3.3V
Ra 100K +/- 1%
B o a r d ID Rb Vu3 BID m -*-n V ad _b i d V a d _b i d max EC AD
0 0 0 V 0 V 0.300 V 0x00 - OxOB MP
i 12K +/- 1% 0.347 V 0.354 V 0.360 V OxOC - OxlC PVT
2 15K +/- 1% 0.423 V 0.430 V 0.438 V OxlD - 0x26 DVT
3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x27 - 0x30 EVT
X
BOM Structure Table
X USB Port Table
BTO Item BOM Structure
3 External
X X USB 2.0 Port 45 LEVEL 45@
USB Port
Connector МЕ0
Address 0 USB Port (Left Side)osB3.o
EC SM Busi address EC SM Bus2 address инею For VILG2 (14") 140
1 USB Port (Left SidepsB3 о
For VILG1 (15") 150
Device Device Address
2 Touch Screen HDMI HDMI0
UHCI1
Sm art B attery 0001 01IX b Therm al Sensor 1001 lOOxb
3 USB Camera Camera CMOS0
EHCIl
4
U S B 3 .0 UHCI2 LAN LDO Mode LDO0
5
PCH SW1 Bus address LAN Switch mode SWR0
6
UHCI3 10/100 LAN(AR8162L) 81620
Device Address
7
10/100 LAN(QCA8172) 81720
DDRDIMM0 1010 OOOXb 8
UHCI4 Green clock(DIS sku) GCLK3O40
DDRDIMM2 lOIOOIOXb 9 U SB /B (R ig h t Side U SB 2.0)
Green clock(UMA sku) GCLK2440
10 Mini Card(WLAN) Green elk support GCLK@
EHCI2 UHCI5
11 Card Reader
NV-GPU SM Bus address 12
No Green elk support NOGCLK6
UHCI6 Touch Screen SKU TS@
Device Address
13
Optimus SKU OPT0
Internal thermal sensor 1001 I l l X b (0x9E)
UMA SKU UMA0
PCH(NM70 sku) NM7O0
PCH(HM70 sku) HM7O0
PCH(HM76 sku) HM7 6@
V R A M (1000MHz) 1OOOM0
V R A M (900MHz) 900M@
SOURCE VGA
T h e rm a l Unpop @
ВАТТ KB9012 S O D IM M W LAN PCH
S ensor
S M B_EC _C K1
S M B J C .D A l
KB9012 X V X X X X X
+3VALW +3VALW
S M B_EC _C K2
V X X X X X
S M B_EC _D A2
KB9012
+3VALW f3VS VGA Js
SM BCLK
X X X X X
SM B DATA
PC H
+3VALW Js Js
S M L0C LK
S M L0D A TA
PC H X X X X X X X
+3VALW Compal Electronics, Inc.
S M L1C LK Deciphered Date
X X X X
SM L I DATA
PC H
+ 3 V A L W + 3 VS4 G A Js Ms THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN ■
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R Document Number
SCHEMATIC M/В LA-990:!
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019N1
Wednesday, May 08. 2013 [Sheet
5 4 3 2 1
PEG_ICOMPI and RCOMPO signals should be

shorted and routed
with - max length = 500 mils - typical
+V1.05S_VCCP impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
max length = 500 mils
1
R1
D - typical impedance = 14.5 mohms D
JCPU1A
2
J22 PEG_COMP
PEG_ICOMPI J21
PEG_ICOMPO
<16> DMI_CRX_PTX_N0 B27
DMI_RX#[0] PEG_RCOMPO
H22 PEG Static Lane Reversal - CFG2 is for the 16x
<16> DMI_CRX_PTX_N1 B25
A25 DMI_RX#[1]
<16> DMI_CRX_PTX_N2 DMI_RX#[2]
<16> DMI_CRX_PTX_N3 B24 K33 1: Normal Operation; Lane # definition matches
DMI_RX#[3] PEG_RX#[0] M35
PEG_RX#[1] CFG2 socket pin map definition
<16> DMI_CRX_PTX_P0 B28 L34
B26 DMI_RX[0] PEG_RX#[2] J35
<16> DMI_CRX_PTX_P1 DMI_RX[1] PEG_RX#[3]
*
<16> DMI_CRX_PTX_P2 A24 J32 0:Lane Reversed
DMI_RX[2] PEG_RX#[4]
DMI
<16> DMI_CRX_PTX_P3 B23 H34
DMI_RX[3] PEG_RX#[5] H31
G21 PEG_RX#[6] G33
<16> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7]
E22 G30
F21 F35
D21 E34
<16> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] E32
G22 PEG_RX#[11] D33
<16> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12]
D22 D31
F20 B33
PCI EXPRESS* - GRAPHICS

C21 C32
J33
PEG_RX[0] L35
PEG_RX[1] K34
A21 PEG_RX[2] H35
<16> FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
C H19 H32 C
E19 G34
F18 G31
Intel(R) FDI
B21 F33
C20 F30
D18 E35
E17 E33
<16> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] F32
PEG_RX[11] D34
A22 PEG_RX[12] E31
<16> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33
E20 B32
G18
<16> FDI_CTX_PRX_P3 FDI0_TX[3]
B20 M29
<16> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32
D19 M31
F17 L32
<16> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] L29
J18 PEG_TX#[4] K31
+V1.05S_VCCP <16> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
<16> FDI_FSYNC1 J17 K28
FDI1_FSYNC PEG_TX#[6] J30
H20 PEG_TX#[7] J28
<16> FDI_INT FDI_INT PEG_TX#[8] H29
PEG_TX#[9]
1
<16> FDI_LSYNC0 J19 G27

R7 H17 FDI0_LSYNC PEG_TX#[10] E29
<16> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
24.9_0402_1% F27
PEG_TX#[12] D28
PEG_TX#[13] F26
PEG_TX#[14]
2
E25
EDP_COMP A18 PEG_TX#[15]
B eDP_COMPIO B
eDP_COMPIO and ICOMPO signals A17
eDP_ICOMPO PEG_TX[0]
M28
eDP_HPD B16 M33
should be shorted near balls eDP_HPD# PEG_TX[1] M30
PEG_TX[2]
and routed with typical PEG_TX[3]
L31
C15 L28
impedance <25 mohms D15 eDP_AUX PEG_TX[4] K30
eDP_AUX# PEG_TX[5] K27
PEG_TX[6]
eDP
J29
C17 PEG_TX[7] J27
F16 eDP_TX[0] PEG_TX[8] H28
C16 eDP_TX[1] PEG_TX[9] G28
G15 eDP_TX[2] PEG_TX[10] E28
eDP_TX[3] PEG_TX[11] F28
C18 PEG_TX[12] D27
E16 eDP_TX#[0] PEG_TX[13] E26
D16 eDP_TX#[1] PEG_TX[14] D25
F15 eDP_TX#[2] PEG_TX[15]
eDP_TX#[3]
TYCO_2013620-2_IVY BRIDGE
ME@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC M/B LA-9902
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
4019N1 B
Date: Wednesday, May 08, 2013 Sheet 5 of 52

5 4 3 2 1
5 4 3 2 1
JCPU1B
D D
A28
BCLK CLK_CPU_DMI <15>
C26 A27
<19> H_SNB_IVB# CLK_CPU_DMI# <15>
MISC
CLOCKS
PROC_SELECT# BCLK#
AN34
SKTOCC# A16 2 R12 1 1K_0402_5%
+V1.05S_VCCP DPLL_REF_CLK A15 2 R13 1 1K_0402_5%
DPLL_REF_CLK# +V1.05S_VCCP
T48 H_CATERR# AL33

CATERR#
R9 1
62_0402_5%
THERMAL
AN33 R8 H_DRAMRST#
<32> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
2
R15 +V1.05S_VCCP
DDR3
MISC
56_0402_5%
<32,37,44> H_PROCHOT# H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 2 R16 1 140_0402_1%
PROCHOT# SM_RCOMP[0] A5 SM_RCOMP1 2 R17 1 25.5_0402_1%
SM_RCOMP[1] A4 SM_RCOMP2 2 R18 1 200_0402_1%
SM_RCOMP[2]
<19> H_THRMTRIP#
AN32
THERMTRIP# DDR3 Compensation Signals
RP13
XDP_TRST# 8 1
AP29 XDP_PRDY# XDP_TDI 7 2
PRDY# T18 PAD
AP27 XDP_PREQ# XDP_TMS 6 3
PREQ# T19 PAD
XDP_TCK 5 4
AR26 XDP_TCK
C TCK AR27 XDP_TMS 51_0804_8P4R_5% C
TMS
PWR MANAGEMENT
AM34
JTAG & BPM

AP30 XDP_TRST# @
<16> H_PM_SYNC PM_SYNC TRST#
AR28 XDP_TDI
TDI AP26 XDP_TDO
TDO T20 PAD
<19> H_CPUPWRGD AP33
UNCOREPWRGOOD
2
R29 AL35 XDP_DBRESET# R28 2 1 1K_0402_5% +3VS

R27 1 2 PM_DRAM_PWRGD_R V8 DBR#
1 SM_DRAMPWROK
C549 10K_0402_5% 130_0402_5%
1
AT28 XDP_BPM#0
BPM#[0] T21 PAD
100P_0402_50V8J AR29 XDP_BPM#1 C45
2 BPM#[1] T22 PAD
1
AR30 XDP_BPM#2 0.047U_0402_16V7K

BPM#[2] T23 PAD
2
BUF_CPU_RST# AR33 AT30 XDP_BPM#3
RESET# BPM#[3] T24 PAD
AP32 XDP_BPM#4
BPM#[4] T25 PAD
AR31 XDP_BPM#5
BPM#[5] T26 PAD
ESD BPM#[6]
AT31 XDP_BPM#6
T27 PAD
BPM#[7]
AR32 XDP_BPM#7
T28 PAD ESD
3/20 Add (ESD request) +3VALW
ME@
+3VALW +3VS
Buffered reset to CPU
2 2
+1.5V_CPU_VDDQ
C852 C853 +3VS
B 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
1 1
1
R30
U1 200_0402_5% +V1.05S_VCCP
5
+3VS 1 R161 2 1
P
10K_0402_5% B 4 PM_SYS_PWRGD_BUF R32

2 O 75_0402_5%
<16> PM_DRAM_PWRGD A
G
5
74AHC1G09GW_TSSOP5 R34 U2
3
43_0402_1% 1 3V
P
BUF_CPU_RST# 1 2 BUFO_CPU_RST# 4 NC
Y 2 PCH_PLTRST#
A PCH_PLTRST# <18>
G
SN74LVC1G07DCKR_SC70-5
A A

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
4019N1 B

5 4 3 2 1
5 4 3 2 1
JCPU1C JCPU1D
<13> DDR_B_D[0..63]
AB6 AE2
<12> DDR_A_D[0..63] SA_CLK[0] M_CLK_DDR0 <12> SB_CLK[0] M_CLK_DDR2 <13>
AA6 AD2
SA_CLK#[0] M_CLK_DDR#0 <12> SB_CLK#[0] M_CLK_DDR#2 <13>
DDR_A_D0 C5 V9 DDR_B_D0 C9 R9
SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <12> SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 D3 SA_DQ[1] DDR_B_D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
DDR_A_D4 D6 SA_DQ[3] AA5 DDR_B_D4 A9 SB_DQ[3] AE1
SA_DQ[4] SA_CLK[1] M_CLK_DDR1 <12> SB_DQ[4] SB_CLK[1] M_CLK_DDR3 <13>
DDR_A_D5 C6 AB5 DDR_B_D5 A8 AD1
SA_DQ[5] SA_CLK#[1] M_CLK_DDR#1 <12> SB_DQ[5] SB_CLK#[1] M_CLK_DDR#3 <13>
DDR_A_D6 C2 V10 DDR_B_D6 D9 R10
SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB <13>
D DDR_A_D7 C3 DDR_B_D7 D8 D
DDR_A_D8 F10 SA_DQ[7] DDR_B_D8 G4 SB_DQ[7]
DDR_A_D9 F8 SA_DQ[8] DDR_B_D9 F4 SB_DQ[8]
DDR_A_D10 G10 SA_DQ[9] AB4 DDR_B_D10 F1 SB_DQ[9] AB2
DDR_A_D11 G9 SA_DQ[10] RSVD_TP[1] AA4 DDR_B_D11 G1 SB_DQ[10] RSVD_TP[11] AA2
DDR_A_D12 F9 SA_DQ[11] RSVD_TP[2] W9 DDR_B_D12 G5 SB_DQ[11] RSVD_TP[12] T9
DDR_A_D13 F7 SA_DQ[12] RSVD_TP[3] DDR_B_D13 F5 SB_DQ[12] RSVD_TP[13]
DDR_A_D14 G8 SA_DQ[13] DDR_B_D14 F2 SB_DQ[13]
DDR_A_D15 G7 SA_DQ[14] DDR_B_D15 G2 SB_DQ[14]
DDR_A_D16 K4 SA_DQ[15] AB3 DDR_B_D16 J7 SB_DQ[15] AA1
DDR_A_D17 K5 SA_DQ[16] RSVD_TP[4] AA3 DDR_B_D17 J8 SB_DQ[16] RSVD_TP[14] AB1
DDR_A_D18 K1 SA_DQ[17] RSVD_TP[5] W10 DDR_B_D18 K10 SB_DQ[17] RSVD_TP[15] T10
DDR_A_D19 J1 SA_DQ[18] RSVD_TP[6] DDR_B_D19 K9 SB_DQ[18] RSVD_TP[16]
DDR_A_D20 J5 SA_DQ[19] DDR_B_D20 J9 SB_DQ[19]
DDR_A_D21 J4 SA_DQ[20] DDR_B_D21 J10 SB_DQ[20]
DDR_A_D22 J2 SA_DQ[21] AK3 DDR_B_D22 K8 SB_DQ[21] AD3
SA_DQ[22] SA_CS#[0] DDR_CS0_DIMMA# <12> SB_DQ[22] SB_CS#[0] DDR_CS2_DIMMB# <13>
DDR_A_D23 K2 AL3 DDR_B_D23 K7 AE3
SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# <12> SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# <13>
DDR_A_D24 M8 AG1 DDR_B_D24 M5 AD6
DDR_A_D25 N10 SA_DQ[24] RSVD_TP[7] AH1 DDR_B_D25 N4 SB_DQ[24] RSVD_TP[17] AE6
DDR_A_D26 N8 SA_DQ[25] RSVD_TP[8] DDR_B_D26 N2 SB_DQ[25] RSVD_TP[18]
DDR_A_D27 N7 SA_DQ[26] DDR_B_D27 N1 SB_DQ[26]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D28 M4 SB_DQ[27]
DDR_A_D29 M9 SA_DQ[28] AH3 DDR_B_D29 N5 SB_DQ[28] AE4
SA_DQ[29] SA_ODT[0] M_ODT0 <12> SB_DQ[29] SB_ODT[0] M_ODT2 <13>
DDR_A_D30 N9 AG3 DDR_B_D30 M2 AD4
M_ODT1 <12> M_ODT3 <13>
DDR SYSTEM MEMORY B

DDR_A_D31 M7 SA_DQ[30] SA_ODT[1] AG2 DDR_B_D31 M1 SB_DQ[30] SB_ODT[1] AD5
DDR SYSTEM MEMORY A

DDR_A_D32 AG6 SA_DQ[31] RSVD_TP[9] AH2 DDR_B_D32 AM5 SB_DQ[31] RSVD_TP[19] AE5
DDR_A_D33 AG5 SA_DQ[32] RSVD_TP[10] DDR_B_D33 AM6 SB_DQ[32] RSVD_TP[20]
DDR_A_D34 AK6 SA_DQ[33] DDR_B_D34 AR3 SB_DQ[33]
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D35 AP3 SB_DQ[34]
DDR_A_D36 AH5 SA_DQ[35] DDR_B_D36 AN3 SB_DQ[35]
SA_DQ[36] DDR_A_DQS#[0..7] <12> SB_DQ[36] DDR_B_DQS#[0..7] <13>
DDR_A_D37 AH6 C4 DDR_A_DQS#0 DDR_B_D37 AN2 D7 DDR_B_DQS#0
DDR_A_D38 AJ5 SA_DQ[37] SA_DQS#[0] G6 DDR_A_DQS#1 DDR_B_D38 AN1 SB_DQ[37] SB_DQS#[0] F3 DDR_B_DQS#1
C DDR_A_D39 AJ6 SA_DQ[38] SA_DQS#[1] J3 DDR_A_DQS#2 DDR_B_D39 AP2 SB_DQ[38] SB_DQS#[1] K6 DDR_B_DQS#2 C
DDR_A_D40 AJ8 SA_DQ[39] SA_DQS#[2] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[39] SB_DQS#[2] N3 DDR_B_DQS#3
DDR_A_D41 AK8 SA_DQ[40] SA_DQS#[3] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[40] SB_DQS#[3] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 DDR_A_DQS#5 DDR_B_D42 AT5 SB_DQ[41] SB_DQS#[4] AP9 DDR_B_DQS#5
DDR_A_D43 AK9 SA_DQ[42] SA_DQS#[5] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[42] SB_DQS#[5] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 SA_DQ[43] SA_DQS#[6] AM15 DDR_A_DQS#7 DDR_B_D44 AP6 SB_DQ[43] SB_DQS#[6] AP15 DDR_B_DQS#7
DDR_A_D45 AH9 SA_DQ[44] SA_DQS#[7] DDR_B_D45 AN8 SB_DQ[44] SB_DQS#[7]
DDR_A_D46 AL9 SA_DQ[45] DDR_B_D46 AR6 SB_DQ[45]
DDR_A_D48 AP11 SA_DQ[47] DDR_B_D48 AR9 SB_DQ[47]
SA_DQ[48] DDR_A_DQS[0..7] <12> SB_DQ[48] DDR_B_DQS[0..7] <13>
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D50 AL12 SA_DQ[49] SA_DQS[0] F6 DDR_A_DQS1 DDR_B_D50 AT8 SB_DQ[49] SB_DQS[0] G3 DDR_B_DQS1
DDR_A_D51 AM12 SA_DQ[50] SA_DQS[1] K3 DDR_A_DQS2 DDR_B_D51 AT9 SB_DQ[50] SB_DQS[1] J6 DDR_B_DQS2
DDR_A_D52 AM11 SA_DQ[51] SA_DQS[2] N6 DDR_A_DQS3 DDR_B_D52 AH11 SB_DQ[51] SB_DQS[2] M3 DDR_B_DQS3
DDR_A_D53 AL11 SA_DQ[52] SA_DQS[3] AL5 DDR_A_DQS4 DDR_B_D53 AR8 SB_DQ[52] SB_DQS[3] AN6 DDR_B_DQS4
DDR_A_D54 AP12 SA_DQ[53] SA_DQS[4] AM9 DDR_A_DQS5 DDR_B_D54 AJ12 SB_DQ[53] SB_DQS[4] AP8 DDR_B_DQS5
DDR_A_D55 AN12 SA_DQ[54] SA_DQS[5] AR11 DDR_A_DQS6 DDR_B_D55 AH12 SB_DQ[54] SB_DQS[5] AK11 DDR_B_DQS6
DDR_A_D56 AJ14 SA_DQ[55] SA_DQS[6] AM14 DDR_A_DQS7 DDR_B_D56 AT11 SB_DQ[55] SB_DQS[6] AP14 DDR_B_DQS7
DDR_A_D57 AH14 SA_DQ[56] SA_DQS[7] DDR_B_D57 AN14 SB_DQ[56] SB_DQS[7]
DDR_A_D59 AK15 SA_DQ[58] DDR_B_D59 AT14 SB_DQ[58]
DDR_A_D60 AL14 SA_DQ[59] DDR_B_D60 AT12 SB_DQ[59]
SA_DQ[60] DDR_A_MA[0..15] <12> SB_DQ[60] DDR_B_MA[0..15] <13>
DDR_A_D61 AK14 AD10 DDR_A_MA0 DDR_B_D61 AN15 AA8 DDR_B_MA0
DDR_A_D62 AJ15 SA_DQ[61] SA_MA[0] W1 DDR_A_MA1 DDR_B_D62 AR15 SB_DQ[61] SB_MA[0] T7 DDR_B_MA1
DDR_A_D63 AH15 SA_DQ[62] SA_MA[1] W2 DDR_A_MA2 DDR_B_D63 AT15 SB_DQ[62] SB_MA[1] R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] W7 DDR_A_MA3 SB_DQ[63] SB_MA[2] T6 DDR_B_MA3
SA_MA[3] V3 DDR_A_MA4 SB_MA[3] T2 DDR_B_MA4
SA_MA[4] V2 DDR_A_MA5 SB_MA[4] T4 DDR_B_MA5
SA_MA[5] W3 DDR_A_MA6 SB_MA[5] T3 DDR_B_MA6
AE10 SA_MA[6] W6 DDR_A_MA7 AA9 SB_MA[6] R2 DDR_B_MA7
<12> DDR_A_BS0 SA_BS[0] SA_MA[7] <13> DDR_B_BS0 SB_BS[0] SB_MA[7]
AF10 V1 DDR_A_MA8 AA7 T5 DDR_B_MA8
V6 W5 DDR_A_MA9 R6 R3 DDR_B_MA9
B AD8 DDR_A_MA10 AB7 DDR_B_MA10 B
SA_MA[10] V4 DDR_A_MA11 SB_MA[10] R1 DDR_B_MA11
SA_MA[11] W4 DDR_A_MA12 SB_MA[11] T1 DDR_B_MA12
AE8 SA_MA[12] AF8 DDR_A_MA13 AA10 SB_MA[12] AB10 DDR_B_MA13
<12> DDR_A_CAS# SA_CAS# SA_MA[13] <13> DDR_B_CAS# SB_CAS# SB_MA[13]
AD9 V5 DDR_A_MA14 AB8 R5 DDR_B_MA14
<12> DDR_A_RAS# SA_RAS# SA_MA[14] <13> DDR_B_RAS# SB_RAS# SB_MA[14]
AF9 V7 DDR_A_MA15 AB9 R4 DDR_B_MA15
<12> DDR_A_WE# SA_WE# SA_MA[15] <13> DDR_B_WE# SB_WE# SB_MA[15]
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

ME@
+1.5V
ME@
1
R37
1K_0402_5%
R38
1K_0402_5%
2
H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2
S
<6> H_DRAMRST# DDR3_DRAMRST# <12,13>

2
Q2
R39 LBSS138LT1G_SOT-23-3
G
2
4.99K_0402_1%
1
A
<10,15> DRAMRST_CNTRL_PCH R48 1 @ 2 DRAMRST_CNTRL_PCH_R A
0_0402_5%
1
Compal Electronics, Inc.
@
C35 Security Classification Compal Secret Data
2
0.047U 16V K X7R 0402
Eiffel used 0.01u THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Module design used 0.047u AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
4019N1 B
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor
D D
Interl request AH26 short GND

JCPU1E check on EVT phase PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane # definition matches

AH27 PAD T13 CFG2
AK28 VCC_DIE_SENSE AH26 socket pin map definition
AK29 CFG[0] VSS_DIE_SENSE
CFG[1]
*
AL26 0:Lane Reversed
AL27 CFG[2]
CFG4 AK26 CFG[3] L7
AL29 CFG[4] RSVD28 AG7 CFG4
AL30 CFG[5] RSVD29 AE7
CFG[6] RSVD30
1
AM31 AK2
AM32 CFG[7] RSVD31
AM30 CFG[8] W8 @ R42
CFG
AM28 CFG[9] RSVD32 1K_0402_1%
AM26 CFG[10]
CFG[11]
2
AN28 AT26
AN31 CFG[12] RSVD33 AM33
AN26 CFG[13] RSVD34 AJ27
AM27 CFG[14] RSVD35
AK31 CFG[15]
AN29 CFG[16]
CFG[17]
Display Port Presence Strap
T8
RSVD37
*
C J16 1 : Disabled; No Physical Display Port C
VCC_AXG_VAL_SENSE AJ31 RSVD38 H16
T14 PAD VAXG_VAL_SENSE RSVD39 CFG4 attached to Embedded Display Port
VSS_AXG_VAL_SENSE AH31 G16
T15 PAD VSSAXG_VAL_SENSE RSVD40
VCC_VAL_SENSE AJ33
T16 PAD VCC_VAL_SENSE
VSS_VAL_SENSE AH33 0 : Enabled; An external Display Port device is
T17 PAD VSS_VAL_SENSE
connected to the Embedded Display Port
Need PWR add new circuit on 1.05V(refer CRB) AJ26 AR35
RSVD5 RSVD_NCTF1 AT34
RSVD_NCTF2
RESERVED
AT33
RSVD_NCTF3 AP35
RSVD_NCTF4 AR34
RSVD_NCTF5
F25
F24 RSVD8
F23 RSVD9
D24 RSVD10 B34
G25 RSVD11 RSVD_NCTF6 A33
G24 RSVD12 RSVD_NCTF7 A34
E23 RSVD13 RSVD_NCTF8 B35
D23 RSVD14 RSVD_NCTF9 C35
C30 RSVD15 RSVD_NCTF10
A31 RSVD16
B30 RSVD17
B29 RSVD18
D30 RSVD19 AJ32
RSVD20 RSVD51
B31
RSVD21 RSVD52
AK32 PCIE Port Bifurcation Straps
A30
C29 RSVD22
RSVD23
11: (Default) x16 - Device 1 functions 1 and 2 disabled
AN35
BCLK_ITP
*
B J20 AM35 CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2 B
B18 RSVD24 BCLK_ITP#
RSVD25 disabled
01: Reserved - (Device 1 function 1 disabled ; function
J15 AT2 2 enabled)
RSVD27 RSVD_NCTF11 AT1
RSVD_NCTF12 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AR1
RSVD_NCTF13
B1
KEY
ME@
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB

CFG7 de assertion
A
0: PEG Wait for BIOS for training A

4019N1 B

5 4 3 2 1
5 4 3 2 1
JCPU1F POWER +V1.05S_VCCP

+VCC_CORE
QC=94A 8.5A
DC=53A
AG35
AG34 VCC1 AH13
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10
D AG31 VCC4 VCCIO3 AC10 D
AG30 VCC5 VCCIO4 Y10
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
AF32 VCC13 VCCIO12 H14
AF29 VCC16 VCCIO15 G14
PEG AND DDR

AF26 VCC19 VCCIO18 F14
AD35 VCC20 VCCIO19 F13
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
AD29 VCC26 E11
AD28 VCC27 VCCIO25 D14
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14
AC30 VCC35 VCCIO33 B14
C AC29 VCC36 VCCIO34 B12 C
AC28 VCC37 VCCIO35 A14
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
AA33 VCC42 J23
AA32 VCC43 VCCIO40
AA31 VCC44 +V1.05S_VCCP
AA30 VCC45
AA29 VCC46
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50
CORE SUPPLY
Y34 VCC51
Y33 VCC52
Y32 VCC53
VCC54
1
Y31
Y30 VCC55 R46
Y29 VCC56
VCC57 75_0402_5%
Y28
VCC58
Y27
VCC59 VR_SVID_CLK series-resistors close to VR
2
Y26
V35 VCC60
V34 VCC61 AJ29 H_CPU_SVIDALRT# 1 R47 2 43_0402_5%
SVID
VCC62 VIDALERT# VR_SVID_ALRT# <44>

V33 AJ30
VCC63 VIDSCLK VR_SVID_CLK <44>
V32 AJ28
VCC64 VIDSOUT VR_SVID_DAT <44>
V31
V30 VCC65
V29 VCC66 R50 2 1 130_0402_5%
VCC67 +V1.05S_VCCP 0.1uF on power side
V28
B V27 VCC68 B
V26 VCC69
U35 VCC70
U34 VCC71
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
VCC76
U29
U28 VCC77 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
U27 VCC78
U26 VCC79
R35 VCC80 +VCC_CORE
R34 VCC81
R33 VCC82
VCC83
1
R32
R31
R30
VCC84
VCC85
Trace Impedance =27-33 ohm R51
R29
R28
VCC86
VCC87
Trace Length Matc < 25 mils 100_0402_1%
SENSE LINES
VCC88
2
R27 AJ35
VCC89 VCC_SENSE VCCSENSE <44>
R26 AJ34
VCC90 VSS_SENSE VSSSENSE <44>
P35
P34 VCC91
VCC92
1
P33
P32 VCC93 B10 R54
VCC94 VCCIO_SENSE VCCIO_SENSE <43>
P31 A10 VSSIO_SENSE_L 1 R74 2 100_0402_1%
P30 VCC95 VSS_SENSE_VCCIO 10_0402_1%
P29 VCC96
VCC97
2
P28 R74 & R79 put together
P27 VCC98 +V1.05S_VCCP
P26 VCC99 R79
A VCC100 2 1 A
VSSIO_SENSE_L <43>
10_0402_1%
VSS_SENCE 100ohm +-1% pull-down to GND near processor
TYCO_2013620-2_IVY BRIDGE Security Classification Compal Secret Data

ME@
4019N1 B

5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V_CPU_VDDQ
Q6
D
1
LBSS138LT1G_SOT-23-3
2
+VREF_DQ_DIMMA G DRAMRST_CNTRL_PCH <15,7>
+VREF_DQ_DIMMB S
3
+V_DDR_REFA_R
+V_DDR_REFB_R
U3
DMN3030LSS-13_SOP8L-8
+VSB 8 1 AP4800 D
1
7 2
D 6 3 Id=9.6A DRAMRST_CNTRL_PCH 2 D
1
5 G
R56 S
3
82K_0402_5% Q9
4
LBSS138LT1G_SOT-23-3
2
R885 R02 M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
RUN_ON_CPU1.5VS3 1 2
15K_0402_1% 1
D +VCC_GFXCORE_AXG
1
2 Q4 C97
<36> SUSP G 2N7002_SOT23 0.047U_0603_25V7K
2
1
S
3
R616
10_0402_1%
POWER
2
VCC_AXG_SENSE <44>
+VCC_GFXCORE_AXG JCPU1G
AT24 AK35
SENSE
LINES
AT23 VAXG1 VAXG_SENSE AK34 +1.5V_CPU_VDDQ
VAXG2 VSSAXG_SENSE VSS_AXG_SENSE <44>
AT21
VAXG3
1
AT20
AT18 VAXG4 R626
VAXG5
1
AT17 10_0402_1%
AR24 VAXG6
AR23 VAXG7
VAXG8 +V_SM_VREF should R67
2
AR21 1K_0402_1%
AR20 VAXG9
VAXG10
have 20 mil trace width
2
AR18 AL1 +V_SM_VREF_CNT
C
AR17 VAXG11 SM_VREF C
VAXG12
1
AP24 1
VREF
AP23 VAXG13
AP21 VAXG14 C98 R78
AP20 VAXG15 B4 +V_DDR_REFA_R 0.1U_0402_10V6K 1K_0402_1%
AP18 VAXG16 SA_DIMM_VREFDQ D1 +V_DDR_REFB_R 2
VAXG17 SB_DIMM_VREFDQ
2
AP17
AN24 VAXG18
AN23 VAXG19
AN21 VAXG20
AN20 VAXG21 +1.5V_CPU_VDDQ
AN18 VAXG22
DDR3 -1.5V RAILS

AN17 VAXG23
AM24 VAXG24 AF7
GRAPHICS
AM23 VAXG25 VDDQ1 AF4
AM21 VAXG26 VDDQ2 AF1
VAXG27 VDDQ3 1 1
AM20 AC7 1 1 1 1
AM18 VAXG28 VDDQ4 AC4 + C127 + C123
10U_0603_6.3V6M
C117
10U_0603_6.3V6M
C119
10U_0603_6.3V6M
C120
10U_0603_6.3V6M
C122
AM17 VAXG29 VDDQ5 AC1 330U_2.5V_M 330U_D2_2V_Y
AL24 VAXG30 VDDQ6 Y7 @
VAXG31 VDDQ7 2 2 2 2 @ 2 2
AL23 Y4
AL21 VAXG32 VDDQ8 Y1
VAXG33 VDDQ9 1/16 Change symbol & value from
AL20 U7
AL18 VAXG34 VDDQ10 U4
SF000002Z00 to SGA20331E10
AL17 VAXG35 VDDQ11 U1
AK24 VAXG36 VDDQ12 P7
AK23 VAXG37 VDDQ13 P4
VAXG38 VDDQ14 1/25 Follow FM-James's comments(Co-lay with C123)
AK21 P1
AK20 VAXG39 VDDQ15
AK18 VAXG40
AK17 VAXG41
AJ24 VAXG42
AJ23 VAXG43
AJ21 VAXG44
AJ20 VAXG45 +VCCSA
B B
AJ18 VAXG46
AJ17 VAXG47 M27 +VCCSA
AH24 VAXG48 VCCSA1 M26
SA RAIL
VAXG49 VCCSA2 1 1 1 1
AH23 L26
10U_0603_6.3V6M
C124
10U_0603_6.3V6M
C125
10U_0603_6.3V6M
C126
AH21 VAXG50 VCCSA3 J26 + C128 @
AH20 VAXG51 VCCSA4 J25 330U_D2_2.5VY_R9M
AH18 VAXG52 VCCSA5 J24 2 2 2
AH17 VAXG53 VCCSA6 H26 2
VAXG54 VCCSA7 H25
VCCSA8
1.8V RAIL
H23
VCCSA_SENSE +VCCSA_SENSE <42>
+1.8VS
R69 0_0805_5% 1.5A
1 2 +1.8VS_VCCPLL B6
A6 VCCPLL1 C22
MISC
VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <42>

@ A2 C24
10U_0603_6.3V6M
C130
1U_0402_6.3V6K
C132
1 1 VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 <42>
2 2 A19
VCCIO_SEL
ME@
A IVY Bridge drives VCCIO_SEL low A
VCCP_PWRCTRL:0
Sandy Bridge is NC for A19
VCCP_PWRCTRL:1
Security Classification Compal Secret Data

Custom
4019N1 B

5 4 3 2 1
5 4 3 2 1
JCPU1H JCPU1I
AT35 AJ22
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30
D D
AT7 VSS10 VSS90 AH35 T27 VSS168 VSS241 E13
AT4 VSS11 VSS91 AH34 T26 VSS169 VSS242 E10
AT3 VSS12 VSS92 AH32 P9 VSS170 VSS243 E9
AR25 VSS13 VSS93 AH30 P8 VSS171 VSS244 E8
AR10 VSS18 VSS99 AH19 N35 VSS176 VSS249 E3
AR2 VSS21 VSS102 AH4 N32 VSS179 VSS252 D35
AP34 VSS22 VSS103 AG9 N31 VSS180 VSS253 D32
AP25 VSS25 VSS106 AF6 N28 VSS183 VSS256 D20
AP22 VSS26 VSS107 AF5 N27 VSS184 VSS257 D17
AP19 VSS27 VSS108 AF3 N26 VSS185 VSS258 C34
AP16 VSS28 VSS109 AF2 M34 VSS186 VSS259 C31
AP13 VSS29 VSS110 AE35 L33 VSS187 VSS260 C28
C
AN30 VSS34 VSS115 AE30 L6 VSS192 VSS265 C1 C
AN27 VSS35 VSS116 AE29 L5 VSS193 VSS266 B22
VSS VSS
AN13 VSS40 VSS121 AD7 K35 VSS198 VSS271 B11
AN10 VSS41 VSS122 AC9 K32 VSS199 VSS272 B9
AM29 VSS44 VSS125 AC5 J34 VSS202 VSS275 B5
AM25 VSS45 VSS126 AC3 J31 VSS203 VSS276 B3
AM22 VSS46 VSS127 AC2 H33 VSS204 VSS277 B2
AM19 VSS47 VSS128 AB35 H30 VSS205 VSS278 A35
AM2 VSS54 VSS135 AB28 H10 VSS212 VSS285
AM1 VSS55 VSS136 AB27 H9 VSS213
AL34 VSS56 VSS137 AB26 H8 VSS214
AL31 VSS57 VSS138 Y9 H7 VSS215
B B
AL13 VSS63 VSS144 W35 H1 VSS221
AL10 VSS64 VSS145 W34 G35 VSS222
AK33 VSS68 VSS149 W30 G23 VSS226
AK22 VSS72 VSS153 W26 F34 VSS230
AK19 VSS73 VSS154 U9 F31 VSS231
AK16 VSS74 VSS155 U8 F29 VSS232
AK13 VSS75 VSS156 U6 VSS233
AK10 VSS76 VSS157 U5
AK7 VSS77 VSS158 U3
AK4 VSS78 VSS159 U2
AJ25 VSS79 VSS160
VSS80
A A
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE
ME@ ME@
Custom
4019N1 B

5 4 3 2 1
5 4 3 2 1
+VREF_DQ_DIMMA +1.5V +1.5V

3A@1. 5V
<7> DDR_A_D[0..63]
DDR3 SO-DIMM A <7> DDR_A_DQS[0..7]
JDIMM1
<7> DDR_A_DQS#[0..7]
+VREF_DQ_DIMMA 1 2
3 VREF_DQ VSS1 4 DDR_A_D4
VSS2 DQ4 <7> DDR_A_MA[0..15]
DDR_A_D0 5 6 DDR_A_D5
0.1U_0402_10V6K
DDR_A_D1 7 DQ0 DQ5 8
C133
1 DQ1 VSS3
9 10 DDR_A_DQS#0
11 VSS4 DQS#0 12 DDR_A_DQS0
13 DM0 DQS0 14
D 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6 +1.5V D
DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
19 DQ3 DQ7 20 RP15
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12 8 1
DQ8 DQ12 +VREF_DQ_DIMMA
DDR_A_D9 23 24 DDR_A_D13 7 2
25 DQ9 DQ13 26 6 3
VSS9 VSS10 +VREF_DQ_DIMMB
DDR_A_DQS#1 27 28 5 4
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <13,7>
31 32 1K_0804_8P4R_1%
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20 +1.5V
43 DQ17 DQ21 44 RP16
DDR_A_DQS#2 45 VSS15 VSS16 46 8 1
DQS#2 DM2 +VREF_CA
DDR_A_DQS2 47 48 7 2
49 DQS2 VSS17 50 DDR_A_D22 6 3
VSS18 DQ22 +VREF_CB
DDR_A_D18 51 52 DDR_A_D23 5 4
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28 1K_0804_8P4R_1%
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
65 DM3 DQS3 66
71 DQ27 DQ31 72
VSS25 VSS26
C
<7> DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA C
CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<7> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
A1 A0
<7> M_CLK_DDR0 M_CLK_DDR0
99
101 VDD9 VDD10
100
102 M_CLK_DDR1 OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
CK0 CK1 M_CLK_DDR1 <7>
<7> M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 <7>
DDR_A_MA10
105
107 VDD11 VDD12
106
108 DDR_A_BS1
Layout Note: (10uF_0603_6.3V)*8
<7> DDR_A_BS0 DDR_A_BS0 109 A10/AP BA1 110 DDR_A_RAS#
DDR_A_BS1 <7>
DDR_A_RAS# <7>
Place near DIMM
BA0 RAS#
<7> DDR_A_WE# DDR_A_WE#
111
113 VDD13 VDD14
112
114 DDR_CS0_DIMMA# (0.1uF_402_10V)*4
WE# S0# DDR_CS0_DIMMA# <7>
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <7>
117 118
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1
A13 ODT1 M_ODT1 <7> +VREF_CA
<7> DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
123 S1# NC2 124 +1.5V
125 VDD17 VDD18 126 +VREF_CA
127 NCTEST VREF_CA 128
0.1U_0402_10V6K
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37
C135
DQ33 DQ37 1 1
133 134
10U_0603_6.3V6M
C139
10U_0603_6.3V6M
C140
10U_0603_6.3V6M
C141
10U_0603_6.3V6M
C142
10U_0603_6.3V6M
C143
10U_0603_6.3V6M
C144
0.1U_0402_10V6K
C145
0.1U_0402_10V6K
C146
0.1U_0402_10V6K
C147
0.1U_0402_10V6K
C148
VSS29 VSS30 1 1 1 1 1 1 1 1 1 1
DDR_A_DQS#4 135 136 + C149 @
B DDR_A_DQS4 137 DQS#4 DM4 138 220U_6.3V_M B
DQS4 VSS31 2 @
139 140 DDR_A_D38
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 2 2 2 2 2 2 2 2 2 2 2
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
DM5 DQS5
155
VSS37 VSS38
156 VDDQ(1.5V) =
DDR_A_D42 157 158 DDR_A_D46
DQ42 DQ46
DDR_A_D43 159
DQ43 DQ47
160 DDR_A_D47 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
161 162
VSS39 VSS40
DDR_A_D48 163
DQ48 DQ52
164 DDR_A_D52 6*0603 10uf (PER CONNECTOR) Layout Note:
DDR_A_D49 165 166 DDR_A_D53
167 DQ49 DQ53 168 Place near DIMM
VSS41 VSS42
DDR_A_DQS#6 169
DQS#6 DM6
170 VTT(0.75V) =
DDR_A_DQS6 171 172
DQS6 VSS43
173
VSS44 DQ54
174 DDR_A_D54 3*0805 10uf 4*0402 1uf
DDR_A_D50 175 176 DDR_A_D55
DQ50 DQ55 +0.75VS
DDR_A_D51 177
DQ51 VSS45
178 VREF =
179 180 DDR_A_D60
VSS46 DQ60
DDR_A_D56 181
DQ56 DQ61
182 DDR_A_D61 1*0402 0.1uf 1*0402 2.2uf
DDR_A_D57 183 184
+3V_DIMM DQ57 VSS47
185
VSS48 DQS#7
186 DDR_A_DQS#7 VDDSPD (3.3V)=
187 188 DDR_A_DQS7
1U_0402_6.3V6K
C150
1U_0402_6.3V6K
C152
DM7 DQS7
189
VSS49 VSS50
190 1*0402 0.1uf 1*0402 2.2uf 1 1
DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196
197 VSS51 VSS52 198 2 2
R136 1 @ 2 0_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 <13,15,26>
A 201 202 SMB_CLK_S3 A
SA1 SCL SMB_CLK_S3 <13,15,26>
203 204
0.1U_0402_10V6K
1 VTT1 VTT2 +0.75VS

C156
205 206 0. 65A@0. 75V

G1 G2
2 LCN_DAN06-K4806-0103
ME@
Custom
4019N1 B

5 4 3 2 1
5 4 3 2 1
+VREF_DQ_DIMMB 3A@1. 5V
<7> DDR_B_D[0..63]
+1.5V +1.5V
<7> DDR_B_DQS[0..7]
JDIMM2
<7> DDR_B_DQS#[0..7]
+VREF_DQ_DIMMB 1 2
3 VREF_DQ VSS1 4 DDR_B_D4
VSS2 DQ4 <7> DDR_B_MA[0..15]
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 7 DQ0 DQ5 8
9 DQ1 VSS3 10 DDR_B_DQS#0
0.1U_0402_10V6K
11 VSS4 DQS#0 12 DDR_B_DQS0
1 DM0 DQS0
13 14
D DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6 D
C157
DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
2 19 DQ3 DQ7 20
DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <12,7>
31 32
37 DQ11 DQ15 38
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D25 59 DQ24 DQ29 60
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
71 DQ27 DQ31 72
VSS25 VSS26
C
<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB C
CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<7> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<7> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <7>
<7> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 <7>
DDR_B_MA10
105
107 VDD11 VDD12
106
108 DDR_B_BS1
Layout Note: (10uF_0603_6.3V)*8
<7> DDR_B_BS0 DDR_B_BS0 109 A10/AP BA1 110 DDR_B_RAS#
DDR_B_BS1 <7>
DDR_B_RAS# <7>
Place near DIMM
BA0 RAS#
<7> DDR_B_WE# DDR_B_WE#
111
113 VDD13 VDD14
112
114 DDR_CS2_DIMMB# (0.1uF_402_10V)*4
WE# S0# DDR_CS2_DIMMB# <7>
<7> DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2
CAS# ODT0 M_ODT2 <7>
117 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3
A13 ODT1 M_ODT3 <7> +VREF_CB
<7> DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
123 S1# NC2 124 +1.5V
125 VDD17 VDD18 126 +VREF_CB
127 NCTEST VREF_CA 128
0.1U_0402_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37
C159
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
DQ33 DQ37 1
133 134
C163
C164
C165
C166
C167
C168
C169
C170
C171
C172
VSS29 VSS30 1 1 1 1 1 1 1 1 1 1
DDR_B_DQS#4 135 136
B DDR_B_DQS4 137 DQS#4 DM4 138 B
DQS4 VSS31 2 @
139 140 DDR_B_D38
DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 2 2 2 2 2 2 2 2 2 2
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
DDR_B_D41 149 DQ40 DQ45 150
VSS36 DQS#5
153
DM5 DQS5
154 DDR_B_DQS5 VDDQ(1.5V) =
155 156
VSS37 VSS38
DDR_B_D42 157
DQ42 DQ46
158 DDR_B_D46 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DDR_B_D43 159 160 DDR_B_D47
DQ43 DQ47
161
VSS39 VSS40
162 6*0603 10uf (PER CONNECTOR) Layout Note:
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53 Place near DIMM
DQ49 DQ53
167
VSS41 VSS42
168 VTT(0.75V) =
DDR_B_DQS#6 169 170
DQS#6 DM6
DDR_B_DQS6 171
DQS6 VSS43
172 3*0805 10uf 4*0402 1uf
173 174 DDR_B_D54
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55 +0.75VS
DDR_B_D51 177 DQ50 DQ55 178
DQ51 VSS45
179
VSS46 DQ60
180 DDR_B_D60 1*0402 0.1uf 1*0402 2.2uf
DDR_B_D56 181 182 DDR_B_D61
DQ56 DQ61
DDR_B_D57 183
DQ57 VSS47
184 VDDSPD (3.3V)=
185 186 DDR_B_DQS#7
1U_0402_6.3V6K
C174
1U_0402_6.3V6K
C176
VSS48 DQS#7
187
DM7 DQS7
188 DDR_B_DQS7 1*0402 0.1uf 1*0402 2.2uf 1 1
189 190
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
195 DQ59 DQ63 196 2 2
197 VSS51 VSS52 198
199 SA0 EVENT# 200 SMB_DATA_S3
+3V_DIMM VDDSPD SDA SMB_DATA_S3 <12,15,26>
A 1 2 201 202 SMB_CLK_S3 A
+3VS SA1 SCL SMB_CLK_S3 <12,15,26>
R97 10K_0402_5% 203 204
0.1U_0402_10V6K
1 VTT1 VTT2 +0.75VS

0. 65A@0. 75V
C178
205 206
G1 G2
2 LCN_DAN06-K4406-0103
ME@
4019N1 B

5 4 3 2 1
5 4 3 2 1
PCH_RTCX1
W=20mils W=20mils 1 2 PCH_RTCX2

R98 10M_0402_5%
+RTCVCC +RTCBATT
NOGCLK@
Y1
R99 1 2
1K_0402_5% 32.768KHZ_12.5PF_CM31532768DZFT
1 2 1 1
C180 NOGCLK@ C181
1 12P_0402_50V8J 12P_0402_50V8J
C179 NOGCLK@ NOGCLK@
1U_0603_10V4Z 2 2
2
D D
R187 1 2 GCLK_32K
GCLK_32K <34>
0_0402_5%
@
CMOS U4A
+RTCVCC
SHORT PADS
CLRP2
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <32>
1
R101 1 2 1M_0402_5% SM_INTRUDER# A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 <32>
C183 PCH_RTCX2 C20 B37 LPC_AD2 EC and Mini card debug port
LPC
RTCX2 FWH2 / LAD2 LPC_AD2 <32>
R102 1 2 330K_0402_5% PCH_INTVRMEN 1U_0603_10V4Z C37 LPC_AD3
2 FWH3 / LAD3 LPC_AD3 <32>
2
1 2 PCH_RTCRST# D20
RTCRST#
INTVRMEN R103 20K_0402_5%
1 2 PCH_SRTCRST# G22 FWH4 / LFRAME#
D36 LPC_FRAME#
LPC_FRAME# <32>
SRTCRST#
* H：Integrated VRM enable R100 20K_0402_5% 1 LDRQ0#
E36
1
L：Integrated VRM disable SM_INTRUDER# K22 K36
SHORT PADS
CLRP3
RTC
C182 INTRUDER# LDRQ1# / GPIO23
(INTVRMEN should always be pull high.) 1U_0603_10V4Z PCH_INTVRMEN C17 V5 SERIRQ SERIRQ <32>
2 INTVRMEN SERIRQ
2
AM3 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 <30>
+3VS HDA_BIT_CLK N34 SATA0RXN AM1 SATA_DTX_C_IRX_P0
HDA_BCLK SATA0RXP SATA_DTX_C_IRX_P0 <30>
AP7 SATA_ITX_C_DRX_N0 HDD
SATA 6G
SATA0TXN SATA_ITX_C_DRX_N0 <30>
R105 1 @ 2 1K_0402_5% HDA_SPKR HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_P0 <30>
HDA_SYNC SATA0TXP
HIGH= Enable ( No Reboot ) HDA_SPKR T10 AM10
<31> HDA_SPKR SPKR SATA1RXN
* LOW= Disable (Default)
HDA_RST# K34
HDA_RST#
SATA1RXP
SATA1TXN
AM8
AP11
AP10
SATA1TXP
C +3V_PCH HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 C
<31> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 <30>
SATA2RXP
AD5 SATA_DTX_C_IRX_P2 SATA_DTX_C_IRX_P2 <30> ODD
R106 2 @ 1 1K_0402_5% ME_FLASH G34 AH5 SATA_ITX_C_DRX_N2
HDA_SDIN1 SATA2TXN SATA_ITX_C_DRX_N2 <30>
AH4 SATA_ITX_C_DRX_P2 SATA_ITX_C_DRX_P2 <30>
SATA2TXP
* Low = Disabled (Default) C34
HDA_SDIN2 AB8
IHDA
High = Enabled [Flash Descriptor Security Overide] A34 SATA3RXN AB10
HDA_SDIN3 SATA3RXP AF3
SATA3TXN AF1 11/30 Add(Share ROM)
SATA3TXP
+3V_PCH <32> ME_FLASH
A36
HDA_SDO Near U5
Y7 RP27
SATA
SATA4RXN Y5 EC_SPI_SO 8 1 SPI_SO_L
SATA4RXP <32> EC_SPI_SO
R108 2 1 1K_0402_5% HDA_SYNC C36 AD3 <32> EC_SPI_SI EC_SPI_SI 7 2 SPI_SI_R
HDA_DOCK_EN# / GPIO33 SATA4TXN AD1 EC_SPI_CLK 6 3 SPI_CLK_PCH_0
SATA4TXP <32> EC_SPI_CLK
N32 <32> EC_SPI_CS# EC_SPI_CS# 5 4 SPI_SB_CS0#
This signal has a weak internal pull-down HDA_DOCK_RST# / GPIO13 Y3
SATA5RXN Y1 0_0804_8P4R_5%
On Die PLL VR is supplied by SATA5RXP
1.5V when smapled high(For mobile only) AB3 @
SATA5TXN
* 1.8V when sampled low(For Desktop only)
Needs to be pulled High for Chief River platfrom
T41 PAD
PCH_JTAG_TCK J3
JTAG_TCK SATA5TXP
AB1
+V1.05S_VCCP
PCH_JTAG_TMS H7 Y11 R111
T35 PAD JTAG_TMS SATAICOMPO 37.4_0402_1%
JTAG
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
+5VS T36 PAD JTAG_TDI SATAICOMPI
8M B SPI ROM FOR M E

PCH_JTAG_TDO H1
T37 PAD JTAG_TDO +V1.05S_VCCP
AB12 R113
SATA3RCOMPO
<31> HDA_BITCLK_AUDIO For EMI HDA_BIT_CLK @ 49.9_0402_1%
& Non- share ROM .

2
Q10 AB13 SATA3_COMP 1 2

G
RP12 LBSS138LT1G_SOT-23-3 SATA3COMPI

<31> HDA_SYNC_AUDIO 8 1 HDA_SYNC_R 3 1 HDA_SYNC
7 2 SPI_CLK_PCH_R T3 AH1 RBIAS_SATA3 1 2
S
6 3 SPI_CLK SATA3RBIAS R115

+3V_ROM
2
B 5 4 HDA_RST# SPI_SB_CS0# Y14 750_0402_1% B

<31> HDA_RST_AUDIO# SPI_CS0#
R878
33_0804_8P4R_5% 1M_0402_5% R175 SPI_SB_CS1# T1
ME_FLASH 1 2 SPI_CS1# P3 SATALED# U6
SPI
<31> HDA_SDOUT_AUDIO SATALED# SPI_SB_CS1# 1 8 0_0402_5%

CS# VCC
1
0_0402_5% SPI_SI V4 V14 SPI_SO_R 1 @ 2 SPI_SO1 2 7

SPI_HOLD#1 R198
SPI_MOSI SATA0GP / GPIO21 R188 0_0402_5% SPI_WP#1 3 SO HOLD# SPI_CLK_PCH_1 1
6 @ 2 SPI_CLK_PCH_R
SPI_SO_R U3 P1 BBS_BIT0_R 4 WP# SCLK 5
SPI_SI1 1 @ 2 SPI_SI
check with vender SPI_MISO SATA1GP / GPIO19
GPIO19 has internal Pull UP For EMI
GND SI R196
Del Q10 check with codec 64M W25Q64FVSSIQ SOIC 8P 0_0402_5%
VDDIO using 3VALW PANTHER-POINT_FCBGA989
+3V_ROM
@ For EMI
HM76@
U4 HM70@
SPI_CLK_PCH_R R266 1 2 SPI_WP#1
3.3K_0402_5%
U6 Rersver 4M+2M Solution
1
R221 1 2SPI_HOLD#1
R124 3.3K_0402_5% +3V_ROM
33_0402_5% SA00005MQ80 R127 1 2 SPI_WP#
@ S IC BD82HM70 SJTNV C1 BGA 989P PCH C38! 3.3K_0402_5%
2
R129 1 2SPI_HOLD#
3.3K_0402_5% U5
DPDG1.1 C190 For EMI SPI_SB_CS0# 1
CS# VCC
8 0_0402_5%
22P_0402_50V8J SPI_SO_R 1 @ 2 SPI_SO_L 2 7
SPI_HOLD# R135
@ R131 0_0402_5% SPI_WP# 3 SO HOLD# 6
SPI_CLK_PCH_0 1 @ 2 SPI_CLK_PCH_R
+3VS 4 WP# SCLK 5
SPI_SI_R 1 @ 2 SPI_SI
GND SI
RP17 For EMI R133
BBS_BIT0_R 8 1 64M W25Q64FVSSIQ SOIC 8P 0_0402_5%
R124;c190 close to U4.T3 pin SATALED# 7 2 For EMI
PCH_GPIO16 6 3
<19> PCH_GPIO16
A SERIRQ 5 4 A
10K_0804_8P4R_5%

4019N1 B

5 4 3 2 1
5 4 3 2 1
U4B
Q60A
2N7002DW-T/R7_SOT363-6
<27> PCIE_PRX_DTX_N1 PCIE_PRX_DTX_N1 BG34 6 1 SMB_CLK_S3
PERN1 SMB_CLK_S3 <12,13,26>
LAN <27> PCIE_PRX_DTX_P1 PCIE_PRX_DTX_P1 BJ34
PERP1 SMBALERT# / GPIO11
E12 PCH_GPIO11 R134 2 1 10K_0402_5% +3V_PCH
<27> PCIE_PTX_C_DRX_N1
<27> PCIE_PTX_C_DRX_P1
C192
C193
1
1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
AV32
AU32 PETN1
PETP1 SMBCLK
H14 PCH_SMBCLK DIMM1
DIMM2
2
+3VS
<26> PCIE_PRX_DTX_N2 PCIE_PRX_DTX_N2 BE34 C9 PCH_SMBDATA
PERN2 SMBDATA
MINI CARD
5
<26> PCIE_PRX_DTX_P2 PCIE_PRX_DTX_P2 BF34
PERP2
WLAN <26> PCIE_PTX_C_DRX_N2
C194 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2 BB32
PETN2
C195 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 AY32 3 4 SMB_DATA_S3
<26> PCIE_PTX_C_DRX_P2 PETP2 SMB_DATA_S3 <12,13,26>
A12 DRAMRST_CNTRL_PCH
SMBUS
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <10,7>
BG36 2N7002DW-T/R7_SOT363-6
BJ36 PERN3 C8 PCH_SML0CLK
PERP3 SML0CLK Q60B
D AV34 2 R139 1 +3V_PCH
D
AU34 PETN3 G12 PCH_SML0DATA 1K_0402_5%
PETP3 SML0DATA Q61A
BF36 2 R140 1 10K_0402_5% 2N7002DW-T/R7_SOT363-6
PERN4 +3V_PCH
BE36 6 1 EC_SMB_CK2
PERP4 EC_SMB_CK2 <29,32>
AY34 C13 PCH_HOT#
PETN4 SML1ALERT# / PCHHOT# / GPIO74
BB34
PETP4
SML1CLK / GPIO58
E14 SML1CLK VGA
EC
2
BG37
PCI-E*
PERN5 +3VS
BH37 M16 SML1DATA
PERP5 SML1DATA / GPIO75
thermal sensor
5
AY36
BB36 PETN5
PETP5 3 4 EC_SMB_DA2
EC_SMB_DA2 <29,32>
BJ38
BG38 PERN6 2N7002DW-T/R7_SOT363-6
AU36 PERP6 M7
Controller
PETN6 CL_CLK1 Q61B
AV36 +3V_PCH
PETP6 +3V_PCH
BG40 T11
Link
PERN7 CL_DATA1
2
BJ40
AY40 PERP7
PETN7
2
BB40 P10 R143
PETP7 CL_RST1# R544 R545
10K_0402_5%
BE38 2.2K_0402_5% 2.2K_0402_5%
PERN8
1
BC38
AW38 PERP8
PETN8
1
AY38 PCH_SML0CLK
PETP8
M10 PCH_SML0DATA
R153 1 @ 2 0_0402_5% CLK_PCIE_LAN#_R Y40 PEG_A_CLKRQ# / GPIO47
<27> CLK_PCIE_LAN# CLKOUT_PCIE0N
LAN <27> CLK_PCIE_LAN
R154 1 @ 2 0_0402_5% CLK_PCIE_LAN_R Y39
CLKOUT_PCIE0P
For EMI CLKOUT_PEG_A_N
AB37
C J2 AB38 C
CLOCKS
<27> CLKREQ_LAN# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P
+3V_PCH R152 2 1 10K_0402_5%
+3V_PCH
R156 1 @ 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 AV22 CLK_CPU_DMI#
<26> CLK_PCIE_WLAN1# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# <6> +3VS
R165 1 @ 2 0_0402_5% CLK_PCIE_WLAN1_R AB47 AU22 CLK_CPU_DMI
<26> CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6>
WLAN For EMI RP23
<26> CLKREQ_WLAN# M1 SML1DATA 8 1
R158 2 1 10K_0402_5% PCIECLKRQ1# / GPIO18 AM12 EC_SMB_DA2 7 2
+3VS CLKOUT_DP_N AM13 SML1CLK 6 3
AA48 CLKOUT_DP_P EC_SMB_CK2 5 4
AA47 CLKOUT_PCIE2N RP8 10K_0804_8P4R_5%
CLKOUT_PCIE2P BF18 CLK_BUF_CPU_DMI# 1 8 2.2K_0804_8P4R_5%
V10 CLKIN_DMI_N BE18 CLK_BUF_CPU_DMI 2 7
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P 3 6 +3V_PCH
4 5
Y37 BJ30 CLKIN_DMI2# +3VS
Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30 CLKIN_DMI2 RP24
CLKOUT_PCIE3P CLKIN_GND1_P PCH_SMBCLK 8 1
A8 SMB_CLK_S3 7 2
PCIECLKRQ3# / GPIO25 G24 CLK_BUF_DREF_96M# R162 1 2 10K_0402_5% PCH_SMBDATA 6 3
CLKIN_DOT_96N E24 CLK_BUF_DREF_96M R163 1 2 10K_0402_5% SMB_DATA_S3 5 4
Y43 CLKIN_DOT_96P
Y45 CLKOUT_PCIE4N 2.2K_0804_8P4R_5%
CLKOUT_PCIE4P AK7 CLK_BUF_PCIE_SATA# R164 1 2 10K_0402_5%
L12 CLKIN_SATA_N AK5 CLK_BUF_PCIE_SATA R166 1 2 10K_0402_5%
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
V45 K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5%

V46 CLKOUT_PCIE5N REFCLK14IN
CLKOUT_PCIE5P
L14 H45 CLK_PCI_LPBACK
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <18>
B B
AB42 V47 XTAL25_IN 0_0402_5% 2 1 R796 GCLK_PCH_25MHZ
CLKOUT_PEG_B_N XTAL25_IN GCLK_PCH_25MHZ <34>
AB40 V49 XTAL25_OUT @
CLKOUT_PEG_B_P XTAL25_OUT
E6 R171 +V1.05S_VCCP
PEG_B_CLKRQ# / GPIO56
Y47 XCLK_RCOMP
90.9_0402_1%
1 2 For EMI
V40
V42 CLKOUT_PCIE6N
XCLK_RCOMP
B Phaes change to GCLK@
CLKOUT_PCIE6P XTAL25_IN
T13 NOGCLK@
PCIECLKRQ6# / GPIO45 27M_SSC XTAL25_OUT 1 2
V38 K43 R169 1M_0402_5%
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS
CLKOUT_PCIE7P F47 3 4
K12 CLKOUTFLEX1 / GPIO65 OSC NC
PCIECLKRQ7# / GPIO46 H47 2 1
AK14 CLKOUTFLEX2 / GPIO66 NC OSC
PCIE_CLK_8N AK13 CLKOUT_ITPXDP_N K49 PCH_GPIO67 Y2
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 PCH_GPIO67 <19>
PCIE_CLK_8P 1 25MHZ_10PF_7V25000014 1
BIOS Request SKU ID C196 NOGCLK@ C197
PANTHER-POINT_FCBGA989 12P_0402_50V8J 12P_0402_50V8J
NOGCLK@ NOGCLK@
2 2
HM76@
A A

4019N1 B

5 4 3 2 1
5 4 3 2 1
+RTCVCC
DSWODVREN R179 2 1 330K_0402_5%
D D
DSWODVREN - On Die DSW VR Enable
U4C * H：Enable
L：Disable
<5> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 <5>

U15 DMI_CTX_PRX_N1 BE20 DMI0RXN FDI_RXN0 AY14 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <5>
MC74VHC1G08DFT2G SC70 5P <5> DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 <5>
DMI2RXN FDI_RXN2
3
@ <5> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3 FDI_CTX_PRX_N3 <5>

1 DMI3RXN FDI_RXN3 BC12 FDI_CTX_PRX_N4
<32,44> VGATE FDI_CTX_PRX_N4 <5>
G
A 4 SYS_PWROK DMI_CTX_PRX_P0 BE24 FDI_RXN4 BJ12 FDI_CTX_PRX_N5

Y <5> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <5>
PCH_PWROK 2 <5> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 <5>
B DMI1RXP FDI_RXN6
P
2 <5> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 FDI_CTX_PRX_N7 <5>

DMI_CTX_PRX_P3 BJ20 DMI2RXP FDI_RXN7
<5> DMI_CTX_PRX_P3 DMI3RXP
5
C854 BG14 FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 <5>

0.1U_0402_16V4Z DMI_CRX_PTX_N0 AW24 FDI_RXP0 BB14 FDI_CTX_PRX_P1
1 <5> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <5>
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 <5>
<5> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2
+3VS DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 <5>
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 FDI_CTX_PRX_P4 <5>
3/20 Add (ESD request) BG12 FDI_CTX_PRX_P5
DMI
FDI
FDI_RXP5 FDI_CTX_PRX_P5 <5>
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 FDI_CTX_PRX_P6 <5>
<5> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 <5>
<5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7
DMI_CRX_PTX_P2 AY18
<5> DMI_CRX_PTX_P2 DMI2TXP
DMI_CRX_PTX_P3 AU18
<5> DMI_CRX_PTX_P3 DMI3TXP AW16 FDI_INT
FDI_INT FDI_INT <5>
+V1.05S_VCCP BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5>
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5>
R177 49.9_0402_1%
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
C DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5> C
R178 750_0402_1%
4mil width and place BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 <5>
within 500mil of the PCH
DSWVRMEN
A18 DSWODVREN Note:This signal must be always pulled-up to VccRTC.
SUSACK# is only used on platform
that support the Deep Sx state.
System Power Management

C12 E22 EC_RSMRST#
SUSACK# DPWROK
SYS_RST# K3 B9 PCIE_WAKE# <26>

<19> SYS_RST# SYS_RESET# WAKE#
R299 10K_0402_5%
SYS_PWROK P12 N3 PM_CLKRUN# 2 1
<32> SYS_PWROK SYS_PWROK CLKRUN# / GPIO32
<32> PCH_PWROK L22 G8 SUS_STAT#

PWROK SUS_STAT# / GPIO61 T38 PAD
PCH_PWROK L10 N14

APWROK SUSCLK / GPIO62 SUSCLK <32>
PM_DRAM_PWRGD B13 D10

<6> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <32>
C21 H4
<32> EC_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <32>
+3V_PCH
SUSWARN# K16 F4
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <32>
2 R192 1 300_0402_5% PM_DRAM_PWRGD
B
<32> PBTN_OUT# E20 G10 Can be left NC when IAMT is not support on the platfrom B
R194 2 1 10K_0402_5% SUSWARN# PWRBTN# SLP_A#
D29 1 2 AC_PRESENT_R H20 G16

<32,37,39> ACIN ACPRESENT / GPIO31 SLP_SUS#
CH751H-40PT_SOD323-2
R197 2 @ 1 10K_0402_5% EC_RSMRST# E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6>
RI# A10 K14 Can be left NC if no use integrated LAN.

RI# SLP_LAN# / GPIO29
PANTHER-POINT_FCBGA989
HM76@
+3V_PCH
R309 1 2 200K_0402_5% AC_PRESENT_R
+3V_PCH
RP25
8 1 PCIE_WAKE#
A 7 2 RI# A
6 3 EC_SMI#
EC_SMI# <19,32>
5 4
10K_0804_8P4R_5%

4019N1 B

5 4 3 2 1
5 4 3 2 1
U4D
R438
D 2 1 ENBKL J47 AP43 D
<32> ENBKL L_BKLTEN SDVO_TVCLKINN
M45 AP45
<23> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
100K_0402_1% P45 AM42
<23> PCH_PWM L_BKLTCTL SDVO_STALLN AM40
EDID_CLK T40 SDVO_STALLP
<23> EDID_CLK L_DDC_CLK
EDID_DATA K47 AP39
<23> EDID_DATA L_DDC_DATA SDVO_INTN AP40
CTRL_CLK T45 SDVO_INTP
CTRL_DATA P39 L_CTRL_CLK
+3VS L_CTRL_DATA
2.37K_0402_1% 2 R206 1 LVDS_IBG AF37 P38 HDMICLK_NB HDMICLK_NB <25>
AF36 LVD_IBG SDVO_CTRLCLK M39 HDMIDAT_NB
LVD_VBG SDVO_CTRLDATA HDMIDAT_NB <25>
RP14 AE48
8 1 EDID_DATA AE47 LVD_VREFH AT49
7 2 EDID_CLK LVD_VREFL DDPB_AUXN AT47
6 3 CTRL_DATA DDPB_AUXP AT40
DDPB_HPD TMDS_B_HPD# <25>
5 4 CTRL_CLK AK39
<23> LVDS_ACLK# LVDSA_CLK#
AK40 AV42 TMDS_B_DATA2#_PCHHDMI@ C200 1 2 0.1U_0402_10V6K
LVDS
<23> LVDS_ACLK LVDSA_CLK DDPB_0N HDMI_TX2-_CK <25>
2.2K_0804_8P4R_5%
AN48 DDPB_0P
AV40 TMDS_B_DATA2_PCH HDMI@
AV45 TMDS_B_DATA1#_PCHHDMI@
C201 1
1
2
2
0.1U_0402_10V6K
HDMI_TX2+_CK <25> HDMI D2
C202 0.1U_0402_10V6K
<23> LVDS_A0# LVDSA_DATA#0 DDPB_1N HDMI_TX1-_CK <25>
<23> LVDS_A1#
AM47
LVDSA_DATA#1 DDPB_1P
AV46 TMDS_B_DATA1_PCH HDMI@ C203 1 2 0.1U_0402_10V6K
Digital Display Interface

C <23> LVDS_A2#
AK47
LVDSA_DATA#2 DDPB_2N
AU48 TMDS_B_DATA0#_PCHHDMI@ C204 1 2 0.1U_0402_10V6K
HDMI_TX0-_CK <25> HDMI C
AJ48
LVDSA_DATA#3 DDPB_2P
AU47 TMDS_B_DATA0_PCH HDMI@
AV47 TMDS_B_CLK#_PCH HDMI@
C205
C206
1
1
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
DDPB_3N HDMI_CLK-_CK <25>
<23> LVDS_A0
AN47
AM49 LVDSA_DATA0 DDPB_3P
AV49 TMDS_B_CLK_PCH HDMI@ C207 1 2 0.1U_0402_10V6K
HDMI_CLK+_CK <25> HDMI CLK
<23> LVDS_A1 LVDSA_DATA1
AK49
<23> LVDS_A2 LVDSA_DATA2
AJ47 P46 CAP move on Conn, side
LVDSA_DATA3 DDPC_CTRLCLK P42
RP20 DDPC_CTRLDATA
8 1 DAC_BLU AF40
7 2 DAC_GRN AF39 LVDSB_CLK# AP47
6 3 DAC_RED LVDSB_CLK DDPC_AUXN AP49
5 4 AH45 DDPC_AUXP AT38
AH47 LVDSB_DATA#0 DDPC_HPD
150_0804_8P4R_1% AF49 LVDSB_DATA#1 AY47
LVDSB_DATA#2 DDPC_0N
Max = 800 mils AF45
LVDSB_DATA#3 DDPC_0P
DDPC_1N
AY49
AY43
AH43 AY45
AH49 LVDSB_DATA0 DDPC_1P BA47
AF47 LVDSB_DATA1 DDPC_2N BA48
AF43 LVDSB_DATA2 DDPC_2P BB47
LVDSB_DATA3 DDPC_3N BB49
DDPC_3P
B DAC_BLU N48 M43 B

<24> DAC_BLU CRT_BLUE DDPD_CTRLCLK
DAC_GRN P49 M36
<24> DAC_GRN CRT_GREEN DDPD_CTRLDATA
DAC_RED T49
<24> DAC_RED CRT_RED
AT45
CRT_DDC_CLK T39 DDPD_AUXN AT43
CRT
<24> CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
CRT_DDC_DATA M40 BH41
<24> CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD
BB43
+3VS M47 DDPD_0N BB45
<24> CRT_HSYNC CRT_HSYNC DDPD_0P
M49 BF44
<24> CRT_VSYNC CRT_VSYNC DDPD_1N BE44
DDPD_1P BF42
DDPD_2N
1
CRT_IREF T43 BE42

R559 R524 T42 DAC_IREF DDPD_2P BJ42
CRT_IRTN DDPD_3N
1
2.2K_0402_5% 2.2K_0402_5% BG42

R211 DDPD_3P
1K_0402_1% PANTHER-POINT_FCBGA989
2
HM76@
CRT_DDC_CLK
2
CRT_DDC_DATA
A A

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
4019N1 B

5 4 3 2 1
5 4 3 2 1
+3VS
RP1
PCI_PIRQA# 1 10
PCI_PIRQD# 2 9 PCH_GPIO2 U4E
PCI_PIRQC# 3 8 DGPU_PWR_EN AY7
PCI_PIRQB# 4 7 PCH_GPIO4 RSVD1 AV7
5 6 PCH_GPIO3 BG26 RSVD2 AU3
+3VS BJ26 TP1 RSVD3 BG4
BH25 TP2 RSVD4
8.2K_1206_10P8R_5% BJ16 TP3 AT10
BG16 TP4 RSVD5 BC8
AH38 TP5 RSVD6
D TP6 D
AH37 AU2
AK43 TP7 RSVD7 AT4
+3VS AK45 TP8 RSVD8 AT3
RP7 C18 TP9 RSVD9 AT1
8 1 DGPU_HOLD_RST# N30 TP10 RSVD10 AY3
7 2 PCH_WL_OFF# H3 TP11 RSVD11 AT5
6 3 PCH_GPIO5 AH12 TP12 RSVD12 AV3
5 4 NVDD_PWR_EN AM4 TP13 RSVD13 AV1
AM5 TP14 RSVD14 BB1
8.2K_0804_8P4R_5% Y13 TP15 RSVD15 BA3
TP16 RSVD16
Pull-up resistors are not required K24
TP17 RSVD17
BB5
L24 BB3
on these signals AB46 TP18 RSVD18 BB7
R292 1 @ 2 8.2K_0402_5% PCH_GPIO51 AB45 TP19 RSVD19 BE8
TP20 RSVD20 BD4
RSVD
R557 1 @ 2 8.2K_0402_5% PCH_GPIO53 RSVD21 BF6
RSVD22
B21 AV5
M20 TP21 RSVD23 AV10
AY16 TP22 RSVD24
BG46 TP23 AT8
TP24 RSVD25
AY5
RSVD26 BA2
USB3_RX1_N BE28 RSVD27
<35> USB3_RX1_N USB3Rn1
<35> USB3_RX2_N USB3_RX2_N BC30 AT12
BE32 USB3Rn2 RSVD28 BF3
C USB3Rn3 RSVD29 C
BJ32
USB3_RX1_P BC28 USB3Rn4
<35> USB3_RX1_P USB3Rp1
<35> USB3_RX2_P USB3_RX2_P BE30
BF32 USB3Rp2 USB DEBUG=PORT1 AND PORT9
Boot BIOS Strap USB3Rp3
BG32 C24 USB20_N0
USB3Rp4 USBP0N USB20_N0 <35>
GPIO51 GPIO19 Boot BIOS <35> USB3_TX1_N
USB3_TX1_N AV26
USB3Tn1 USBP0P
A24 USB20_P0
USB20_P0 <35> LEFT USB
GNT1#/ Destination <35> USB3_TX2_N
USB3_TX2_N BB26
USB3Tn2 USBP1N
C25 USB20_N1
USB20_N1 <35> (USB 3.0)
GPIO51 Bit11 Bit10 AU28
AY30 USB3Tn3 USBP1P
B25
C26
USB20_P1
USB20_N2
USB20_P1 <35> LEFT USB
USB3Tn4 USBP2N USB20_N2 <35>
0 1 Reserved <35> USB3_TX1_P
USB3_TX1_P AU26
USB3_TX2_P AY26 USB3Tp1 USBP2P
A26
K28
USB20_P2
USB20_N3
USB20_P2 <35> Touch Screen
SATA1GP/ <35> USB3_TX2_P USB3Tp2 USBP3N USB20_N3 <23>
GPIO19 1 0 PCI AV28
AW30 USB3Tp3 USBP3P
H28
E28
USB20_P3
USB20_P3 <23> USB Camera
USB3Tp4 USBP4N
Internal 1 1 * SPI (Default) USBP4P
D28
C28 HM76 not support USB2.0 for port 6-7
PH 0 0 LPC USBP5N A28
USBP5P
USBP6N
C29
B29
HM70 not support USB2.0 for port 4-7 &12 &13
USBP6P
PCI_PIRQA#
PCI_PIRQB#
K40
K38 PIRQA# USBP7N
N28
M28
NM70 not support USB2.0 for port 4-7 &12 &13
PCI_PIRQC# H38 PIRQB# USBP7P L30
PCI
PCI_PIRQD# G38 PIRQC# USBP8N K30
PIRQD# USBP8P G30 USB20_N9
USBP9N USB20_N9 <33>
DGPU_HOLD_RST#
NVDD_PWR_EN
C46
C44 REQ1# / GPIO50 USBP9P
E30
C30
USB20_P9
USB20_N10
USB20_P9 <33> USB2.0
USB
REQ2# / GPIO52 USBP10N USB20_N10 <26>
<32> DGPU_PWR_EN
E40
REQ3# / GPIO54 USBP10P
A30
L32
USB20_P10
USB20_N11
USB20_P10 <26> WLAN
B USBP11N USB20_N11 <33> B
PCH_GPIO51
PCH_GPIO53
D47
E42 GNT1# / GPIO51 USBP11P
K32
G32
USB20_P11
USB20_P11 <33> CARD READER
PCH_WL_OFF# F46 GNT2# / GPIO53 USBP12N E32
<26> PCH_WL_OFF# GNT3# / GPIO55 USBP12P C32
USBP13N A32
PCH_GPIO2 G42 USBP13P
GPIO55 PIRQE# / GPIO2
PCH_GPIO3 G40
PCH_WL_OFF# R215 1 @ 2 1K_0402_5% PCH_GPIO4 C42 PIRQF# / GPIO3 C33 USBRBIAS 1 R218 2
PCH_GPIO5 D44 PIRQG# / GPIO4 USBRBIAS# 22.6_0402_1%
PIRQH# / GPIO5
B33
Within 500 mils
PCI_PME# K10 USBRBIAS
A16 swap overide Strap/Top-Block T39 PAD PME#
Swap Override jumper For LEFT USB3.0 Port
PCH_PLTRST# C6 A14 USB_OC0#
<6> PCH_PLTRST# PLTRST# OC0# / GPIO59 USB_OC0# <35>
Low=A16 swap K20 USB_OC1#
OC1# / GPIO40
override/Top-Block For EMI OC2# / GPIO41
B17 USB_OC2#
PCI_GNT3# Swap Override enabled 22_0402_5% 1 2 R219 CLK_PCI_LPBACK_R H49 C16 USB_OC3#
<15> CLK_PCI_LPBACK CLKOUT_PCI0 OC3# / GPIO42
High=Default * <32> CLK_PCI_EC
22_0402_5% 1 2 R220 CLK_PCI_EC_R H43
CLKOUT_PCI1 OC4# / GPIO43
L16 USB_OC4#
USB_OC4# <33>
J48 A16 USB_OC5#
K42 CLKOUT_PCI2 OC5# / GPIO9 D14 USB_OC6# For RIGHT USB2.0 Port +3V_PCH
CLKOUT_PCI3 OC6# / GPIO10 RP18
H40 C14 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14 USB_OC0# 1 10
USB_OC1# 2 9 USB_OC4#
PANTHER-POINT_FCBGA989 USB_OC2# 3 8 USB_OC5#
HM76@ USB_OC3# 4 7 USB_OC6#
5 6 USB_OC7#
+3V_PCH
A A
R222 10K_1206_10P8R_5%
1 2 PCH_PLTRST#
<26,27,32> PLT_RST#
0_0402_5% @
1

R223
100K_0402_5%
2
4019N1 B

5 4 3 2 1
5 4 3 2 1
+3VS +3VS
+3VS
PCH_GPIO71 Function
PCH_GPIO69 PCH_GPIO70 Function
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
R702 R703
@ HM70@
1 N14M-GE 1000MHz R704
- - NM70 1000M@
1
PCH_GPIO69 PCH_GPIO70
0 N14M-GE 900MH
1
PCH_GPIO71
- - Reserved
2
R707 R705
- 1 HM70
D D
@ HM76@ R706
10K_0402_5% 10K_0402_5% 900M@
1
10K_0402_5%
- 0 HM76
1
U4F
T7 C40
BMBUSY# / GPIO0 TACH4 / GPIO68
A42 B41 PCH_GPIO69
TACH1 / GPIO1 TACH5 / GPIO69
GPIO28
On-Die PLL Voltage Regulator H36 C41 PCH_GPIO70 +3VS
This signal has a weak internal pull up
<32> EC_SCI# EC_SCI# E38 A40 PCH_GPIO71
*
2
H：On-Die voltage regulator enable
L：On-Die PLL Voltage Regulator disable <16,32> EC_SMI# EC_SMI# C10 R236
GPIO8
10K_0402_5%
R240 1 @ 2 1K_0402_5% PCH_GPIO28 C4
LAN_PHY_PWR_CTRL / GPIO12
1
R230 1 2 1K_0402_5% EC_LID_OUT# G2 P4 +3VS
+3V_PCH GPIO15 A20GATE GATEA20 <32>
<32> EC_LID_OUT#
AU16
PCH_GPIO16 U2 PECI
<14> PCH_GPIO16 SATA4GP / GPIO16
* PCH_GPIO27 (Have internal Pull-High) RCIN#
P5 KBRST#
KBRST# <32>
KBRST# R226 1 2 10K_0402_5%
PAD T67 DGPU_PWROK D40 AY11
GPIO
High: VCCVRM VR Enable TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <6>
CPU/MISC
Low: VCCVRM VR Disable <26> PCH_BT_ON#
PCH_BT_ON# T5
SCLOCK / GPIO22 THRMTRIP#
AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP# H_THRMTRIP# <6>
C R239 390_0402_5% C
R245 1 @ 2 10K_0402_5% PCH_GPIO27 ODD_EN E8 T14
+3V_PCH <30> ODD_EN GPIO24 INIT3_3V#
PCH_GPIO27 E16 AY1
R241 GPIO27 DF_TVS
INIT3_3V
1 2 10K_0402_5% PCH_GPIO28 P8 This signal has weak internal PU,can't pull low
GPIO28 AH8
TS_VSS1
GPIO36, 37 <26> INTEL_BT_OFF# INTEL_BT_OFF# K1
STP_PCI# / GPIO34 +1.8VS
1 R242 2 10K_0402_5% AK11
+3VS When Unused as GPIO or SATA*GP +3VS
PCH_GPIO35 K4 TS_VSS2
GPIO35
Use 8.2K-10K pull-down
+3VSto ground.
TS_VSS3
AH10 DMI Termination Voltage
PCH_GPIO36 V8
SATA2GP / GPIO36
1
1
AK10 Set to Vcc when HIGH
R244 @ R250 @ PCH_GPIO37 M5 TS_VSS4
SATA3GP / GPIO37 NV_CLE
10K_0402_5% 10K_0402_5% Set to Vss when LOW R216
PCH_GPIO38 N2 P37 2.2K_0402_5%
SLOAD / GPIO38 NC_1
2
2
PCH_GPIO37 PCH_GPIO36 PCH_GPIO39 M3 NV_CLE 2 1 H_SNB_IVB# <6>
SDATAOUT0 / GPIO39 R217 1K_0402_5%
1
V13 BG2 Weak internal CLOSE TO THE BRANCHING POINT

SDATAOUT1 / GPIO48 VSS_NCTF_15
1
PU,Do not pull low

R881 V3 BG48
10K_0402_5% R547 SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
@ 10K_0402_5% D6 BH3
GPIO57 VSS_NCTF_17
2
@
2
BH47
VSS_NCTF_18
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
A44 BJ44
B VSS_NCTF_2 VSS_NCTF_20 B
A45 BJ45
A46 BJ46
NCTF
+3VS VSS_NCTF_4 VSS_NCTF_22
BIOS Request SKU ID
A5 BJ5
RP10 VSS_NCTF_5 VSS_NCTF_23
+3VS 8 1 PCH_GPIO39 A6 BJ6
7 2 SYS_RST# VSS_NCTF_6 VSS_NCTF_24
SYS_RST# <16>
6 3 PCH_BT_ON# B3 C2
5 4 PCH_GPIO35 VSS_NCTF_7 VSS_NCTF_25
B47 C48
10K_0804_8P4R_5% VSS_NCTF_8 VSS_NCTF_26
2
BD1 D1
10K_0402_5%
R246 VSS_NCTF_9 VSS_NCTF_27

R711 UMA@ BD49 D49
UMA@ 10K_0402_5% VSS_NCTF_10 VSS_NCTF_28
BE1 E1
1
PCH_GPIO38 BE49 E49

PCH_GPIO67 PCH_GPIO67 <15> BF1 F1
BF49 F49
2
1
10K_0402_5%
R708 R298 PANTHER-POINT_FCBGA989

OPT@ OPT@
10K_0402_5% PCH_GPIO38 PCH_GPIO67 Function HM76@
1
A A
0 0 Optimus
0 1 Reserved Security Classification Compal Secret Data Compal Electronics, Inc.
1 0 DIS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1 1 UMA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
4019N1 B

5 4 3 2 1
5 4 3 2 1
L1 Change to 1 ohm P/N

S RES 1/10W 1 +-1% 0603
+V1.05S_VCCP U4G POWER +3VS
PCH Power Rail Table
Near AA23
1300mA L1 3.3_0603_1% Refer to CPU EDS R1.5
AA23 U48 +VCCADAC 2 1
VCCCORE[1] 1mA VCCADAC
AC23
VCCCORE[2] 1 1 1 1 1 S0 Iccmax
AD21 C231 Voltage Rail Voltage Current (A)
1U_0402_6.3V6K
C210
1U_0402_6.3V6K
C211
1U_0402_6.3V6K
C212
1 1 1 1
CRT
AD23 VCCCORE[3] U47 C213 C214 C215 C229 22U_0805_6.3V6M
10U_0603_6.3V6M
C209
AF21 VCCCORE[4] VSSADAC 0.01U_0402_25V7K 0.1U_0402_10V7K 10U_0603_6.3V6M 10U_0603_6.3V6M
VCCCORE[5]
VCC CORE
AF23 2 2 2@ 2@ 2 V_PROC_IO 1.05 0.001
D 2 2 2 2 AG21 VCCCORE[6] +3VS D
AG23 VCCCORE[7]
VCCCORE[8]
AG24
VCCCORE[9] 1mA VCCALVDS AK36 V5REF 5 0.001
AG26
AG27 VCCCORE[10] AK37
VCCCORE[11] VSSALVDS
AG29
VCCCORE[12]
V5REF_Sus 5 0.001
AJ23 +1.8VS
AJ26 VCCCORE[13] AM37 L2
LVDS
VCCCORE[14] VCCTX_LVDS[1]
AJ27
VCCCORE[15]
0.1UH_MLF1608DR10KT_10%_1608 Vcc3_3 3.3 0.228
AJ29 AM38 +VCCTX_LVDS 2 1
AJ31 VCCCORE[16] VCCTX_LVDS[2] 0.1uH inductor, 200mA
VCCCORE[17] 1 1 1
+V1.05S_VCCP
60mA VCCTX_LVDS[3] AP36 VccADAC 3.3 0.001
C216 C217 C218
AP37 0.01U_0402_25V7K 0.01U_0402_25V7K 22U_0805_6.3V6M
VCCTX_LVDS[4] 2 2 2
AN19
VCCIO[28]
VccADPLLA 1.05 0.075
+VCCAPLLEXP BJ22 +3VS VccADPLLB 1.05 0.075

T29 PAD VCCAPLLEXP Near V33
This pin can be left as no connect in VCC3_3[6]
V33
AN16 VccCore 1.05 1.3
HVCMOS
On-Die VR enabled mode (default). VCCIO[15]
1
AN17
VCCIO[16]
VCC3_3[7]
V34 C219 VccDMI 1.05 0.042
0.1U_0402_10V7K
AN21 2
VCCIO[17]
VccIO 1.05 3.709
AN26 +1.5VS
VCCIO[18]
AN27
VCCIO[19]
3711mA VCCVRM[3]
AT16 VccASW 1.05 0.903
+V1.05S_VCCP
+V1.05S_VCCP Near AN16 AP21
VCCIO[20] Near AT20
C VccSPI 3.3 0.01 C
AP23 AT20
VCCIO[21] VCCDMI[1]
1
AP24 Near AB36 +V1.05S_VCCP VccDSW 3.3 0.001
1U_0402_6.3V6K
C222
1U_0402_6.3V6K
C223
1U_0402_6.3V6K
C224
1U_0402_6.3V6K
C225
DMI
1 1 1 1 1 VCCIO[22] C220
10U_0603_6.3V6M
C221
VCCIO
AP26 20mA VCCCLKDMI AB36 1U_0402_6.3V6K
VCCIO[23] 2
1 VccDFTERM 1.8 0.002
2 2 2 2 2 AT24
VCCIO[24] C226
1U_0402_6.3V6K VccRTC 3.3 6 uA
AN33 2
VCCIO[25]
AN34
VCCIO[26] VCCDFTERM[1]
AG16 VccSus3_3 3.3 0.065
+3VS
BH29 AG17 +1.8VS VccSusHDA 3.3 / 1.5 0.01

VCC3_3[3] 190mA VCCDFTERM[2]
Near AG16
DFT / SPI
1
C227
0.1U_0402_10V7K +1.5VS
VCCDFTERM[3]
AJ16 VccVRM 1.8 / 1.5 0.167
2 1
AP16 C228
VCCVRM[2]
VCCDFTERM[4]
AJ17 0.1U_0402_10V7K VccCLKDMI 1.05 0.075
This pin can be left as no connect in T30 +1.05VS_VCCAPLL_FDI BG6 2
On-Die VR enabled mode (default). +V1.05S_VCCP PAD VccAFDIPLL +3V_ROM VccSSC 1.05 0.095
AP17 Near V1
VCCIO[27]
20mA VCCSPI
V1 VccDIFFCLKN 1.05 0.055
FDI
1
+V1.05S_VCCP AU20
VCCDMI[2] C230 VccALVDS 3.3 0.001
1U_0402_6.3V6K
B PANTHER-POINT_FCBGA989 2 B
VccTX_LVDS 1.8 0.04
HM76@
11/30 Add(Share ROM)
+3VALW +3V_ROM +3VS
1 R413 2
0_0402_5%
NOSROM@
@
Q21
AO3413_SOT23
+5VALW
3 1 1 R419 2
D
0_0402_5%
1
@ @
.1U_0402_16V7K
C243
1
Intel recommand VCCVRM==>1.5V FOR MOBILE @
G
2
R418
stuff R265 and unstuff R266 VCCVRM==>1.8V FOR DESKTOP 100K_0402_5%
2
2
VCCVRM = 160mA detal waiting for newest spec 12/20 Place @ first
@ Q22
D
1
R40
1 2 PCH_PWR_EN_R 2
<32> PCH_PWR_EN
0_0402_5%
.1U_0402_16V7K
G
2N7002H_SOT23-3 @
.1U_0402_16V7K
C237
C252
1 S 1
3
@
@
A A
2 2

4019N1 B

5 4 3 2 1
5 4 3 2 1
Have internal VRM

+3VS +V1.05S_VCCP R268 @
0_0603_5%
2 1 +VCCACLK
Near T38
POWER
+3V_PCH
Near T16 U4J +V1.05S_VCCP
+3VALW
PJ1
@ +3V_PCH
1
2 1
1U_0402_6.3V6K
C232
1 AD49 N26
VCCACLK VCCIO[29] JUMP_43X118
2 1
C234 P26
0.1U_0402_10V7K T16 VCCIO[30] C233
D 2 VCCDSW3_3 3mA P28 1U_0402_6.3V6K D
@ VCCIO[31] 2
2 1 +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]
C235 T29
0.1U_0402_10V7K T38 VCCIO[33] +3V_PCH
+3VS VCC3_3[5]
On-Die PLL Voltage Regulator
H：On-Die PLL voltage regulator enable T23
+VCCAPLL_CPY_PCH BH23 119mA VCCSUS3_3[7]
T31 PAD VCCAPLLDMI2
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 T24 +3V_PCH
0.1U_0402_10V7K
C236
VCCSUS3_3[8] 1 +5VALW +3V_PCH
AL29
,VCCAPLLSATA +V1.05S_VCCP VCCIO[14] V23
VCCSUS3_3[9]
USB
2 1
2
+VCCSUS1 AL24 V24
DCPSUS[3] VCCSUS3_3[10] C238 R275 D1
1
P24 0.1U_0402_10V7K 100_0402_1% CH751H-40PT_SOD323-2
@ C239 VCCSUS3_3[6] 2 +V1.05S_VCCP
1U_0402_6.3V6K AA19
2 VCCASW[1]
1
T26 +PCH_V5REF_SUS
+V1.05S_VCCP VCCIO[34]
Near AA19 AA21
VCCASW[2]
1010mA 1
AA24 M26 +PCH_V5REF_SUS C240
VCCASW[3] 1mA V5REF_SUS 0.1U_0603_25V7K
1 1 2
AA26
22U_0805_6.3V6M
C241
22U_0805_6.3V6M
C242
VCCASW[4]
Clock and Miscellaneous

AN23 +VCCA_USBSUS
AA27 DCPSUS[4] T33 PAD
2 2 VCCASW[5] AN24
VCCSUS3_3[1] +3V_PCH
AA29
VCCASW[6]
AA31 +5VS +3VS
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN +3V_PCH
VCCASW[8] 1mA V5REF
2
C C
1 1 1
AC27 R279 D2
1U_0402_6.3V6K
C244
1U_0402_6.3V6K
C245
1U_0402_6.3V6K
C246
VCCASW[9] N20 CH751H-40PT_SOD323-2
VCCSUS3_3[2] 1 100_0402_1%
+V1.05S_VCCP AC29
PCI/GPIO/LPC
2 2 2 VCCASW[10] N22 C247
VCCSUS3_3[3]
1
AC31 1U_0402_6.3V +PCH_V5REF_RUN
VCCASW[11] P20 2 +3VS
VCCSUS3_3[4] 1
AD29
VCCASW[12] P22 C248
AD31 VCCSUS3_3[5] 1U_0603_10V6K
VCCASW[13] 1 2
C249
W21 AA16 0.1U_0402_10V7K
VCCASW[14] VCC3_3[1]
L6 W23 W16 2 +3VS
1 2 +1.05VS_VCCA_A_DPL VCCASW[15] VCC3_3[8]
10UH_LB2012T100MR_20% W24 T34
VCCASW[16] VCC3_3[4]
1 1
W26
220U_B2_2.5VM_R35
C250
1U_0402_6.3V6K
C251
1U_0402_6.3V6K
C253
1 1 VCCASW[17]
+ C254
@ W29 +3VS 0.1U_0402_10V7K
VCCASW[18] 2
2 2 2 W31 AJ2
VCCASW[19] VCC3_3[2] +V1.05S_VCCP
1
W33
VCCASW[20] AF13
VCCIO[5] C255
2 0.1U_0402_10V7K 1
+VCCRTCEXT N16
+1.5VS DCPRTC AH13 C257
1 VCCIO[12]
C258 1U_0402_6.3V6K
0.1U_0402_10V7K Y49 AH14 2
VCCVRM[4] VCCIO[13]
2
B
Near AF17 +1.05VS_VCCA_A_DPL BD47 VCCIO[6]
AF14 B
+V1.05S_VCCP VCCADPLLA 80mA AK1 +VCCSATAPLL
SATA
+1.05VS_VCCA_A_DPL BF47 VCCAPLLSATA +1.5VS T34 PAD
1 VCCADPLLB 80mA On-Die PLL Voltage Regulator
C256 H：On-Die PLL voltage regulator enable
1U_0402_6.3V6K AF11
VCCVRM[1] +V1.05S_VCCP
2
AF17
VCCIO[7] VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
AF33
Near AF33 AF34 VCCDIFFCLKN[1]
55mA AC16 ,VCCAPLLSATA
AG34 VCCDIFFCLKN[2] VCCIO[2]
+V1.05S_VCCP VCCDIFFCLKN[3]
1 AC17 1
VCCIO[3] C261
C259 AG33 AD17 1U_0402_6.3V6K
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4]
2 2
+VCCSST V16 +V1.05S_VCCP
DCPSST
Near AG33 C263
1
+V1.05S_VCCP
1 0.1U_0402_10V7K +1.05VM_VCCSUS T17 T21
T32 PAD DCPSUS[1] VCCASW[22]
V19
C262 2 DCPSUS[2]
MISC
1U_0402_6.3V6K +V1.05S_VCCP V21

2 VCCASW[23]
Near BJ8 BJ8

CPU
V_PROC_IO 1mA T19

VCCASW[21]
1 1
+RTCVCC +3V_PCH
4.7U_0603_6.3V6K
C265
0.1U_0402_10V7K
C266
@
@ A22 P32
10mA VCCSUSHDA
RTC
2 2 VCCRTC
HDA
0.1U_0402_10V7K
C269
1 1
PANTHER-POINT_FCBGA989 C271
A HM76@ 0.1U_0402_16V4Z A
2 2

4019N1 B

5 4 3 2 1
5 4 3 2 1
U4I
AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
D U4H B15 VSS[163] VSS[263] K7 D
H5 B19 VSS[164] VSS[264] L18
VSS[0] B23 VSS[165] VSS[265] L2
AA17 AK38 B27 VSS[166] VSS[266] L20
AA2 VSS[1] VSS[80] AK4 B31 VSS[167] VSS[267] L26
AB11 VSS[5] VSS[84] AL16 F45 VSS[171] VSS[271] M12
AB14 VSS[6] VSS[85] AL17 BB12 VSS[172] VSS[272] P16
AB39 VSS[7] VSS[86] AL19 BB16 VSS[173] VSS[273] M18
AC19 VSS[12] VSS[91] AL27 BB30 VSS[178] VSS[278] M34
AC33 VSS[16] VSS[95] AL48 BC14 VSS[182] VSS[282] M46
AC34 VSS[17] VSS[96] AM11 BC18 VSS[183] VSS[283] M8
AC48 VSS[18] VSS[97] AM14 BC2 VSS[184] VSS[284] N18
AD10 VSS[19] VSS[98] AM36 BC22 VSS[185] VSS[285] P30
AD11 VSS[20] VSS[99] AM39 BC26 VSS[186] VSS[286] N47
AD19 VSS[23] VSS[102] AM46 BC36 VSS[189] VSS[289] T33
AD26 VSS[25] VSS[104] AN2 BC42 VSS[191] VSS[291] P43
AD27 VSS[26] VSS[105] AN29 BC48 VSS[192] VSS[292] P47
AD33 VSS[27] VSS[106] AN3 BD46 VSS[193] VSS[293] P7
AD34 VSS[28] VSS[107] AN31 BD5 VSS[194] VSS[294] R2
C AD36 VSS[29] VSS[108] AP12 BE22 VSS[195] VSS[295] R48 C
AD37 VSS[30] VSS[109] AP19 BE26 VSS[196] VSS[296] T12
AD38 VSS[31] VSS[110] AP28 BE40 VSS[197] VSS[297] T31
AD39 VSS[32] VSS[111] AP30 BF10 VSS[198] VSS[298] T37
AD40 VSS[34] VSS[113] AP38 BF16 VSS[200] VSS[300] W34
AD46 VSS[38] VSS[117] AP8 BF26 VSS[204] VSS[304] V11
AD8 VSS[39] VSS[118] AR2 BF28 VSS[205] VSS[305] V17
AE2 VSS[40] VSS[119] AR48 BD3 VSS[206] VSS[306] V26
AE3 VSS[41] VSS[120] AT11 BF30 VSS[207] VSS[307] V27
AF10 VSS[42] VSS[121] AT13 BF38 VSS[208] VSS[308] V29
AF12 VSS[43] VSS[122] AT18 BF40 VSS[209] VSS[309] V31
AD14 VSS[44] VSS[123] AT22 BF8 VSS[210] VSS[310] V36
AD16 VSS[45] VSS[124] AT26 BG17 VSS[211] VSS[311] V39
AF16 VSS[46] VSS[125] AT28 BG21 VSS[212] VSS[312] V43
AF19 VSS[47] VSS[126] AT30 BG33 VSS[213] VSS[313] V7
AF24 VSS[48] VSS[127] AT32 BG44 VSS[214] VSS[314] W17
AF26 VSS[49] VSS[128] AT34 BG8 VSS[215] VSS[315] W19
AF27 VSS[50] VSS[129] AT39 BH11 VSS[216] VSS[316] W2
AF38 VSS[53] VSS[132] AT7 BH19 VSS[219] VSS[319] Y12
AF4 VSS[54] VSS[133] AU24 H10 VSS[220] VSS[320] Y38
AF42 VSS[55] VSS[134] AU30 BH27 VSS[221] VSS[321] Y4
AF46 VSS[56] VSS[135] AV16 BH31 VSS[222] VSS[322] Y42
AF8 VSS[59] VSS[138] AV30 BH39 VSS[225] VSS[325] BG29
AG19 VSS[60] VSS[139] AV38 BH43 VSS[226] VSS[328] N24
B AG2 VSS[61] VSS[140] AV4 BH7 VSS[227] VSS[329] AJ3 B
AG31 VSS[62] VSS[141] AV43 D3 VSS[228] VSS[330] AD47
AG48 VSS[63] VSS[142] AV8 D12 VSS[229] VSS[331] B43
AH11 VSS[64] VSS[143] AW14 D16 VSS[230] VSS[333] BE10
AH3 VSS[65] VSS[144] AW18 D18 VSS[231] VSS[334] BG41
AH36 VSS[66] VSS[145] AW2 D22 VSS[232] VSS[335] G14
AH39 VSS[67] VSS[146] AW22 D24 VSS[233] VSS[337] H16
AH40 VSS[68] VSS[147] AW26 D26 VSS[234] VSS[338] T36
AH7 VSS[71] VSS[150] AW34 D34 VSS[237] VSS[343] C22
AJ19 VSS[72] VSS[151] AW36 D38 VSS[238] VSS[344] AP13
AJ21 VSS[73] VSS[152] AW40 D42 VSS[239] VSS[345] M14
AJ24 VSS[74] VSS[153] AW48 D8 VSS[240] VSS[346] AP3
AJ33 VSS[75] VSS[154] AV11 E18 VSS[241] VSS[347] AP1
AJ34 VSS[76] VSS[155] AY12 E26 VSS[242] VSS[348] BE16
AK12 VSS[77] VSS[156] AY22 G18 VSS[243] VSS[349] BC16
AK3 VSS[78] VSS[157] AY28 G20 VSS[244] VSS[350] BG28
VSS[79] VSS[158] G26 VSS[245] VSS[351] BJ28
PANTHER-POINT_FCBGA989 G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
HM76@ VSS[249]
H12
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
A A
PANTHER-POINT_FCBGA989
HM76@

4019N1 B

5 4 3 2 1
5 4 3 2 1
LCD POWER CIRCUIT CMOS Camera

+3VS
W=60mils
(20 MIL)
+3VS +LCDVDD_CONN
W=60mils U72 Q83
CMOS@ +3VS_CMOS
D 1 +LCDVDD_CONN PMV65XP_SOT23-3~D D
5 VOUT
(20 MIL)
4.7U_0603_6.3V6K
VIN 3 1
D
2
C516
GND 1 1 1
4 CMOS@
SS C518 C519 @
G
2
1 3 0.1U_0402_16V4Z R02 10U_0603_6.3V6M
EN 2 R435CMOS@ 2 2
C4 APL3512ABI-TRG_SOT23-5 150K_0402_5%
1500P_0402_50V7K 4.7V
2 <32> CMOS_ON#
1 R296 for CMOS shake issue reserve

<17> PCH_ENVDD
C520 CMOS@
0.1U_0402_16V4Z
2
C
VGA LCD/PANEL BD. Conn. C
12/12 Mount C539/C541 of 680pF,Chanage R813

to 220 ohm bead.(For EMI request)
+LEDVDD B+
R813
FBMA-L11-201209-221LMA30T_0805
BKOFF# 1 2
<32> BKOFF#
1
1
C539 C541
R716 680P_0402_50V7K 680P_0402_50V7K
2
10K_0402_5%
2
JLVDS1
1 2
1 2 PCH_PWM <17>
3 4
5 3 4 6 USB20_N3_R
B B
BKOFF# 7 5 6 8 USB20_P3_R
9 7 8 10
11 9 10 12
<17> LVDS_ACLK 11 12 LVDS_A1 <17>
13 14
<17> LVDS_ACLK# 13 14 LVDS_A1# <17>
15 16
For EMI
17 15 16 18
<17> LVDS_A2 17 18 LVDS_A0 <17>
19 20
<17> LVDS_A2# 19 20 LVDS_A0# <17>
21 22
23 21 22 24
<17> EDID_DATA 23 24 (60 MIL)
<18> USB20_P3 USB20_P3 2 R688 1 0_0402_5% USB20_P3_R 25 26 +LCDVDD_CONN
<17> EDID_CLK 25 26
<18> USB20_N3 USB20_N3 2 R684 1 0_0402_5% USB20_N3_R 27 28 +3VS
29 27 28 30
+3VS 29 30 +3VS_CMOS
L58 @ 31 32
USB20_P3 1 2 USB20_P3_R GNDGND
1 2 ACES_87142-3041-BS
ME@
USB20_N3 4 3 USB20_N3_R
4 3
WCM-2012-900T_4P
A A

Custom
4019N1 B

5 4 3 2 1
A B C D E
1 1
FCM1608CF-121T03 0603
1 2 RED
<17> DAC_RED
L30
FCM1608CF-121T03 0603
1 2 GREEN
<17> DAC_GRN
L31
FCM1608CF-121T03 0603
1 2 BLUE
<17> DAC_BLU
L32
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
C522
C523
C524
C525
C526
C527
1 1 1 1 1 1
RP22
8 1 DAC_BLU 2 2 2 2 2 2 +5V_DISPLAY
7 2 DAC_GRN
6 3 DAC_RED
5 4
150_0804_8P4R_1% @ @ @ @ @ @ JCRT1
6
For EMI
PAD T66 NC11 11
RED 1
7
CRT_DDC_DAT_CONN 12
GREEN 2
8 G 16
2 JVGA_HS_R 13 17 2
G
BLUE 3
9
JVGA_VS_R 14
4
10
CRT_DDC_CLK_CONN 15
5
SUYIN_070546FR015S251ZR
ME@
+5VS
1 1
C529 C531
U10
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 @ 1 8 1 2
VCC_SYNC BYP C6 0.22U_0402_10V6K +5V_DISPLAY
2 3 RED
+3VS VCC_VIDEO VIDEO1
1
7 4 GREEN
VCC_DDC VIDEO2 R31 R33
1 4.7K_0402_5% 4.7K_0402_5%
<17> CRT_DDC_DATA 10 5 BLUE
C537 DDC_IN1 VIDEO3
2
0.1U_0402_16V4Z
3 2 11 9 CRT_DDC_DAT_CONN 3
<17> CRT_DDC_CLK DDC_IN2 DDC_OUT1
13 12 CRT_DDC_CLK_CONN
<17> CRT_VSYNC SYNC_IN1 DDC_OUT2
15 14 JVGA_VS 1 @ 2 JVGA_VS_R
<17> CRT_HSYNC SYNC_IN2 SYNC_OUT1 R411 0_0402_5%
6 16 JVGA_HS 1 @ 2 JVGA_HS_R
GND SYNC_OUT2 R412 0_0402_5%
10P_0402_50V8J
TPD7S019-15DBQR_SSOP16
10P_0402_50V8J
1 1
C411
@ C412 @
2 2
4 4

Custom
4019N1 B

A B C D E
5 4 3 2 1
For EMI
+5V_DISPLAY
U73
+5VS 3
W=40mils
OUT
1
L35 HDMI@ 1
HDMI_CLK+_CK 1 2 HDMI_CLK+_CONN +3VS IN C543
<17> HDMI_CLK+_CK 1 2 1
2
C544 GND 0.1U_0402_16V4Z 2
<17> HDMI_CLK-_CK HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN 0.1U_0402_16V4Z
4 3 2
2
AP2330W-7_SC59-3
D WCM-2012HS-900T R485 ZZZ3 45@ D
1M_0402_5% Q93
L36 HDMI@ HDMI@ HDMI@
2
HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN 2N7002H_SOT23-3
G
<17> HDMI_TX0+_CK 1 2
1
TMDS_B_HPD# 3 1
<17> TMDS_B_HPD#
HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN HDMI Logo
D
<17> HDMI_TX0-_CK 4 3
WCM-2012HS-900T RO0000003HM
2
L37 HDMI@ R488
<17> HDMI_TX1+_CK HDMI_TX1+_CK 1 2 HDMI_TX1+_CONN 20K_0402_5%
1 2 HDMI@
JHDMI1
1
<17> HDMI_TX1-_CK HDMI_TX1-_CK 4 3 HDMI_TX1-_CONN HDMI_DET 19
4 3 18 HP_DET
+5V_DISPLAY +5V
WCM-2012HS-900T 17
HDMIDAT_R 16 DDC/CEC_GND
L38 HDMI@ HDMICLK_R 15 SDA
HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN 14 SCL
<17> HDMI_TX2+_CK 1 2 Reserved
13
HDMI_CLK-_CONN 12 CEC 20
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN 11 CK- GND 21
<17> HDMI_TX2-_CK 4 3 CK_shield GND
HDMI_CLK+_CONN 10 22
C
WCM-2012HS-900T HDMI_TX0-_CONN 9 CK+ GND 23
C
8 D0- GND For LAN

HDMI_TX0+_CONN 7 D0_shield CHASSIS1_GND
+3VS HDMI_TX1-_CONN 6 D0+
5 D1-
HDMI_TX1+_CONN 4 D1_shield
HDMI_TX2-_CONN 3 D1+
2 D2-
HDMI_TX2+_CONN 1 D2_shield
D2+
CONCR_099ATAC19NBLCNF
ME@
+3VS Q63A
HDMI@
+5V_DISPLAY
2
RP21 2N7002DW-T/R7_SOT363-6
8 1 HDMIDAT_NB
7 2 HDMIDAT_R <17> HDMICLK_NB 1 6 HDMICLK_R
6 3 HDMICLK_NB
5
5 4 HDMICLK_R
RP19
2.2K_0804_8P4R_5% <17> HDMIDAT_NB 4 3 HDMIDAT_R
HDMI@ HDMI_CLK-_CONN 1 10
Q63B HDMI_CLK+_CONN 2 9 HDMI_TX0-_CONN
B HDMI@ HDMI_TX1-_CONN 3 8 HDMI_TX0+_CONN B
2N7002DW-T/R7_SOT363-6 HDMI_TX1+_CONN 4 7 HDMI_TX2+_CONN
5 6 HDMI_TX2-_CONN
680_1206_10P8R_5%
ESD HDMI@
@ D32 @ D28 @ D33

HDMIDAT_R 9 10 1 1 HDMIDAT_R HDMI_CLK-_CONN 9 10 1 1 HDMI_CLK-_CONN HDMI_TX0-_CONN 9 10 1 1 HDMI_TX0-_CONN
HDMICLK_R 8 9 2 2 HDMICLK_R HDMI_CLK+_CONN 8 9 2 2 HDMI_CLK+_CONN HDMI_TX0+_CONN 8 9 2 2 HDMI_TX0+_CONN

+3VS
HDMI_DET 7 7 4 4 HDMI_DET HDMI_TX1-_CONN 7 7 4 4 HDMI_TX1-_CONN HDMI_TX2-_CONN 7 7 4 4 HDMI_TX2-_CONN
D
1
6 6 5 5 HDMI_TX1+_CONN 6 6 5 5 HDMI_TX1+_CONN HDMI_TX2+_CONN 6 6 5 5 HDMI_TX2+_CONN 2
G
3 3 3 3 3 3 S Q95
3
HDMI@
8 8 8 2N7002H_SOT23-3
YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9

A A

4019N1 B

5 4 3 2 1
A B C D E
Mini-Express Card for WLAN/WiMAX(Half)
1 1
+3VS 80mil +3VS_WLAN

J6
@
1 2
1 2 +1.5VS
JUMP_43X79
JWLN1
<16> PCIE_WAKE# 1 R508 2 @ PCIE_WAKE#_WLAN 1 2
0_0402_5% 3 1 2 4
5 3 4 6
<19> PCH_BT_ON# 5 6
<15> CLKREQ_WLAN# 7 8
9 7 8 10
11 9 10 12
<15> CLK_PCIE_WLAN1# 11 12
13 14
<15> CLK_PCIE_WLAN1 13 14
15 16
17 15 16 18
19 17 18 20
19 20 PCH_WL_OFF# <18>
21 22
21 22 PLT_RST# <18,27,32>
23 24 +3VS_WLAN
2 <15> PCIE_PRX_DTX_N2 23 24 2
25 26
<15> PCIE_PRX_DTX_P2 25 26
27 28
29 27 28 30 1 R501 2 @ 0_0402_5%
29 30 SMB_CLK_S3 <12,13,15>
31 32 1 R502 2 @ 0_0402_5% SMB_DATA_S3 <12,13,15>
<15> PCIE_PTX_C_DRX_N2 31 32
33 34
<15> PCIE_PTX_C_DRX_P2 33 34
35 36
+3VS_WLAN 35 36 USB20_N10 <18>
37 38
37 38 USB20_P10 <18>
39 40
41 39 40 42
43 41 42 44
100_0402_1% 45 43 44 46
R505 47 45 46 48
1 2 49 47 48 50
<32> EC_TX 49 50
1 2 EC_RX_R 51 52
<32> EC_RX 51 52
R506
100_0402_1% 53 54
R801 2 1 1K_0402_5% GND1 GND2
<19> INTEL_BT_OFF#
LOTES_AAA-PCI-046-K01
2
For EC to detect ME@
R507
debug card insert. 100K_0402_5%
3 3
Reserve for SW mini-pcie debug card.

Series resistors closed to KBC side.
4 4

4019N1 B

A B C D E
5 4 3 2 1
For LAN & Green CLK +3VALW +3V_LAN

+LX
Close together
J12
@ LL2 LL3 SWR@
1 2 LL1 SWR@
1 2 +LX_R 1 2 +LX FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P
4.7UH_SIA4012-4R7M_20% +1.1_AVDDL_L 1 2 +1.1_AVDDL 1 2 +LX_R
1000P_0402_50V7K
10U_0603_6.3V6M
0.1U_0402_16V4Z
JUMP_43X79
CL1
CL2
1 1
0.1U_0402_16V4Z
1U_0402_6.3V4Z
4.7U_0603_6.3V6K
Note: Place Close to LAN chip
CL4
CL5
CL6
D 1 1 1 D
3 1
D
2 2 LL1 DCR< 0.15 ohm
CL3
RL3
Rate current > 1A
QL1 2 2 2
G
@
2
LAN_PWR_ON# 2 1 LP2301ALT1G-SOT23-3
<32> LAN_PWR_ON#
2 @ 10U
@
10K_0402_5% CL7 SWR@ SWR@ SWR@
1
0.1U_0402_16V7K Place close to Pin34
Close to
Pin40
Vendor recommand reseve the

PU resistor close LAN chip
RL4 1 2 4.7K_0402_5% UL1 8172@ +3V_LAN

+3V_LAN
@
PLT_RST#
<18,26,32> PLT_RST#
QCA8172-BL3A-R Configure signal Description
1U_0402_6.3V4Z
0.1U_0402_16V4Z
Pin
CL8
CL10
1 Switch mode regulator(SWR) mode 1 1
LED[1] Regulator select
*
@
UL1
0 Linear regulator (LDO) mode
C
Place Close to Chip 2 2
C
<15> PCIE_PRX_DTX_N1 CL9 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N1 29 38 RL12 10K_0402_5%

TX_N LED_0 39 2 LDO@ 1
CL11 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P1 30
Atheros LED_1 23
mount RL12 if use LDO modue
<15> PCIE_PRX_DTX_P1 TX_P LED_2
AR8151/AR8161 Place close to Pin16
36
<15> PCIE_PTX_C_DRX_N1 RX_N 12 MDI0-
TRXN0 MDI0- <28>
35 11 MDI0+
<15> PCIE_PTX_C_DRX_P1 RX_P TRXP0 MDI0+ <28>
15 MDI1-
TRXN1 MDI1- <28>
32 14 MDI1+
<15> CLK_PCIE_LAN# REFCLK_N TRXP1 MDI1+ <28>
33 18
<15> CLK_PCIE_LAN REFCLK_P TRXN2 17
PLT_RST# 2 TRXP2 21
PERST# TRXN3 20
PCIE_WAKE#_R 3 TRXP3 Place Close to PIN1
RL7 1 @ 2 0_0402_5% WAKE#
<32> LAN_WAKE# +3V_LAN
25 10 LAN_RBIAS 1 2
RL9 1 2 4.7K_0402_5% 26 SMCLK RBIAS RL8 2.37K_0402_1%
+3V_LAN SMDATA
@ Place Close to PIN1
28 1 +3V_LAN
NC VDD33
Vendor recommand reseve the 27
CL12
CL13
CL14
CL15
CL16
1000P_0402_50V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V4Z
1U_0402_6.3V4Z
TESTMODE 1 1 1 1
2
PU resistor close LAN chip 40 +LX
LX +LX
LAN_XTALO 7 @
XTLO 2 2 2 2 don't @ (could be B C cost done)
1
LAN_XTALI 8 RL10 30K_0402_5%
RL11 1 @ 2 4.7K_0402_5% XTLI 5 +1.7_VDDCT 1 2
+3V_LAN VDDCT/ISOLAN +3V_LAN
<15> CLKREQ_LAN# 4
CLKREQ# 24 @ @
B DVDDL/PPS 37 +LX_R B
+1.1_AVDDL 13 DVDDL_REG/DVDDL
+1.1_AVDDL 19 AVDDL +2.7_AVDDH
+1.1_AVDDL 31 AVDDL 16 +3V_LAN
+1.1_AVDDL_L 34 AVDDL AVDDH/AVDD33 22 +2.7_AVDDH
+1.1_AVDDL 6 AVDDL AVDDH 9 +2.7_AVDDH
AVDDL_REG/AVDDL AVDDH_REG
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
CL17
CL18
CL19
CL20
CL21
1 1 1 1 1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
41
CL22
CL23
CL24
CL25
CL26
GND 1 1 1 1 1
AR8162-BL3A-R_QFN40_5X5 @ @
2 2 2 2 2 8162@
Near 2 2 2 2 2
Pin6
@
For EMI
B Phaes change to GCLK@
Near
Near Near Near Pin9 Near Near
@
Pin13 Pin19 Pin31 RL13 1 2 0_0402_5% Pin22 Pin37
<34> GCLK_LAN_25MHZ
1
CL27
value shoud be discuss 5P_0402_50V8C
2 @
ORB 5P LAN_XTALI
A YL1 LAN_XTALO A
4 3
NC OSC
1 2
OSC NC
1 25MHZ_10PF_7V25000014 1
CL28
15P_0402_50V8J
CL29
15P_0402_50V8J
NOGCLK@
2 2 Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
NOGCLK@ NOGCLK@
Custom
4019N1 B

5 4 3 2 1
5 4 3 2 1
ESD
@
DL1
AZC099-04S.R7G_SOT23-6
Place Close to TL1 Reserve gas tube for EMI go rural solution
MDI1+ 1 4 MDI0+
I/O1 I/O3
D D
DL1
For EMI
2 5
GND VDD
1'S PN:SC300001G00
2'S PN:SC300002E00 MDI0- 3
I/O2 I/O4
6 MDI1-
RL14 CL30
1 2 1 2
CHASSIS1_GND
75_0805_5% 10P_0603_50V
2 1
TL1
For EMI
DLL1
MDI0+ 1 16 MDO0+ BS4200N-C-LV_SMB-F2
<27> MDI0+ TD+ TX+
MDI0- 2 15 MDO0- GAS@
<27> MDI0- TD- TX-
3 14 MCT
4 CT CT 13
NC NC
5
NC NC
12 Place Close to TL1
6 11 MCT
C
MDI1+ 7 CT CT 10 MDO1+
C
1 <27> MDI1+ RD+ RX+
MDI1- 8 9 MDO1-
For EMI
<27> MDI1- RD- RX-
12/12 Change BOM Structure of CL31 from @ to CL31
0.01U_0402_16V7K
mount(EMI request) 2 MHPC_NS681612A
CL63 1 2 0.1U_0603_50V7K
CHASSIS1_GND
JLAN1
MCT 8
PR4-
MCT 7
PR4+
B B
MDO1- 6
PR2-
MCT 5
PR3-
MCT 4
PR3+
MDO1+ 3
PR2+
MDO0- 2
PR1-
MDO0+ 1
PR1+
10
SHLD1
9
SHLD2
PS_HPKR0125-08A1A0R
ME@
CHASSIS1_GND
A A

4019N1 B

5 4 3 2 1
5 4 3 2 1
2 Channel
D D
SMSC thermal sensor

placed near VRAM
+3VS
U9
1 8 EC_SMB_CK2
VDD SCLK EC_SMB_CK2 <15,32>
1
REMOTE1+ 2 7 EC_SMB_DA2
D+ SDATA EC_SMB_DA2 <15,32>
C587
2200P_0402_50V7K REMOTE1- 3 6
@ 2 D- ALERT#
C +3VS 1 R335 2 4 5 C
THERM# GND
4.7K_0402_5%
@ EMC1402-2-ACZL-TR MSOP 8P
Address is 1001100xb
REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"
B B
MINI WLAN VGA CPU

H1 H2 H4 H5 H6 H7
H_3P3 H_3P3 H_3P3 H_3P8 H_3P8 H_3P8 FD1 FD2 FD3 FD4
1
1
FAN1 Conn
+5VS
@
R581
JFAN1 11/20 Change symbol of JFAN1 to SP020008X00
2 1 1
2 1 H14 H15 H19 H20 H22 H23
0_0603_5%
<32>
<32> EC_TACH
EC_FAN_PWM 3 2
3
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 R
4 H16 H24 H25
5 4 H_3P0X4P0N H_3P0N H_3P0N
2 G5
6
G6
1
1
C591
10U_0603_6.3V6M ACES_85205-04001
1
1
ME@
SP020008X00
A E A
M/B 圓孔
M/B 橢圓孔

Custom
4019N1 B

5 4 3 2 1
A B C D E F G H
SATA HDD Conn.

Near Connector
JHDD1
1
0.01U_0402_25V7K 2 1 C184 SATA_ITX_DRX_P0 2 GND
<14> SATA_ITX_C_DRX_P0 RX+
<14> SATA_ITX_C_DRX_N0 0.01U_0402_25V7K 2 1 C185 SATA_ITX_DRX_N0 3
4 RX-
SATA_DTX_C_IRX_N0 C596 1 2 0.01U_0402_25V7K SATA_DTX_IRX_N0 5 GND
<14> SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 C597 1 2 0.01U_0402_25V7K SATA_DTX_IRX_P0 6 TX-
<14> SATA_DTX_C_IRX_P0 7 TX+
GND
1 1
R551 0_0805_5% 8
1 2 +3VS_HDD 9 3.3V 26
+3VS 3.3V boss
10 25
@ 11 3.3V boss
12 GND 24
13 GND GND 23
R550 0_0805_5% 14 GND GND
1 2 +5VS_HDD 15 5V
+5VS 5V
16
@ 17 5V
18 GND
19 Rsv
20 GND
21 12V
+5VS_HDD 22 12V
12V
Near HDD LCN_ASF98-2231S10-0002
1 1 1 ME@
@
C598 C599 C602
1000P_0402_50V7K 0.1U_0402_16V4Z 10U_0603_6.3V6M
2 2 2
ODD Power Control 1/16 Change footprint of JHDD1 from SANTA_191501-1_22P to

LCN_ASF98-2231S10-0002_22P (DC010005W00 toDC010009C00)
2 2
@ J9
1 2
1 2 +5V_ODD FOR 15"
+5VALW +5VS JUMP_43X79
SATA ODD FFC Conn.
Near Connector
3 1 JODD2
S
1
1
1
Q99 <14> SATA_ITX_C_DRX_P2 SATA_ITX_C_DRX_P2 15@ C605 1 2 0.01U_0402_25V7K SATA_ITX_DRX_P2_15 2

R552 @ PMV65XP_SOT23-3~D SATA_ITX_C_DRX_N2 15@ C606 1 2 0.01U_0402_25V7K SATA_ITX_DRX_N2_15 3 2
G
<14> SATA_ITX_C_DRX_N2 3
2
R568 10K_0402_5% @ 4
10K_0402_5% R675 SATA_DTX_C_IRX_N2 R403 1 15@ 2 0_0402_5% SATA_DTX_IRX_N2_15 5 4
@ 100K_0402_5% <14> SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 R404 1 15@ 2 0_0402_5% SATA_DTX_IRX_P2_15 6 5
1 <14> SATA_DTX_C_IRX_P2 6
2
1 2 1 2 ODD_DETECT# 7
@ C608 R710 @ 0_0402_5% +5V_ODD 8 7
8
1
1 10U_0603_6.3V6M 9
2 ODD_DA# 10 9
OUT
@ C607 <32> ODD_DA# 10 11

GND 12
0.01U_0402_25V7K GND
2 2 1 R555 2
<19> ODD_EN IN +3VS
10K_0402_5% ACES_88058-100N
GND
@ ME@
Q100
DTC124EKAT146_SC59-3
SP010016C00
3
@ 11/20 Change symbol of JODD2 to SP010016C00
3 3
Co-lay
FOR 14"
SATA ODD Conn.
Near Connector JODD1
1
SATA_ITX_C_DRX_P2 14@C616 1 2 0.01U_0402_25V7K SATA_ITX_DRX_P2_14 2 GND
SATA_ITX_C_DRX_N2 14@C615 1 2 0.01U_0402_25V7K SATA_ITX_DRX_N2_14 3 A+
4 A-
SATA_DTX_C_IRX_N2 14@C614 1 2 0.01U_0402_25V7K SATA_DTX_IRX_N2_14 5 GND
SATA_DTX_C_IRX_P2 14@C613 1 2 0.01U_0402_25V7K SATA_DTX_IRX_P2_14 6 B-
7 B+
GND
ODD_DETECT# 8
+5V_ODD 9 DP
10 +5V 14
ODD_DA# 11 +5V GND 15
12 MD GND 16
13 GND GND 17
GND GND
4 SANTA_202801-1 4
ME@

Custom
4019N1 B

A B C D E F G H
5 4 3 2 1
CX20757 Sense resistors must be

connected same power
High Definition Audio Codec SoC that is used for VAUX_3.3
With Integrated Class-D Stereo
RA5 1 2 5.11K_0402_1%
Amplifier. +3VS
An integrated 5 V to 3.3 V Low-dropout RA6 10K_0402_1%

mount RA6 on the Jack Sense circuit
voltage regulator (LDO). 1 2 to configure Port-C for mono MIC.
An integrated 3.3 V to 1.8V Low-dropout JSENSE RA7 1 2 20K_0402_1%

voltage regulator (LDO). RA8 1 2 39.2K_0402_1% PLUG_IN
PLUG_IN <33>
+VREF_1V65 CA3 vendor suggest For Universal jack
D
For no Speaker Hum Noise feature change to 2.2U Don't support LINE_IN function D
+LDO_OUT_3.3V
RA7 could be @
RA11 1 @ 2 0_0402_5% +3V_AVDD_HP
1U_0603_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
+3VLP
1 1 2 1 AVDD_3.3 pinis output of
RA10 1 @ 2 0_0402_5%
CA1
CA2
CA4
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
+3V_PCH internal LDO. NOT connect
CA3
1 1 to external supply.
CA5
CA6
2 2 1 2
2 @ 2
+3VS
+3VS
1U_0603_10V4Z
1U_0603_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1
CA8
CA9
1 1
@
CA15
CA10
Should be same supply rail as used for 2 2
@
PCH HDA bus controller section Layout Note:Path from +5VS to LPWR_5.0
2 2
RPWR_5.0 must be very low
resistance (<0.01 ohms)
RA3
+3VS 1 @ 2 0_0402_5% +VDDIO_HDA
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
+LDO_1.8V +5VS
+3V_PCH RA4 1 @ 2 0_0402_5% 1 1
CA16
CA17
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
+5VS
1 1
10 mils
CA18
CA19
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@ 2 2
1 1 1 1
@
CA20
CA21
CA22
CA23
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
2 2
1 1
For EMI
@
CA24
CA25
2 2 2 2
0.1U_0402_16V4Z
C @ 2 2 For Layout C
1
18
29
27
28
24
3
7
2
CA7 @ UA1
CA26
1 RA21 2 For Layout
VDD_IO
VREF_1.65V
AVDD_5V
FILT_1.8
VDDO_3.3
DVDD_3.3
AVDD_3.3
AVDD_HP
Please bypass caps very close to device.
22P_0402_50V8J 33_0402_5% 13 2
LPWR_5.0 16
HDA_RST_AUDIO# 9 RPWR_5.0 11
<14> HDA_RST_AUDIO# RESET# CLASS-D_REF
HDA_BITCLK_AUDIO 5
<14> HDA_BITCLK_AUDIO BIT_CLK
HDA_SYNC_AUDIO 8 38 JSENSE
For EMI
<14> HDA_SYNC_AUDIO SYNC JSENSE
RA9 1 2 33_0402_5% HDA_SDIN0_R 6
<14> HDA_SDIN0 SDATA_IN
HDA_SDOUT_AUDIO 4 34 +MICBIASB HGNDA, HGNDB 80mils
<14> HDA_SDOUT_AUDIO SDATA_OUT MICBIASB 35 +MICBIASC
MICBIASC
PC_BEEP 10 32 MICB_L
39 PC_BEEP PORTB_L_LINE 33 MICB_R 1 2 CA28 1 2 2.2U_0402_6.3V6M
<32> EC_MUTE# SPKR_MUTE# PORTB_R_LINE Universal Jack APPLE_MIC
NOKIA_MIC
RA16
RA12 1 2
100_0402_1%
100_0402_1% CA27 1 2 2.2U_0402_6.3V6M
HGNDB
HGNDA
HGNDB <33>
HGNDA <33>
30 APPLE_MIC External MIC HP_L RA13 1 2 15_0402_5% HPOUT_L
PORTD_A_MIC HPOUT_L <33>
31 NOKIA_MIC HP_R RA14 1 2 15_0402_5% HPOUT_R
PORTD_B_MIC HPOUT_R <33>
1 25 HGNDA
For EMI
40 DMIC_DAT/GPIO1 HGNDA 26 HGNDB
DMIC_CLK / MUSIC_REQ/GPIO0 HGNDB
Internal analog MIC MIC_IN 36

37 MUSIC_REQ/GPIO0/PORTC_L_MIC PORTA_L
22
23
HP_L
For Universal jack
GPIO1/PORTC_R_MIC PORTA_R
HP_R Headphone
CA64 1 2 0.1U_0402_16V7K
SPK_L2+ 12
CA65 1 2 0.1U_0402_16V7K SPK_L1- 14 LEFT+ CA36
LEFT- MICB_L RA17 1 2 100_0402_1% 1 2 HP_L
CA66 1 2 0.1U_0402_16V7K
Internal SPEAKER SPK_R2+ 17 AVEE
21
19 CA46
2.2U_0402_6.3V6M
SPK_R1- 15 RIGHT+ FLY_P 20 1 2 MICB_R RA18 1 2 100_0402_1% 1 2 HP_R
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
RIGHT- FLY_N CA29 1U_0603_10V4Z 2.2U_0402_6.3V6M
1 2
RA20 1 2 3K_0402_5%
CA35
CA30
GND
+MICBIASB RA19 1 2 3K_0402_5%

B
CX20751-11Z_QFN40 2 1 B
41
12/12 Change BOM Structure of CA64~CA66 from @ to

mount(EMI request)
follow vendor suggest

& reserver default design
LA1 LA2
0_0603_5% 0_0603_5% 11/20 Change symbol of JSPK1 to SP02000H700
@ @
LA3 LA4
PC Beep 0_0603_5% 0_0603_5%
wide 40MIL
@ @ JSPK1
6
GND2
EC Beep 1 2 RA492
5
GND1
<32> BEEP#
CA37 0.1U_0402_16V4Z 1 2 PC_BEEP SPK_R1- LA1 1 2
FBMA-L11-160808-121LMT_0603 SPK_R1-_CONN 4
1 2 33_0402_5% SPK_R2+ LA2 1 2
FBMA-L11-160808-121LMT_0603 SPK_R2+_CONN 3 4
<14> HDA_SPKR 3
ICH Beep CA45 0.1U_0402_16V4Z
Place colose to Codec chip
SPK_L1-
SPK_L2+
LA3
LA4
1
1
2
FBMA-L11-160808-121LMT_0603
2
FBMA-L11-160808-121LMT_0603
SPK_L1-_CONN
SPK_L2+_CONN
2
1 2
1
For EMI
1
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
SP02000H700
RA22 +MICBIASC +5VS ME@
1 1 1 1
10K_0402_5% ESD ACES_88231-04001
CA38
CA39
CA40
CA43
@
2
DA3
For EMI
RA23 2 2 2 2 SPK_R1-_CONN 6 3 SPK_L2+_CONN
I/O4 I/O2
2.2K_0402_5%
2
MIC1 CA41 1U_0603_10V4Z 5 2

1 EXT_MIC 1 2 MIC_IN VDD GND
A A
2 GNDA
1 1
WM-64PCY_2P SPK_R2+_CONN 4 1 SPK_L1-_CONN
0.1U_0402_16V4Z
0.1U_0402_16V4Z
MIC@ I/O3 I/O1

AZC099-04S.R7G_SOT23-6
2 2
CA42
CA44
@ @
Custom
4019N1 B

5 4 3 2 1
+3VALW
+3VLP
R416
R304
2 1 +3V_EC 1 2
0_0603_5% @ 1
@ 0_0603_5% C535
100P_0402_50V8J
@
Vcc 3.3V
2
L44
FBM-11-160808-601-T_0603 1 1 1 1
R694 100K +/- 1%
1 2 +EC_VCCA Board ID R695 VAD_BID min V AD_BID typ VAD_BID max EC AD
0.1U_0402_16V4Z
C653
0.1U_0402_16V4Z
C654
1000P_0402_50V7K
C657
1000P_0402_50V7K
C658
+3V_EC +EC_VCCA
1 @ @
C656 2 2 2 2 0 0 0 V 0 V 0.300 V 0x00 - 0x0B MP

1 12K +/- 1% 0.347 V 0.354 V 0.360 V 0x0C - 0x1C PVT
111
125
0.1U_0402_16V4Z U31
22
33
96
67
2 ECAGND
9
1 2
L45
2 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1D - 0x26 DVT
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
EC_VDD0
FBM-11-160808-601-T_0603
ECAGND
3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x27 - 0x30 EVT
1 21 ADP_65
<19> GATEA20 GATEA20/GPIO00 GPIO0F ADP_65 <38>
2 23 BEEP#
<19> KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# <31>
3 26 EC_FAN_PWM +3VALW
<14> SERIRQ SERIRQ GPIO12 EC_FAN_PWM <29>
4 27 ACOFF
<14> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF <39>
LPC_AD3 5
<14> LPC_AD3 LPC_AD3
2
LPC_AD2 7 PWM Output
<14> LPC_AD2 LPC_AD2
LPC_AD1 8 63 BATT_TEMP
<14> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP <37,38>
LPC_AD0 10 LPC & MISC 64 GPU_IMON R694
<14> LPC_AD0 LPC_AD0 GPIO39 GPU_IMON <44>
2 1 2 1 65 ADP_I +5VALW 100K_0402_1%
ADP_I/GPIO3A ADP_I <38,39>
@ C660 22P_0402_50V8J @ R589 10_0402_5% 12 AD Input 66 ADP_ID
<18> CLK_PCI_EC CLK_PCI_EC GPIO3B ADP_ID <37>
1
13 75 BRDID BRDID
<18,26,27> PLT_RST# PCIRST#/GPIO05 GPIO42
1 2 EC_RST# 37 76
+3V_EC EC_RST# IMON/GPIO43 ENBKL <17>
2
R590 47K_0402_5% EC_SCI# 20 R695
<19> EC_SCI# EC_SCII#/GPIO0E
2 BATT_LEN# 38 R594 @
<38> BATT_LEN# GPIO1D
1 68 ADP_90 USB_ON# 1 2 R695
DAC_BRIG/GPIO3C ADP_90 <38>
C661 C47 70 12K_0402_1%
EN_DFAN1/GPIO3D
0.1U_0402_16V4Z
1
DA Output IREF/GPIO3E
71 10K_0402_5%
1
100P_0402_50V8J KSI0 55 72 +3VALW
2 KSI1 56 KSI0/GPIO30 CHGVADJ/GPIO3F HM70@
KSI2 57 KSI1/GPIO31 EC_MUTE# 1 R593 2 10K_0402_5% 27K_0402_1%
KSO[0..17] KSI3 58 KSI2/GPIO32 83
<33> KSO[0..17] KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <31>
KSI4 59 84 USB_ON#
KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# <33,35>
<33> KSI[0..7]
KSI[0..7] ESD KSI5 60
KSI5/GPIO35 CAP_INT#/GPIO4C
85 ADP_135
ADP_135 <38>
KSI6 61 PS2 Interface 86 SYS_PWROK_R R417 1 2 0_0402_5%
KSI6/GPIO36 EAPD/GPIO4D SYS_PWROK <16>
KSI7 62 87 TP_CLK @
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <33> +5VS
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <33>
KSO1 40
KSO2 41 KSO1/GPIO21 TP_CLK R603 1 2 4.7K_0402_5%
KSO3 42 KSO2/GPIO22 97 EC_TS_ON# TP_DATA R598 1 2 4.7K_0402_5%
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 EC_TS_ON# <35>
KSO4 43 98
44 KSO4/GPIO24 WOL_EN/GPXIOA01 99
KSO5/GPIO25 Int. K/B
KSO5 ME_FLASH
HDA_SDO/GPXIOA02 ME_FLASH <14>
KSO6 45 109
46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 NTC_V <38>
+3V_EC
KSO7
KSO7/GPIO27 SPI Device Interface
KSO8 47
48 KSO8/GPIO28 119 1 2
1
R600
2 EC_SMB_CK1
KSO9
KSO10 49 KSO9/GPIO29 SPIDI/GPIO5B 120
EC_SPI_SO
EC_SPI_SI
EC_SPI_SO <14> 10/26 Add(Reserve for SPI ROM Interface share) BATT_TEMP
C663 100P_0402_50V8J
KSO10/GPIO2A SPIDO/GPIO5C EC_SPI_SI <14>
2.2K_0402_5% KSO11 50 SPI Flash ROM 126 EC_SPI_CLK ACIN 1 2
KSO11/GPIO2B SPICLK/GPIO58 EC_SPI_CLK <14>
R604 KSO12 51 128 EC_SPI_CS# C664 100P_0402_50V8J
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS# <14>
1 2 EC_SMB_DA1 KSO13 52
2.2K_0402_5% KSO14 53 KSO13/GPIO2D 3/20 Add (ESD request) 1 R522 2
KSO15 54 KSO14/GPIO2E 73 4.7K_0402_5%
KSO15/GPIO2F ENBKL/GPIO40 IMVP_IMON <44>
KSO16 81 74 VGATE @
KSO16/GPIO48 PECI_KB930/GPIO41 VGATE <16,44> +5VS
KSO17 82 89
KSO17/GPIO49 FSTCHG/GPIO50 LAN_PWR_ON# <27>
90 BATT_CHG_LED#
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# <33>
91 CAPS_LED# 2
CAPS_LED#/GPIO53 CAPS_LED# <33>
EC_SMB_CK1 77 GPIO 92
<38,39> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# <33>
+3VALW EC_SMB_DA1 78 93 BATT_LOW_LED# C851
<38,39> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# <33>
EC_SMB_CK2 79 SM Bus 95 SYSON 0.1U_0402_16V4Z
<15,29> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <41> 1
EC_SMB_DA2 80 121
<15,29> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <44>
127 PM_SLP_S4# <16>
1 2 LAN_WAKE# PM_SLP_S4#/GPIO59
R606 10K_0402_5% H_PROCHOT# <37,44,6>
6 100
<16> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <16>
14 101 EC_LID_OUT#
<16> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <19> D
1
EC_SMI# 15 102 Turbo_V 1
<16,19> EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 Turbo_V <38>
16 103 PROCHOT 2
<23> CMOS_ON# GPIO0A H_PROCHOT#_EC/GPXIOA06 PROCHOT <38>
+3VS 17 104 MAINPWON_R R738 1 2 0_0402_5% G C493
GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON <40>
18 GPO 105 BKOFF# @ Q37 S 47P_0402_50V8J
GPIO0C BKOFF#/GPXIOA08 BKOFF# <23> 2
3
ODD_DA# 19 GPIO 106 PBTN_OUT# 2N7002H_SOT23-3
<30> ODD_DA# GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# <16>
ADP_ID_CLOSE 25 107 PCH_PWR_EN
<37> ADP_ID_CLOSE EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 PCH_PWR_EN <20>
1 2 EC_TACH EC_TACH 28 108 SA_PGOOD <42>
<29> EC_TACH FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
R605 10K_0402_5% LAN_WAKE# 29
<27> LAN_WAKE# EC_PME#/GPIO15
EC_TX 30 +3VALW
<26> EC_TX EC_TX/GPIO16
EC_RX 31 110 ACIN
<26> EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <16,37,39>
PCH_PWROK 32 112 EC_ON
<16> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <40>
NOVO# 34 114 ON/OFF <33>
<33> NOVO# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03
2 1 NUM_LED# 36 GPI 115 LID_SW# LID_SW# 1 R618 2
<33> NUM_LED# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <33>
@ R608 116 SUSP# 100K_0402_5%
SUSP#/GPXIOD05 SUSP# <36,41,43> +V1.05S_VCCP
10K_0402_5% 117 NUVOTON_VTT
GPXIOD06 118 PECI_KB9012 1 2
PECI_KB9012/GPXIOD07 H_PECI <6>
122 R669 43_0402_1% NUVOTON_VTT R410 1 @ 2 0_0402_5%
AGND/AGND
<16> SUSCLK XCLKI/GPIO5D

DGPU_PWR_EN 123 124 +V18R
GND/GND
GND/GND
GND/GND
GND/GND
<18> DGPU_PWR_EN XCLKO/GPIO5E V18R
C667
4.7U_0603_6.3V6K 1
1
GND0
1
R740 C93
100K_0402_5% 20P_0402_50V8 KB9012QF A4 LQFP 128P_14X14 2
2
11
24
35
94
113
69
@ @
2
ECAGND
EMC Request
SYSON
PN : SA00004OB20 S IC KB9012QF A3 LQFP 128P KB CONTROLLER
0.1U_0402_10V6K
C492
1
@
2

4019N1 B

+3VLP
Key Board Conn. KSI[0..7]
PWR Button For Debug

KSI[0..7] <32>
KSO[0..17]
KSO[0..17] <32>
For 15" For 14"
2
R415
100K_0402_5%
@ @
JKB1
1 R414 2
1
KSI1 1 JKB2
0_0402_5% KSI7 2 1 KSI1 1
KSI6 3 2 KSI7 2 1
KSO9 4 3 KSI6 3 2
+3VALW KSI4 5 4 KSO9 4 3
KSI5 6 5 KSI4 5 4
+3VLP KSO0 7 6 KSI5 6 5
7 6
2
KSI2 8 KSO0 7
R642 KSI3 9 8 KSI2 8 7
9 8
2
100K_0402_5% KSO5 10 KSI3 9

KSO1 11 10 KSO5 10 9
R701 KSI0 12 11 KSO1 11 10
12 11
1
100K_0402_5% D26 +3VS KSO2 13 KSI0 12
NOVO# 2 KSO4 14 13 KSO2 13 12
<32> NOVO# 14 13
1
1 NOVO_BTN# KSO7 15 KSO4 14

ON/OFF 3 KSO8 16 15 KSO7 15 14
KSO6 17 16 KSO8 16 15
17 16
1
KSO3 18 KSO6 17
ON/OFF DAN202UT106_SC70-3 R745 R744 KSO12 19 18 KSO3 18 17
ON/OFF <32> 19 18
300_0402_5% 300_0402_5% KSO13 20 KSO12 19
15@ KSO14 21 20 KSO13 20 19
KSO11 22 21 KSO14 21 20
22 21
2
KSO10 23 KSO11 22
KSO15 24 23 KSO10 23 22
KB1 25 24 KSO16 R747 1 15@ 2 0_0402_5% KSO15 24 23
KB2 26 25 KB_LED_PWR R746 1 14@ 2 0_0402_5% KB1 25 24
KB_LED_PWR 27 26 KSO17 R748 1 15@ 2 0_0402_5% KB2 26 25
28 27 CAPS_LED# R749 1 14@ 2 0_0402_5% 26 27
<32> CAPS_LED# 28 GND2
KB_LED_PWR_2 29 31 28
30 29 GND 32 GND1
<32> NUM_LED# 30 GND
ACES_88514-3001 ACES_88514-02601-071
ME@ ME@
SP010011A00
11/20 Change symbol of
JKB1 to SP010011A00
IO/B Conn.
For EMI
Ext. USB2.0 R868 2 @ 1 0_0402_5%
+3VS
JIO1
14 16
L66 USB20_N11 13 14 G2 15
<18> USB20_N11 13 G1
USB20_N9 4 3 USB20_N9_R USB20_P11 12
<18> USB20_N9 4 3 +USB_VCCB <18> USB20_P11 12
W=80mils USB20_N9_R
11
10 11
USB20_P9 1 2 USB20_P9_R USB20_P9_R 9 10
<18> USB20_P9 1 2 9
+USB_VCCB 8
+5VALW +USB_VCCB 8
2
WCM-2012-900T_4P @ @ 1 7
R503 R504 C714 6 7
1 6
U36 10_0402_5% 10_0402_5% + HPOUT_L 5
<31> HPOUT_L 5
1 8 R869 2 @ 1 0_0402_5% 220U_6.3V_M C715 HPOUT_R 4
GND VOUT <31> HPOUT_R 4
2 7 470P_0402_50V7K HGNDA 3
VIN VOUT 2 2 <31> HGNDA 3
1
3 6 HGNDB 2
VIN VOUT <31> HGNDB 2
4 5 1 1 PLUG_IN 1
<32,35> USB_ON# EN FLG USB_OC4# <18> <31> PLUG_IN 1
@ @ 6.3Φ * 5.9
G547I2P81U_MSOP8 C701 C702 SF000001500 ACES_85202-1405N
1.2P_0402_50V8C 1.2P_0402_50V8C ME@
2 2
11/30 Change U36 symbol & PN from SA00003XM00 to SA00003TV00
TP Switch & TP Conn. LED PWR/B Conn.

+5VS LED1 14@
JPWRB1
<32> PWR_LED# PWR_LED# 1 2 2 R623 1 +3VALW 1
300_0402_5% 2 1
NOVO_BTN# 3 2
14@ 3
JTP1 19-213A-T1D-CP2Q2HY-3T_WHITE ON/OFF 4
8 5 4
7 GND LED2 14@ 6 5
GND 6
2
6 <32> BATT_LOW_LED# BATT_LOW_LED# 1 2 2 R764 1 +3VALW 7
TP_CLK 5 6 470_0402_5% 8 GND
<32> TP_CLK 5 GND
TP_DATA 4 D24
<32> TP_DATA 4 14@
TP_3 3 19-217-S2C-FM2P1VY-3T_ORANGE ACES_88058-060N
TP_2 2 3 L30ESD24VC3-2 3P C/A SOT-23 ME@
2
1
TP_1 1 LED5 14@ SP010010T00
1
SP010010T00 <32> BATT_CHG_LED# BATT_CHG_LED# 1 2 2 R765 1 +3VALW 11/20 Change symbol of
300_0402_5%
C490
C491
0.1U_0402_10V6K
0.1U_0402_10V6K
ME@ JPWRB1 to SP010010T00

1 1 ACES_88058-060N 14@
15@ 19-213A-T1D-CP2Q2HY-3T_WHITE ESD
2 R627 1 TP_3
Lid SW(For 14")

0_0402_5% @ @
2 2
2 R619 1 14@ TP_1 11/20 Change symbol of +3VALW
0_0402_5%
JTP1 to SP010010T00
L R LED/B Conn.
2
JLED1 1
VDD
SW4 14@ SW5 14@ 1
SMT1-05_4P SMT1-05_4P
15" 14" +3VALW
LID_SW# 2 1
14@
C551
2
5
6
5
6
3 LID_SW# 3 0.1U_0402_16V4Z
3 <32> LID_SW# OUTPUT 2
4 2 4 2 PWR_LED# 4
TP_3 TP_2
1 VCC 1 VCC BATT_LOW_LED# 5 4
GND
3 1 3 1 BATT_CHG_LED# 6 5
6 2
2 CLK 2 CLK 7
C550
14@
GND
1
8 10P_0402_50V8J
GND 1
3 DAT 3 DAT ACES_88058-060N
ME@ 11/30 Change PN of U40 from
4 GND 4 L SP010010T00 SA000031C00 to SA00005LN00 14@ U40
For 15" 12/4 Change symbol of

SW6 15@ SW7 15@ S-5712ACDL2-M3T1U_SOT23-3
SMT1-05_4P SMT1-05_4P
JLED1 to SP010010T00
5
6
5
6
4 2 4 2
5 L 5 R
Compal Electronics, Inc.
TP_2 TP_1
3 1 3 1 Security Classification Compal Secret Data
GND
6 R 6 Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
C
4019N1 B

A B C D E
For UMA Every power trace need:

U71 GCLK244@
W=20mils
1 1
SLG3NB244VTR_TQFN16_2X3
For GreenCLK generate CLK:
+CHGRTC_R Mount: All parts in this page except
+RTCBATT
Swing Level RES (Marked "*")
1
+3VLP RG12
NA: PD108,
2
390_0402_5%
GCLK@ RG10 @
0_0402_5% Y1,R98,C180,C181,
2
+V1.05S_VCCP +3V_LAN +3V_LAN
1 Y2,R169,C196,C197,
1
CG3 GCLK@
22U_0805_6.3V6M Y6,C968,C969
+GCLK_VBAT
@ 1 1
For DIS
2
1
CG2
GCLK@ RG8
CG4
0.1U_0402_16V7K
2.2U_0402_6.3V6M
0_0402_5%
2 U71 2 GCLK@
1
RG11
For EMI
2
0_0402_5% 10 14
2
GCLK@ VBAT VDD_RTC_OUT 2
@ 1 15
+V3.3A
2
CG5 @
2 1 +3VS_GCLK 2
0.1U_0402_16V7K
VDD
PCH_32.768K
@ 1 CG1 9 GCLK_32K_R RG1 1 2 0_0402_5% GCLK_32K
2 32kHz GCLK_32K <14>
CG7 0.1U_0402_16V7K GCLK@
0.1U_0402_16V7K
11 12
2 VDDIO_27M 27MHz
8
VDDIO_25M_A 25MHz_A
6 GCLK_LAN_25MHZ_R RG3 1
GCLK@
2 0_0402_5% GCLK_LAN_25MHZ
GCLK_LAN_25MHZ <27> LAN
PCH_GCLK 3
VDDIO_25M_B 25MHz_B
5 GCLK_PCH_25MHZ_R RG4 1
GCLK@
2 0_0402_5% GCLK_PCH_25MHZ
GCLK_PCH_25MHZ <15> PCH_25M
Close to GCLK
GREENCLK_XTALI 1
Y8 GREENCLK_XTALO 16 XTAL_IN
4 3 XTAL_OUT
GND1
GND2
GND3
GND4
NC OSC
1 2
OSC NC
SLG3NB304VTR_TQFN16_2X3
4
7
13
17
1 GCLK@ 1
GCLK@ CG8 25MHZ_10PF_7V25000014 GCLK@ CG9 GCLK304@
15P_0402_50V8J 15P_0402_50V8J
2 2
3 3
Reserved for Swing Level adjustment

( Close GCLK side )
GCLK_LAN_25MHZ RG6 *1 @
2 0_0402_5%
RG7 * 1
@
GCLK_PCH_25MHZ 2 0_0402_5%
4
For EMI 4

B
4019N1 B

A B C D E
5 4 3 2 1
Touch Screen
+3VS +3VS_TS
1 TS@ 2
R799 0_0402_5% +3VS_TS
JTS1
D 1 D
3 1 2 1
D
3 2
<18> USB20_N2 3
4
<18> USB20_P2 4
R798 @ Q156 5
G
5
2
100K_0402_5% PMV65XP_SOT23-3 EC_TS_ON# R726 1 TS@ 2 0_0402_5% TS_RST# 6
1 2 @ 7 6
0.1U_0402_16V7K
<32> EC_TS_ON# GND
1 2 8
GND
C669 @ C668 ACES_50208-00601-P01
0.1U_0402_16V7K TS@ ME@
2 1
SP010013W10
11/20 Change symbol of
JTS1 to SP010013W10
USB3.0
2A/Active Low ESD
+5VALW +USB3_VCCA
D27 D30 D22 D31
@ @ @ @
U35 W=80mils U3RXDN1 9 10 1 1U3RXDN1 U3RXDN2 9 10 1 1U3RXDN2 U2DN1 3
I/O2 I/O4
6 U2DP2 3
I/O2 I/O4
6
1 8
2 GND VOUT 7 U3RXDP1 8 9 2 2U3RXDP1 U3RXDP2 8 9 2 2U3RXDP2
3 VIN VOUT 6
4 VIN VOUT 5 U3TXDN1 7 7 4 4U3TXDN1 U3TXDN2 7 7 4 4U3TXDN2 2 5 2 5
<32,33> USB_ON# EN FLG USB_OC0# <18> GND VDD +5VALW GND VDD +5VALW
C C
G547I2P81U_MSOP8 U3TXDP1 6 6 5 5U3TXDP1 U3TXDP2 6 6 5 5U3TXDP2
11/30 Change U35 symbol & PN from 3 3 3 3 1 4 U2DP1 1 4 U2DN2

I/O1 I/O3 I/O1 I/O3
SA00003XM00 to SA00003TV00 1
1 C735 8 8
+ AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6
C736 470P_0402_50V7K
220U_6.3V_M @ YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9
SF000002Y00 2 2
For EMI
For EMI
Intel_PCH_USB2.0 Intel_PCH_USB2.0
B B
WCM-2012-900T_4P WCM-2012-900T_4P
1 2 U2DN1 1 2 U2DN2
<18> USB20_N0 1 2 <18> USB20_N1 1 2
4 3 U2DP1 4 3 U2DP2
<18> USB20_P0 4 3 <18> USB20_P1 4
USB2@ USB2@ 3
L51 L55
Left Ext.USB Conn. 1

Intel_PCH_USB3.0 Left Ext.USB Conn. 2
WCM-2012-900T_4P +USB3_VCCA Intel_PCH_USB3.0
1 2 U3RXDN1 WCM-2012-900T_4P +USB3_VCCA
<18> USB3_RX1_N 1 2
W=80mils <18> USB3_RX2_N
1
1 2
2 U3RXDN2
4 3 U3RXDP1 JUSB1
W=80mils
<18> USB3_RX1_P 4 3
USB3@ U3TXDP1 9 4 3 U3RXDP2 JUSB2
SSTX+ <18> USB3_RX2_P 4
L50 1 USB3@ 3 U3TXDP2 9
U3TXDN1 8 VBUS L54 1 SSTX+
U2DP1 3 SSTX- U3TXDN2 8 VBUS
7 D+ U2DP2 3 SSTX-
U2DN1 2 GND_D 10 7 D+
U3RXDP1 6 D- GND1 11 U2DN2 2 GND_D 10
C849 4 SSRX+ GND2 12 U3RXDP2 6 D- GND1 11
.1U_0402_16V7K WCM-2012-900T_4P U3RXDN1 5 GND GND3 13 C850 4 SSRX+ GND2 12
1 2 U3TXDN1_L 1 2 U3TXDN1 SSRX- GND4 .1U_0402_16V7K WCM-2012-900T_4P U3RXDN2 5 GND GND3 13
<18> USB3_TX1_N 1 2 SSRX- GND4
USB3@ OCTEK_USB-09EAAB 1 2 U3TXDN2_L 1 2 U3TXDN2
<18> USB3_TX2_N 1 2
ME@ USB3@ OCTEK_USB-09EAAB
1 2 U3TXDP1_L 4 3 U3TXDP1 ME@
<18> USB3_TX1_P 4 3
USB3@ USB3@ 1 2 U3TXDP2_L 4 3 U3TXDP2
<18> USB3_TX2_P 4
C847 L49 USB3@ USB3@ 3
.1U_0402_16V7K C848 L53
.1U_0402_16V7K
A A
Place TX AC coupling Cap (C843~C850). Close to connector

4019N1 B

5 4 3 2 1
A B C D E
+5VALW to +5VS
+3VALW to +3VS
+5VALW +5VS +3VALW +3VS
U38
U39
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
DMN3030LSS-13_SOP8L-8 DMN3030LSS-13_SOP8L-8
8 1 8 1
7 2 7 2
C720
C721
C723
C724
1 1 1 1 1 1 1 1
6 3 @ 6 3 @
5 C722 5 C725
@ 1U_0603_10V4Z 1U_0603_10V4Z
2 @ 2 2 2@ 2 @ 2
4
+VSB +VSB
1
+3VALW
R646
150K_0402_5% R647 100U_1206_6.3V6M
470K_0402_1%
1 1 1
2
2
5VS_GATE2 R649 15VS_GATE_R
1 1 C737 C738 C739
D D
1
1
100U_1206_6.3V6M @ 100U_1206_6.3V6M
SUSP 2 Q110 82K_0402_5% C726 SUSP 2 Q111 C727 @ 2 2 2
@
G 2N7002_SOT23 0.01U_0402_25V7K G 2N7002_SOT23 0.01U_0402_25V7K
S 2 S 2
3
3
1/28 Add
2 2
+1.5V to +1.5VS
+0.75VS
+1.5V Q8 +1.5VS
1
PMV65XP_SOT23-3~D
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
R658 3 1
D
22_0603_5%
C717
C718
1 1 1
@
1 2
@ C719
G
D
2
@ 1U_0603_10V4Z
2 SUSP 2 2 2
G
S Q115
3
2N7002_SOT23
+3VALW
1
For Intel S3 Power Reduction. 100K_0402_5%
R648
R651
2
2 @ 1 1.5VS_GATE
+RTCVCC +3VLP Q112 0_0402_5%
D 1
1
3 3
SUSP# 2 C729
2
G 0.1U_0402_10V7K
R652 @ 2N7002_SOT23 S 2
3
220K_0402_5% R653
100K_0402_5%
1
SUSP
<10> SUSP
Q117
1
DTC124EKAT146_SC59-3
OUT
2
<32,41,43> SUSP# IN
GND
1
R795 @
100K_0402_5%
2
4 4

Size Document Number
Rev
Custom
4019N1 B

A B C D E
5 4 3 2 1
ADP_ID
JDCIN1
VIN AC Adapter 90W 65W
1
1
2
APDIN
1 2 APDIN1
EMI@ PL101
1 2 R(K ohm) open 10
2
3
3
4 PF101 FBCA-K5B-302540-L1-T_2P ADP_ID(V) 3.3 1.65
4 5 7A_24VDC_429007.WRML
Detection voltage >2.64 1.32~1.98
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
5
ACES_88299-0510
1
CONN@
EMI@ PC101
EMI@ PC102
EMI@ PC103
EMI@ PC104
2
2
D D
PQ102A
L2N7002DW1T1G_SC88-6
1 2 6 1
680P_0603_50V7K
+3VALW PR102 ADP_ID <32>
0.1U_0402_16V7K
750_0402_1%
A/D
1
PC108
PC109
2
PR111
2
100K_0402_5%
1 2
VIN
3
1
PR112
PQ102B
5 ADP_ID_CLOSE <32>
100K_0402_5%
4
+CHGRTC
PR103
1K_0603_5%
1 2
PD101 +3VLP
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCBATT 1
C 3 PR101 C
1K_0603_5% JRTC1 @ JRTC2 @
1 2 1 1
2 1 2 1
3 2 3 2
4 GND 4 GND
GND GND
ACES_50271-0020N-001 ACES_50271-0020N-001
RTC Battery +5VS
+3VALW
<32,44,6> H_PROCHOT#
47K_0402_1%
@
@
PR106
2
PU101A
10K_0402_1%
2N7002KDW-2N_SOT363-6
AS393MTR-E1 SO 8P OP
PR108
1
8
@
@ PC105 3 BATT_TEMP <32,38>
P
2 2 1 1 +
PQ101A
1N4148WS-7-F_SOD323-2
1
2
-
G
0.022U_0402_16V7K
1.5M_0402_5%
1
100K_0402_1%
100P_0402_50V8J
4
1
@ @
PR104
@
PD105
PR109
PC107
2
@
2
1
B @ +5VS B
H_PROCHOT#
2
47K_0402_1%
@
PR107
2N7002KDW-2N_SOT363-6
3
@
1
8
PC106 5
P
5 2 1 7 +
PQ101B
O 6 ACIN <16,32,39>
1N4148WS-7-F_SOD323-2
-
G
0.022U_0402_16V7K
4
@ PU101B
1.5M_0402_5%
@ AS393MTR-E1 SO 8P OP
PD104
PR105
@
2
A A

VILG1/G2 MB LA9902P Schematic B

5 4 3 2 1
5 4 3 2 1
VMB2 VMB
CONN@ PF201 EMI@ PL201
JBAT1 12A_65V_451012MRL FBCA-K5B-302540-L1-T_2P
SUYIN_200082GR007M229ZR
1 1 2 1 2
1 BATT+
2
2 3 EC_SMCA
3 4 EC_SMDA
4 5
5 6
6
1
7
7
1
D 8 EMI@ EMI@ D
100_0402_1%
100_0402_1%
GND 9 PC201 PC203
GND 1000P_0402_50V7K 0.01U_0402_25V7K
2
PR201
PR204
2
2
EC_SMB_CK1 <32,39>
EC_SMB_DA1 <32,39> 90W(DIS) : 6.65K 100W active 90W recovery

PH201 under CPU botten side :
65W(UMA): 1.65K 70W active 65W recovery
1
PR209
2 +3VLP CPU thermal protection at 93 +-3 degree C 20120314
CONN@
6.49K_0402_1%
1 2 +3VALW
Recovery at 56 +-3 degree C Change to +EC_VCCA from +3VLP
JBAT2 @ PR206
SUYIN_200082GR007M229ZR
6.49K_0402_1%
1
1 1 2
BATT_TEMP <32,37,38> A/D
2
2
3
PR207
10K_0402_5%
+EC_VCCA
3 4 <32,39> ADP_I
4 5
12.7K_0402_1%
5 <32> PROCHOT
1
6
6 7
10K_0402_1%
PR226
7
2
8
6.65K_0402_1%
GND 9
PR975
GND
PR221
2
<32> NTC_V
1
C C
<32> Turbo_V
1
PH201
2
100K_0402_1%_TSM0B104F4251RZ
PR222
5.9K_0402_1%
2
10K_0402_1%
25.5K_0402_1%
1
1
9.31K_0402_1%
PR974
1
1
PR972
PR973
VL +3VALW
2
2
ECAGND
2N7002KDW-2N_SOT363-6
2
2N7002KDW-2N_SOT363-6
VL
6
PR214
D
2
1
PC202 PR211 100K_0402_1% 2 PQ207
1
2 2N7002KW_SOT323-3
PQ206A
G
6 1
1
0.01U_0402_25V7K 100K_0402_1% 5
PQ206B
BATT_OUT <39> S
3
PR202 PR210
2
1
2
75K_0402_1% 47K_0402_1%
4
PQ202A
2 L2N7002DW1T1G_SC88-6
2
PC208
1
1
8
0.068U_0402_16V7K~N
<32,37,38> BATT_TEMP 3 PQ202B <32> ADP_65 ECAGND <32> ADP_135
P
+ 1 1 2 5 L2N7002DW1T1G_SC88-6 <32> ADP_90 ECAGND

2 O ECAGND
-
G
PU201A
4
1
B AS393MTR-E1 SO 8P OP PJ202 B
1N4148WS-7-F_SOD323-2
4
2
@ JUMP_43X39
PD201
PR213 PR205 B+ 1 2
1 2 +VSB
1
100K_0402_1%
1
PC207 1.5M_0402_5%
2
100P_0402_50V8J
1
VL +3VLP
+3V_LDO
100K_0402_1%
VMB
2
1
PR220
@ PR212
75K_0402_1%
2
47K_0402_1%
@ PR203
<32> BATT_LEN# D
1
8
@ PC209
D
2
5 0.068U_0402_16V7K~N 2 PQ205
P
+ 7 1 2 2 @ PQ208 G 2N7002KW_SOT323-3
O
1
6 G 2N7002KW_SOT323-3 S
-
3
G
S
3
2
1
100K_0402_1%
1.5M_0402_5%
100P_0402_50V8J
1N4148WS-7-F_SOD323-2
4
1
PU201B
@ PR208
@ PD202
AS393MTR-E1 SO 8P OP
@ PR215
@ PC210
2
1
+5VALW
22U_0603_6.3V6M
@ PU202
1
1 5
@ PC212
A IN OUT +3V_LDO A
4.7U_0402_6.3V6M
1
2
GND
2
3 4
@ PC213
SHDN# BYP
2
G9191-330T1U_SOT23-5
1

2
PC211 2011/06/15 2012/07/11

@
Issued Date Title

Deciphered Date
1U_0402_16V6K

5 4 3 2 1
5 4 3 2 1
P3
B+
P2
PQ301 PQ302
AO4407AL_SO8 AO4423L_SO8
VIN 8
7
1
2
1
2
8
7
PR301
0.01_1206_1% CHG_B+
6 3 3 6
5 5 1 4 1 2 PQ312
EMI@ PL301 AO4407AL_SO8
2 3 1UH_NRS4018T1R0NDGJ_3.2A_30% 1 8
4
2 7
3 6
2200P_0402_50V7K
PQ304 5
10U_0805_25V6K
10U_0805_25V6K
470P_0402_50V8J
D D
47K_0402_5%
EMI@ PC319
1
2
200K_0402_1%
0.1U_0603_25V7K
4
1
DTA144EUA_SC70-3 DISCHG_G
PR302
PC315
PC316
EMI@ PC318
3
PC302
PR304
1
1 2 PR322
200K_0402_1%
2
2
2 PC301 1 2
VIN
2
5600P_0402_25V7K ACN
2ACOFF-1
1SS355_SOD323-2
2
1
ACP PR321
1DISCHG_G-1
47K_0402_1%
1
2
PD302
P2-1 PR325
0.1U_0402_25V6
1
2 200K_0402_1%
PQ303 PQ311
1
PC307 PC311 DTC115EUA_SC70-3
1
DTC115EUA_SC70-3
PR306 1 2 2 1
3
20K_0402_1%
1 2 0.1U_0402_25V6 2 1 2
6
PQ306
D
1
2N7002KW_SOT323-3 PC308 PD303 PQ313

150K_0402_1%
PQ307A 2 1SS355_SOD323-2
PR305
BATT_OUT <38,39>
2 L2N7002DW1T1G_SC88-6 G 0.1U_0402_25V6 P2 2N7002KW_SOT323-3
D
1
0.1U_0402_25V6
S
3
2 1 2 PACIN
1
1
PC324
VIN G
S
3
ACPRN
392K_0402_1%
2
1
P2-2
ACON
10_1206_5%
2
5
C C
PR309
1
PQ309
PR319
3
PQ307B
ACOK
CMPOUT
ACP
CMPIN
ACN
PR303 PR308
2
47K_0402_1% 64.9K_0402_1% 21
TP
1
PACIN 1 2 5 1 2 6 2 1 4
<32,38> ADP_I ACDET PC314
PC303 20 BQ24737VCC 1 2 PR326
VCC
4
1 2 1 2 7 2.2_0402_5%
IOUT AON7408L_DFN8-5 PL302 PR324
1U_0603_25V6K
3
2
1
1
PQ305 0.1U_0402_25V6 PC304 100P_0402_50V8J 19 4.7UH_PCMC063T-4R7MN_5.5A_20% 0.01_1206_1%

DTC115EUA_SC70-3
<32,38> EC_SMB_DA1
8
SDA
PU301 PHASE
BATT+
BQ24727RGRR_VQFN20_3P5X3P5 LX_CHG 1 2 CHG 1 4
PR328 18 DH_CHG
HIDRV
5
1 2ACOFF-1 2 9 2 3
<32> ACOFF <32,38> EC_SMB_CK1 SCL
1
10K_0402_5% PR315 PR320 PC317 PQ310
4.7_1206_5%
316K_0402_1% 2.2_0603_5% 0.047U_0603_16V7K
EMI@ PR323
1 2 10 17 BST_CHG 1 2 2 1 SRP SRN
10U_0805_25V6K
10U_0805_25V6K
124737_SN
ILIM BTST
1
+3VALW PD301
3
PR316 4
LODRV
1
100K_0402_1% 16 2 1
PC322
PC323
GND
REGN
SRN
SRP
BM
PQ314
2N7002KW_SOT323-3
RB751V-40_SOD323-2
2
2
AON7408L_DFN8-5
680P_0603_50V7K
D
11
12
13
14
15
3
2
1
1
EMI@ PC320
2
2 PC312
6.8_0402_5%
<38,39> BATT_OUT
1 BQ24737VDD
10_0402_5%
G 1U_0603_25V6K
2
PR317
PR318
S
3
PC306 DL_CHG
2
2
B 0.1U_0402_25V6 B
2 1
1
PC305 1 PC309
0.1U_0402_25V6 0.1U_0402_25V6
2
BQ24737VDD
PR314
10K_0402_1%
1
1 2 ACIN <16,32,37>
PR310
PR307 10K_0402_1%
47K_0402_1%
PACIN
2
1 2
PR312
ACPRN 2
12K_0402_1%
2
PQ308
A DTC115EUA_SC70-3 A
3

CHARGER
Size
Document Number Rev
5 4 3 2 1
A B C D E
PR402
499K_0402_1%
ENLDO_3V5V 2 1
1 B+ EMI@ PL401 B+ 1
HCB1608KF-121T30_0603 PU401
1
1 2 3V_VIN 7 1 3V5V_EN PC405 PR409
150K_0402_1%
IN EN1 0.01U_0402_25V4Z 1K_0402_5%
PR403
8 3 3V_FB 1 2 1 2
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
IN EN2 PR401 PC402
6 BST_3V 1 2 1 2
@EMI@ PC403
BS
2
1
1
EMI@ PC404 2.2_0603_5%
PC406
0.1U_0603_25V7K
PL402
2
2
10 LX_3V 1 2
LX +3VALWP
9 4 1.5UH_PCMC063T-1R5MN_9A_20%
GND OUT
470P_0805_50V8
470P_0805_50V8
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
2 5
4.7_1206_5%
PG LDO +3VLP
PC408
PC409
PC410
PC411
EMI@ PC412
EMI@ PC413
1
SY8208BQNC_QFN10_3X3
EMI@ PC415 EMI@ PR404
2
PC414
13V_SN
4.7U_0603_6.3V6M
680P_0603_50V7K
2
2 2
B+ EMI@PL403 PC407 PR410

HCB2012KF-121T50_0805 PU402 6800P_0402_25V7K 1K_0402_5%
1 2 5V_VIN 8 1 3V5V_EN 5V_FB 1 2 1 2
IN EN1
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0402_25V6
3 PC421
EN2 PR405 0.1U_0603_25V7K
1
6 BST_5V 1 2 1 2
PC420
PC427
EMI@ PC417
@EMI@ PC418
BS 2.2_0603_5%
2
PL404 @ PJ401
9 10 LX_5V 1 2 +5VALWP +3VALWP 1 2 +3VALW
GND LX 1 2
5V_VCC 5 4 1.5UH_PCMC063T-1R5MN_9A_20% JUMP_43X118
VCC OUT
1
470P_0805_50V8
470P_0805_50V8
680P_0603_50V7K 4.7_1206_5%
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
2 7
PG LDO VL
1
PC422
EMI@ PC429 EMI@ PR406
PC423
PC424
PC425
PC426
EMI@ PC416
EMI@ PC419
4.7U_0603_6.3V6M
SY8208CQNC_QFN10_3X3
2
@ PJ402
15V_SN
2
2
1
+5VALWP 1 2 +5VALW
PC430
4.7U_0603_6.3V6M
3 1 2 3
JUMP_43X118
2
PR407
2.2K_0402_5%
2 1
<32> EC_ON
PR408
1 2
<32> MAINPWON
0_0402_5%
3V5V_EN
4.7U_0402_6.3V6M
1
1M_0402_5%
PC431 @
1
@ PR411
2
2
4 4


A B C D E
A B C D
EMI@ PL502
1.5V_B+ 1 2 B+
HCB2012KF-121T50_0805
STATE S3 S5 1.5VP VTT_REFP 0.75VSP
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
4.7U_0805_25V6-K
1
1
S0 Hi Hi On On On
PC501
PC520
@EMI@ PC509
EMI@ PC513
5
Off
2
@
S3 Lo Hi On On (Hi-Z) +1.5VP
UG_1.5V 4 PQ501
S4/S5 Lo Lo Off Off Off MDV1525URH_PDFN33-8-5
1 1
1
LX_1.5V
3
2
1
@ PR503
Note: S3 - sleep ; S5 - power off 0_0603_5%
PR501 PC512 PL501 Vo=1.518V
2
2.2_0603_5% 0.1U_0603_25V7K 1UH_PCMB104T-1R0MH_18A_20%
BST_1.5V 1 2 BST_1.5V-11 2 2 1
+0.75VSP +1.5VP
10U_0805_25V6K
10U_0805_25V6K
1
MDU1511RH_POWERDFN56-8-5
1
5
@EMI@
PC504
20
19
18
17
16
1
PU501 PR515
PC505
4.7_1206_5%
VTT
VLDOIN
BOOT
UGATE
PHASE
2
21 1
PAD
2
PQ502
1 15 LG_1.5V 4 +
VTTGND LGATE PC521
2 330U_2.5V_M
1
2 14 @EMI@
VTTSNS PGND PR511 PC517
3
2
1
6.65K_0402_1% 680P_0603_50V7K
2
3 13 2 1
GND RT8207MZQW_WQFN20_3X3 CS
4 12
+VTT_REFP VTTREF VDDP
Rds( on) =2. 7m- 3. 3m ohm
5 11 2 1
+1.5VP VDDQ VDD
+5VALW
1
PR514
+3VALW
PGOOD
PC506 5.1_0603_5%
1U_0603_10V6K
TON
0.033U_0402_16V7K
FB
S3
S5
2
2 2
1
PC511
10K_0402_5%
PC510
6
10
1U_0603_10V6K
PR510
S3_1.5V
2
PR502
S5_1.5V
49.9K_0402_5% @
2
<32,36,41,43> SUSP# 1 2 PGOOD_1.5V
PR509
@ PR505 887K_0402_1%
<32> SYSON 1 2 2 1 1.5V_B+
@
PJ504
0_0402_5% PR507
1
PC503 @ PC508 5.9K_0402_1% 1 2

0.1U_0402_16V6K 0.1U_0402_16V7K 2 1 1 2
JUMP_43X118
2
FB=Vref=0.75V @
PJ505
+1.5VP Ipeak=14A ; Imax=9.8A
1
+1.5VP 1 2 +1.5V
PR506 Delta I=4.8476A=>1/2Delta I=2.4238A 1 2
5.76K_0402_1% Rton= 887K ohm,F= 285K Hz JUMP_43X118
Rds(on)=3.3m ohm(max) ; Rds(on)=2.7m ohm(typical)
2
PR511=6.65K ohm
@
Ilimit_min=(6.65K*10uA)/(10*3.3m*1.2)=16.793A PJ506
Ilimit_max=(6.65K*10uA)/(10*2.7m*1.2)=20.525A +0.75VSP 1
1 2
2 +0.75VS
Iocp=Ilimit+1/2Delta I=19.217 ~ 22.948A
JUMP_43X39
3 3
PU502
SY8033BDBC_DFN10_3X3
@ PL503 Vo=1.8V
PJ502
4
1UH_PH041H-1R0MS_3.8A_20%
1 2 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
+3VALW +1.8VSP
PG
1 2 PVIN LX
9 3
@EMI@ PR508
4.7_0603_5%
JUMP_43X79 PVIN LX
1
1
PC502 8
22U_0805_6.3VAM SVIN
68P_0402_50V8J
1
6 FB=0.6Volt
FB
2
1
5
22U_0805_6.3VAM
22U_0805_6.3VAM
PC525
EN
1 2
1
PR512 @
NC
NC
TP
PJ507
20K_0402_1%
680P_0603_50V7K
PC514
PC515
<32,36,41,43> SUSP#
2
@ PR516 +1.8VSP 1 2 +1.8VS
@EMI@ PC523
1 2
11
2
1 2 EN_1.8VSP
2
0_0402_5% JUMP_43X79
0.1U_0402_10V7K
1
PC507 @
1
1M_0402_5%
PR504 1.8VSP_FB
2
2
PR513
10K_0402_1%
4 4
2


A B C D
5 4 3 2 1
VID [0] VID[1] VCCSA Vout

0 0 0.9V
0 1 0.8V NONCR@ PR603
0.001_1206_1%
+VCCSA
1 0 0.725V +V1.05S_VCCP 1 2
D
1 1 0.675V @CR@ PJ602
+VCCSA
D
+VCCSAP 2
2 1
1
output voltage adjustable network JUMP_43X118
CR@ PU601 CR@ PL601

@CR@ PJ601 SY8037BDCC_DFN12_3X3 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
+3VALW 1
1 2
2 +VCCSA_PWR_SRC 12
PVIN LX
1 +VCCSA_PHASE 1 2 +VCCSAP
22U_0805_6.3V6M
1
11 2 @EMI@
JUMP_43X79 PVIN LX SA_PGOOD <32>
PR602
22U_0805_6.3V6M
22U_0805_6.3V6M
2
CR@ PC602 10 3 CR@ PR601 4.7_0603_5%
CR@ PC601
SVIN LX
2
68P_0402_50V8J 100K_0402_5%
CR@ PC603
CR@ PC604
2 1 FB_VCCSA_IC9 4 1 2
FB PG +3VS
1
8 5 +VCCSA_EN 1 2 @EMI@
VOUT EN
1
NONCR@ PR608 PC605
GND
7 6 0_0402_5% 680P_0402_50V7K
VID1 VID0
+V1.05S_VCCP_PWRGOOD <43>
2
13
2
@CR@ PC606
.1U_0402_16V7K
1
H_VCCSA_VID0 <10>
FB_VCCSA
PR604
1K_0402_5%
2 1 The 1k PD on the VCCSA VIDs are empty.
C C
PR605 These should be stuffed to ensure that
1K_0402_5% VCCSA VID is 00 prior to VCCIO stability.
2 1
H_VCCSA_VID1 <10> CR@ PR606

100_0402_1%
2 1
@ PR607
1 2
+VCCSA_SENSE <10>
0_0402_5%
B B
A A

C

5 4 3 2 1
5 4 3 2 1
D D
PJ701
PR701 +1.05VS_VCCPP Ipeak=15.2A ; Imax=10.64A 2 1
<32,36,41> SUSP# 60.4K_0402_1%
Delta I=2.48=>1/2Delta I=1.24A (F=400K Hz) D-CAP 2
2 1
1 2 @ JUMP_43X118
Rds(on)=3.3m ohm(max) ; Rds(on)=2.7m ohm(typical) +1.05VS_VCCPP PJ703 +V1.05S_VCCP
@ 10K_0402_1%
2
2 1
.1U_0402_16V7K
+3VS PR711=47K ohm 2 1
1
PR706
Vtrip=(Rtrip*10uA)/8= 58.75mV @ JUMP_43X118
100K_0402_1%
PC701
Iocp=19.043~22.999A
2
1
2
PR710
100K_0402_1%
EMI@ PL702
2
HCB2012KF-121T50_0805
PR712
<42> +V1.05S_VCCP_PWRGOOD 1.05VS_B+ 2 1
B+
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
1
1
PR713 PC707
PC712
2.2_0603_5% 0.1U_0603_25V7K
EMI@ PC711
@EMI@ PC715
1
BST_1.05VS_VCCP 2 1 2
2
10.7K_0402_1%~N
17
16
15
14
13
PU701 4 PQ701
C C
MODE
BST
PAD
PGOOD
EN
2
MDV1525URH_PDFN33-8-5
PR704
1 12 LX_1.05VS_VCCP PL701
0.1U_0402_25V6
VREF SW
3
2
1
1UH_PCMB104T-1R0MH_18A_20%
+1.05VS_VCCPP
1
2 1
12K_0402_1%
1
PC702
2 11 DH_1.05VS_VCCP
REFIN DH
2
1000P_0603_50V7K 4.7_1206_5%
PR705
5
PC703
TPS51219RTER_QFN16_3X3
@EMI@ PR714
0.01UF_0402_25V7K
1
@ PR702 3 10 DL_1.05VS_VCCP PC714 1

1 2 GSNS DL
1
2
+
S TR MDU1511RH 1N POWERDFN56-8
0_0402_5% 4
4
VSNS V5
9
+5VALW 330U_2.5V_M
2 +1.05VP
OCP min 20A
COMP
1
PGND
PQ702
TRIP
GND
OVP min 1.24V
3
2
1
<9> VSSIO_SENSE_L
@EMI@ PC709
2
PC706
5
8
<9> VCCIO_SENSE
1
1 2
PR703
PC708
47K_0402_1%
1
1 2 0.01UF_0402_25V7K 1U_0603_10V6K
2
10_0402_1%
Rds( on) =2. 7m- 3. 3m ohm
PR711
2
B PC704 B
1000P_0402_50V7K
1
PR709
1 2
10_0402_1%
2
PC705
1000P_0402_50V7K
1
A A

Custom

5 4 3 2 1
5 4 3 2 1
PC902
1 2
.1U_0402_16V7K
1 PR904 2
2P: 24K 24.9K_0402_1%

1P: 24.9K PR915,PR946=200K(setting 113 degreeC)
PR915,PR946=8.25K(setting 93 degreeC)
PC901
<32> GPU_IMON
1 PR9012 FBA3 1 2
1200P_0402_50V7K
680P_0402_50V7K
D PUT COLSE D
10_0402_1% 0.033U_0402_16V7K
75K_0402_1%
TO GT
1
PR903
TRBSTA# 1 PR9022 FBA1 1 2 PH901 Inductor
PC903
PC904
PR905
PR906 PC906
1
1
1.21K_0402_1% 10.7K_0402_1% 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
PC905
2
PR908 PC907 PC908 2 PR9071 NTC_PH203 1K_0402_1% 1000P_0402_50V7K
2
0.033U_0402_16V7K 1 2 FBA2 1 2 1 2 165K_0402_1%
10_0402_1% 2P: 1.65K
680P_0402_50V7K PR910 10P_0402_50V8JPC909
1 PR9092 1 2 COMPA11 2 1P: 1K TSENSEA
15.8K_0402_1%
1K_0402_1% 6.04K_0402_1% 2200P_0402_50V7K CSREFA
1
PC910
2
1 PR9122 SWN1A 0.047U_0402_16V7K @ PR916
0_0402_5%
2P: 21.5K 63.4K_0603_1% PR913 6.98K_0402_1%
1
CSP1A 1 2
1P: 15.8K SWN1A <45>
2
2
2
@ PR937
CSCOMPA
1 2 PC911
<10> VCC_AXG_SENSE
2
1000P_0402_50V7K @
1PR914
1
0_0402_5% PC912
2
@ PR954 1000P_0402_50V7K
200K_0402_1%
CSREFA <45>
1
1 2 PH904
<10> VSS_AXG_SENSE
PC914
PR915
CSP2A
CSP1A
0_0402_5% 1 2 100K_0402_1%_TSM0B104F4251RZ
TRBSTA#
DROOPA
CSSUMA
TSENSEA
COMPA
1
.1U_0402_16V7K
FBA
DIFFA
ILIMA
+V1.05S_VCCP
PR927=95.3K ohm,F=300Khz PR918 2P: 36K

1 2
PR927=63.4K ohm,F=450Khz 26.1K_0402_1% 1P: 26.1K
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
6132_PWMA
C
+5VS 1 PR9192 PU901 PUT COLSE C
2_0603_5%
TO V_GT
VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PAD
PC915
1 2 6132_VCC HOT SPOT
1 45 PR921 PC918
.1U_0402_16V7K
2 2.2U_0603_10V7K VCC PWMA 44 BSTA1 1 2 BSTA1_11 2

3 VDDBP BSTA 43 2.2_0603_5% 0.22U_0603_25V7K +5VS
130_0402_1%
54.9_0402_1%
VRDYA HGA HG1A <45>

PR922 2
VR_ON_CPU 4 42
<32> VR_ON EN SWA SW1A <45>
PC917 VR_SVID_DAT1 5 41 PC919
PR923
SDIO LGA LG1A <45>

VR_SVID_ALRT# 6
ALERT# BST2
40 BST2 1 PR9242 BST2_1 1 2 2Phase: @
2
PR927 PR925 VR_SVID_CLK 7 39 2.2_0603_5% 0.22U_0603_25V7K

SCLK HG2 HG2 <45>
Option for 1Phase: install
1
0_0402_5% 95.3K_0402_1% 1 2 VBOOT 8 38
VBOOT SW2 <45>
NCP6132AMNR2G_QFN60_7X7 SW2
1
1@ PR926 2VR_SVID_DAT1 1 2 10K_0402_1% ROSC_CPU 9 37 PC920 1 phase GFX

<9> VR_SVID_DAT ROSC LG2 LG2 <45> 0_0402_5%
CPU_B+ 1 2 VRMP 10 36 6132P_VCCP 1 PR930 2 1 2
<9> VR_SVID_ALRT# VRMP PVCC
H_PROCHOT# 11 35 0_0402_5% 2.2U_0603_10V7K @ PR928
<9> VR_SVID_CLK <32,37,6> H_PROCHOT# VRHOT# PGND
PR929 1K_0402_1% VGATE 12 34
0.01U_0402_25V7K
VRDY LG1 LG1 <45> +5VS
2
1
13 33 CSP2A
VSN SW1 SW1 <45>
PC921 14 32 PC922
+3VS VSP HG1 HG1 <45>
DIFF_CPU 15 31 BST1 1 PR9312 BST1_1 1 2
DIFF BST1
CSCOMP
2
2.2_0603_5% 0.22U_0603_25V7K
TRBST#
DROOP
CSSUM
DRVEN
CSREF
COMP
TSNS
CSP3
CSP2
CSP1
PWM
IOUT
ILIM
1
FB
PR933 +5VS
10K_0402_5%
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
2
COMP_CPU
Option for 3Phase: @
1
VGATE FB_CPU
TRBST#
<16,32> VGATE
@ PR936 3P: 73.2K 2 phase CPU 2Phase: install
DROOP
0_0402_5%
TSENSE
ILIM_CPU
<9> VSSSENSE
1 2 VSN 3P: 22p 6132_PWM 1 PR9342
2P: 41.2K
1
41.2K_0402_1% @ PR935
0_0402_5% PC923 2P: 10p
2
@ PR938 1000P_0402_50V7K CSP3
2
1 2 VSP PC924
<9> VCCSENSE
2
1 2
PR939 12.4K_0402_1%
0_0402_5% .1U_0402_16V7K
IMVP_IMON
B B
PC926 CSP1
3P: 330p 1 PR940 2 2 1 CSP2 CSP2 1 PR9412
SWN2 <45>
1
2
1K_0402_1% CSP3 PC927 6.98K_0402_1% TSENSE
2P: 1000p
1
10P_0402_50V8J 0.047U_0402_16V7K
@
3P: 21K
1
PR942 PC928 PR943 PC929 PR960
2
1 2FB_CPU1 1 2 2 1COMP_CPU12 1 CSREF 6.98K_0402_1% @ PR917
2P: 12.4K
1
PR944 PC930 49.9_0402_1% 4.32K_0402_1% 0_0402_5%
1 2FB_CPU3 1 2 1000P_0402_50V7K 3300P_0402_50V7K CSP1 1 PR9452
SWN1 <45>
3P: 6.04K
2
10_0402_1% 6.98K_0402_1%
CSREF <45>
CSCOMP
2
2
1
0.033U_0402_16V7K PC931
PR947 PR948 2P: 4.32K PC932 @ PR961
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 3P: 1500p0.047U_0402_16V7K 6.98K_0402_1%
1
2
CSREF
0.033U_0402_16V7K
2P: 1200p
1
3P: 2200p
1
8.06K_0402_1% 806_0402_1%
PC933 @
2P: 3300p CSSUM
200K_0402_1%
2
3P: 348 3P: 3.65K
PR946 1
2
PC934
1 2 PH902
2P: 1.21K 2P: 9.53K 1000P_0402_50V7K 1 PR9492 SWN1
124K_0603_1% 100K_0402_1%_TSM0B104F4251RZ
24.9K_0402_1%
2
.1U_0402_16V7K
1
3P: 23.7K 1 2 PC936 1 PR9512 SWN2
PC935
820P_0402_25V7 124K_0603_1%
PR950
2P: 24.9K
1
1 PR952 2NTC_PH201 1 PR953 2 PR949.PR951 need link SD014124380.

1
75K_0402_1%
PR955 PC937 165K_0402_1%
CSCOMP 1 2 DROOP 1 2 CSREF PH903 PUT COLSE
PUT COLSE TO VCORE
1K_0402_1% 1000P_0402_50V7K 2 1
3P: 806 TO VCORE HOT SPOT
2P: 1K Phase 1 220K_0402_5%_ERTJ0EV224J
A Inductor A
<32> IMVP_IMON

Custom VILG1/G2 MB LA9902P Schematic B
5 4 3 2 1
5 4 3 2 1
CPU_B+
CPU_B+
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
B+
2200P_0402_25V7K
2200P_0402_25V7K
0.1U_0402_25V6
0.1U_0402_25V6
5
5
EMI@ PL901
EMI@ PC944
EMI@ PC945
HCB4532KF-800T90_1812
1
1 2
PC938
PC939
EMI@ PC940
EMI@ PC941
PC942
PC943
CPU_B+
PR962 PR963
68U_25V_M
68U_25V_M
1 1
2
1 2 4 1 2 4
<44> HG1 <44> HG2
1
2.2_0402_5% PQ901 + + 2.2_0402_5%
+VCC_CORE +VCC_CORE
PC970
PC969
PQ902
@EMI@ PC971
@EMI@ PC972
470P_0402_50V8J
470P_0402_50V8J
2 2
2
S TR MDU1516URH 1N POWERDFN56-8 PL902 S TR MDU1516URH 1N POWERDFN56-8 PL903
3
2
1
3
2
1
D D
0.36UH_PCMB104T-R36MH1R105_30A_20% 0.36UH_PCMB104T-R36MH1R105_30A_20%
1 4 1 4
<44> SW1 <44> SW2
1
2 3 DCR: 1.10m ±5% ohm 2 3 DCR: 1.10m ±5% ohm
5
EMI@ EMI@
PR956 PR957
4.7_1206_5% 4.7_1206_5%
2
PR958
4 V1N_CPU 2 1 4 V2N_CPU 2 PR959 1 CSREF
<44> LG1 CSREF <44> <44> LG2
1SNUB_CPU1
SNUB_CPU2
10_0402_1%
10_0402_1%
PQ903
PQ904
SWN1 <44> SWN2 <44>
3
2
1
3
2
1
S TR MDU1511RH 1N POWERDFN56-8 EMI@
PC948 S TR MDU1511RH 1N POWERDFN56-8
EMI@
680P_0603_50V7K
1
PC949
Rds( on) =2. 7m- 3. 3m ohm Rds( on) =2. 7m- 3. 3m ohm
2
680P_0603_50V7K
2
C C
QC 45W CPU DC 35W CPU

VID1=0.9V VID1=1.05V
IccMax=94A IccMax=53A
Icc_Dyn=66A Icc_Dyn=43A
Icc_TDC=52A Icc_TDC=36A
R_LL=1.9m ohm R_LL=1.9m ohm
OCP~110A OCP~65A
CPU_B+
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_25V7K
0.1U_0402_25V6
B B
EMI@ PC946
EMI@ PC947
1
1
PC957
PC958
2
2
5
PR964
1 2 4
<44> HG1A
2.2_0402_5%
PQ907
S TR MDU1516URH 1N POWERDFN56-8 PL905 +VCC_GFXCORE_AXG
3
2
1
0.36UH_PCMB104T-R36MH1R105_30A_20%
1 4
<44> SW1A
1
2 3 DCR: 1.10m ±5% ohm

5
EMI@
PR967
V1N_GFX
4.7_1206_5%
2
4
<44> LG1A
1SNUB_GFX1
PQ909
2 PR971 1
CSREFA <44>
3
2
1
S TR MDU1511RH 1N POWERDFN56-8
EMI@ 10_0402_1%
PC968
680P_0603_50V7K
Rds( on) =2. 7m- 3. 3m ohm SWN1A <44>
2
A A
QC 45W GT2 DC 35W GT2

VID1=1.23V VID1=1.23V
IccMax=46A IccMax=33A
Icc_Dyn=37A Icc_Dyn=20.2A Security Classification Compal Secret Data Compal Electronics, Inc.
Icc_TDC=38A Icc_TDC=21.5A Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
R_LL=3.9m ohm R_LL=3.9m ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
OCP~55A OCP~40A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C VILG1/G2 MB LA9902P Schematic B
5 4 3 2 1
5 4 3 2 1
+VCC_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.

+VCC_CORE +VCC_GFXCORE_AXG
1 1 1 1 1
5 x 22 µF (0805)
Socket Bottom 5 x (0805) no-stuff
1
PC1
PC2 PC3 PC4 PC5 @EMI@ PC11
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM 470P_0402_50V8J
+VCC_GFXCORE_AXG sites
2
D
7 x 22 µF (0805) D
Socket Top 2 x (0805) no-stuff
sites
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1
PC13
PC15
PC17
PC18
PC19
PC6 PC7 PC8 PC9 PC10
10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM
2 2 2 2 2 2 2 2 2 2
+V1.05S_VCCP
+VCC_CORE +V1.05S_VCCP
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1
PC27
PC28
PC29
PC30
PC31
PC32
PC33
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
2 2 2 2 2 1 1 1 1 1 1 1 2 2 2 2 2 2 2
PC36
PC38
PC39
PC40
PC41
PC42
PC43
2 2 2 2 2 2 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1
1 1 1 1 1
PC50
PC51
PC52
PC53
PC56
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2
2 2 2 2 2
470U_D2_2VM_R4.5M
390U_2.5V_M
1 1
+ +
PC58
PC59
C C
2 2
330U_D2_2V_Y
330U_D2_2V_Y
1 1
1 1 1 1
PC58 ESR= 4. 5m ohm + +
PC66
PC67
PC61 PC62 PC63 PC64
2
22U_0805_6.3V6M
2
22U_0805_6.3V6M
2
22U_0805_6.3V6M
2
22U_0805_6.3V6M PC59 ESR= 9m ohm ESR= 9m ohm 2 2
1 1
PC71 PC72
22U_0805_6.3V6M 22U_0805_6.3V6M
2 2
+VCC_CORE
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
1 1 1
+ + +
PC73
PC74
PC76
B 2 2 2 B
330U_D2_2V_Y
330U_D2_2V_Y
1 1
+ +
PC77
PC78
ESR= 9m ohm
2 2
A A

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019N1 B
5 4 3 2 1
5 4 3 2 1
Version c hange list (P. I . R. List) Page 1 of 2

f or PW R
I tem Reason f or change PG# Modif y List Date Phase
Design Change of IC Package. 40 Change PU401 to SA000061M00(S IC SY8208BQNC QFN 10P PWM) 2012/11/22 DVT
1
D D
2 Design Change of IC Package. 40 Change PU402 to SA000061N00(S IC SY8208CQNC QFN 10P PWM) 2012/11/22 DVT
Add PQ102 to SB00000EO10(S TR 2N7002KDW 2N SOT-363-6 PANJIT)

3 Add ADP_ID Circuit. 37 Add PR111.PR112 to SD028100380(S RES 1/16W 100K +-5% 0402) 2012/12/03 DVT
4 Factory lack of material. 41 Change PC521 to SF000003H00(S_A-P_CAP 330U 2.5V M 6.3X4.2 LESR16M SL) 2012/12/06 DVT
Factory lack of material. 45 Change PL902.PL903.PL905 to SH00000N900(S COIL .36U PCMB104T-R36MH1R105 30A GLUE) 2012/12/06 DVT
5
EMI request adjust +3VALWP/+5VALWP snubber function. 40 Change @PR404.@PC415.@PR406.@PC429 to PR404.PC415.PR406.PC429. 2012/12/06 DVT
6
7 EMI request adjust +3VALWP/+5VALWP boost resistor. 40 Change PR401.PR405 to SD013220B80(S RES 1/10W 2.2 +-5% 0603). 2012/12/06 DVT
C C
EMI request add bypass capacitor. 40 Add PC412.PC413.PC416.PC419 to SE001471J80(S CER CAP 470P 50V J NPO 0805 H0.6) 2012/12/06 DVT
8
EMI request adjust CPU/GFX CORE snubber function. 45 Change @PR956.@PC948.@PR957.@PC949.@PR967.@PC968 to PR956.PC948.PR957.PC949.PR967.PC968. 2012/12/06 DVT
9
EMI request adjust bypass capacitor. 45 Change @PC940 to PC940. 2012/12/06 DVT
10
Add PC944.PC946 to SE00000G880(S CER CAP 0.1U 25V K X5R 0402)
11 EMI request add bypass capacitor. 45 Add PC945.PC947 to SE075222K80(S CER CAP 2200P 25V K X7R 0402) 2012/12/06 DVT
Change PC420 to SE00000OF80(S CER CAP 4.7U 25V K X6S 0805 H1.25)
12 Design Change of input capacitor. 40 Add PC427 to SE00000OF80(S CER CAP 4.7U 25V K X6S 0805 H1.25) 2012/12/07 DVT
Add @PR409.@PR410 to SD028100180(S RES 1/16W 1K +-5% 0402)

Add @PC405 to SE075472K80(S CER CAP 4700P 25V K X7R 0402)
Design Change of IC Application. 40 Add @PC407 to SE075472K80(S CER CAP 0.047U 25V K X7R 0402) 2012/12/10 DVT
13 Add PR411 to SD028000080(S RES 1/16W 0 +-5% 0402)
B Change PC936 to SE000008980(S CER CAP 820P 25V K X7R 0402) B

Change PC929 to SE074332K80(S CER CAP 3300P 50V K X7R 0402)
Change PC926 to SE071100J80(S CER CAP 10P 50V J NPO 0402)
14 Design Change of IC Application. 44 Change PC928 to SE074102K80(S CER CAP 1000P 50V K X7R 0402) 2012/12/17 DVT
Change PR943 to SD00000J280(S RES 1/16W 4.32K +-1% 0402)
Change PR949.PR951 to SD014124380(S RES 1/10W 124K +-1% 0603 YAGEO)
Design Change of CPU/GFX CORE Choke. 45 Change PL902.PL903.PL905 to SH00000NM00(S COIL 0.22UH +-20% PCMB104T-R22MS 35A) 2012/12/21 DVT
15
Design Change of VCCSA(LDO). 42 Delete PC607.PC608.PC609.PC610.PC611.PC612.PC613.PC614.PJ603.PJ604.PR608.PR609.PR610.PR611.PU602 2012/12/21 DVT
16
Reduction Part Count. 37 Delete PR110. 2013/01/18 PVT
17
18
Reduction Part Count. 44 Delete PC916. 2013/01/18 PVT
19
Design Change of IC Application. 40 Change @PC405.@PR490.@PC407.@PR410 to PC405.PR490.PC407.PR410. 2013/01/18 PVT
A 20 Change PR411 to SD028000080(S RES 1/16W 0 +-5% 0402) A

Rev
Custom

5 4 3 2 1
5 4 3 2 1
Version c hange list (P. I . R. List) Page 2 of 2

f or PW R
Change PR505.PR516 to SD028000080(S RES 1/16W 0 +-5% 0402) 2013/01/18 PVT
21 Reduction Part Count. 41 Change PR503 to SD013000080(S RES 1/10W 0 +-5% 0603)
D D
Design Change of Thermal Application. 41 Change PC521 to SGA20331E10(S POLY C 330U 2V Y D2 LESR9M EEFSX H1.9) 2013/01/18 PVT
22
Reduction Part Count. 43 Change PR702 to SD028000080(S RES 1/16W 0 +-5% 0402) 2013/01/18 PVT
23
Reduction Part Count. 44 Change PR926.PR916.PR917 to SD028000080(S RES 1/16W 0 +-5% 0402) 2013/01/18 PVT
24
Design Change of CPU/GFX CORE Choke. 45 Change PL902.PL903.PL905 to SH00000N900(S COIL .36U PCMB104T-R36MH1R105 30A GLUE) 2013/01/18 PVT
25
Design Change of CPU/GFX CORE Frequence. 44 Change PR927 to SD034953280(S RES 1/16W 95.3K +-1% 0402) 2013/01/18 PVT
26
Factory lack of material. 40 Change PC420.PC427 to SE000006R80(S CER CAP 4.7U 25V K X5R 0805 H1.25) 2013/01/18 PVT
27
28
Design Change of Power Circuit Application. 38 Change PC208 to SE000003J80(S CER CAP 0.068U 16V K X7R 0402) 2013/01/23 PVT
C
29 C
Add PR328 to SD028100280(S RES 1/16W 0 +-5% 0402)

Design Change of Power Circuit Application. 39 Add PQ314 to SB000009Q80(S TR 2N7002KW 1N SOT323-3) 2013/01/23 PVT
30
Change PC405 to SE072103Z80(S CER CAP .01U 25V Z Y5V 0402)
31 Design Change of Power Circuit Application. 40 Change PC407 to SE075682K80(S CER CAP 6800P 25V K X7R 0402) 2013/03/04 PVT
Design Change of Power Circuit Application. 42 Add PR608 to SD028000080(S RES 1/16W 0 +-5% 0402) 2013/03/14 Pre-MP
32
B B
A A

Rev
Custom

5 4 3 2 1
5 4 3 2 1
COMPAL CONFIDENTIAL
MODEL NAME: Power Sequence Block Diagram
PCB NAME: LA-9901P
D REVISION: 0.2 JUMP
D
DATE: 2013/01/14 6 +3V_PCH
A1 PCH_PWROK 14
AC
VIN
MODE 7 EC_RSMRST#
B+ PU401 +3VALW
PU301 6 8 PBTN_OUT# SYS_PWROK 19
2 PU402 +5VALW
DGPU_PWROK
BATT PM_SLP_S3#
BATT+ 16
EC_ON 5
MODE
B1 3 ACIN
PM_SLP_S4#
PM_SLP_S5# 9 PCH 15 PM_DRAM_PWRGD
ON/OFF EC 16 H_CPUPWRGD
SW3
CPU
4 GC6_FB_CLAMP_TGL_REQ#
GC6_FB_CLAMP
20 PLT_RST#
C
12 SA_PGOOD 14 SVID C
11 SUSP# 17
DGPU_PWR_EN 11
-->UMA 11 SYS_PWROK
SYSON 10 -->DIS 11 VGATE 18
10 SVID
B+
NVDD_PWR_EN
SW1,SW2
DGPU_PWROK
+VCC_CORE NVDD_PWR_EN 16
VR_ON 13 PU901 B+
SW1A +VCC_GFXCORE_AXG PU801 +VGA_CORE
EC_VGA_EN
JUMP 15
SYSON +1.5VP +1.5V
PU501 JUMP
B+ +0.75VSP +0.75VS 16
FBVDDQ_PWR_EN
DV2
SUSP# JUMP UV11 +1.5V GC6_EN
PU502 +1.8VSP +1.8VS
DGPU_PWROK
+1.05VS_VCCP
+3VALW 17
B+
SUSP +5VS PU602
B
+5VALW U38 U73 +5VS_DISPLAY 16 B
18
+3VS +1.5VS_VGA JUMP
QV11
SUSP JUMP
+3VALW U39 +3VS_WLAN
+3VS_VGA 13
12
QV5 VRAM 19
DGPU_PWR_EN
SUSP# Q8 20 PLT_RST# 22 +1.05VS_VGA

+1.5VS
+1.5V PLT_RST_VGA#
DGPU_HOLD_RST# UV2
SUSP PCH
+1.5V U3 +1.5V_CPU_VDDQ 21
VGA
JUMP
SUSP# +1.05VS_VCCP JUMP
PU701 +3VALW +VCCSA
B+
+1.05VS_VCCP_PWRGD +VCCSA_EN PU601
SA_PGOOD
GC6_FB_CLAMP
A A
GC6_FB_CLAMP_TGL_REQ#

4019N1 B

5 4 3 2 1
5 4 3 2 1
VILG1/G2 HW PIR List

I t em Page MODI FI CATI ON LI ST PURPOSE
EVT TO DVT
1 P. 5~11 Change f oot pr i nt of J CPU1 For Lenovo r ul e
D
2 P. 14 Add R406, R407, R408, R409 Reser ve f or i mpr ovement f act or y pr ocesses D
3 P. 42 Add EC_SPI _SO, EC_SPI _SI , EC_SPI _CLK, EC_SPI _CS# t o EC Reser ve f or i mpr ovement f act or y pr ocesses
4 P. 42 Add PCH_PWR_EN t o EC Pi n. 107 Reser ve f or i mpr ovement f act or y pr ocesses
5 P. 42 Reser ve R410 Reser ve Pul l - hi gh f or GPI O use
6 P. 42 Change EC_FAN_PWM f r om EC Pi n. 34 t o EC Pi n. 26 For common desi gn
7 P. 42 Change NOVO# f r om EC Pi n. 26 t o EC Pi n. 34 For common desi gn
8 P. 42 Change ENBKL f r om EC Pi n. 73 t o EC Pi n. 76 For common desi gn
9 P. 42 Change I MVP_I MON f r om EC Pi n. 76 t o EC Pi n. 73 For common desi gn
10 P. 42 Change DGPU_PWR_EN f r om EC Pi n. 107 t o EC Pi n. 123 For common desi gn
11 P. 34 Add R411, R412, C411, C412 Reser ve f or EMI
12 P. 20 Add Q21, R40, C237, Q22, R418, C243, C252, R413 Reser ve f or power consumpt i on
C C
13 P. 25 Del Q12/ R806 For Change Audi o J ack t ype f r om Nor mal cl ose t o Nor mal open
B B
A A

4019N1 B

5 4 3 2 1
5 4 3 2 1
VILG1/G2 HW PIR List

I t em Page MODI FI CATI ON LI ST PURPOSE
DVT TO PVT
1 P. 26 Reser ve R508 For l eakage cur r ent i ssue of At her os WLAN
D D
2 P. 31 Change RA22 t o r eser ve For PC Beep i ssue( can' t hear d sound of " di " on BI OS set up menu)
3 P. 31 Reser ve RA10/ RA11 For sol ve Codec speaker Hum noi se i ssue( Zi zi )
4 P. 32 Reser ve R416 Reser ve +3VLP power r ai l t o EC
5 P. 32 Change EC_RST# power r ai l t o +3V_EC Usi ng power r ai l whi ch t he same wi t h EC
6 P. 32 Change EC_SMB_CK1 & EC_SMB_DA1 power r ai l t o +3V_EC Usi ng power r ai l whi ch t he same wi t h EC
7 P. 14 Change U5 f r om 4MB t o 8MB ROM Fol l ow common desi gn
PVT TO Pr e- MP
1 P. 32 Chagne R416 t o shor t pad
2 P. 42 Reser ve +1. 05S_VCCP_PWRGOOD of +V1. 05S_VCCP t o connect t o SA_PGOOD For Cel er on/ Pent i um CPU
C C
B B
A A

4019N1 B

5 4 3 2 1
5 4 3 2 1
Version c hange list (P. I . R. List) Page 3 of 3 f or H W PI R
44
D D
45
46
47
48
49
C C
50
51
52
52
53
B B
A A

4019N1 B

5 4 3 2 1
www.s-manuals.com

Compal Confidential: G400S/G500S UMA M/В Schematics Document

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Compal Confidential: G400S/G500S UMA M/В Schematics Document

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Compal Confidential

G400S/G500S UMA M/В Schematics Document

Board ID PCB Revision Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+VCC_G FXCO RE_AXG

PEG_ICOMPI and RCOMPO signals should be

PCI EXPRESS* - GRAPHICS

<16> FDI_LSYNC0 J19 G27

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Wednesday, May 08, 2013 Sheet 5 of 52

T48 H_CATERR# AL33

JTAG & BPM

R29 AL35 XDP_DBRESET# R28 2 1 1K_0402_5% +3VS

AR30 XDP_BPM#2 0.047U_0402_16V7K

10K_0402_5% B 4 PM_SYS_PWRGD_BUF R32

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Wednesday, May 08, 2013 Sheet 6 of 52

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY A

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

<6> H_DRAMRST# DDR3_DRAMRST# <12,13>

Date: Wednesday, May 08, 2013 Sheet 7 of 52

CFG Straps for Processor

Interl request AH26 short GND

1: Normal Operation; Lane # definition matches

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Wednesday, May 08, 2013 Sheet 8 of 52

JCPU1F POWER +V1.05S_VCCP

PEG AND DDR

VCC62 VIDALERT# VR_SVID_ALRT# <44>

VSS_SENCE 100ohm +-1% pull-down to GND near processor

TYCO_2013620-2_IVY BRIDGE Security Classification Compal Secret Data

Date: Wednesday, May 08, 2013 Sheet 9 of 52

DDR3 -1.5V RAILS

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <42>

1 1 VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 <42>

A IVY Bridge drives VCCIO_SEL low A

Security Classification Compal Secret Data

Date: Wednesday, May 08, 2013 Sheet 10 of 52

Date: Wednesday, May 08, 2013 Sheet 11 of 52

+VREF_DQ_DIMMA +1.5V +1.5V

1 VTT1 VTT2 +0.75VS

205 206 0. 65A@0. 75V

Date: Wednesday, May 08, 2013 Sheet 12 of 52

1 VTT1 VTT2 +0.75VS

Date: Wednesday, May 08, 2013 Sheet 13 of 52

W=20mils W=20mils 1 2 PCH_RTCX2

8M B SPI ROM FOR M E

& Non- share ROM .

Q10 AB13 SATA3_COMP 1 2

RP12 LBSS138LT1G_SOT-23-3 SATA3COMPI

6 3 SPI_CLK SATA3RBIAS R115

B 5 4 HDA_RST# SPI_SB_CS0# Y14 750_0402_1% B

<31> HDA_SDOUT_AUDIO SATALED# SPI_SB_CS1# 1 8 0_0402_5%

0_0402_5% SPI_SI V4 V14 SPI_SO_R 1 @ 2 SPI_SO1 2 7

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Wednesday, May 08, 2013 Sheet 14 of 52

V45 K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Wednesday, May 08, 2013 Sheet 15 of 52

DSWODVREN R179 2 1 330K_0402_5%

<5> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 <5>