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Digitall Electron
nics

Syynchron
nous Co
ounterss
In a syncchronous counnter, also kn
nown as a parallel
p counnter, all the flip-

flops in
n the couunter chan
nge state at the same
s timee in

m
synchro
onism with the input clock
c signaal. The clocck signal in this

co
case is simultaneou
s ock inputs of all the flip-
usly appliedd to the clo

n.
flops. The delay in t case is equal to th
nvolved in this he propagattion delay of
o one flip--flop

io
only, irrrespective of
o the num
mber of flip
p-flops usedd to constrruct the co
ounter. In other
o

at
words, the
t delay is
i independdent of thee size of th
uc he counterr. Since thee different flip-

flops in
n a synchro
onous couunter are clocked
c at the same time, therre needs to
o be
ed

addition
nal logic cirrcuitry to ensure
e that the variouus flip-flops toggle at the right time.
t

Using parallel
p coun
nters, any binary
b or non-binary
n sequences can be obtained by using
u
hi

the desiggn proceduure.

ks

MOD 8 Counter:
a
.s

To obttain MOD 8 parallel counter, 3 flip-flopss are requiired. Clockk input willl be
w

common
n for all flip-flops
f a hence the flip-flo
and ops shouldd not be in
n toggle mode
m
w

always and
a additio
onal hardwaare is requiired to obttain the seqquence. The state diaggram
w

and tablle for the reequired couunter is as shown

s belo
ow.

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0 0 0
0 0 1
0 1 0

m
0 1 1
1 0 0

co
1 0 1

n.
1 1 0

io
1 1 1

at
uc
In the given count sequence, we find that flip-flop FF0 toggles with every clock pulse,
flip-flop FF1 toggles only when the output of FF0, is in the ‘1’ state, flip-flop FF2
ed

toggles only with those clock pulses when the outputs of FF0 and FF1 are both in the
hi

logic ‘1’ state. Such logic can be easily implemented with AND gates.
a ks
.s
w
w
w

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MOD 8 DOWN Counter:
′ ′
The circuit diagram for DOWN counter is as shown below where are
given to the inputs of flip-flop directly (or using AND gate).

m
co
n.
io
at
uc
ed

Examples:

1. Design a BCD counter using JK flip-flops.

hi

Sol:
ks

To design a BCD counter or decade counter or MOD 10 counter, 4 flip-flops are

a

required.
.s

State diagram:
w
w
w

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State table:
Present State (PS) Next State (NS)

0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1

m
0 0 1 1 0 1 0 0

co
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0

n.
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0

io
1 0 0 0 1 0 0 1
1 0 0 1
at 0 0 0 0
uc
Circuit excitation and output table:
ed

Present State (PS) Next State (NS) Flip-flop Input functions

hi
ks

0 0 0 0 0 0 0 1 0 0 0 1
a

0 0 0 1 0 0 1 0 0 0 1 1
.s

0 0 1 0 0 0 1 1 0 0 0 1
0 0 1 1 0 1 0 0 0 1 1 1
w

0 1 0 0 0 1 0 1 0 0 0 1
w

0 1 0 1 0 1 1 0 0 0 1 1
w

0 1 1 0 0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 1
1 0 0 1 0 0 0 0 1 0 0 1

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By using K-maps, we get expressions for the flip-flop input functions.

′
1; , ; ; ,

m
co
n.
io
at
uc
ed

2. Design a counter using JK flip-flops for the following binary sequence: 0, 4, 2,

hi

1, 6 and repeat.
ks

Sol:
a

Present State Next State

.s

(PS) (NS)
w
w

0 0 0 1 0 0
w

0 0 1 1 1 0
0 1 0 0 0 1
1 0 0 0 1 0
1 1 0 0 0 0

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Circuit Excitation and output table:

Present State Next State Flip-flop Input functions

(PS) (NS)

0 0 0 1 0 0 1 0 0

m
0 0 1 1 1 0 1 1 1
0 1 0 0 0 1

co
0 1 1
1 0 0 0 1 0 1 1 0

n.
1 1 0 0 0 0 1 1 0

io
at
uc
By using K-maps, we get.
′ ′
, 1; , 1; , 1;
ed
hi
a ks
.s
w
w
w

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Lockout:

The counter just discussed utilizes only five out the total number of eight states
available in a counter having three flip-flops. The counter may enter one of the
unused states and may keep moving between the unused states and not come out of
this situation. This condition may develop because of external noise, which may affect

m
states of the flip-flops. If a counter has unused states with this characteristic, it is said
to suffer from lockout. The lockout situation can be avoided by so arranging the

co
circuit that whenever the counter happens to be in an unused state, it reverts to one of

n.
the used states. The above circuit can be designed to avoid lock out by making the
next states of unused states (3, 5, 7) to any valid state. Hence to avoid lockout or to

io
make the counter self-starting, the next state of any invalid state must be a valid initial

at
state.
uc
The advantages of parallel counter are its speed of operation and any type of sequence
can be obtained. The drawback is its hardware part where we require additional gates
ed

along with required number of flip-flops.

hi
a ks
.s
w
w
w

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