Boolean Functions and Their Realizations

3
Boolean Functions and Their Realizations

3.1 Boolean Functions
A Boolean is an expression formed with binary variables, AND, OR and NOT operators.
Boolean Function  These are the functions which are used to give some logical output with the help of
logic gate.
n
2
Note : Maximum number of boolean functions using ‘n’ variables = 2
3.2 Representation of Boolean Functions
3.2.1 Standard Form
(a) Sum of product
This is a boolean expression which contain AND terms. Sum denotes ORing of these AND terms.
Example :
F1 = y  xy  xyz
(b) Product of Sum
It is a Boolean expression which contains OR terms and product indicate AND operation of OR terms.
Example :
F2 = X(Y  Z) (X  Y  Z  W)
3.2.2 Canonical Forms
When each product or sum term of a boolean function contain all the logical variables of the function the
representation of the function is called canonical form. Canonical form consists of two classes :
(a) Minterms Form
(b) Maxterms Form
(a) Minterm Form : If each term in SOP form contain all the variables of the function then each term is
called minterm or standard product and representation is called Minterm form. Minterm is represented
by ‘m’. The main property of minterm is that only one minterm has value ‘1’ for one combination of input
variables. Canonical sum of product expression can also be expressed as the sum of decimal codes
corresponding to the minterms as in the following example.
Note : For ‘n’ variable maximum number of distinct minterms = 2n.
Example : 1
ABCD  ABCD  ABCD  ABCD
f (A, B, C, D) =    
0 13 12 11
= m0 + m13 + m12 + m11
or f (A, B, C, D) = (0, 11, 12, 13)
= sum of minterms.
Conversion from Boolean function to minterms form :
Example :
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Logic Gates & Boolean Algebra DIGITAL ELECTRONICS 2
Express the Boolean function in minterm form :

F(ABC) = A + BC
F = A(B  B) (C  C)  (A  A) (BC)
= (AB  AB) (C  C)  ABC  A BC
= ABC  ABC  ABC  ABC  ABC  ABC
= ABC
  ABC
  ABC
  ABC
  ABC

7 6 5 4 1
F = m1 + m4 + m5 + m6 + m7
F = (1, 4, 5, 6, 7)
(b) Maxterm Form :
If each term in POS form contain all the variables of the function then each term is called maxterm or
standard sum and function is called Maxterm form. The Maxterm is representated by “M”. The main prop-
erty of maxterm is that it possesses ‘0’ value only for one combination of input variables. The canonical
product of sum can also be expressed as the product of decimal codes corresponding to the maxterm as in
following example.
Note : For ‘n’ variable, maximum number of Distinct Maxterms = 2 n
Note : All the term missing in min term of SOP form is called as max term of POS form
Maxterm and Minterm table
Variables Minterm (m) Maxterm (M)
ABC
0 0 0 ABC  m 0 A + B + C = M0
0 0 1 ABC  m1 A  B  C  M1
0 10 ABC  m 2 A  B  C  M2
0 1 1 ABC  m3 A  B  C  M3
1 0 0 ABC  m 4 A  B  C  M4
1 0 1 ABC  m5 A  B  C  M5
1 1 0 ABC  m6 A  B  C  M6
1 1 1 ABC  m 7 A  B  C  M7
Note : Each maxterm is complement of corresponding minterm. For example maxterm corresponding to minterm
A BC is A BC which is equivalent to A + B + C.
Example :
(A  B  C) (A  B  C) (A  B  C) (A  B  C)
F (A, B, C) =    
M3 M1 M0 M2
F (A, B, C) = M0 . M1. M2 .M3

F(A, B, C) =  (0, 1, 2, 3)
Conversion of a boolean function to maxterm form :
Example :
Express the function given below in Maxterm Form.
F = xy  xz
= ( xy  x ) ( xy  z ) [ using distributive law]
= ( x  y ) ( z  y ) ( x  z ) ( x  x ) [ x  x  1, x x  x
= ( x  y) ( z  y) ( x  z )
= ( x  y  zz ) ( z  y  xx )( x  yy  z )
= ( x  y  z ) ( x  y  z )( x  y  z )
( x  y  z) ( x  y  z) ( x  y  z)
x  y  z) ( x  y  z ) ( x  y  z) ( x  y  z)
= (    
M4 M5 M0 M2
F = M0 . M2 . M4 . M5
F = (0, 2, 4, 5) =  (0, 2, 4, 5)
3.3 Conversion of Canonical Forms
3.3.1 SOP to POS Conversion
The compliment of a function expressed is the sum of minterms equals the sum of maxterms missing from the
original function. The conversion from canonical SOP to canonical POS is illustrated in example below.
Example :
Consider a functions F given in canonical SOP form. It can be converted to canonical POS as under,
F(A, B, C) = (1, 2, 3, 5)
Then F(A, B, C) = (0, 4, 6, 7)
or F(A, B, C) = m0 + m4 + m6 + m7
or F(A, B, C) = (m0  m4  m6  m7 )
= m0 . m4 . m6 . m7
F(A, B, C) = M0. M4 . M6. M7
 F(A, B, C) = (0, 4, 6, 7) – Maxterms
3.3.2 POS to SOP Conversion
The compliment of a function expressed in canonical POS is equal to POS of minterms missing from original
function.
If F (x, y, z) = (0, 2, 4, 5) – Maxterms
then F(x, y, z) = (1, 3, 6, 7) – Minterms
3.3.3 SOP and POS expressions from truth table
SOP expression is obtained by adding all product terms of truth table for which value of output is ‘1’. Similarly
POS expressions is obtained by all POS term for which function value is zero. In sum term the input variable
appears in a uncomplimented form if it has the value ‘0’ and in the complimented form if it has the value ‘1’.
The conversion of canonical POS and SOP is illustrated in table given below,
Inputs Outputs Product Sum term

A B C Y
0 0 0 0 ABC
0 0 1 1 A BC
0 1 0 0 ABC
0 1 1 0 ABC
1 0 0 1 A BC
1 0 1 1 A BC
1 1 0 0 ABC
1 1 1 1 A BC
The expression in SOP from,
y = A B C  A B C  A BC  ABC
=  (1, 4,5,7)
The expression in POS form,
y = (A  B  C) (A  B  C) (A  B  C) (A  B  C)
= (0, 2, 3, 6)
3.4 Realization of Boolean Functions given in POS and SOP forms
Case I : AND-OR realization of function given in SOP form:
In SOP expression each product term indicates AND operation and sum of product terms indicates OR
operation.
Each Product Term  AND operation
Sum  OR operation.
Example :
F = A  BC  ABC
A. AND-OR Realization
A
B BC
C
– ––
A Y=A+B C+AB C
–
B ––
– AB C
C
B . NAND-NAND : Complementing the given function,

F = A  BC  A BC
 F = A.BC.ABC
B BC
C F
–
A
–
B
– –––
C ABC
C. NOR-NOR :
F = A  BC  ABC
F = A.BC.(ABC)
F = A.(B  C) (A  B  C)
F = A  (B  C)  (A  B  C)
F = A  (B  C)  (A  B  C)
–
A
–
B
– F
C
A
B
C
Example : 2
Realize the following function :
F = (A + B) (C + D) E
A. Using AND-OR
A A+ B
B
C
F
D C+D
E
B. Using NAND gates
F = AB.CD.E
–
A AB
B
C CD F = A B C D·E
D
E F =AB C D E
C. Using NOR gates :

F = (A  B) (C  D) E
F = (A  B)  (C  D)  E
A A+ B
B
C C+D
F
D
3.5 Kernaugh’s map

K-map is a method to simplifying boolean function in a systematic mathematical way. In an n-variable K-
map, there are 2n cells. Each cell of K-map corresponds to one combination of n variables. So, each cell K-
map corresponds to either a minterm or a maxterm. The K-maps of 2, 3 and 4 variales are given below,
Note : K-maps are used to minimize the number of gates and fan in of a digital circuits.
Two Variable Karnaugh’s map :
Three Variable K-map 

(a) SOP BC B C B C BC BC
00 01 11 10
A
A 0 A B C0 A B C 1 A B C3 A B C2
A 1 A B C A B C ABC A B C
4 5 7 6
POS BC B+C B+C B+C B+C

00 01 11 10
A
A 0 A+B+C 0 A+B+C 1 A+B+C 3 A+B+C 2
A 1 A+B+C 4 A+B+C 5 A+B+C7 A+B+C 6
Four Variable K-map For SOP form
CD CD CD CD CD
(LSB) 00 01 11 10
(MSB) AB
AB 00 A B C D 0 A B C D 1 ABC D 3 ABC D 2
AB 01 A B C D 4 A B C D 5 ABC D 7 ABC D 6
AB 11 A B C D 12 A B C D 13 A B C D 15 A B C D 14
AB 10 ABC D 8 ABCD 9 A B C D 11 A B C D 10
D. Five variable K-maps :
A= 0
DE
BC 00 01 11 10
0 1 3 2
00
4 5 7 6
01
12 13 15 14
11
8 9 11 10
10
A= 1
CE
BC 00 01 11 10
00 16 17 19 18
01
20 21 23 22
11 30
28 29 31
10 26
24 25 27
Application of Karnaugh maps : Used to minimize the function.

Disadvantage  Can be used upto six variables only.
Advantage Simple.
3.6 Simplification of Boolean Functions using Kernaugh’s map
Rules of simplification : Rules from pg. 58 (Salivahanon)
3.6.1 Minimization of Boolean function from POS & SOP forms
Example : 1
Minimize the following function and realize using (i) NAND gates only (ii) NOR gates only.
F = A C  A B  A BC  BC
Solution :
BC – – – –
A BC BC BC BC
–
A 1 1 1
A 1 1
F = C  AB
Example : 2
Minimize the following function
F(A, B, C, D) = ABCD  ABCD  ACD  ABD  AD  A BC
Solution :
CD
AB –– – –
CD CD CD CD
–– 1
AB
0 4 12 8
– 1 1
AB
1 5 13 9
AB 1 1
3 7 15 11
– 1 1 1
AB 2 6 10
14
F = AD  ABC  ABC  ABCD

Example : 3
Minimize the following function using K-map
F(A, B, C) = (A  B) (A  C) (A  B  C)
Solution :
B+C – – – –
A B+C B+C B+C B+C
A 0 0
–
A 0 0 0
F = (B  C) (A  B) (A  B)
Example : 4
Simplify the following function using K-map.
F (A, B, C, D) = (A  B  C  D) (A  C  D)
(A  B  C  D) (B  D) (A  B)
Solution :
CD – – – –
AB C+D C+D C+D C+D
A+B 0 4
012 8
– 0 0 0 0
A+B 1 5 13 9
– – 0 0
A+B 3 11
7 15
– 0
A+B
2 6 14 10
F = (A  B) (C  D) (A  B  D)
3.6.2 Minimization of Boolean Function From Minterms and Maxterms

Example : 1
Minimize the following function using K-map.
F(A, B, C) = m(0, 1, 5, 7)
Solution :
BC BC BC BC BC
A 00 01 11 10
A0 0 1 3 2
1 1
A1 4 5 7 6
1 1
F = A B  AC
Example : 2
Simplify the following function using K-map,
F(A, B, C, D) = M(4, 6, 10, 12, 13, 15)
C+D
A+B
0+0 0+1 1+1 1+0
0 1 3 2
0+0
4 5 7 6
0+1
0 0
12 13 15 14
1+1
0
8 9 11 10
1+0
0 0 0
F = (A  B)(A  B  D)(A  C  D)
3.6.3 Don’t care condition
In some digital systems some combinations of input variables never occur, such combinations are called
don’t care conditions. The don’t care conditions can be paired with 1’s in case SOP and with 0’s in case of
POS expression.
Example : 3
Minimize the following :
F(A, B, C, D) = m (1, 3, 7, 11, 15) + d (0, 2, 5)
Solution :
CD
AB 00 01 11
10
0 1 3 2
00 d 1 1 d
4 5 7 6
01 d 1
12 13 15 14
11 1
8 9 11 10
10 1
––
F = AB + CD
Example : 4
Simplify the following function using K-map :
F(A, B, C, D) = M(4, 5, 6, 7, 8, 12).d(1, 2, 3, 9, 11, 14)
Solution :
CD
AB 00 01 11 10
0 1 3 2
00 d d d
4 5 7 6
01 0 0 0 0
12 13 15 14
11 0 d
8 9 11 10
10 0 d d
F = (A  B) (A  C  D)
Note : Minimized terms are called prime implicants and term consisting of all variable of function in minimized form
is called essential prime implicant.
3.6.4 Ex-OR and Ex-NOR simplification of K-maps :

A. Ex-OR simification of k maps :
i)
B
A 0 1
0 1
1 1
Y=A B
ii)
BC
A 00 01 11 10
0 1 3 2
0 1 1
41 5 71 6
1
Y=A B  C
iii)
CD
AB 00 01 11 10
0 1 3 2
00 1 1
4 5 7 6
01 1 1
12 13 15 14
11 1 1
8 9 11 10
10 1 1
Y=A B  C D
B. Ex-NOR Simplification :
i)
B
A 0 1
0 1
1 1
Y=A B
ii)
BC
A 00 01 11 10
0 1 1
1 1 1
Y=A B  C
iii)
CD
AB 00 01 11 10
00 1 1
01 1 1
11 1 1
10 1 1
Y=A B  C D

Boolean Functions & K-map DIGITAL ELECTRONICS 11
Objective Questions
Q.1 What Boolean function does the following circuit represent ?
(a) A[F+(B+C).(D+E)] (b) A[F+(B+C).(DE)]

(c) A[F.(BC+DE)] (d) A.[F.(B+C)+(D+E)]
IES (E & T)
Q.2 The minimum boolean for the following circuit is
B
A
C
A
A B
C
B
(a) AB + AC + BC (b) A + BC
(c) A + B (d) A + B + C
Q.3 The switching circuit given in the figure an be expressed in binary logic notation as
(a) L = (A + B) (C + D) E (b) L = AB + CD + E
(c) L = E + (A + B) (C + D) (d) L = (AB + CD) E
IES (EE)
Q.4 The Venn diagram representing the Boolean expression A + ( A . B) is
IES (E & T)
Q.5 The Boolean expression for the shaded area in the given venn diagram is]
(a) AB + BC + CA (b) ABC  ABC  ABC
(c) ABC  A B C (d) C B A  A B C
IES (E & T)
Q.6 The expression for shaded area shown below is ;
(a) A B  B C (b) ABC  A BC
(c) A B C  A B C (d) None of the above.
IES (E & T)
Q.7 Consider the folloing logic circuit:
What is the required input condition (A,B,C) to make the output X=1, for the above logic circuit?
(a) (1,0,1) (b) (0,0,1)
(c) (1,1,1) (d) (0,1,1)
IES (E & T)
Q.8
The circuit shown above is functionally equivalent to

(a) NOR gate (b) OR gate
(c) EX-OR gate (d) NAND gate
IES (E & T)
Q.9
Which one of the following circuits is the minimised logic circuit for the circuit shown in Figure -1 ?
IES (E & T)
Q.10 The output X of the logic circuit shown in the figure is
(a) A + BC (b) BC
(c) AB (d) AB + C
IES (E & T)
Q.11 The logic circuit shown in the given figure can be minimized to
IES (E & T)
Q.12
The minimized version of the logic circuit shown in figure is :
IES (E & T)
Q.13 The output X of the circuit shown in the figure will be
(a) A B (b) A B
(c) A B (d) A B
IES (E & T)
Q.14 Which one of the following is the truth table of the given logic circuit?
X Y Z X Y Z
0 0 1 0 0 0
(a ) 0 1 1 b bg 0 1 1
1 0 1 1 0 1
1 1 1 1 1 1
X Y Z X Y Z
0 0 1 0 0 0
bc g 0 1 0 bd g 0 1 1
1 0 0 1 0 1
1 1 0 1 1 0
IES (E & T)
Q.15 In Fig. the LED
(a) emits light when both S1 and S2 are closed

(b) emits light when both S1 and S2 are open
(c) emits light when only of S1 or S2 is closed
(d) does not emit light, irrespective of the switch positions.
GATE (E & T)
Q.16
The output of the gated network shown in the above figure is

(a) c AB h cC D h c EF h (b) AB  C D  EF
(c) AB + CD + EF (d) (A+B) (C+D) (E+F)
(IAS)
Q.17 A bulb is controlled by two switches A and B. The bulb glows only when either switch A or switch B is ON.
Its Boolean expression is
(a) AB  A B (b) A B  AB
(c) AB (d) A+B
(IAS)
Q.18 Given Boolean theorem AB  AC  BC  AB  AC
Which one of the following identies is true
(a) b A  B g .c A  C h .b B  C g  b A  B g .c A  C h
(b) AB  AC  BC  AB  BC
b gc
(c) AB  AC  BC  A  B . A  C . B  C hb g
(d) b A  Bg.c A  Ch.b B  Cg  AB  AC

IES (E & T)
Q.19 TheBooleantheorem AB  AC  BC  AC  AB corresponds to
(a) b A  Bgc A  Ch.b B  Cg  b A  Bg.c A  Ch

(b) AB  AC  BC  AB  BC
b gc hb g
(c) AB  AC  BC  A  B . A  C . B  C
(d) b A  Bg.c A  Ch.b B  Cg  AB  AC

IES (E & T)
Q.20 Which one of the following is the dual-form of the Boolean identity
b
AB  AC  A  C A  B gc h
(a) AB  AC  AC  AB
(b) b A  Bgc A  Ch  b A  Cgc A  Bh
(c) b A  Bgc A  Ch  AC  AB
(d) AB  AC  AB  AC  BC
IES (E & T)
Q.21 What is dual of X + XY = X + Y
(a) X  Y  X Y (b) X  X Y  XY
c
(c) X X  Y  X Y h c
(d) X XY Z  X Y Z  XYZ h
IES (E & T)
Q.22 What is dual of A + [B (A + C)] + D
(a) A + [(B(A + C)] + D (b) A [B + AC] D
(c) A + [B(A + C)] D (d) A [ B (A + C ) ] D
IES (E & T)
Q.23 With 4 Boolean variables, how many Boolean expressions can be formed ?
(a) 16 (b) 256
(c) 1024 (1K) (d) 64 K (64  1024)
IES (E & T)
Q.24 The number of switching function of 3 variables is
(a) 8 (b) 64
(c) 128 (d) 256
IES (E & T)
Q.25 The number of Boolean functions which can be generated with four variables is
(a) 4 (b) 16
(c) 256 (d) 65,536
IES (E & T)
Q.26 The number of Boolean functions that can be generated by n variables, is equal to
n
(a) 2n (b) 2 2
(c) 2n – 1 (d) 2n
GATE (E & T)
Q.27 c h
For the product-of-sums expression L = (X+Y) X  Z , the equivalent sum-of-products expression will be
(a) XY  X Z (b) X Y  XZ
(c) XY  XZ (d) XY  XZ
(IAS)
Q.28 The Boolean expression for the output Y in the logic circuit is
(a) ABC (b) ABC

(c) ABC (d) A B C
Q.29 The output of a two level AND-OR gate network is F. What is the output when all the gates are replaced by
NOR gates?
(a) F (b) F
(c) FD (d) F D
D
where F is the dual function of F.
Q.30 What is the minimum number of NAND gates required to implement A  AB  ABC ?
(a) 0 (b) 1
(c) 4 (d) 7
IES (E & T)
Q.31 Which one of the following is equivalent to AND-OR realization.
(a) NAND-NOR realization (b) NOR-NOR realization
(c) NOR-NAND realization (d) NAND-NAND realization
IES (E & T)
Q.32 The boolean function F = A.B. + C.D. + E can be realised
IES (E & T)
Q.33 The minimum number of 2-input NAND gates required to implement the Booleam function Z  ABC ,
assuming that A, B and C are available, is
(a) two (b) three
(c) five (d) six
GATE (E & T)
Q.34 Match List-I (Boolean function) with List-II (Minimum number of two-input NAND gates) and select the
correct answer using the codes given below the Lists:
List-I List-II
A. Y  ABC  ABC 1. Five
B. Y  A B  AB  C 2. Four
C. Y  AB  AB  ABC 3. Six
Codes:
A B C
(a) 3 1 2
(b) 1 3 2
(c) 2 1 3
(d) 1 2 3
(IAS)
Q.35 A, B and C are three Boolean variables. Which one of the following Boolean expressions cannot be minimized
any further?
(a) Z  A. B . C  A. B. C  A. B. C. A. B . C
(b) Z  A. B . C  A. B. C  A. B. C  A. B . C
(c) Z  A. B . C  A. B . C  A. B. C. A . B. C
(d) Z  A. B. C  A. B. C  A. B. C  A. B . C
IES (E & T)
Q.36
The minimized expression for the given K map (  don’t care) is

(a) A + B C (b) B + A C
(c) C + A B (d) A B C
IES (E & T)
Q.37 For the Karanaugh map shown in the given figure, the minimum boolean function is
(a) x' y' z' yz (b) xz' z  zy'

(c) xy  z  y' z (d) x  y  z
IES (E & T)
Q.38 Karnaugh map is used to
(a) minimise the number of flip-flop in a digital circuit
(b) minimise the number of gates only a digital circuit
(c) minimise the number of gates and fan-in of a digital circuit
(d) design gates
IES (E & T)
Q.39 Y = f (A, B) =  M (0, 1, 2, 3) represents (M is Maxterm)
(a) NOR gate
(b) NAND gate
(c) OR gate
(d) a situation where output is independent of input

IES (E & T)
Q.40 How many minterms (excluding redundant terms) does the minimal switching function
b g
f v , w, x , y , z  x  yz originally have ?
(a) 16 (b) 20
(c) 24 (d) 32
IES (E & T)
Q.41 While obtaining minimal sum of products expression,
(a) all don’t cares are ignored
(b) all don’t cares are treated as logic ones
(c) all don’t cares are treated as logic zeros
(d) only such don’t cares that aid minimisation are treated as logi cones
IES (E & T)
Q.42 The minimised expression for the given K-map is (X : don’t care)
(a) C B  BD  CD (b) AB  CB  BC
(c) CB  AC  BC (d) CB  CD  CB
IES (E & T)
Q.43 The product -of sum expression for given truth table is :
X Y Z
0 0 1
0 1 0
1 0 1
1 1 0
(a) c X  Y hb X  Y g (b) c X  Y hc X  Y h
(c) c X  Y hc X  Y h (d) None of the above
IES (E & T)
Q.44 The term AB + AC + C B reduce to
(a) AB + CA (b) AC + BC
(c) AC + B C (d) AB + B C
Q.45 The reduced form of the Boolean expression A B  C AB  AC b g is
(a) AB (b) AB
(c) AB (d) AB  BC
IES (EE)
Q.46 A combinational circuit has input A,B and C and its Karanaugh Map is a as shown. The output of the circuit
is given by
(a) c A B  A B hC (b) c AB  A B hC
(c) A B C (d) A  B  C
IES (EE)
Q.47 The Boolean expression AC  BC is equivalent to
(a) AC  BC  AC
(b) BC  AC  BC  ACB
(c) AC  BC  BC  ABC
(d) ABC  ABC  ABC  ABC
GATE (E & T)
Q.48 If the functions W,X,Y and Z are as follows
W  R  PQ  RS
X  PQR S  P Q R S  PQ R S
Y  RS  PR  PQ  P Q
Z  R  S  PQ  P Q R  P Q S
Then
(a) W  Z , X  Z (b) W=Z, X=Y
(c) W = Y (d) W  Y  Z
GATE (E & T)
Q.49 The minimal product-of-sums function described by the K-map given in.
AB
C 00 01 11 10
0 1 1  0
1 0 0  0
(a) A’C’ (b) A’+C’

(c) A + C (d) AC
GATE (EE)
Q.50 Consider the following expression:
1. Y = f (A,B,C,D) =  (1,2,4,7,8,11,13,14)
2. Y = f (A,B,C,D) =  (3,5,7,10,11,12,13,14)
3. Y = f (A,B,C,D) =  (0,3,5,6,9,10,12,15)
4. Y = f (A,B,C,D) = (0,1,2,4,6,8,9,15)
Which of these expressions are equivalent to the expression, Y  A  B  C  D ?
(a) 2 and 3 (b) 1 and 4
(c) 2 and 4 (d) 1 and 3
(IAS)
Q.51
AB
CD 00 01 11 10
00 1 0 0 1
01 1 1 1 1
11 0 0 0 0
10 1 0 0 1
The minimized expression for the K-map shown in the above figure is
(a) A BC D  ABCD  A BC  ABC  BC D
(b) CD + ABC + ABC + ABCD + ABCD
(c) BCD + BCD + CD
(d) B D  C D
(IAS)
Q.52 Consider following gate network
Which one of the following gates is redundant?

(a) Gate No. 1 (b) Gate No. 2
(c) Gate No. 3 (d) Gate No. 4
Q.53
If M (ABC) = AB + AC + BC, then M
cM b x x x g M b x x x g M bx x x gh will be
1 2 3 1 2 3 1 2 3
(a) x1  x2  x3 (b) x1  x2  x3
(c) x1 x2 x3  x1 x2 x3  x1 x2 x3 (d) x1 x2  x1 x3  x2  x3
IES (EE)
Q.54 There are four Boolean variables x1, x2, x3 and x4. The following functions are defined on sets of them:
b g  b3,4,5g
f x3 , x2 , x1 
g b x , x , x g   b1,6,7g
4 3 2
h b x , x , x x g  fg.
4 3 2 1
Then h b x , x , x , x g is
4 3 2 1
(a) zero (b)  b3,12,13g

(c)  b3,4,5,1,6,7g (d)  b3,12,15g
IES (EE)
Q.55 c hc
The simplified form of Boolean function A  B . A  C . B  C is : hc h
(a) b A  Bg . C (b) c A  B h . C
(c) c A  Bh . C (d) cA  Bh .C
(UPPCS)
Q.56 The number of rows in the truth table for 4-input OR gate is:
(a) 16 (b) 8
(c) 4 (d) 2
(MPPCS)
Q.57 The logic circuit shown below, is equivalent to a:
(a) NOR gate (b) OR gate

(c) AND gate (d) NAND gate
(MPPCS)
Q.58 The Boolean equation Y = ABC + ABC + ABC can simplified to:
(a) AB (c) AC
(c) A (B + C) (d) ABC
(MPPCS)
Q.59 The Boolean equation Y = (A + B) (A + B) can be simplified to
(a) A  B (b) AB
(c) A + B (d) AB
(MPPCS)
Q.60 What would be the output of circuit built using NAND gates shown in Figure given below:
(a) A.B (b) A + B

(c) A  B (d) AB  AB
(MPPCS)
Q.61 In the circuit shown below, the output Z is
(a) (A + B) (C + D) (b) A B  C D
(c) b A  B g  bC  Dg (d) b A  B g  b C  Dg
(RAS)
Q.62 The minimum number of NAND gates required to implement the Boolean functions A + AB + ABC is equal
to:
(a) Zero (b) One
(c) Four (d) Seven
(MPPCS
Q.63 In the fig. below if x1, x2, x3, x4 and x5 signals are 1, then the output is:
(a) 1 (b) 0
(c) 1 + 0 (d) either (A) or (B)
(MPPCS)
Q.64 The Karnaugh map for a four variable Boolean function is given in Fig. The correct Boolean sum of product
is
(a) PQRS + QS (b) PQRS + QS

(c) PQR + QS (d) PQRS + Q
GATE (INST)
Q.65 The minimal sum of products form of f  ABCD  ABC  BCD is
(a) AC  BD (b) CD + ABC
(c) AC  BD (d) AB  CD
GATE (INST)
Q.66 A combinatorial circuit has input A,B and C and its Karnaugh map is given in Fig. The output of the circuit is
AB
C 00 01 11 10
D 1 1
1 1 1
c
(a) AB  AB C h (b) c AB  AB h C
(c) A  B  C (d) A B C
GATE (INST)
Q.67 The Boolean expression
X ( P,Q,R) =  ( 0,5 )
Is to be realized using only two 2 - input gates. Which are these gates?
(a) AND and OR (b) NAND and OR
(c) AND and XOR (d) OR and XOR
Q.68
The circuit shown above is to be used to implement the function Z= f (A, B) = A + B. What values are to se
selected for I and J ?
(a) I = 0, J = B (b) I = 1, J = B
(c) I = B , J = 1 (d) I = B , J = 0
IES (E & T)
Q.69 The Boolean expressionY (A,B,C) = A + BC
Is to be realized using 2-input gates of only one type. What is the minimum number of gates required for the
realization?
(a) 1 (b) 2
(c) 3 (d) 4 or more
IES (E & T)
Q.70
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
What is the Boolean expression for the truth table shown above ?
(a) B( A  C)( A  C ) (b) B( A  C )( A  C )
(c) B  ( A  C )( A  C ) (d) B( A  C )( A  C )
IES (E & T)
Q.71
Which one of the following logic operations is performed by the digital circuit shown above ?
(a) NOR (b) NAND
(c) EX - OR (d) OR
IES (E & T)
Q.72
f1
f2
f
f3= ?
Consider the logic circuit shown in the figure given above. The functions f1, f2 and f (in canonical sum of
products form in decimal notation) are:
f1 (w,x,y,z) = 8,9,10
f2 (w,x,y,z) =  7,8,12,13,14,15
f (w,x,y,z) =  8,9
Which one of the following is the function f 3?
(a)  9,10 (b) 9
(c) 1,8,9 (d)  8,10,15
(IAS)
Q.73 Four logical expressions are given below:
1. A. B . C . D . E . F . G . H
2. AB. CD. EF . GH
3. A  B C  D  E  F G  H
4. c A  B hcC  D hc E  F hcG  H h
Two of these expressions are equal. They are
(a) 1 and 2 (b) 3 and 4
(c) 1 and 3 (d) 2 and 4
Q.74 Min - term (Sum of Products) expression for a Boolean function is given as follows)
f ( A,B,C) = m ( 0,1,2,3,5,6)
Where A is the MSB and C is the LSB. The minimized expression for the function is
(a) A + (B C ) (b) ( A  B )  C
(c) A  ( B  C ) (d) ABC
GATE (INST)
Q.75 The Boolen expression
F  A. B. C  A. B . C  A. B . C  A. B. C
after simplification yields the value of F as:
(a) A.B.C (b) A+B+C
(c) A+B (d) A
(UPPCS)
Q.76 Which of the following statements is not corrent?
 
(a) X + X Y = X (b) X ( X + Y) = X Y
 
(c) X + X Y = X (d) Z X + Z X Y = Z X + Z Y
IES (EE)
Q.77 AB + A C = (A + C) ( A + B).....
Which one of the following is the dual form of the Boolean identity given above ?
(a) AB + A C = AC + A B
(b) (A + B) ( A +C) = (A + C) ( A + B)
(c) (A + B) ( A + C) = AC + A B
(d) AB + A C = AB + A C + BC
IES (E & T)
Q.78
For the circuit shown above, the Boolean expression for the output Y in terms of inputs P, Q, R and S is
(a) P’ + Q’ + R’ + S’ (b) P + Q + R + S
(c) (P’ + Q’) (R’ + S’) (d) (P + Q)(R + S)
(IAS)
Q.79
If the input to the digital circuit consisting of a cascde of 20 XOR gates is X, then the output Y is equal to
(a) X’ (b) X
(c) 0 (d) 1
(IAS)
Q.80 The logic circuit shown converts y1.y2 into:

(a) gray code (b) excess 3-code

(c) BCD (d) error detecting code
IES (E & T)
Q.81 The circuit shown in Fig. is equivalent to
(a) (b)
(c) (d)
IES (E & T)
Answers & Explanations
Q.1 Ans. (a)

B D
A
C E
out
Switches in series : When switches are in series combination in electrical sense, they are said to be in AND
operation logically.
Switches in Parallel : When switches are in parallel combination in electrical sense, they are said to be in
OR operation logically.
In the given figure, B and C are in parallel so logically they result in (B + C)
Similarly D and E results in (D + E)
Now (B+C) and (D+E) are in series, so the resultant is (B+C) · (D+E).
Now this resultant (B+C) · (D+E) is in parallel to F so the resultant is F + (B + C) · (D + E)
Again this resultant {F + (B + C) · (D + E)} is in series with A
So the net logical resultant is [A ·{F  (B  C)·(D  E)}]
Q.2 Ans. (d)
d i c
then F  A. B  C  A . B  A  B . Ch
F = AB  AC  AB  AC  CB
F = c A  AhB  AcC  Ch  CB
F = B  A  CB  A  b B  C gc B  B h
F = A BC
Q.3 Ans. (a)
A C L
E
~ B D
(A+B) E
(C+D)
= ~
(A+B) · (C+D) · E
= ~
Q.4 Ans. (a)
F = A  AB  (A  A)(A  B)  A  B
Figure a represents A + B
A B
Q.5 Ans. (b)

In Venn diagram representation
1)
S
A
A
AA = S
2) A. B :– The area which is common to both A and B.
A·B
A B
3) A + B :– The area under A or B or both
A B
Now according to given figure
A.B.C
A B
C
A.B.C ABC
A·B·CA  B  C :– The area common to A, B and C
A·B·CA  B  C :– The area common to A, B and C
A·B·CA  B  C :– The area common to A , B and C

The resultant Boolean expression for the shaded area = A·B·C  ABC  ABC
Q.6 Ans. (c)
A ·B·C
A B
A ·B·C
C
A·B·C :– The area common to A, B and C
A·B·C :– The area common to A , B and C

The expression for shaded area
A·B·C  A·B·C
Q.7 Ans. (d)
A
A+ B
A·B (X)
A  B = AB  AB
B  C = BC  BC
X = (AB  AB)·(BC  BC)·C
= (AB  AB)·(B·C·C  BCC)
= (AB  AB)·(B·C  0)
= (AB)·(B·C)  (AB) (B·C)

= 0  A BC
= A·B·C
 X = A·B·C
For X = 1,
A = 0,
B = 1,
C = 1
Q.8 Ans. (c)
A
A
A·B
B
B
A
A
A·B
B
B
Y =  A·B· A·B
= A ·B  A·B
= A·B  A·B
This expression represents an Ex-OR gate
Q.9 Ans. (c)
A
B F
F = A  C  A BC
= ACABC
F = A BC
= A BC
A
B F = A+ B + C
C
Q.10 Ans. (c)

A A+B
B
(A + B) · (B + C)
(B + C)
B X
B
C
X = (A  B)·(B  C)·B
X = [AB  AC  BC]B
= AB + ABC
= AB (1 + C)
X = AB
Q.11 Ans. (d)
Q.12 Ans. (a)
x x
x.y.z F
y
z z
F = x  x·y·z  z
= x  (x  y  z)  z
= xxyzz
= xyz
x
x+y+z
y
z
Which is equivalent to
x
F
y
z
Q.13 Ans. (b)

A A+ B
B
X
A+B
X = [A  B]·[A  B]
X = [AB  AB] [A·B]
X = AB  0
= AB
Q.14 Ans. (a)
X
XY
Y Z
(X + Y)
Then Z = XYXY
Z = 1
The output is always 1 for all the possible combination of the inputs.
Q.15 Ans.(d)
+VCC
1K 1K
1K
LED
1
3
1K
S1 S2
2
LED will emit ligth only when the output of gate 3 is zero.
Case-1 :– When S1 and S2 both are open then
+VCC
1
1
1 1
1
3
1
2
0
1
The output of gate 3 will be 1 and LED will not emit light
Case-II :– When S1 is open and S2 is close
+VCC
LED
1
0
1
1
3
1K
2
1
1
again the output of gate 3 is logic 1 so, LED will not emit light
Case-III :– When S1 is close and S2 is open.
+VCC
LED
0
0
1 1
1 1
3
1 1K
2
0
1
LED will not emit light
Case-IV :– When both S1 and S2 are close
+VCC
LED
0
0
1
0
0 1
3
0 1K
2
1
1
the LED will not emit light. Thus, we can say that for any state of the suitable the LED will not emit light.
Q.16 Ans. (c)
A
A ·B
C
C ·D Y
E
E ·F
This circuit can be drawn as
C
Y
Y = AB + CD + EF
Q.17 Ans. (a)
The bulb is controlled by two switches A and B such that the bulb glows only when either switch A or switch
B is ON then truth table will be
A B Output
0 0 0
0 1 1
1 0 1
1 1 0
output = A B  A B
Q.18 Ans. (a)
AB  A C + BC = AB  A C
to find out the dual of any Boolean expression we just replace AND opeation by OR and OR operation by
AND operation (A  B)·(A  C)·(B  C)  (A  B)·(A  C)

Q.20 Ans. (c)
to find out the dual of any Boolean expression we just replace AND opeation by OR and OR operation by
AND operation
A B  A C = (A  C)·(A  B)
then we have to find out its dual
(A  B) (A  C) = A·C  A·B
Q.21 Ans. (c)
XXY = X + Y
its dual will be
X·[ X  Y] = X · Y
Q.22 Ans. (b)
F = A + [B · (A + C)] + D then its dual will be
F D = A · [B + A · C] · D
Q.23 Ans. (d)
n
With n Boolean variables, we can form (22 ) different Boolean expression.
For n = 4
4
We can form 22 = 216 = 26.210
Since 2 10 = 1 K or 1024
 2 · 210 = 64 K
6
or (64 × 1024) Boolean expressions

Q.24 Ans. (d)
n
For n variables, the number of switching functions = 22
For n = 3
3
Number of switching functions = 22 = 28 = 256
Q.25 Ans. (d)
n
With n variables we can generate 22 Boolean functions
4
So with n = 4 we cna generate 22 = 216 = 216 = 65, 536 Boolean functions
Q.26 Ans. (b)
n
By n variables we can generate 22 Boolean functions.
Q.27 Ans. (c)
We are provided with the POS expression
L = ( X  Z)·(X  Y)·1
= ( X  Z) (X  Y) (X  X)
L = ( X  Z) (X  XY)
= X Y  ZX  X Y Z
L = X Y(1  Z)  ZX
= X Y  ZX
Q.28 Ans. (b)
A
A
B Y
A C
Y = A·(A  A)·B·C
= ABC
Q.29 Ans. (c)
* Any Boolean expression which is given in the SOP form can be realized by the two level AND-OR gates
or using two-level NAND implementation.
* Any Boolean expression given in the POS form can be realized by two level OR-AND gates or NOR
implementation.
* NOR is dual of NAND gate. Consider an example
F = AB + CD (say)
A
B
F
C
D
in this logic circuit if we replace all the gates by NOR gate

A
B
F´
C
D
F´ = (A  B)  (C  D)
F´ = (A + B) · (C + D)
Now finding the dual of F
F D = (A + B) · (C + D)
So, FD  F
Q.30 Ans. (a)
F = A  AB  ABC
F = A[1  B  BC]
FA
There is no need of any NAND gate to realize A since it is given input
Q.31 Ans. (d)
A two level AND-OR gate network can be easily converted to a NAND-NAND gate network.
(a)
(b)
(c)
Q.32 Ans. (a)

F = A·B+C·D+E
First of all implement this gate using two-level AND-OR implementation
A A ·B
C C ·D
F
D
A A ·B
C C ·D
F
D
Inverted input OR gate NAND gate

A
C
F
D
Q.33 Ans. (c)

Z = A BC
= AC·B
Z = AC  B
A
C
A
1 2
C
Z
4 5
B 3
Q.34 Ans. (a)

A) Y = (A B  AB)·C
Y = (A  B)·C
A 2
1 4 Y
5 6
B 3
A3
B) Y = (A B  AB)  C
= (A B  A B)  C
Y = (A  B)  C
= (A  B)·C
A
2
1 4
B 3
Y
C 5
B 1
C) Y = AB  AB  ABC
Y = AB  (1  C)  AB
Y = AB  AB
= AB
Minimum four gates are reguired.
C2
Q.35 Ans. (c)
A) Z = A·BC  ABC  ABC  A BC
BC
A BC BC BC BC
A 1
A 1 1 1
Z = BC  AB
(It can be minimized)
B) Z = ABC  ABC  ABC  ABC
BC
A BC BC BC BC
A 1
A 1 1 1
Z = ABC  AC  AB
It can also be minimized
C) Z = ABC  ABC  ABC  ABC
BC
A BC BC BC BC
A 1 1
A 1 1
It can not be minimized further

Q.36 Ans. (a)
AB A B AB AB AB
CD 00 01 11 10
CD 00 0 0 1 1
CD 01 0 X X 1
CD 11 X X 1 X
CD 10 1 0 1 1
X = A  CB
Q.37 Ans. (a)
x x
yz 0 1 z
00 1 1
01 1
11 1 1 y
10 1 1
x
K map gives the expression
xyz
Now the expression given in alternative (a)
x y  z  yz
= x y  (z  z)(z  y)
= xyzy
= (x  y) (y  y)  z
= xyz
Hence alternative (a) is correct
Q.38 Ans. (c)
A K-Map is used to simplify the expressions thus it minimizes the number of gates of a digital circuit. The fan-
in of a gate is the number of inputs connected to the gate without any degradation in the voltage levels.
thus K Map minimizes the number of gates and fan-in of a digital circuit.
Q.39 Ans. (d)
y = f (A, B)
= M (0, 1, 2, 3)
A
B 0 1
0 0 0
y=0
1 0 0
Thus output is 0 for all inputs. It is independent of the input

Q.40 Ans. (b)
f (v, w, x, y, z) = x  y Z
xyz
vw 000 001 011 010 110 111 101 100
00 0 1 0 0 1 1 1 1
01 0 1 0 0 1 1 1 1
11 0 1 0 0 1 1 1 1
10 0 1 0 0 1 1 1 1
there are 20 minterms in the function

Q.41 Ans. (d)
A function with don’t care comninations is simplified to obtain minimal SOP expression the value 1 can be
assigned to selected don’t care combination.
This is done in order to increase the number of 1’s in the selected groups, wherever further simplification is
possible.
Also, a don’t care combination need not be used in grouping if it does not cover a large number of 1’s.
Q.42 Ans. (d)
AB
CD 00 01 11 10
00 1 1
01 1 X
11 1 1 X X
10 1 X X
F = BC  BC  CD
Q.43 Ans. (b)
X Y Z
0 0 1
0 1 0
1 0 1
1 1 0
Now draw the 2-variable K-map in POS form
Y Y Y
X 0 1
X 0 1 0
X 1 1 0
* We do not have to minimize it. We have to write the function in the POS form
then F = (X  Y) (X  Y)
Q.44 Ans. (c)
F = AB  AC  CB
BC
A 00 01 11 10
0 0 0 0 1
1 0 1 1 1
F = AC  BC
Q.45 Ans. (c)

F = A  B  C[AB  AC]
F = A  B  C A(B  C) 
F = A  B  C{A  B·C}
F = AB  AC [A  BC]
F = AB
Q.46 Ans. (d)
BC
C 00 01 11 10
0 1 1
1 1 1
Then F = ABC  ABC  ABC  ABC

F = A (BC  BC)  A (BC  BC)
F = A ·(B  C)  A (BC  BC)

F = A ·(B  C)  A (B  C)
F = A  BC
then
Q.47 Ans. (d)
F = AC  BC
F = AC·1  BC·1
F = AC(B  B)  BC(A  A)
F = ABC  ABC  ABC  ABC
Q.48 Ans. (a)
W = R  PQ  RS , draw K-map
RS
00 01 11 10
PQ
00 0 1 1 1
01 1 1 1 1
11 0 1 1 1
10 0 1 1 1
Fig. (a)
X = PQ RS  PQ RS  PQRS ,
draw K-map
RS
00 01 11 10
PQ
00 1 1 0 0
01 0 1 0 0
11 1 1 0 0
10 1 1 0 0
Fig. (b)
Y = RS   PR  PQ  PQ 
 
Y = RS   PR  Q (P  P) 
 
Y = RS   PR  Q 
 
Y = RS  PR ·Q
Y = RS  (P  R) Q
Y = RS  PQ  Q·R , draw K-map
RS
00 01 11 10
PQ
00 0 0 1 0
01 1 1 1 1
11 1 1 1 0
10 0 0 1 0
Fig. (c)
Z = R  S   PQ  PQR  PQS
 
Z = R  S  PQ·(PQR)·(PQS)
Z = R  S  (P  Q) (P  Q  R) (P  Q  S)
Z = R  S  (P  Q  R) (P  QS)
Z = R  S  P Q , draw K-map
RS
00 01 11 10
PQ
00 0 1 1 1
01 1 1 1 1
11 1 1 1 1
10 0 1 1 1
Fig. (d)
from fig (a) and fig (d) it is clear that

WZ
from fig b and fig (d) & fig (a) it is clear that
X = ZW
Q.49 Ans. (a)
AB
A+B A+B A+B A+B
C 00 01 11 10
C 0 1 1  0
C 1 0 0  0
We have to find out the minimized Boolean expression in POS form. So, we will combine the zero.
F = (C)·(A)
= C·A
Q.50 Ans. (d)
(1)
CD
00 01 11 10
AB
00 0 1 0 1
01 1 0 1 0
11 0 1 0 1
10 1 0 1 0
This is equivalent to Y  A  B  C  D
(2)
CD
00 01 11 10
AB
00 0 0 1 0
01 0 1 1 0
11 1 1 0 1
10 0 0 1 1
Number this iss not equivalent to A  B   D

(3)
C·D
00 01 11 10
A·B
00 0 1 0 1
01 1 0 1 0
11 0 1 0 1
10 1 0 1 0
Yes, this is equivalent to the Y  A  B  C  D

Q.51 Ans. (d)
AB
CD 00 01 11 10
00 1 0 0 1
01 1 1 1 1
11 0 0 0 0
10 1 0 0 1
X = C D  BD
Q.52 Ans. (b)
W
W 1
WX output
2 4
X
5
Y 3
Z XYZ
Output = W  WX  XYZ
Output = W(1  X)  XYZ
= W  XYZ
So, we can say that gate number 2 is redundant.
Q.53 Ans. (c)
x1 x2
00 01 11 10
x3 x4
00 1 d d
01 1 d 1
11 d 1
10 1 d d
f = x 2 x 4  x 2 x 4  x1 x 3
Q.54 Ans. (b)
f (X3, X2, X1) =  (3, 4,5)
x2 x1
x3 00 01 11 10
0 0 0 1 0
1 1 1 0 0
F = X 3 ·X 2  X 3 X 2 ·X1
g(x4 , x3 , x2) =  (1,6,7)
x3 x2
x4 00 01 11 10
0 0 1 0 0
1 0 0 1 1
g = x 4 ·x 3  x 4 x 3 ·x 2
f · g = X 3 ·X 2  X 3 X 2 ·X1 )
X 3 ·X 2  X 3 X 2 ·X1 )
f · g = (X 4 X 3 X 2  X 4 X 3 X 2 X1 )
h(X4, X3, X2, X1) = f · g
x 2 x1
x4 x3 00 01 11 10
00 0 0 1 0
01 0 0 0 0
11 1 1 0 0
10 0 0 0 0
h(X4, X3, X2, X1) =  (3,12,13)

Q.55 Ans. (c)
= (A  B)·(A  C)·(B  C)
= (A  B)·(A B  A C  C B  CC)
= (A  B)·(A B  A C  C B  C)
[CC  C]
= (A  B)·{(AB  (A  B  1)C}
[ 1  A  B  1]
= (A  B)·{AB  C}
= (A  B)·(A·B)  (A  B)C
= A·(AB)  B(A·B)  (A  B)C
= 0  0  (A  B) C
= (A  B) C
Q.56 Ans. (a)
The Truth table of 4 input OR gate will be as follows
A B C D Y
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
There are 16 rows

Q.57 Ans. (b)
A
A
B
B
Y = A·B
= AB
= A+B
Thus the logic circuit shown behaves as OR gate
Note :–
Bubbled NAND = OR
Bubbled NOR = AND
Q.58 Ans. (d)

Y = ABC + ABC + ABC
= ABC (1 + 1 + 1)
= ABC (1)
= ABC
Q.59 Ans. (c)
Y = (A + B) (A + B)
= AA + AB + BA + BB
= A + AB + B
= A [1 + B] + B
= A+B
 AA  A 
 BB  B 
 
 AB  BA  AB
Q.60 Ans. (b)
A
A
B
B
Y = A·B
= AB
= A+B
Q.61 Ans. (b)
A (A + B)
OR
B
NAND Z
A (C + D)
OR
B
Z = (A  B)·(C  D)
= (A  B)  (C  D)
= A·B  C·D
HINT :– [By using Demorgan’s theorem]
Q.62 Ans. (a)
Y = A + AB + ABC
= A [1 + B + B · C]
= A
 Y = A
There is no need of any NAND gate to implement A since it is already available input.
Q.63 Ans. (a)
The output of an X-OR gate is 1 only when inputs are not all same.
If all inputs of an X-OR gate are same its output is 0.
XOR
x1 P1
1 XOR
x2
P2
2 XOR
x3
P3
3
XOR
x4
P4
4
x5
For X OR gate (i)

Since x 1 = x2 = 1
 P1 = 0
Now for XOR gate (2)
P 1 = 0,
x3 = 1
 P2 = 1
P 2 = 1,
x4 = 1
 P3 = 0
P 3 = 0,
x5 = 1
 y =1
Q.64 Ans. (b)
PQ
RS 00 01 11 10
00 0 0 0 01
01 1 0 0 1
11 1 0 0 1
10 0 1 0 0
Y = QS  P Q RS
Q.65 Ans. (b)
Q.66 Ans. (c)
AB
C 00 01 11 10
0 1 1
1 1 1
Y = ABC  ABC  ABC  ABC

= (AB  AB)C  (AB  AB)C
= (A  B)C  (A  B)C
= A  BC
Q.67 Ans. (d)
X (P, Q, R) =  (0.5)
PQ
R 00 01 11 10
0 0
1 0
Y = (P  Q  R) (P  Q  R)
= PP  PQ  PR  QP  QQ  QR  RP  RQ  RR
= Q(P  P)  Q  PR  QR  RP  RQ
= Q  P  P  RR   PR  PR
= Q  PR  PR
= Q  P  R 
Hence we need OR gate and XOR gate
Q.68 Ans. (b)
Q.69 Ans. (d)
Q.70 Ans. (a)
AB
C 00 01 11 10
0 0 0 1 0
1 0 1 0 0
Y = (A  C) (C  A)B
Q.71 Ans. (d)
A
A A
A
Y
A
B
AB
Y = A  AB
= (A  A)(A  B)
= A+B
Q.72 Ans. (b)
Q.73 Ans. (d)
 A·B· C·D · E·F · G·H 

=  A  B · C  D · E  F · G  H 
Hence 2 and 4 are equal
Q.74 Ans. (c)
Q.75 Ans. (d)
F = A·B·C  A·B·C  A·B·C  A·B·C
= A·B  C  C   A·B  C  C 
= A·B  A B  B  B  1
= A  B  B 
= A
Q.76 Ans. (a)
a) X  XY = X  YX  X
= X+Y
Hence (a) is not correct
b) X XY  = XX  XY
= XY
 (b) is correct
c) X  XY = X 1  Y 
 
= X
 (c) is correct
d) ZX  ZXY = Z  X  XY 
= Z  X  X   X  Y 
= Z [X + Y]
= ZX + ZY
 (d) is correct
Q.77 Ans. (c)
To find out the dual of any Boolean expression we just replace AND opeation by OR and OR operation by
AND operation
A B  A C = (A  C)·(A  B)
then we have to find out its dual
(A  B) (A  C) = A·C  A·B
Q.78 Ans. (b)
P
P
(P · Q)
Q (P · Q) = P · Q
Q
Y
R
R (R · S)
(R · S) = R · S
S
S
This circuit can be drawn as

Y = (P + Q) + (R + S)
[as due know that NAND gate is equivalen to inverted input OR gate]
Q.79 Ans. (d)
Q.80 Ans. (a)

y2 y2 y1
x2
y1 y2
y1 x1
clearly x 1 = y1
x2 = y1  y 2
This circuit shows a binary to Gray code conversion
Point : Binary to Gray code conversion
1. MSB of Gray code is the same as MSB of binary number
2. The second bit of Gray code equals the exclusive-OR of the first (MSB) and second bits of the binary
number
3. The third Gray code bit equals the exclusive-OR of the second and third bits of the binary number and so
on.
Q.81 Ans. (d)

Boolean Functions and Their Realizations

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3

Boolean Functions and Their Realizations

Express the Boolean function in minterm form :

F (A, B, C) = M0 . M1. M2 .M3

Inputs Outputs Product Sum term

The expression in SOP from,

B . NAND-NAND : Complementing the given function,

C. Using NOR gates :

3.5 Kernaugh’s map

Three Variable K-map 

POS BC B+C B+C B+C B+C

A 1 A+B+C 4 A+B+C 5 A+B+C7 A+B+C 6

Four Variable K-map For SOP form

D. Five variable K-maps :

Application of Karnaugh maps : Used to minimize the function.

F = AD  ABC  ABC  ABCD

3.6.2 Minimization of Boolean Function From Minterms and Maxterms

3.6.4 Ex-OR and Ex-NOR simplification of K-maps :

Q.1 What Boolean function does the following circuit represent ?

(a) A[F+(B+C).(D+E)] (b) A[F+(B+C).(DE)]

The circuit shown above is functionally equivalent to

The minimized version of the logic circuit shown in figure is :

(a) emits light when both S1 and S2 are closed

The output of the gated network shown in the above figure is

(d) b A  Bg.c A  Ch.b B  Cg  AB  AC

(a) b A  Bgc A  Ch.b B  Cg  b A  Bg.c A  Ch

(d) b A  Bg.c A  Ch.b B  Cg  AB  AC

(a) ABC (b) ABC

The minimized expression for the given K map (  don’t care) is

(a) x' y' z' yz (b) xz' z  zy'

(d) a situation where output is independent of input

Q.45 The reduced form of the Boolean expression A B  C AB  AC b g is

(a) A’C’ (b) A’+C’

Which one of the following gates is redundant?

(a) zero (b)  b3,12,13g

(a) NOR gate (b) OR gate

(a) A.B (b) A + B

(a) PQRS + QS (b) PQRS + QS

(a) gray code (b) excess 3-code

Answers & Explanations

Q.1 Ans. (a)

Q.5 Ans. (b)

3) A + B :– The area under A or B or both

Now according to given figure

A·B·CA  B  C :– The area common to A, B and C

A·B·CA  B  C :– The area common to A, B and C

A·B·CA  B  C :– The area common to A , B and C

A·B·C :– The area common to A, B and C

A·B·C :– The area common to A , B and C

= (AB)·(B·C)  (AB) (B·C)

Q.10 Ans. (c)

Q.13 Ans. (b)

LED will not emit light

Case-IV :– When both S1 and S2 are close

This circuit can be drawn as

AND operation (A  B)·(A  C)·(B  C)  (A  B)·(A  C)

or (64 × 1024) Boolean expressions

in this logic circuit if we replace all the gates by NOR gate

Q.32 Ans. (a)

Inverted input OR gate NAND gate

Q.33 Ans. (c)

Q.34 Ans. (a)