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special for radar ECM applications are introduced in Denoting the content in the curly brackets from Equation
Section3. Section 4 put forward some simulations of the
(5) as:
designed DRFM function and jamming information
P 1 nS
modulation. H l ( w ) = ¦ h ( n K l )e j w n K e 2
j
(6)
n 0
jamming system.
Based on the assumption of input signal represented in The equivalent expression in time domain is:
complex format, reference [6] brought out an efficient K 1 2 K 1 2 S 2S
jl
y k ( n )= ¦ {{ x ( n l )
hl ( n )}e
jkl
implementation way for digital channelized receiver with 4 K
}e K
(8)
K channels in Fast Fourier Transform (FFT) format. But as l 0
to the applications in real world, they always have real Considering k and l as variables, Equation (8) is
signal as their input. On this occasion, half of the total equivalent to an Inverse Fast Fourier Transform (IFFT)
divided channels in the structure from [6] will have operation. When K is even, basic diagram of digital
redundant information. Reference [7] then proposed a channelized receiver can have its realization in poly-phase
channelized receiver architecture for real input. According structure in which the decimation operation has been
to its channel division, every channel has useful signal and carried out just before poly-phase filter in every channel
the central frequency of every channel is: according to Reference [8]. Diagram of AFB realization
2K 1 2S structure shown in Figure3 can be acquired. SFB has a
Ȧk ( k ) , k 0,1...K 1 (1) coupled architecture to AFB, which is described in Figure
4 K
4.
Channel number K equals to decimate index M in the
architecture defined in reference [7], which means the X(z) y0(n)
M H0(zF ) k 0 n 0
corresponding Discrete Fourier Transform (DFT)
filter-bank is implemented under a critical-sampled Z-1 y1(n)
H1(zF ) k 1 n 1
condition. Over-sampled DFT filter-bank with K>M has M
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Radar Signal
Parameters
Measurement Delay Control
for Channel A
N
r¦ fd A _ i
i 1
Channel JA-buffer-1
A N
Data r¦ fd B _ i Data
to Signal JB-buffer-1
i 1 to
Detecting 0 DAC
ADC N Synthesis
AFB and SFB. AFB analyzes input signal in interested ADC Analysis
Filter Bank
&
Adaptive
Channel
+
Synthesis
to
DAC
whole spectrum range and SFB reconstructs the signal Selecting Channel
B
Buffer-2 FIFO
0 Filter Bank
f
i 1
+
also have d Hz frequency compared with input signal.
Spectrum shifting in frequency domain is equivalent to Figure 7 Realization structure of modulation in serial
multiplication operation in time domain, so proper multiply
operation at the output of every channel can fulfill the
Doppler modulation implementation.
The frequency modulation method proposed above may 4 Simulation and Performance Evaluation
result in some amplitude distortions at the overlapped
boundary between neighbor channels. Analysis and 4.1 ASFB DRFM function verification
simulation have shown that only when the offset of
frequency shifting is large enough to the Megahertz level, The simulation prototype is established as Figure8. Only the
the possible distortion can lead to serious impact on the channels enclosing the input signal have the connecting
system performance. Doppler modulation in common paths between AFB and SFB, and the others input port in
jamming applications always has the frequency shifting no SFB are fed with zeros directly.
more than hundreds of KHz in usual jamming system
applications, so this method is applicable.
Connecting AFB, SFB and the Jamming Information
Modulation module together, we can establish the
fundamental part of the designed jamming system.
x n
Supposing the input signal has the bandwidth occupying
two continuous channels at most while modulation of N
deceptive targets in distance and two deceptive targets in
Doppler frequency domain are wanted, Figure 6 and Figure
7 give out two possible implementation schemes. Figure 6 Figure 8 Verifying simulation of synthesis with
generates multiple deceptive jamming targets in range with partial channel
block memory buffers working in parallel and Figure 7
generate these jamming signal through some
Taking a Chirp pulse train for simulation, it has pulse width
of 10 P s and modulated frequency band from 100 MHz to
First-In-First-Out(FIFO) memories working in serial. Both
of the two modulation architecture can realize deceptive
300 MHz. The spectrum of the input Chirp signal will
Doppler modulation in frequency domain.
appear in a group of channels as [5,6,7,9,10,11,12]. A
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70
0
68
-50
66
dB
all channels synthesis
64 single channel synthesis
Amplitude, dB
-100
62
-150
60
-200 58
Spectrum of filter bank input 50 100 150 200 250 300 350 400 450 500 550
MHz
Spectrum of filter bank output
-250
0 200 400 600
Frequency, MHz
800 1000 1200
Figure 11 SNR improvement in partial channel synthesis
-40
SNR. Simulation and practice have proved that the method
-60
proposed is effective and applicable.
-80 References
-100
0 20 40 60 80 100
[1] S. J. Roome, "Digital radio frequency memory,"
Frequency, KHz Electronics & Communication Engineering Journal, vol. 2,
Figure 10 Detecting result of Doppler frequency pp. 147-153, 1990.
[2] Sun Guoying, Li Yunjie, Gao Meiguo. An improved
modulated signal DRFM system based on digital channelized receiver[C].
Congress on Image and Signal Processing 2009:
3617-3620.
4.3 SNR improvement in partial channels synthesis [3] P. P. Vaidyanathan, Multirate systems and filter banks:
Prentice-Hall, Inc. Upper Saddle River, NJ, USA, 1993.
For an AFB and SFB implementation with 16 channels, [4] L. Xiaojian, "Acoustic echo cancellation over nonlinear
simulation has CW signal contaminated by noise as the channels." vol. PH.D: McGill University (Canada). , 2004.
input signal. The frequency of the input signal changes [5] P. P. V. Yuan-Pei Lin, "Application of DFT filter banks
from channel 1 to channel 16. Under the condition of input and cosine modulated filter banks in filtering," 1994.
signal with SNR as 60dB, results comparison between total [6] Y. Shi, "Design and Estimate for Multirate Systems."
channel synthesis and partial channel synthesis are plotted vol. PH.D: University of Alberta, 2006.
together in Figure12. [7] Zahirniak D R, Sharpin D L, Fields T W. A
Hardware-Efficient, MuItirate, Digital Channe1ized
Receiver Architecture; IEEE Transactions on Aerospace
and Electronic Systems, VOL.34, NO.1, January 1998.
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[8] Xu Hua, Lu Wusheng ˈ Efficient Iterative Design [9] Qi. Zhang, “Research and Realization of Broadband
Method for Cosine-Modulated QMF Banks; IEEE Digital Receiver”, Beijing Institute of Technology, 2006.
Transactions on Signal Processing, VOL.44, NO.7, July [10] Zong Bo. Wang, “Research on Jamming Techniques
1996. for Broadband and Widepulse Signal”, Beijing Institute of
Technology, 2009.
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