SCHOOL OF ELECTRICAL ENGINEERING

LAB MANUAL / RECORD

On

EEE 4028
VLSI DESIGN LABORATORY

Name: Adil Ahamed

Register Number: 18BEE0307
Lab Slot: L37+L38

Semester: Fall Semester 21-22

This work is submitted in partial fulfilment of the requirement of the award of the degree of
Bachelor of Technology in EEE/EIE

Internal Examiner External Examiner

1
 INDEX

Sl.No Date Title Marks Page No.

1. 10/08/2021 4-BIT RIPPLE CARRY ADDER 4

2. 17/08/2021 4-BIT CARRY LOOK AHEAD ADDER 8

3. 24/08/2021 4-BIT CARRY SAVE ARRAY MULTIPLIER 12

4. 31/08/2021 4-BIT BOUGH-WOOLEY ARRAY MULTIPLIER 16

5. 07/09/2021 4-BIT WALLACE TREE MULTIPLIER 21

6. 28-09-2021 4-BIT DADDA TREE MULTIPLIER 4

7. 05-10-2021 BINARY SQUARER 9

8. 09-11-2021 PIPELINED MAC DESIGN 17

9. 16-11-2021 FIR FILTER DESIGN 22

10. 23-11-2021 DCT DESIGN 26

2
Objectives:

• To provide students with the background needed to design, develop,

and test digital arithmetic circuits using IEEE standard Verilog HDL.

• To provide an understanding complex arithmetic circuit design principles and its

architecture design.

Outcomes:

• After completion of this course the students will be familiar with

design and implementation of Digital Arithmetic building blocks using Verilog HDL
and Modelsim Software.

3
Exp.No: 6
Date : 28/09/2021

4-BIT DADDA TREE MULTIPLIER

AIM:
Design a 4-bit dadda-tree multiplier using full adders and half adders.
REQUIRED SOFTWARE:
ModelSim SE
Microsoft Visio
CIRCUIT DIAGRAM:

4
Design Code:
Verilog module
module dadda_tree_mul(
input [3:0] a,
input [3:0] b,
output [7:0] p
);
wire [17:1]w;
assign p[0]=a[0]&b[0];
ha_df ha1((a[3]&b[0]),(a[2]&b[1]),w[1],w[2]);
ha_df ha2((a[3]&b[1]),(a[2]&b[2]),w[3],w[4]);
ha_df ha3((a[2]&b[0]),(a[1]&b[1]),w[5],w[6]);

fa_df fa1((a[1]&b[2]),(a[0]&b[3]),w[1],w[7],w[8]);
fa_df fa2((a[1]&b[3]),w[2],w[3],w[9],w[10]);
fa_df fa3((a[3]&b[2]),(a[2]&b[3]),w[4],w[11],w[12]);

ha_df ha4((a[0]&b[1]),(a[1]&b[0]),p[1],w[13]);

fa_df fa4((a[0]&b[2]),w[5],w[13],p[2],w[14]);
fa_df fa5(w[6],w[7],w[14],p[3],w[15]);
fa_df fa6(w[8],w[9],w[15],p[4],w[16]);
fa_df fa7(w[16],w[10],w[11],p[5],w[17]);
fa_df fa8(w[17],w[12],(a[3]&b[3]),p[6],p[7]);
endmodule

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module ha_df(input a,b, output sum,cout);
assign sum=a^b;
assign cout=a&b;
endmodule

module fa_df(input a,b,cin, output sum,cout);

assign sum=a^b^cin;
assign cout=(a&b)|(cin&(a^b));
endmodule

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Verilog test fixture
module dadda_tree_mul_test();
wire [7:0]p;
reg [3:0]a,b;
reg[7:0]check;
dadda_tree_mul UUT(a,b,p);
initial repeat(10) begin
a=$random;
b=$random;
check=a*b;
#10 $display($time,"%d*%d=%d[%d]",a,b,p,check);
end
endmodule

OUTPUT:

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CONSOLE OUTPUT:

# 10 4* 1= 4[ 4]
# 20 9* 3= 27[ 27]
# 3013*13=169[169]
# 40 5* 2= 10[ 10]
# 50 1*13= 13[ 13]
# 60 6*13= 78[ 78]
# 7013*12=156[156]
# 80 9* 6= 54[ 54]
# 90 5*10= 50[ 50]
# 100 5* 7= 35[ 35]

RESULT:
4-bit Dadda tree multiplier has been designed and the output is verified
successfully.
INFERENCE:
In this experiment learnt about how to construct multiple-bit multipliers.

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Exp.No: 7
Date : 05/10/2021

BINARY SQUARER
AIM:
Design 4-bit and 6-bit Binary Squarer using full adders and half adders.
REQUIRED SOFTWARE:
ModelSim SE
Microsoft Visio
CIRCUIT DIAGRAM:

9
4-BIT:
Design Code:
Verilog module
module squarer_4bit(input [3:0] a,output [7:0] p);
wire[4:1]w;
supply0 zero;
assign p[0]=a[0];
assign p[1]=zero;
assign p[2]=a[1]&(~a[0]);
ha_df ha1((a[1]&a[0]),(a[2]&a[0]),p[3],w[1]);
fa_df fa1((a[3]&a[0]),(a[2]&(~a[1])),w[1],p[4],w[2]);
fa_df fa2((a[2]&a[1]),(a[3]&a[1]),w[2],p[5],w[3]);
ha_df ha2((a[3]&(~a[2])),w[3],p[6],w[4]);
ha_df ha3((a[3]&a[2]),w[4],p[7],zero);
endmodule

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Verilog test fixture
module squarer_4bit_test( );
reg[3:0]a;
wire[7:0]p;
reg[7:0]check;
squarer_4bit uut(a,p);
initial repeat (10) begin
a=$random;
check=a*a;
#10 $display($time," %d * %d = %d [%d]",a,a,p,check);
end
endmodule

OUTPUT:

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CONSOLE OUTPUT:

# 10 4 * 4 = 16 [ 16]
# 20 1 * 1 = 1 [ 1]
# 30 9 * 9 = 81 [ 81]
# 40 3 * 3 = 9 [ 9]
# 50 13 * 13 = 169 [169]
# 60 13 * 13 = 169 [169]
# 70 5 * 5 = 25 [ 25]
# 80 2 * 2 = 4 [ 4]
# 90 1 * 1 = 1 [ 1]
# 100 13 * 13 = 169 [169]

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6-BIT:
Design Code:
Verilog module
module squarer_6bit(input signed[5:0]a,output signed[12:0]p);
wire[20:1]w;
supply0 zero;

assign p[0]=a[0];
assign p[1]=zero;
assign p[2]=(a[1]&~a[0]);

ha_df ha1((a[1]&a[0]),(a[2]&a[0]),p[3],w[1]);
ha_df ha2((a[2]&~a[1]),(a[3]&a[0]),w[2],w[3]);
fa_df fa1((a[2]&a[1]),(a[4]&a[0]),(a[3]&a[1]),w[4],w[5]);
fa_df fa2((a[3]&~a[2]),(a[5]&a[0]),(a[4]&a[1]),w[6],w[7]);
fa_df fa3((a[3]&a[2]),(a[1]&a[5]),(a[2]&a[4]),w[8],w[9]);
ha_df ha3((a[4]&~a[3]),(a[2]&a[5]),w[10],w[11]);
ha_df ha4((a[4]&a[3]),(a[3]&a[5]),w[12],w[13]);

ha_df ha5(w[1],w[2],p[4],w[14]);
fa_df fa4(w[3],w[4],w[14],p[5],w[15]);
fa_df fa5(w[5],w[6],w[15],p[6],w[16]);
fa_df fa6(w[7],w[8],w[16],p[7],w[17]);
fa_df fa7(w[9],w[10],w[17],p[8],w[18]);
fa_df fa8(w[11],w[12],w[18],p[9],w[19]);

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fa_df fa9((a[5]&~a[4]),w[13],w[19],p[10],w[20]);
ha_df ha6((a[5]&a[4]),w[20],p[11],p[12]);
endmodule

module ha_df(input a,b, output sum,cout);

assign sum=a^b;
assign cout=a&b;
endmodule

module fa_df(input a,b,cin, output sum,cout);

assign sum=a^b^cin;
assign cout=(a&b)|(cin&(a^b));
endmodule

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Verilog test fixture
module squarer_6bit_test;
reg[5:0]a;
wire[12:0]p;
reg[12:0]check;
squarer_6bit uut(.a(a),.p(p));
initial repeat (10) begin
a=$random;
check=a*a;
#10
$display($time," %d*%d=%d[%d]",a,a,p,check);
end
endmodule

OUTPUT:

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CONSOLE OUTPUT:

# 10 36*36=1296[1296]
# 20 1* 1= 1[ 1]
# 30 9* 9= 81[ 81]
# 40 35*35=1225[1225]
# 50 13*13= 169[ 169]
# 60 13*13= 169[ 169]
# 70 37*37=1369[1369]
# 80 18*18= 324[ 324]
# 90 1* 1= 1[ 1]
# 100 13*13= 169[ 169]

RESULT:
Binary Squarer of 4-bit and 6-bit has been designed and the output is
verified successfully.
INFERENCE:
In this experiment learnt about how to construct multiple-bit multipliers.

16
Exp.No: 8
Date : 09/11/2021

PIPELINED MAC DESIGN

AIM:
Design Pipelined MAC and implement circuit using ModelSim.
REQUIRED SOFTWARE:
ModelSim SE
Microsoft Visio
CIRCUIT DIAGRAM:

17
Design Code:
Verilog module
module pipelined_mac(
input [3:0] a,b,
input rst,clk,
output [9:0] y
);
wire [3:0]w1,w2;
wire [7:0]w3,w4;
wire [9:0]w5,w6;
reg_4bit r1(a,rst,clk,w1);
reg_4bit r2(b,rst,clk,w2);
assign w3=w1*w2;
reg_8bit r3(w3,rst,clk,w4);
assign w5=w4+w6;
reg_10bit r4(w5,rst,clk,w6);
assign y=w6;
endmodule
module reg_4bit(input [3:0]a, input rst,clk, output reg [3:0]y);
always @(posedge clk or negedge rst)
if(!rst)
y<=4'b0000;
else
y<=a;
endmodule

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module reg_8bit(input [7:0]a, input rst,clk, output reg [7:0]y);
always @(posedge clk or negedge rst)
if(!rst)
y<=8'b0000;
else
y<=a;
endmodule
module reg_10bit(input [9:0]a, input rst,clk, output reg [9:0]y);
always @(posedge clk or negedge rst)
if(!rst)
y<=10'b0000;
else
y<=a;
endmodule

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Verilog test fixture
module pipelined_mac_test();
reg [3:0] a,b;
reg clk,rst;
wire [9:0] y;
pipelined_mac UUT(a,b,rst,clk,y);
initial begin
rst=1'b0;
clk=1'b0;
#10;
rst=1'b1;
a=4'b0100;
b=4'b0101;
#10;
end
always #5 clk=~clk;
endmodule

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OUTPUT:

RESULT:
Pipelined MAC has been designed and the output is verified successfully.
INFERENCE:
In this experiment learnt about how to construct multiple-bit multipliers.

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Exp.No: 9
Date : 16/11/2021

FIR FILTER DESIGN

AIM:
Design FIR Filter and implement circuit using ModelSim.
REQUIRED SOFTWARE:
ModelSim SE
Microsoft Visio
CIRCUIT DIAGRAM:

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Design Code:
Verilog module
module FIR_design(input [3:0]x, input clk, rst, output [9:0]y);
wire [3:0] w1, w2, w3, w4;
wire [7:0] w5, w6, w7, w8;
wire [9:0] w9, w10;
parameter b0 = 4'b0001;
parameter b1 = 4'b0010;
parameter b2= 4'b0011;
parameter b3 = 4'b0100;
pipo p1(x, clk, rst, w1);
pipo p2(w1, clk, rst, w2);
pipo p3(w2, clk, rst, w3);
pipo p4(w3, clk, rst, w4);
assign w5 = b0*w1;
assign w6 = b1*w2;
assign w7 = b2*w3;
assign w8 = b3*w4;
assign w9 = w5+w6;
assign w10 = w7+w9;
assign y = w8+w10;
endmodule

module pipo(input [3:0] d, input clk,rst, output reg[3:0]q);

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always @(posedge clk or negedge rst)
if(!rst)
q<=4'b0000;
else
q<=d;
endmodule

Verilog test fixture

module FIR_test;
reg clk,rst;
reg [3:0] x;
wire [9:0] y;
FIR_design UUT(x,clk,rst,y);
initial begin
clk= 1'b0;
rst= 1'b0;
#15;
rst = 1'b1;
x = 4'b0001;
#10;
x = 4'b0010;
#10;
x = 4'b0011;
#10;
x = 4'b0100;
#10;
x = 4'b0000;
#10;
end
always #5 clk=~clk;
endmodule

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OUTPUT:

RESULT:
FIR Filter has been designed and the output is verified successfully.
INFERENCE:
In this experiment learnt about how to construct multiple-bit multipliers.

25
Exp.No: 10
Date : 23/11/2021

DCT DESIGN
AIM:
Design 4-point DCT and implement circuit using ModelSim.
REQUIRED SOFTWARE:
ModelSim SE
Microsoft Visio
CIRCUIT DIAGRAM:

26
Design Code:
Verilog module
module dct(input[3:0]a0,a1,a2,a3,output signed [11:0]y0,y1,y2,y3);
wire signed [4:0] m0,m1,p0,p1;
wire signed [5:0] w1,w2;
parameter c1=1;
parameter c2=2;
parameter c3=3;
assign m0=a0-a3;
assign m1=a1-a2;
assign p0=a0+a3;
assign p1=a1+a2;
assign w1=p0+p1;
assign w2=p0-p1;
assign y0=w1*c2;
assign y1=m0*c1+m1*c3;
assign y2=w2*c2;
assign y3=m0*c3-m1*c1;
endmodule

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Verilog test fixture
module dct_test();
reg [3:0]a0,a1,a2,a3;
wire signed [11:0]y0,y1,y2,y3;
dct UUT(.a0(a0),.a1(a1),.a2(a2),.a3(a3),.y0(y0),.y1(y1),.y2(y2),.y3(y3));
initial repeat(10) begin
a0=1;
a1=2;
a2=3;
a3=4;
#10;
end
endmodule

OUTPUT:

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RESULT:
DCT has been designed and the output is verified successfully.
INFERENCE:
In this experiment learnt about how to construct multiple-bit multipliers.

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