CCa Stats Out of Order

---------- Begin Simulation Statistics ----------
simSeconds 0.000029 #
Number of seconds simulated (Second)
simTicks 28931000 #
Number of ticks simulated (Tick)
finalTick 28931000 #
Number of ticks from beginning of simulation (restored from checkpoints and never
reset) (Tick)
simFreq 1000000000000 # The
number of ticks per simulated second ((Tick/Second))
hostSeconds 0.25 # Real
time elapsed on the host (Second)
hostTickRate 115878443 # The
number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 684444 #
Number of bytes of host memory used (Byte)
simInsts 51443 #
Number of instructions simulated (Count)
simOps 51443 #
Number of ops (including micro ops) simulated (Count)
hostInstRate 205930 #
Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 205917 #
Simulator op (including micro ops) rate (op/s) ((Count/Second))
system.clk_domain.clock 1000 # Clock
period in ticks (Tick)
system.cpu.numCycles 57863 #
Number of cpu cycles simulated (Cycle)
system.cpu.numWorkItemsStarted 0 #
Number of work items this cpu started (Count)
system.cpu.numWorkItemsCompleted 0 #
Number of work items this cpu completed (Count)
system.cpu.instsAdded 52637 #
Number of instructions added to the IQ (excludes non-spec) (Count)
system.cpu.nonSpecInstsAdded 13 #
Number of non-speculative instructions added to the IQ (Count)
system.cpu.instsIssued 52475 #
Number of instructions issued (Count)
system.cpu.squashedInstsIssued 20 #
Number of squashed instructions issued (Count)
system.cpu.squashedInstsExamined 1206 #
Number of squashed instructions iterated over during squash; mainly for profiling
(Count)
system.cpu.squashedOperandsExamined 509 #
Number of squashed operands that are examined and possibly removed from graph
(Count)
system.cpu.squashedNonSpecRemoved 3 #
Number of squashed non-spec instructions that were removed (Count)
system.cpu.numIssuedDist::samples 47988 #
Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::mean 1.093503 #
system.cpu.numIssuedDist::stdev 0.547254 #
system.cpu.numIssuedDist::underflows 0 0.00% 0.00% #
system.cpu.numIssuedDist::0 4703 9.80% 9.80% #
system.cpu.numIssuedDist::overflows 0 0.00% 100.00% #
system.cpu.numIssuedDist::min_value 0 #
system.cpu.numIssuedDist::max_value 6 #
system.cpu.numIssuedDist::total 47988 #
system.cpu.statFuBusy::No_OpClass 30 1.89% 1.89% #
attempts to use FU when none available (Count)
system.cpu.statFuBusy::IntAlu 30 1.89% 3.77% #
system.cpu.statFuBusy::IntMult 30 1.89% 5.66% #
system.cpu.statFuBusy::IntDiv 30 1.89% 7.55% #
system.cpu.statFuBusy::FloatAdd 30 1.89% 9.43% #
system.cpu.statFuBusy::FloatCmp 30 1.89% 11.32% #
system.cpu.statFuBusy::FloatCvt 30 1.89% 13.21% #
system.cpu.statFuBusy::FloatMult 30 1.89% 15.09% #
system.cpu.statFuBusy::FloatMultAcc 30 1.89% 16.98% #
system.cpu.statFuBusy::FloatDiv 30 1.89% 18.87% #
system.cpu.statFuBusy::FloatMisc 30 1.89% 20.75% #
system.cpu.statFuBusy::FloatSqrt 30 1.89% 22.64% #
system.cpu.statFuBusy::SimdAdd 30 1.89% 24.53% #
system.cpu.statFuBusy::SimdAddAcc 30 1.89% 26.42% #
system.cpu.statFuBusy::SimdAlu 30 1.89% 28.30% #
system.cpu.statFuBusy::SimdCmp 30 1.89% 30.19% #
system.cpu.statFuBusy::SimdCvt 30 1.89% 32.08% #
system.cpu.statFuBusy::SimdMisc 30 1.89% 33.96% #
system.cpu.statFuBusy::SimdMult 30 1.89% 35.85% #
system.cpu.statFuBusy::SimdMultAcc 30 1.89% 37.74% #
system.cpu.statFuBusy::SimdShift 30 1.89% 39.62% #
system.cpu.statFuBusy::SimdShiftAcc 30 1.89% 41.51% #
system.cpu.statFuBusy::SimdDiv 30 1.89% 43.40% #
system.cpu.statFuBusy::SimdSqrt 30 1.89% 45.28% #
system.cpu.statFuBusy::SimdFloatAdd 30 1.89% 47.17% #
system.cpu.statFuBusy::SimdFloatAlu 30 1.89% 49.06% #
system.cpu.statFuBusy::SimdFloatCmp 30 1.89% 50.94% #
system.cpu.statFuBusy::SimdFloatCvt 30 1.89% 52.83% #
system.cpu.statFuBusy::SimdFloatDiv 30 1.89% 54.72% #
system.cpu.statFuBusy::SimdFloatMisc 30 1.89% 56.60% #
system.cpu.statFuBusy::SimdFloatMult 30 1.89% 58.49% #
system.cpu.statFuBusy::SimdFloatMultAcc 30 1.89% 60.38% #
system.cpu.statFuBusy::SimdFloatSqrt 30 1.89% 62.26% #
system.cpu.statFuBusy::SimdReduceAdd 30 1.89% 64.15% #
system.cpu.statFuBusy::SimdReduceAlu 30 1.89% 66.04% #
system.cpu.statFuBusy::SimdReduceCmp 30 1.89% 67.92% #
system.cpu.statFuBusy::SimdFloatReduceAdd 30 1.89% 69.81% #
system.cpu.statFuBusy::SimdFloatReduceCmp 30 1.89% 71.70% #
system.cpu.statFuBusy::SimdAes 30 1.89% 73.58% #
system.cpu.statFuBusy::SimdAesMix 30 1.89% 75.47% #
system.cpu.statFuBusy::SimdSha1Hash 30 1.89% 77.36% #
system.cpu.statFuBusy::SimdSha1Hash2 30 1.89% 79.25% #
system.cpu.statFuBusy::SimdSha256Hash 30 1.89% 81.13% #
system.cpu.statFuBusy::SimdSha256Hash2 30 1.89% 83.02% #
system.cpu.statFuBusy::SimdShaSigma2 30 1.89% 84.91% #
system.cpu.statFuBusy::SimdShaSigma3 30 1.89% 86.79% #
system.cpu.statFuBusy::SimdPredAlu 30 1.89% 88.68% #
system.cpu.statFuBusy::MemRead 30 1.89% 90.57% #
system.cpu.statFuBusy::MemWrite 30 1.89% 92.45% #
system.cpu.statFuBusy::FloatMemRead 30 1.89% 94.34% #
system.cpu.statFuBusy::FloatMemWrite 30 1.89% 96.23% #
system.cpu.statFuBusy::IprAccess 30 1.89% 98.11% #
system.cpu.statFuBusy::InstPrefetch 30 1.89% 100.00% #
system.cpu.statIssuedInstType_0::No_OpClass 52475 1.89% 1.89% #
Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::IntAlu 52475 1.89% 3.77% #
system.cpu.statIssuedInstType_0::IntMult 52475 1.89% 5.66% #
system.cpu.statIssuedInstType_0::IntDiv 52475 1.89% 7.55% #
system.cpu.statIssuedInstType_0::FloatAdd 52475 1.89% 9.43% #
system.cpu.statIssuedInstType_0::FloatCmp 52475 1.89% 11.32% #
system.cpu.statIssuedInstType_0::FloatCvt 52475 1.89% 13.21% #
system.cpu.statIssuedInstType_0::FloatMult 52475 1.89% 15.09% #
system.cpu.statIssuedInstType_0::FloatMultAcc 52475 1.89% 16.98% #
system.cpu.statIssuedInstType_0::FloatDiv 52475 1.89% 18.87% #
system.cpu.statIssuedInstType_0::FloatMisc 52475 1.89% 20.75% #
system.cpu.statIssuedInstType_0::FloatSqrt 52475 1.89% 22.64% #
system.cpu.statIssuedInstType_0::SimdAdd 52475 1.89% 24.53% #
system.cpu.statIssuedInstType_0::SimdAddAcc 52475 1.89% 26.42% #
system.cpu.statIssuedInstType_0::SimdAlu 52475 1.89% 28.30% #
system.cpu.statIssuedInstType_0::SimdCmp 52475 1.89% 30.19% #
system.cpu.statIssuedInstType_0::SimdCvt 52475 1.89% 32.08% #
system.cpu.statIssuedInstType_0::SimdMisc 52475 1.89% 33.96% #
system.cpu.statIssuedInstType_0::SimdMult 52475 1.89% 35.85% #
system.cpu.statIssuedInstType_0::SimdMultAcc 52475 1.89% 37.74% #
system.cpu.statIssuedInstType_0::SimdShift 52475 1.89% 39.62% #
system.cpu.statIssuedInstType_0::SimdShiftAcc 52475 1.89% 41.51% #
system.cpu.statIssuedInstType_0::SimdDiv 52475 1.89% 43.40% #
system.cpu.statIssuedInstType_0::SimdSqrt 52475 1.89% 45.28% #
system.cpu.statIssuedInstType_0::SimdFloatAdd 52475 1.89% 47.17% #
system.cpu.statIssuedInstType_0::SimdFloatAlu 52475 1.89% 49.06% #
system.cpu.statIssuedInstType_0::SimdFloatCmp 52475 1.89% 50.94% #
system.cpu.statIssuedInstType_0::SimdFloatCvt 52475 1.89% 52.83% #
system.cpu.statIssuedInstType_0::SimdFloatDiv 52475 1.89% 54.72% #
system.cpu.statIssuedInstType_0::SimdFloatMisc 52475 1.89% 56.60% #
system.cpu.statIssuedInstType_0::SimdFloatMult 52475 1.89% 58.49% #
system.cpu.statIssuedInstType_0::SimdFloatMultAcc 52475 1.89%
60.38% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatSqrt 52475 1.89% 62.26% #
system.cpu.statIssuedInstType_0::SimdReduceAdd 52475 1.89% 64.15% #
system.cpu.statIssuedInstType_0::SimdReduceAlu 52475 1.89% 66.04% #
system.cpu.statIssuedInstType_0::SimdReduceCmp 52475 1.89% 67.92% #
system.cpu.statIssuedInstType_0::SimdFloatReduceAdd 52475 1.89%
system.cpu.statIssuedInstType_0::SimdFloatReduceCmp 52475 1.89%
system.cpu.statIssuedInstType_0::SimdAes 52475 1.89% 73.58% #
system.cpu.statIssuedInstType_0::SimdAesMix 52475 1.89% 75.47% #
system.cpu.statIssuedInstType_0::SimdSha1Hash 52475 1.89% 77.36% #
system.cpu.statIssuedInstType_0::SimdSha1Hash2 52475 1.89% 79.25% #
system.cpu.statIssuedInstType_0::SimdSha256Hash 52475 1.89% 81.13%
# Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSha256Hash2 52475 1.89% 83.02%
# Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdShaSigma2 52475 1.89% 84.91% #
system.cpu.statIssuedInstType_0::SimdShaSigma3 52475 1.89% 86.79% #
system.cpu.statIssuedInstType_0::SimdPredAlu 52475 1.89% 88.68% #
system.cpu.statIssuedInstType_0::MemRead 52475 1.89% 90.57% #
system.cpu.statIssuedInstType_0::MemWrite 52475 1.89% 92.45% #
system.cpu.statIssuedInstType_0::FloatMemRead 52475 1.89% 94.34% #
system.cpu.statIssuedInstType_0::FloatMemWrite 52475 1.89% 96.23% #
system.cpu.statIssuedInstType_0::IprAccess 52475 1.89% 98.11% #
system.cpu.statIssuedInstType_0::InstPrefetch 52475 1.89% 100.00% #
system.cpu.statIssuedInstType_0::total 2781175 #
system.cpu.issueRate 0.906884 # Inst
issue rate ((Count/Cycle))
system.cpu.fuBusy 30 # FU
busy when requested (Count)
system.cpu.fuBusyRate 0.000572 # FU
busy rate (busy events/executed inst) ((Count/Count))
system.cpu.intInstQueueReads 152988 #
Number of integer instruction queue reads (Count)
system.cpu.intInstQueueWrites 53857 #
Number of integer instruction queue writes (Count)
system.cpu.intInstQueueWakeupAccesses 52092 #
Number of integer instruction queue wakeup accesses (Count)
system.cpu.fpInstQueueReads 0 #
Number of floating instruction queue reads (Count)
system.cpu.fpInstQueueWrites 0 #
Number of floating instruction queue writes (Count)
system.cpu.fpInstQueueWakeupAccesses 0 #
Number of floating instruction queue wakeup accesses (Count)
system.cpu.vecInstQueueReads 0 #
Number of vector instruction queue reads (Count)
system.cpu.vecInstQueueWrites 0 #
Number of vector instruction queue writes (Count)
system.cpu.vecInstQueueWakeupAccesses 0 #
Number of vector instruction queue wakeup accesses (Count)
system.cpu.intAluAccesses 52495 #
Number of integer alu accesses (Count)
system.cpu.fpAluAccesses 0 #
Number of floating point alu accesses (Count)
system.cpu.vecAluAccesses 0 #
Number of vector alu accesses (Count)
system.cpu.idleCycles 0 #
Number of cycles IEW is idle (Cycle)
system.cpu.squashCycles 286 #
Number of cycles IEW is squashing (Cycle)
system.cpu.blockCycles 66 #
Number of cycles IEW is blocking (Cycle)
system.cpu.unblockCycles 0 #
Number of cycles IEW is unblocking (Cycle)
system.cpu.dispatchedInsts 52650 #
Number of instructions dispatched to IQ (Count)
system.cpu.dispSquashedInsts 278 #
Number of squashed instructions skipped by dispatch (Count)
system.cpu.dispLoadInsts 603 #
Number of dispatched load instructions (Count)
system.cpu.dispStoreInsts 576 #
Number of dispatched store instructions (Count)
system.cpu.dispNonSpecInsts 13 #
Number of dispatched non-speculative instructions (Count)
system.cpu.iqFullEvents 0 #
Number of times the IQ has become full, causing a stall (Count)
system.cpu.lsqFullEvents 0 #
Number of times the LSQ has become full, causing a stall (Count)
system.cpu.memOrderViolationEvents 1 #
Number of memory order violations (Count)
system.cpu.predictedTakenIncorrect 51 #
Number of branches that were predicted taken incorrectly (Count)
system.cpu.predictedNotTakenIncorrect 281 #
Number of branches that were predicted not taken incorrectly (Count)
system.cpu.branchMispredicts 332 #
Number of branch mispredicts detected at execute (Count)
system.cpu.numInsts 52210 #
Number of executed instructions (Count)
system.cpu.numLoadInsts 573 #
Number of load instructions executed (Count)
system.cpu.numSquashedInsts 265 #
Number of squashed instructions skipped in execute (Count)
system.cpu.numSwp 0 #
Number of swp insts executed (Count)
system.cpu.numNop 0 #
Number of nop insts executed (Count)
system.cpu.numRefs 1081 #
Number of memory reference insts executed (Count)
system.cpu.numBranches 8933 #
Number of branches executed (Count)
system.cpu.numStoreInsts 508 #
Number of stores executed (Count)
system.cpu.numRate 0.902304 # Inst
execution rate ((Count/Cycle))
system.cpu.instsToCommit 52135 #
Cumulative count of insts sent to commit (Count)
system.cpu.writebackCount 52092 #
Cumulative count of insts written-back (Count)
system.cpu.producerInst 25379 #
Number of instructions producing a value (Count)
system.cpu.consumerInst 25487 #
Number of instructions consuming a value (Count)
system.cpu.wbRate 0.900264 # Insts
written-back per cycle ((Count/Cycle))
system.cpu.wbFanout 0.995763 #
Average fanout of values written-back ((Count/Count))
system.cpu.timesIdled 123 #
Number of times that the entire CPU went into an idle state and unscheduled itself
(Count)
system.cpu.idleCycles 9875 # Total
number of cycles that the CPU has spent unscheduled due to idling (Cycle)
system.cpu.committedInsts 51443 #
Number of Instructions Simulated (Count)
system.cpu.committedOps 51443 #
Number of Ops (including micro ops) Simulated (Count)
system.cpu.cpi 1.124798 # CPI:
Cycles Per Instruction ((Cycle/Count))
system.cpu.totalCpi 1.124798 # CPI:
Total CPI of All Threads ((Cycle/Count))
system.cpu.ipc 0.889048 # IPC:
Instructions Per Cycle ((Count/Cycle))
system.cpu.totalIpc 0.889048 # IPC:
Total IPC of All Threads ((Count/Cycle))
system.cpu.intRegfileReads 77394 #
Number of integer regfile reads (Count)
system.cpu.intRegfileWrites 42799 #
Number of integer regfile writes (Count)
system.cpu.miscRegfileReads 10 #
number of misc regfile reads (Count)
system.cpu.MemDepUnit__0.insertedLoads 603 #
Number of loads inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__0.insertedStores 576 #
Number of stores inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__0.conflictingLoads 0 #
Number of conflicting loads. (Count)
system.cpu.MemDepUnit__0.conflictingStores 0 #
Number of conflicting stores. (Count)
system.cpu.branchPred.lookups 9361 #
Number of BP lookups (Count)
system.cpu.branchPred.condPredicted 8898 #
Number of conditional branches predicted (Count)
system.cpu.branchPred.condIncorrect 388 #
Number of conditional branches incorrect (Count)
system.cpu.branchPred.BTBLookups 8684 #
Number of BTB lookups (Count)
system.cpu.branchPred.BTBHits 8409 #
Number of BTB hits (Count)
system.cpu.branchPred.BTBHitRatio 0.968333 # BTB
Hit Ratio (Ratio)
system.cpu.branchPred.RASUsed 0 #
Number of times the RAS was used to get a target. (Count)
system.cpu.branchPred.RASIncorrect 0 #
Number of incorrect RAS predictions. (Count)
system.cpu.branchPred.indirectLookups 229 #
Number of indirect predictor lookups. (Count)
system.cpu.branchPred.indirectHits 11 #
Number of indirect target hits. (Count)
system.cpu.branchPred.indirectMisses 218 #
Number of indirect misses. (Count)
system.cpu.branchPred.indirectMispredicted 89 #
Number of mispredicted indirect branches. (Count)
system.cpu.commit.commitSquashedInsts 1206 # The
number of squashed insts skipped by commit (Count)
system.cpu.commit.commitNonSpecStalls 10 # The
number of times commit has been forced to stall to communicate backwards (Count)
system.cpu.commit.branchMispredicts 274 # The
number of times a branch was mispredicted (Count)
system.cpu.commit.numCommittedDist::samples 47636 #
Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::mean 1.079919 #
system.cpu.commit.numCommittedDist::stdev 0.579535 #
system.cpu.commit.numCommittedDist::underflows 0 0.00% 0.00% #
system.cpu.commit.numCommittedDist::0 5401 11.34% 11.34% #
system.cpu.commit.numCommittedDist::overflows 0 0.00% 100.00% #
system.cpu.commit.numCommittedDist::min_value 0 #
system.cpu.commit.numCommittedDist::max_value 8 #
system.cpu.commit.numCommittedDist::total 47636 #
system.cpu.commit.instsCommitted 51443 #
Number of instructions committed (Count)
system.cpu.commit.opsCommitted 51443 #
Number of ops (including micro ops) committed (Count)
system.cpu.commit.memRefs 868 #
Number of memory references committed (Count)
system.cpu.commit.loads 437 #
Number of loads committed (Count)
system.cpu.commit.amos 0 #
Number of atomic instructions committed (Count)
system.cpu.commit.membars 0 #
Number of memory barriers committed (Count)
system.cpu.commit.branches 8737 #
Number of branches committed (Count)
system.cpu.commit.vectorInstructions 0 #
Number of committed Vector instructions. (Count)
system.cpu.commit.floating 0 #
Number of committed floating point instructions. (Count)
system.cpu.commit.integer 51409 #
Number of committed integer instructions. (Count)
system.cpu.commit.functionCalls 151 #
Number of function calls committed. (Count)
system.cpu.commit.committedInstType_0::No_OpClass 51443 1.89%
1.89% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::IntAlu 51443 1.89% 3.77% #
Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::IntMult 51443 1.89% 5.66% #
system.cpu.commit.committedInstType_0::IntDiv 51443 1.89% 7.55% #
system.cpu.commit.committedInstType_0::FloatAdd 51443 1.89% 9.43%
# Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatCmp 51443 1.89% 11.32%
system.cpu.commit.committedInstType_0::FloatCvt 51443 1.89% 13.21%
system.cpu.commit.committedInstType_0::FloatMult 51443 1.89% 15.09%
system.cpu.commit.committedInstType_0::FloatMultAcc 51443 1.89%
system.cpu.commit.committedInstType_0::FloatDiv 51443 1.89% 18.87%
system.cpu.commit.committedInstType_0::FloatMisc 51443 1.89% 20.75%
system.cpu.commit.committedInstType_0::FloatSqrt 51443 1.89% 22.64%
system.cpu.commit.committedInstType_0::SimdAdd 51443 1.89% 24.53% #
system.cpu.commit.committedInstType_0::SimdAddAcc 51443 1.89%
system.cpu.commit.committedInstType_0::SimdAlu 51443 1.89% 28.30% #
system.cpu.commit.committedInstType_0::SimdCmp 51443 1.89% 30.19% #
system.cpu.commit.committedInstType_0::SimdCvt 51443 1.89% 32.08% #
system.cpu.commit.committedInstType_0::SimdMisc 51443 1.89% 33.96%
system.cpu.commit.committedInstType_0::SimdMult 51443 1.89% 35.85%
system.cpu.commit.committedInstType_0::SimdMultAcc 51443 1.89%
system.cpu.commit.committedInstType_0::SimdShift 51443 1.89% 39.62%
system.cpu.commit.committedInstType_0::SimdShiftAcc 51443 1.89%
system.cpu.commit.committedInstType_0::SimdDiv 51443 1.89% 43.40% #
system.cpu.commit.committedInstType_0::SimdSqrt 51443 1.89% 45.28%
system.cpu.commit.committedInstType_0::SimdFloatAdd 51443 1.89%
system.cpu.commit.committedInstType_0::SimdFloatAlu 51443 1.89%
system.cpu.commit.committedInstType_0::SimdFloatCmp 51443 1.89%
system.cpu.commit.committedInstType_0::SimdFloatCvt 51443 1.89%
system.cpu.commit.committedInstType_0::SimdFloatDiv 51443 1.89%
system.cpu.commit.committedInstType_0::SimdFloatMisc 51443 1.89%
system.cpu.commit.committedInstType_0::SimdFloatMult 51443 1.89%
system.cpu.commit.committedInstType_0::SimdFloatMultAcc 51443 1.89%
system.cpu.commit.committedInstType_0::SimdFloatSqrt 51443 1.89%
system.cpu.commit.committedInstType_0::SimdReduceAdd 51443 1.89%
system.cpu.commit.committedInstType_0::SimdReduceAlu 51443 1.89%
system.cpu.commit.committedInstType_0::SimdReduceCmp 51443 1.89%
system.cpu.commit.committedInstType_0::SimdFloatReduceAdd 51443 1.89%
system.cpu.commit.committedInstType_0::SimdFloatReduceCmp 51443 1.89%
system.cpu.commit.committedInstType_0::SimdAes 51443 1.89% 73.58% #
system.cpu.commit.committedInstType_0::SimdAesMix 51443 1.89%
system.cpu.commit.committedInstType_0::SimdSha1Hash 51443 1.89%
system.cpu.commit.committedInstType_0::SimdSha1Hash2 51443 1.89%
system.cpu.commit.committedInstType_0::SimdSha256Hash 51443 1.89%
system.cpu.commit.committedInstType_0::SimdSha256Hash2 51443 1.89%
system.cpu.commit.committedInstType_0::SimdShaSigma2 51443 1.89%
system.cpu.commit.committedInstType_0::SimdShaSigma3 51443 1.89%
system.cpu.commit.committedInstType_0::SimdPredAlu 51443 1.89%
system.cpu.commit.committedInstType_0::MemRead 51443 1.89% 90.57% #
system.cpu.commit.committedInstType_0::MemWrite 51443 1.89% 92.45%
system.cpu.commit.committedInstType_0::FloatMemRead 51443 1.89%
system.cpu.commit.committedInstType_0::FloatMemWrite 51443 1.89%
system.cpu.commit.committedInstType_0::IprAccess 51443 1.89% 98.11%
system.cpu.commit.committedInstType_0::InstPrefetch 51443 1.89%
system.cpu.commit.committedInstType_0::total 2726479 #
system.cpu.commit.commitEligibleSamples 16 #
number cycles where commit BW limit reached (Cycle)
system.cpu.dcache.demandHits::writebacks 841 #
number of demand (read+write) hits (Count)
system.cpu.dcache.demandHits::functional 841 #
system.cpu.dcache.demandHits::interrupt 841 #
system.cpu.dcache.demandHits::cpu.mmu.dtb.walker 841
# number of demand (read+write) hits (Count)
system.cpu.dcache.demandHits::cpu.mmu.itb.walker 841
system.cpu.dcache.demandHits::cpu.inst 841 #
system.cpu.dcache.demandHits::cpu.data 841 #
system.cpu.dcache.demandHits::total 5887 #
system.cpu.dcache.overallHits::writebacks 841 #
number of overall hits (Count)
system.cpu.dcache.overallHits::functional 841 #
system.cpu.dcache.overallHits::interrupt 841 #
system.cpu.dcache.overallHits::cpu.mmu.dtb.walker 841
# number of overall hits (Count)
system.cpu.dcache.overallHits::cpu.mmu.itb.walker 841
system.cpu.dcache.overallHits::cpu.inst 841 #
system.cpu.dcache.overallHits::cpu.data 841 #
system.cpu.dcache.overallHits::total 5887 #
system.cpu.dcache.demandMisses::writebacks 154 #
number of demand (read+write) misses (Count)
system.cpu.dcache.demandMisses::functional 154 #
system.cpu.dcache.demandMisses::interrupt 154 #
system.cpu.dcache.demandMisses::cpu.mmu.dtb.walker 154
# number of demand (read+write) misses (Count)
system.cpu.dcache.demandMisses::cpu.mmu.itb.walker 154
system.cpu.dcache.demandMisses::cpu.inst 154 #
system.cpu.dcache.demandMisses::cpu.data 154 #
system.cpu.dcache.demandMisses::total 1078 #
system.cpu.dcache.overallMisses::writebacks 154 #
number of overall misses (Count)
system.cpu.dcache.overallMisses::functional 154 #
system.cpu.dcache.overallMisses::interrupt 154 #
system.cpu.dcache.overallMisses::cpu.mmu.dtb.walker 154
# number of overall misses (Count)
system.cpu.dcache.overallMisses::cpu.mmu.itb.walker 154
system.cpu.dcache.overallMisses::cpu.inst 154 #
system.cpu.dcache.overallMisses::cpu.data 154 #
system.cpu.dcache.overallMisses::total 1078 #
system.cpu.dcache.demandMissLatency::writebacks 8175500
# number of demand (read+write) miss ticks (Tick)
system.cpu.dcache.demandMissLatency::functional 8175500
system.cpu.dcache.demandMissLatency::interrupt 8175500 #
number of demand (read+write) miss ticks (Tick)
system.cpu.dcache.demandMissLatency::cpu.mmu.dtb.walker 8175500
system.cpu.dcache.demandMissLatency::cpu.mmu.itb.walker 8175500
system.cpu.dcache.demandMissLatency::cpu.inst 8175500 #
system.cpu.dcache.demandMissLatency::cpu.data 8175500 #
system.cpu.dcache.demandMissLatency::total 57228500 #
system.cpu.dcache.overallMissLatency::writebacks 8175500
# number of overall miss ticks (Tick)
system.cpu.dcache.overallMissLatency::functional 8175500
system.cpu.dcache.overallMissLatency::interrupt 8175500
system.cpu.dcache.overallMissLatency::cpu.mmu.dtb.walker 8175500
system.cpu.dcache.overallMissLatency::cpu.mmu.itb.walker 8175500
system.cpu.dcache.overallMissLatency::cpu.inst 8175500 #
number of overall miss ticks (Tick)
system.cpu.dcache.overallMissLatency::cpu.data 8175500 #
system.cpu.dcache.overallMissLatency::total 57228500 #
system.cpu.dcache.demandAccesses::writebacks 995 #
number of demand (read+write) accesses (Count)
system.cpu.dcache.demandAccesses::functional 995 #
system.cpu.dcache.demandAccesses::interrupt 995 #
system.cpu.dcache.demandAccesses::cpu.mmu.dtb.walker 995
# number of demand (read+write) accesses (Count)
system.cpu.dcache.demandAccesses::cpu.mmu.itb.walker 995
system.cpu.dcache.demandAccesses::cpu.inst 995 #
system.cpu.dcache.demandAccesses::cpu.data 995 #
system.cpu.dcache.demandAccesses::total 6965 #
system.cpu.dcache.overallAccesses::writebacks 995 #
number of overall (read+write) accesses (Count)
system.cpu.dcache.overallAccesses::functional 995 #
system.cpu.dcache.overallAccesses::interrupt 995 #
system.cpu.dcache.overallAccesses::cpu.mmu.dtb.walker 995
# number of overall (read+write) accesses (Count)
system.cpu.dcache.overallAccesses::cpu.mmu.itb.walker 995
system.cpu.dcache.overallAccesses::cpu.inst 995 #
system.cpu.dcache.overallAccesses::cpu.data 995 #
system.cpu.dcache.overallAccesses::total 6965 #
system.cpu.dcache.demandMissRate::writebacks 0.154774 #
miss rate for demand accesses (Ratio)
system.cpu.dcache.demandMissRate::functional 0.154774 #
system.cpu.dcache.demandMissRate::interrupt 0.154774 #
system.cpu.dcache.demandMissRate::cpu.mmu.dtb.walker 0.154774
# miss rate for demand accesses (Ratio)
system.cpu.dcache.demandMissRate::cpu.mmu.itb.walker 0.154774
system.cpu.dcache.demandMissRate::cpu.inst 0.154774 #
system.cpu.dcache.demandMissRate::cpu.data 0.154774 #
system.cpu.dcache.demandMissRate::total 0.154774 # miss
rate for demand accesses (Ratio)
system.cpu.dcache.overallMissRate::writebacks 0.154774 #
miss rate for overall accesses (Ratio)
system.cpu.dcache.overallMissRate::functional 0.154774 #
system.cpu.dcache.overallMissRate::interrupt 0.154774 #
system.cpu.dcache.overallMissRate::cpu.mmu.dtb.walker 0.154774
# miss rate for overall accesses (Ratio)
system.cpu.dcache.overallMissRate::cpu.mmu.itb.walker 0.154774
system.cpu.dcache.overallMissRate::cpu.inst 0.154774 #
system.cpu.dcache.overallMissRate::cpu.data 0.154774 #
system.cpu.dcache.overallMissRate::total 0.154774 # miss
rate for overall accesses (Ratio)
system.cpu.dcache.demandAvgMissLatency::writebacks 53087.662338
# average overall miss latency ((Cycle/Count))
system.cpu.dcache.demandAvgMissLatency::functional 53087.662338
system.cpu.dcache.demandAvgMissLatency::interrupt 53087.662338
system.cpu.dcache.demandAvgMissLatency::cpu.mmu.dtb.walker 53087.662338
system.cpu.dcache.demandAvgMissLatency::cpu.mmu.itb.walker 53087.662338
system.cpu.dcache.demandAvgMissLatency::cpu.inst 53087.662338
system.cpu.dcache.demandAvgMissLatency::cpu.data 53087.662338
system.cpu.dcache.demandAvgMissLatency::total 53087.662338 #
average overall miss latency ((Cycle/Count))
system.cpu.dcache.overallAvgMissLatency::writebacks 53087.662338
system.cpu.dcache.overallAvgMissLatency::functional 53087.662338
system.cpu.dcache.overallAvgMissLatency::interrupt 53087.662338
system.cpu.dcache.overallAvgMissLatency::cpu.mmu.dtb.walker 53087.662338
system.cpu.dcache.overallAvgMissLatency::cpu.mmu.itb.walker 53087.662338
system.cpu.dcache.overallAvgMissLatency::cpu.inst 53087.662338
system.cpu.dcache.overallAvgMissLatency::cpu.data 53087.662338
system.cpu.dcache.overallAvgMissLatency::total 53087.662338 #
system.cpu.dcache.blockedCycles::no_mshrs 15 #
number of cycles access was blocked (Cycle)
system.cpu.dcache.blockedCycles::no_targets 15 #
system.cpu.dcache.blockedCauses::no_mshrs 2 #
number of times access was blocked (Count)
system.cpu.dcache.blockedCauses::no_targets 2 #
system.cpu.dcache.avgBlocked::no_mshrs 7.500000 #
average number of cycles each access was blocked ((Cycle/Count))
system.cpu.dcache.avgBlocked::no_targets 7.500000 #
system.cpu.dcache.demandMshrHits::writebacks 106 #
number of demand (read+write) MSHR hits (Count)
system.cpu.dcache.demandMshrHits::functional 106 #
system.cpu.dcache.demandMshrHits::interrupt 106 #
system.cpu.dcache.demandMshrHits::cpu.mmu.dtb.walker 106
# number of demand (read+write) MSHR hits (Count)
system.cpu.dcache.demandMshrHits::cpu.mmu.itb.walker 106
system.cpu.dcache.demandMshrHits::cpu.inst 106 #
system.cpu.dcache.demandMshrHits::cpu.data 106 #
system.cpu.dcache.demandMshrHits::total 742 #
system.cpu.dcache.overallMshrHits::writebacks 106 #
number of overall MSHR hits (Count)
system.cpu.dcache.overallMshrHits::functional 106 #
system.cpu.dcache.overallMshrHits::interrupt 106 #
system.cpu.dcache.overallMshrHits::cpu.mmu.dtb.walker 106
# number of overall MSHR hits (Count)
system.cpu.dcache.overallMshrHits::cpu.mmu.itb.walker 106
system.cpu.dcache.overallMshrHits::cpu.inst 106 #
system.cpu.dcache.overallMshrHits::cpu.data 106 #
system.cpu.dcache.overallMshrHits::total 742 #
system.cpu.dcache.demandMshrMisses::writebacks 48 #
number of demand (read+write) MSHR misses (Count)
system.cpu.dcache.demandMshrMisses::functional 48 #
system.cpu.dcache.demandMshrMisses::interrupt 48 #
system.cpu.dcache.demandMshrMisses::cpu.mmu.dtb.walker 48
# number of demand (read+write) MSHR misses (Count)
system.cpu.dcache.demandMshrMisses::cpu.mmu.itb.walker 48
system.cpu.dcache.demandMshrMisses::cpu.inst 48 #
system.cpu.dcache.demandMshrMisses::cpu.data 48 #
system.cpu.dcache.demandMshrMisses::total 336 #
system.cpu.dcache.overallMshrMisses::writebacks 48
# number of overall MSHR misses (Count)
system.cpu.dcache.overallMshrMisses::functional 48
system.cpu.dcache.overallMshrMisses::interrupt 48 #
number of overall MSHR misses (Count)
system.cpu.dcache.overallMshrMisses::cpu.mmu.dtb.walker 48
system.cpu.dcache.overallMshrMisses::cpu.mmu.itb.walker 48
system.cpu.dcache.overallMshrMisses::cpu.inst 48 #
system.cpu.dcache.overallMshrMisses::cpu.data 48 #
system.cpu.dcache.overallMshrMisses::total 336 #
system.cpu.dcache.demandMshrMissLatency::writebacks 2776500
# number of demand (read+write) MSHR miss ticks (Tick)
system.cpu.dcache.demandMshrMissLatency::functional 2776500
system.cpu.dcache.demandMshrMissLatency::interrupt 2776500
system.cpu.dcache.demandMshrMissLatency::cpu.mmu.dtb.walker 2776500
system.cpu.dcache.demandMshrMissLatency::cpu.mmu.itb.walker 2776500
system.cpu.dcache.demandMshrMissLatency::cpu.inst 2776500
system.cpu.dcache.demandMshrMissLatency::cpu.data 2776500
system.cpu.dcache.demandMshrMissLatency::total 19435500 #
number of demand (read+write) MSHR miss ticks (Tick)
system.cpu.dcache.overallMshrMissLatency::writebacks 2776500
# number of overall MSHR miss ticks (Tick)
system.cpu.dcache.overallMshrMissLatency::functional 2776500
system.cpu.dcache.overallMshrMissLatency::interrupt 2776500
system.cpu.dcache.overallMshrMissLatency::cpu.mmu.dtb.walker 2776500
system.cpu.dcache.overallMshrMissLatency::cpu.mmu.itb.walker 2776500
system.cpu.dcache.overallMshrMissLatency::cpu.inst 2776500
system.cpu.dcache.overallMshrMissLatency::cpu.data 2776500
system.cpu.dcache.overallMshrMissLatency::total 19435500
system.cpu.dcache.demandMshrMissRate::writebacks 0.048241
# mshr miss ratio for demand accesses (Ratio)
system.cpu.dcache.demandMshrMissRate::functional 0.048241
system.cpu.dcache.demandMshrMissRate::interrupt 0.048241
system.cpu.dcache.demandMshrMissRate::cpu.mmu.dtb.walker 0.048241
system.cpu.dcache.demandMshrMissRate::cpu.mmu.itb.walker 0.048241
system.cpu.dcache.demandMshrMissRate::cpu.inst 0.048241 #
mshr miss ratio for demand accesses (Ratio)
system.cpu.dcache.demandMshrMissRate::cpu.data 0.048241 #
system.cpu.dcache.demandMshrMissRate::total 0.048241 #
system.cpu.dcache.overallMshrMissRate::writebacks 0.048241
# mshr miss ratio for overall accesses (Ratio)
system.cpu.dcache.overallMshrMissRate::functional 0.048241
system.cpu.dcache.overallMshrMissRate::interrupt 0.048241
system.cpu.dcache.overallMshrMissRate::cpu.mmu.dtb.walker 0.048241
system.cpu.dcache.overallMshrMissRate::cpu.mmu.itb.walker 0.048241
system.cpu.dcache.overallMshrMissRate::cpu.inst 0.048241
system.cpu.dcache.overallMshrMissRate::cpu.data 0.048241
system.cpu.dcache.overallMshrMissRate::total 0.048241 #
mshr miss ratio for overall accesses (Ratio)
system.cpu.dcache.demandAvgMshrMissLatency::writebacks 57843.750000
# average overall mshr miss latency ((Cycle/Count))
system.cpu.dcache.demandAvgMshrMissLatency::functional 57843.750000
system.cpu.dcache.demandAvgMshrMissLatency::interrupt 57843.750000
system.cpu.dcache.demandAvgMshrMissLatency::cpu.mmu.dtb.walker 57843.750000
system.cpu.dcache.demandAvgMshrMissLatency::cpu.mmu.itb.walker 57843.750000
system.cpu.dcache.demandAvgMshrMissLatency::cpu.inst 57843.750000
system.cpu.dcache.demandAvgMshrMissLatency::cpu.data 57843.750000
system.cpu.dcache.demandAvgMshrMissLatency::total 57843.750000
system.cpu.dcache.overallAvgMshrMissLatency::writebacks 57843.750000
system.cpu.dcache.overallAvgMshrMissLatency::functional 57843.750000
system.cpu.dcache.overallAvgMshrMissLatency::interrupt 57843.750000
system.cpu.dcache.overallAvgMshrMissLatency::cpu.mmu.dtb.walker 57843.750000
system.cpu.dcache.overallAvgMshrMissLatency::cpu.mmu.itb.walker 57843.750000
system.cpu.dcache.overallAvgMshrMissLatency::cpu.inst 57843.750000
system.cpu.dcache.overallAvgMshrMissLatency::cpu.data 57843.750000
system.cpu.dcache.overallAvgMshrMissLatency::total 57843.750000
system.cpu.dcache.replacements 0 #
number of replacements (Count)
system.cpu.dcache.ReadReq.hits::writebacks 505 #
number of ReadReq hits (Count)
system.cpu.dcache.ReadReq.hits::functional 505 #
system.cpu.dcache.ReadReq.hits::interrupt 505 #
system.cpu.dcache.ReadReq.hits::cpu.mmu.dtb.walker 505
# number of ReadReq hits (Count)
system.cpu.dcache.ReadReq.hits::cpu.mmu.itb.walker 505
system.cpu.dcache.ReadReq.hits::cpu.inst 505 #
system.cpu.dcache.ReadReq.hits::cpu.data 505 #
system.cpu.dcache.ReadReq.hits::total 3535 #
system.cpu.dcache.ReadReq.misses::writebacks 59 #
number of ReadReq misses (Count)
system.cpu.dcache.ReadReq.misses::functional 59 #
system.cpu.dcache.ReadReq.misses::interrupt 59 #
system.cpu.dcache.ReadReq.misses::cpu.mmu.dtb.walker 59
# number of ReadReq misses (Count)
system.cpu.dcache.ReadReq.misses::cpu.mmu.itb.walker 59
system.cpu.dcache.ReadReq.misses::cpu.inst 59 #
system.cpu.dcache.ReadReq.misses::cpu.data 59 #
system.cpu.dcache.ReadReq.misses::total 413 #
system.cpu.dcache.ReadReq.missLatency::writebacks 3423500
# number of ReadReq miss ticks (Tick)
system.cpu.dcache.ReadReq.missLatency::functional 3423500
system.cpu.dcache.ReadReq.missLatency::interrupt 3423500
system.cpu.dcache.ReadReq.missLatency::cpu.mmu.dtb.walker 3423500
system.cpu.dcache.ReadReq.missLatency::cpu.mmu.itb.walker 3423500
system.cpu.dcache.ReadReq.missLatency::cpu.inst 3423500
system.cpu.dcache.ReadReq.missLatency::cpu.data 3423500
system.cpu.dcache.ReadReq.missLatency::total 23964500 #
number of ReadReq miss ticks (Tick)
system.cpu.dcache.ReadReq.accesses::writebacks 564 #
number of ReadReq accesses(hits+misses) (Count)
system.cpu.dcache.ReadReq.accesses::functional 564 #
system.cpu.dcache.ReadReq.accesses::interrupt 564 #
system.cpu.dcache.ReadReq.accesses::cpu.mmu.dtb.walker 564
# number of ReadReq accesses(hits+misses) (Count)
system.cpu.dcache.ReadReq.accesses::cpu.mmu.itb.walker 564
system.cpu.dcache.ReadReq.accesses::cpu.inst 564 #
system.cpu.dcache.ReadReq.accesses::cpu.data 564 #
system.cpu.dcache.ReadReq.accesses::total 3948 #
system.cpu.dcache.ReadReq.missRate::writebacks 0.104610 #
miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.missRate::functional 0.104610 #
system.cpu.dcache.ReadReq.missRate::interrupt 0.104610 #
system.cpu.dcache.ReadReq.missRate::cpu.mmu.dtb.walker 0.104610
# miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.missRate::cpu.mmu.itb.walker 0.104610
system.cpu.dcache.ReadReq.missRate::cpu.inst 0.104610 #
system.cpu.dcache.ReadReq.missRate::cpu.data 0.104610 #
system.cpu.dcache.ReadReq.missRate::total 0.104610 # miss
rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.avgMissLatency::writebacks 58025.423729
# average ReadReq miss latency ((Tick/Count))
system.cpu.dcache.ReadReq.avgMissLatency::functional 58025.423729
system.cpu.dcache.ReadReq.avgMissLatency::interrupt 58025.423729
system.cpu.dcache.ReadReq.avgMissLatency::cpu.mmu.dtb.walker 58025.423729
system.cpu.dcache.ReadReq.avgMissLatency::cpu.mmu.itb.walker 58025.423729
system.cpu.dcache.ReadReq.avgMissLatency::cpu.inst 58025.423729
system.cpu.dcache.ReadReq.avgMissLatency::cpu.data 58025.423729
system.cpu.dcache.ReadReq.avgMissLatency::total 58025.423729
system.cpu.dcache.ReadReq.mshrHits::writebacks 38 #
number of ReadReq MSHR hits (Count)
system.cpu.dcache.ReadReq.mshrHits::functional 38 #
system.cpu.dcache.ReadReq.mshrHits::interrupt 38 #
system.cpu.dcache.ReadReq.mshrHits::cpu.mmu.dtb.walker 38
# number of ReadReq MSHR hits (Count)
system.cpu.dcache.ReadReq.mshrHits::cpu.mmu.itb.walker 38
system.cpu.dcache.ReadReq.mshrHits::cpu.inst 38 #
system.cpu.dcache.ReadReq.mshrHits::cpu.data 38 #
system.cpu.dcache.ReadReq.mshrHits::total 266 #
system.cpu.dcache.ReadReq.mshrMisses::writebacks 21
# number of ReadReq MSHR misses (Count)
system.cpu.dcache.ReadReq.mshrMisses::functional 21
system.cpu.dcache.ReadReq.mshrMisses::interrupt 21
system.cpu.dcache.ReadReq.mshrMisses::cpu.mmu.dtb.walker 21
system.cpu.dcache.ReadReq.mshrMisses::cpu.mmu.itb.walker 21
system.cpu.dcache.ReadReq.mshrMisses::cpu.inst 21 #
number of ReadReq MSHR misses (Count)
system.cpu.dcache.ReadReq.mshrMisses::cpu.data 21 #
system.cpu.dcache.ReadReq.mshrMisses::total 147 #
system.cpu.dcache.ReadReq.mshrMissLatency::writebacks 1204500
# number of ReadReq MSHR miss ticks (Tick)
system.cpu.dcache.ReadReq.mshrMissLatency::functional 1204500
system.cpu.dcache.ReadReq.mshrMissLatency::interrupt 1204500
system.cpu.dcache.ReadReq.mshrMissLatency::cpu.mmu.dtb.walker 1204500
system.cpu.dcache.ReadReq.mshrMissLatency::cpu.mmu.itb.walker 1204500
system.cpu.dcache.ReadReq.mshrMissLatency::cpu.inst 1204500
system.cpu.dcache.ReadReq.mshrMissLatency::cpu.data 1204500
system.cpu.dcache.ReadReq.mshrMissLatency::total 8431500
system.cpu.dcache.ReadReq.mshrMissRate::writebacks 0.037234
# mshr miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.mshrMissRate::functional 0.037234
system.cpu.dcache.ReadReq.mshrMissRate::interrupt 0.037234
system.cpu.dcache.ReadReq.mshrMissRate::cpu.mmu.dtb.walker 0.037234
system.cpu.dcache.ReadReq.mshrMissRate::cpu.mmu.itb.walker 0.037234
system.cpu.dcache.ReadReq.mshrMissRate::cpu.inst 0.037234
system.cpu.dcache.ReadReq.mshrMissRate::cpu.data 0.037234
system.cpu.dcache.ReadReq.mshrMissRate::total 0.037234 #
mshr miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.avgMshrMissLatency::writebacks 57357.142857
# average ReadReq mshr miss latency ((Tick/Count))
system.cpu.dcache.ReadReq.avgMshrMissLatency::functional 57357.142857
system.cpu.dcache.ReadReq.avgMshrMissLatency::interrupt 57357.142857
system.cpu.dcache.ReadReq.avgMshrMissLatency::cpu.mmu.dtb.walker 57357.142857
system.cpu.dcache.ReadReq.avgMshrMissLatency::cpu.mmu.itb.walker 57357.142857
system.cpu.dcache.ReadReq.avgMshrMissLatency::cpu.inst 57357.142857
system.cpu.dcache.ReadReq.avgMshrMissLatency::cpu.data 57357.142857
system.cpu.dcache.ReadReq.avgMshrMissLatency::total 57357.142857
system.cpu.dcache.WriteReq.hits::writebacks 336 #
number of WriteReq hits (Count)
system.cpu.dcache.WriteReq.hits::functional 336 #
system.cpu.dcache.WriteReq.hits::interrupt 336 #
system.cpu.dcache.WriteReq.hits::cpu.mmu.dtb.walker 336
# number of WriteReq hits (Count)
system.cpu.dcache.WriteReq.hits::cpu.mmu.itb.walker 336
# number of WriteReq hits (Count)
system.cpu.dcache.WriteReq.hits::cpu.inst 336 #
system.cpu.dcache.WriteReq.hits::cpu.data 336 #
system.cpu.dcache.WriteReq.hits::total 2352 #
system.cpu.dcache.WriteReq.misses::writebacks 95 #
number of WriteReq misses (Count)
system.cpu.dcache.WriteReq.misses::functional 95 #
system.cpu.dcache.WriteReq.misses::interrupt 95 #
system.cpu.dcache.WriteReq.misses::cpu.mmu.dtb.walker 95
# number of WriteReq misses (Count)
system.cpu.dcache.WriteReq.misses::cpu.mmu.itb.walker 95
# number of WriteReq misses (Count)
system.cpu.dcache.WriteReq.misses::cpu.inst 95 #
system.cpu.dcache.WriteReq.misses::cpu.data 95 #
system.cpu.dcache.WriteReq.misses::total 665 #
system.cpu.dcache.WriteReq.missLatency::writebacks 4752000
# number of WriteReq miss ticks (Tick)
system.cpu.dcache.WriteReq.missLatency::functional 4752000
system.cpu.dcache.WriteReq.missLatency::interrupt 4752000
system.cpu.dcache.WriteReq.missLatency::cpu.mmu.dtb.walker 4752000
system.cpu.dcache.WriteReq.missLatency::cpu.mmu.itb.walker 4752000
system.cpu.dcache.WriteReq.missLatency::cpu.inst 4752000
system.cpu.dcache.WriteReq.missLatency::cpu.data 4752000
system.cpu.dcache.WriteReq.missLatency::total 33264000 #
number of WriteReq miss ticks (Tick)
system.cpu.dcache.WriteReq.accesses::writebacks 431
# number of WriteReq accesses(hits+misses) (Count)
system.cpu.dcache.WriteReq.accesses::functional 431
system.cpu.dcache.WriteReq.accesses::interrupt 431 #
number of WriteReq accesses(hits+misses) (Count)
system.cpu.dcache.WriteReq.accesses::cpu.mmu.dtb.walker 431
system.cpu.dcache.WriteReq.accesses::cpu.mmu.itb.walker 431
system.cpu.dcache.WriteReq.accesses::cpu.inst 431 #
system.cpu.dcache.WriteReq.accesses::cpu.data 431 #
system.cpu.dcache.WriteReq.accesses::total 3017 #
system.cpu.dcache.WriteReq.missRate::writebacks 0.220418
# miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.missRate::functional 0.220418
system.cpu.dcache.WriteReq.missRate::interrupt 0.220418 #
miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.missRate::cpu.mmu.dtb.walker 0.220418
system.cpu.dcache.WriteReq.missRate::cpu.mmu.itb.walker 0.220418
system.cpu.dcache.WriteReq.missRate::cpu.inst 0.220418 #
system.cpu.dcache.WriteReq.missRate::cpu.data 0.220418 #
system.cpu.dcache.WriteReq.missRate::total 0.220418 #
system.cpu.dcache.WriteReq.avgMissLatency::writebacks 50021.052632
# average WriteReq miss latency ((Tick/Count))
system.cpu.dcache.WriteReq.avgMissLatency::functional 50021.052632
system.cpu.dcache.WriteReq.avgMissLatency::interrupt 50021.052632
system.cpu.dcache.WriteReq.avgMissLatency::cpu.mmu.dtb.walker 50021.052632
system.cpu.dcache.WriteReq.avgMissLatency::cpu.mmu.itb.walker 50021.052632
system.cpu.dcache.WriteReq.avgMissLatency::cpu.inst 50021.052632
system.cpu.dcache.WriteReq.avgMissLatency::cpu.data 50021.052632
system.cpu.dcache.WriteReq.avgMissLatency::total 50021.052632
system.cpu.dcache.WriteReq.mshrHits::writebacks 68
# number of WriteReq MSHR hits (Count)
system.cpu.dcache.WriteReq.mshrHits::functional 68
system.cpu.dcache.WriteReq.mshrHits::interrupt 68 #
number of WriteReq MSHR hits (Count)
system.cpu.dcache.WriteReq.mshrHits::cpu.mmu.dtb.walker 68
system.cpu.dcache.WriteReq.mshrHits::cpu.mmu.itb.walker 68
system.cpu.dcache.WriteReq.mshrHits::cpu.inst 68 #
system.cpu.dcache.WriteReq.mshrHits::cpu.data 68 #
system.cpu.dcache.WriteReq.mshrHits::total 476 #
system.cpu.dcache.WriteReq.mshrMisses::writebacks 27
# number of WriteReq MSHR misses (Count)
system.cpu.dcache.WriteReq.mshrMisses::functional 27
system.cpu.dcache.WriteReq.mshrMisses::interrupt 27
system.cpu.dcache.WriteReq.mshrMisses::cpu.mmu.dtb.walker 27
system.cpu.dcache.WriteReq.mshrMisses::cpu.mmu.itb.walker 27
system.cpu.dcache.WriteReq.mshrMisses::cpu.inst 27
system.cpu.dcache.WriteReq.mshrMisses::cpu.data 27
system.cpu.dcache.WriteReq.mshrMisses::total 189 #
number of WriteReq MSHR misses (Count)
system.cpu.dcache.WriteReq.mshrMissLatency::writebacks 1572000
# number of WriteReq MSHR miss ticks (Tick)
system.cpu.dcache.WriteReq.mshrMissLatency::functional 1572000
system.cpu.dcache.WriteReq.mshrMissLatency::interrupt 1572000
system.cpu.dcache.WriteReq.mshrMissLatency::cpu.mmu.dtb.walker 1572000
system.cpu.dcache.WriteReq.mshrMissLatency::cpu.mmu.itb.walker 1572000
system.cpu.dcache.WriteReq.mshrMissLatency::cpu.inst 1572000
system.cpu.dcache.WriteReq.mshrMissLatency::cpu.data 1572000
system.cpu.dcache.WriteReq.mshrMissLatency::total 11004000
system.cpu.dcache.WriteReq.mshrMissRate::writebacks 0.062645
# mshr miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.mshrMissRate::functional 0.062645
system.cpu.dcache.WriteReq.mshrMissRate::interrupt 0.062645
system.cpu.dcache.WriteReq.mshrMissRate::cpu.mmu.dtb.walker 0.062645
system.cpu.dcache.WriteReq.mshrMissRate::cpu.mmu.itb.walker 0.062645
system.cpu.dcache.WriteReq.mshrMissRate::cpu.inst 0.062645
system.cpu.dcache.WriteReq.mshrMissRate::cpu.data 0.062645
system.cpu.dcache.WriteReq.mshrMissRate::total 0.062645 #
mshr miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.avgMshrMissLatency::writebacks 58222.222222
# average WriteReq mshr miss latency ((Tick/Count))
system.cpu.dcache.WriteReq.avgMshrMissLatency::functional 58222.222222
system.cpu.dcache.WriteReq.avgMshrMissLatency::interrupt 58222.222222
system.cpu.dcache.WriteReq.avgMshrMissLatency::cpu.mmu.dtb.walker 58222.222222
system.cpu.dcache.WriteReq.avgMshrMissLatency::cpu.mmu.itb.walker 58222.222222
system.cpu.dcache.WriteReq.avgMshrMissLatency::cpu.inst 58222.222222
system.cpu.dcache.WriteReq.avgMshrMissLatency::cpu.data 58222.222222
system.cpu.dcache.WriteReq.avgMshrMissLatency::total 58222.222222
system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 28931000
# Cumulative time (in ticks) in various power states (Tick)
system.cpu.dcache.power_state.pwrStateResidencyTicks::ON 28931000
system.cpu.dcache.power_state.pwrStateResidencyTicks::CLK_GATED 28931000
system.cpu.dcache.power_state.pwrStateResidencyTicks::SRAM_RETENTION 28931000
system.cpu.dcache.power_state.pwrStateResidencyTicks::OFF 28931000
system.cpu.dcache.tags.tagsInUse 15.759636 #
Average ticks per tags in use ((Tick/Count))
system.cpu.dcache.tags.totalRefs 889 # Total
number of references to valid blocks. (Count)
system.cpu.dcache.tags.sampledRefs 48 #
Sample count of references to valid blocks. (Count)
system.cpu.dcache.tags.avgRefs 18.520833 #
Average number of references to valid blocks. ((Count/Count))
system.cpu.dcache.tags.warmupTick 307000 # The
tick when the warmup percentage was hit. (Tick)
system.cpu.dcache.tags.occupancies::writebacks 15.759636 #
Average occupied blocks per tick, per requestor ((Count/Tick))
system.cpu.dcache.tags.occupancies::functional 15.759636 #
system.cpu.dcache.tags.occupancies::interrupt 15.759636 #
system.cpu.dcache.tags.occupancies::cpu.mmu.dtb.walker 15.759636
# Average occupied blocks per tick, per requestor ((Count/Tick))
system.cpu.dcache.tags.occupancies::cpu.mmu.itb.walker 15.759636
system.cpu.dcache.tags.occupancies::cpu.inst 15.759636 #
system.cpu.dcache.tags.occupancies::cpu.data 15.759636 #
system.cpu.dcache.tags.avgOccs::writebacks 0.015390 #
Average percentage of cache occupancy ((Ratio/Tick))
system.cpu.dcache.tags.avgOccs::functional 0.015390 #
system.cpu.dcache.tags.avgOccs::interrupt 0.015390 #
system.cpu.dcache.tags.avgOccs::cpu.mmu.dtb.walker 0.015390
# Average percentage of cache occupancy ((Ratio/Tick))
system.cpu.dcache.tags.avgOccs::cpu.mmu.itb.walker 0.015390
system.cpu.dcache.tags.avgOccs::cpu.inst 0.015390 #
system.cpu.dcache.tags.avgOccs::cpu.data 0.015390 #
system.cpu.dcache.tags.avgOccs::total 0.107732 #
system.cpu.dcache.tags.occupanciesTaskId::0 48 #
Occupied blocks per task id (Count)
system.cpu.dcache.tags.ageTaskId_0::0 48 #
Occupied blocks per task id, per block age (Count)
system.cpu.dcache.tags.ratioOccsTaskId::0 0.046875 #
Ratio of occupied blocks and all blocks, per task id (Ratio)
system.cpu.dcache.tags.tagAccesses 2038 #
Number of tag accesses (Count)
system.cpu.dcache.tags.dataAccesses 2038 #
Number of data accesses (Count)
system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 28931000
system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::ON 28931000
system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::CLK_GATED 28931000
system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::SRAM_RETENTION
28931000 # Cumulative time (in ticks) in various power states
(Tick)
system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::OFF 28931000
system.cpu.decode.idleCycles 3354 #
Number of cycles decode is idle (Cycle)
system.cpu.decode.blockedCycles 389 #
Number of cycles decode is blocked (Cycle)
system.cpu.decode.runCycles 43948 #
Number of cycles decode is running (Cycle)
system.cpu.decode.unblockCycles 11 #
Number of cycles decode is unblocking (Cycle)
system.cpu.decode.squashCycles 286 #
Number of cycles decode is squashing (Cycle)
system.cpu.decode.branchResolved 8491 #
Number of times decode resolved a branch (Count)
system.cpu.decode.branchMispred 120 #
Number of times decode detected a branch misprediction (Count)
system.cpu.decode.decodedInsts 53548 #
Number of instructions handled by decode (Count)
system.cpu.decode.squashedInsts 154 #
Number of squashed instructions handled by decode (Count)
system.cpu.dtb_walker_cache.blockedCycles::no_mshrs 0
# number of cycles access was blocked (Cycle)
system.cpu.dtb_walker_cache.blockedCycles::no_targets 0
system.cpu.dtb_walker_cache.blockedCauses::no_mshrs 0
# number of times access was blocked (Count)
system.cpu.dtb_walker_cache.blockedCauses::no_targets 0
system.cpu.dtb_walker_cache.avgBlocked::no_mshrs nan
# average number of cycles each access was blocked ((Cycle/Count))
system.cpu.dtb_walker_cache.avgBlocked::no_targets nan
system.cpu.dtb_walker_cache.replacements 0 #
system.cpu.dtb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED
(Tick)
system.cpu.dtb_walker_cache.power_state.pwrStateResidencyTicks::ON 28931000
system.cpu.dtb_walker_cache.power_state.pwrStateResidencyTicks::CLK_GATED
(Tick)
system.cpu.dtb_walker_cache.power_state.pwrStateResidencyTicks::SRAM_RETENTION
(Tick)
system.cpu.dtb_walker_cache.power_state.pwrStateResidencyTicks::OFF 28931000
system.cpu.dtb_walker_cache.tags.tagsInUse 0 #
system.cpu.dtb_walker_cache.tags.totalRefs 0 #
Total number of references to valid blocks. (Count)
system.cpu.dtb_walker_cache.tags.sampledRefs 0 #
system.cpu.dtb_walker_cache.tags.avgRefs nan #
system.cpu.dtb_walker_cache.tags.warmupTick 0 #
The tick when the warmup percentage was hit. (Tick)
system.cpu.dtb_walker_cache.tags.tagAccesses 0 #
system.cpu.dtb_walker_cache.tags.dataAccesses 0 #
system.cpu.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED
(Tick)
system.cpu.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::ON
(Tick)
system.cpu.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::CLK_GATED
(Tick)
system.cpu.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::SRAM_RETENTION
(Tick)
system.cpu.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::OFF
(Tick)
system.cpu.fetch.icacheStallCycles 3112 #
Number of cycles fetch is stalled on an Icache miss (Cycle)
system.cpu.fetch.insts 54361 #
Number of instructions fetch has processed (Count)
system.cpu.fetch.branches 9361 #
Number of branches that fetch encountered (Count)
system.cpu.fetch.predictedBranches 8420 #
Number of branches that fetch has predicted taken (Count)
system.cpu.fetch.cycles 44476 #
Number of cycles fetch has run and was not squashing or blocked (Cycle)
system.cpu.fetch.squashCycles 800 #
Number of cycles fetch has spent squashing (Cycle)
system.cpu.fetch.cacheLines 631 #
Number of cache lines fetched (Count)
system.cpu.fetch.icacheSquashes 97 #
Number of outstanding Icache misses that were squashed (Count)
system.cpu.fetch.nisnDist::samples 47988 #
Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::mean 1.132804 #
system.cpu.fetch.nisnDist::stdev 0.581647 #
system.cpu.fetch.nisnDist::underflows 0 0.00% 0.00% #
system.cpu.fetch.nisnDist::0 3641 7.59% 7.59% #
system.cpu.fetch.nisnDist::overflows 0 0.00% 100.00% #
system.cpu.fetch.nisnDist::min_value 0 #
system.cpu.fetch.nisnDist::max_value 8 #
system.cpu.fetch.nisnDist::total 47988 #
system.cpu.fetch.branchRate 0.161779 #
Number of branch fetches per cycle (Ratio)
system.cpu.fetch.rate 0.939478 #
Number of inst fetches per cycle ((Count/Cycle))
system.cpu.icache.demandHits::writebacks 448 #
system.cpu.icache.demandHits::functional 448 #
system.cpu.icache.demandHits::interrupt 448 #
system.cpu.icache.demandHits::cpu.mmu.dtb.walker 448
system.cpu.icache.demandHits::cpu.mmu.itb.walker 448
system.cpu.icache.demandHits::cpu.inst 448 #
system.cpu.icache.demandHits::cpu.data 448 #
system.cpu.icache.demandHits::total 3136 #
system.cpu.icache.overallHits::writebacks 448 #
system.cpu.icache.overallHits::functional 448 #
system.cpu.icache.overallHits::interrupt 448 #
system.cpu.icache.overallHits::cpu.mmu.dtb.walker 448
system.cpu.icache.overallHits::cpu.mmu.itb.walker 448
system.cpu.icache.overallHits::cpu.inst 448 #
system.cpu.icache.overallHits::cpu.data 448 #
system.cpu.icache.overallHits::total 3136 #
system.cpu.icache.demandMisses::writebacks 183 #
system.cpu.icache.demandMisses::functional 183 #
system.cpu.icache.demandMisses::interrupt 183 #
system.cpu.icache.demandMisses::cpu.mmu.dtb.walker 183
system.cpu.icache.demandMisses::cpu.mmu.itb.walker 183
system.cpu.icache.demandMisses::cpu.inst 183 #
system.cpu.icache.demandMisses::cpu.data 183 #
system.cpu.icache.demandMisses::total 1281 #
system.cpu.icache.overallMisses::writebacks 183 #
system.cpu.icache.overallMisses::functional 183 #
system.cpu.icache.overallMisses::interrupt 183 #
system.cpu.icache.overallMisses::cpu.mmu.dtb.walker 183
system.cpu.icache.overallMisses::cpu.mmu.itb.walker 183
system.cpu.icache.overallMisses::cpu.inst 183 #
system.cpu.icache.overallMisses::cpu.data 183 #
system.cpu.icache.overallMisses::total 1281 #
system.cpu.icache.demandMissLatency::writebacks 9457000
system.cpu.icache.demandMissLatency::functional 9457000
system.cpu.icache.demandMissLatency::interrupt 9457000 #
system.cpu.icache.demandMissLatency::cpu.mmu.dtb.walker 9457000
system.cpu.icache.demandMissLatency::cpu.mmu.itb.walker 9457000
system.cpu.icache.demandMissLatency::cpu.inst 9457000 #
system.cpu.icache.demandMissLatency::cpu.data 9457000 #
system.cpu.icache.demandMissLatency::total 66199000 #
system.cpu.icache.overallMissLatency::writebacks 9457000
system.cpu.icache.overallMissLatency::functional 9457000
system.cpu.icache.overallMissLatency::interrupt 9457000
system.cpu.icache.overallMissLatency::cpu.mmu.dtb.walker 9457000
system.cpu.icache.overallMissLatency::cpu.mmu.itb.walker 9457000
system.cpu.icache.overallMissLatency::cpu.inst 9457000 #
system.cpu.icache.overallMissLatency::cpu.data 9457000 #
system.cpu.icache.overallMissLatency::total 66199000 #
system.cpu.icache.demandAccesses::writebacks 631 #
system.cpu.icache.demandAccesses::functional 631 #
system.cpu.icache.demandAccesses::interrupt 631 #
system.cpu.icache.demandAccesses::cpu.mmu.dtb.walker 631
system.cpu.icache.demandAccesses::cpu.mmu.itb.walker 631
system.cpu.icache.demandAccesses::cpu.inst 631 #
system.cpu.icache.demandAccesses::cpu.data 631 #
system.cpu.icache.demandAccesses::total 4417 #
system.cpu.icache.overallAccesses::writebacks 631 #
system.cpu.icache.overallAccesses::functional 631 #
system.cpu.icache.overallAccesses::interrupt 631 #
system.cpu.icache.overallAccesses::cpu.mmu.dtb.walker 631
system.cpu.icache.overallAccesses::cpu.mmu.itb.walker 631
system.cpu.icache.overallAccesses::cpu.inst 631 #
system.cpu.icache.overallAccesses::cpu.data 631 #
system.cpu.icache.overallAccesses::total 4417 #
system.cpu.icache.demandMissRate::writebacks 0.290016 #
system.cpu.icache.demandMissRate::functional 0.290016 #
system.cpu.icache.demandMissRate::interrupt 0.290016 #
system.cpu.icache.demandMissRate::cpu.mmu.dtb.walker 0.290016
system.cpu.icache.demandMissRate::cpu.mmu.itb.walker 0.290016
system.cpu.icache.demandMissRate::cpu.inst 0.290016 #
system.cpu.icache.demandMissRate::cpu.data 0.290016 #
system.cpu.icache.demandMissRate::total 0.290016 # miss
rate for demand accesses (Ratio)
system.cpu.icache.overallMissRate::writebacks 0.290016 #
system.cpu.icache.overallMissRate::functional 0.290016 #
system.cpu.icache.overallMissRate::interrupt 0.290016 #
system.cpu.icache.overallMissRate::cpu.mmu.dtb.walker 0.290016
system.cpu.icache.overallMissRate::cpu.mmu.itb.walker 0.290016
system.cpu.icache.overallMissRate::cpu.inst 0.290016 #
system.cpu.icache.overallMissRate::cpu.data 0.290016 #
system.cpu.icache.overallMissRate::total 0.290016 # miss
rate for overall accesses (Ratio)
system.cpu.icache.demandAvgMissLatency::writebacks 51677.595628
system.cpu.icache.demandAvgMissLatency::functional 51677.595628
system.cpu.icache.demandAvgMissLatency::interrupt 51677.595628
system.cpu.icache.demandAvgMissLatency::cpu.mmu.dtb.walker 51677.595628
system.cpu.icache.demandAvgMissLatency::cpu.mmu.itb.walker 51677.595628
system.cpu.icache.demandAvgMissLatency::cpu.inst 51677.595628
system.cpu.icache.demandAvgMissLatency::cpu.data 51677.595628
system.cpu.icache.demandAvgMissLatency::total 51677.595628 #
system.cpu.icache.overallAvgMissLatency::writebacks 51677.595628
system.cpu.icache.overallAvgMissLatency::functional 51677.595628
system.cpu.icache.overallAvgMissLatency::interrupt 51677.595628
system.cpu.icache.overallAvgMissLatency::cpu.mmu.dtb.walker 51677.595628
system.cpu.icache.overallAvgMissLatency::cpu.mmu.itb.walker 51677.595628
system.cpu.icache.overallAvgMissLatency::cpu.inst 51677.595628
system.cpu.icache.overallAvgMissLatency::cpu.data 51677.595628
system.cpu.icache.overallAvgMissLatency::total 51677.595628 #
system.cpu.icache.blockedCycles::no_mshrs 0 #
system.cpu.icache.blockedCycles::no_targets 0 #
system.cpu.icache.blockedCauses::no_mshrs 0 #
system.cpu.icache.blockedCauses::no_targets 0 #
system.cpu.icache.avgBlocked::no_mshrs nan #
system.cpu.icache.avgBlocked::no_targets nan #
system.cpu.icache.writebacks::writebacks 16 #
number of writebacks (Count)
system.cpu.icache.writebacks::functional 16 #
system.cpu.icache.writebacks::interrupt 16 #
system.cpu.icache.writebacks::cpu.mmu.dtb.walker 16
# number of writebacks (Count)
system.cpu.icache.writebacks::cpu.mmu.itb.walker 16
# number of writebacks (Count)
system.cpu.icache.writebacks::cpu.inst 16 #
system.cpu.icache.writebacks::cpu.data 16 #
system.cpu.icache.writebacks::total 112 #
system.cpu.icache.demandMshrHits::writebacks 35 #
system.cpu.icache.demandMshrHits::functional 35 #
system.cpu.icache.demandMshrHits::interrupt 35 #
system.cpu.icache.demandMshrHits::cpu.mmu.dtb.walker 35
system.cpu.icache.demandMshrHits::cpu.mmu.itb.walker 35
system.cpu.icache.demandMshrHits::cpu.inst 35 #
system.cpu.icache.demandMshrHits::cpu.data 35 #
system.cpu.icache.demandMshrHits::total 245 #
system.cpu.icache.overallMshrHits::writebacks 35 #
system.cpu.icache.overallMshrHits::functional 35 #
system.cpu.icache.overallMshrHits::interrupt 35 #
system.cpu.icache.overallMshrHits::cpu.mmu.dtb.walker 35
system.cpu.icache.overallMshrHits::cpu.mmu.itb.walker 35
system.cpu.icache.overallMshrHits::cpu.inst 35 #
system.cpu.icache.overallMshrHits::cpu.data 35 #
system.cpu.icache.overallMshrHits::total 245 #
system.cpu.icache.demandMshrMisses::writebacks 148 #
system.cpu.icache.demandMshrMisses::functional 148 #
system.cpu.icache.demandMshrMisses::interrupt 148 #
system.cpu.icache.demandMshrMisses::cpu.mmu.dtb.walker 148
system.cpu.icache.demandMshrMisses::cpu.mmu.itb.walker 148
system.cpu.icache.demandMshrMisses::cpu.inst 148 #
system.cpu.icache.demandMshrMisses::cpu.data 148 #
system.cpu.icache.demandMshrMisses::total 1036 #
system.cpu.icache.overallMshrMisses::writebacks 148
system.cpu.icache.overallMshrMisses::functional 148
system.cpu.icache.overallMshrMisses::interrupt 148 #
system.cpu.icache.overallMshrMisses::cpu.mmu.dtb.walker 148
system.cpu.icache.overallMshrMisses::cpu.mmu.itb.walker 148
system.cpu.icache.overallMshrMisses::cpu.inst 148 #
system.cpu.icache.overallMshrMisses::cpu.data 148 #
system.cpu.icache.overallMshrMisses::total 1036 #
system.cpu.icache.demandMshrMissLatency::writebacks 7999000
system.cpu.icache.demandMshrMissLatency::functional 7999000
system.cpu.icache.demandMshrMissLatency::interrupt 7999000
system.cpu.icache.demandMshrMissLatency::cpu.mmu.dtb.walker 7999000
system.cpu.icache.demandMshrMissLatency::cpu.mmu.itb.walker 7999000
system.cpu.icache.demandMshrMissLatency::cpu.inst 7999000
system.cpu.icache.demandMshrMissLatency::cpu.data 7999000
system.cpu.icache.demandMshrMissLatency::total 55993000 #
number of demand (read+write) MSHR miss ticks (Tick)
system.cpu.icache.overallMshrMissLatency::writebacks 7999000
system.cpu.icache.overallMshrMissLatency::functional 7999000
system.cpu.icache.overallMshrMissLatency::interrupt 7999000
system.cpu.icache.overallMshrMissLatency::cpu.mmu.dtb.walker 7999000
system.cpu.icache.overallMshrMissLatency::cpu.mmu.itb.walker 7999000
system.cpu.icache.overallMshrMissLatency::cpu.inst 7999000
system.cpu.icache.overallMshrMissLatency::cpu.data 7999000
system.cpu.icache.overallMshrMissLatency::total 55993000
system.cpu.icache.demandMshrMissRate::writebacks 0.234548
system.cpu.icache.demandMshrMissRate::functional 0.234548
system.cpu.icache.demandMshrMissRate::interrupt 0.234548
system.cpu.icache.demandMshrMissRate::cpu.mmu.dtb.walker 0.234548
system.cpu.icache.demandMshrMissRate::cpu.mmu.itb.walker 0.234548
system.cpu.icache.demandMshrMissRate::cpu.inst 0.234548 #
system.cpu.icache.demandMshrMissRate::cpu.data 0.234548 #
system.cpu.icache.demandMshrMissRate::total 0.234548 #
system.cpu.icache.overallMshrMissRate::writebacks 0.234548
system.cpu.icache.overallMshrMissRate::functional 0.234548
system.cpu.icache.overallMshrMissRate::interrupt 0.234548
system.cpu.icache.overallMshrMissRate::cpu.mmu.dtb.walker 0.234548
system.cpu.icache.overallMshrMissRate::cpu.mmu.itb.walker 0.234548
system.cpu.icache.overallMshrMissRate::cpu.inst 0.234548
system.cpu.icache.overallMshrMissRate::cpu.data 0.234548
system.cpu.icache.overallMshrMissRate::total 0.234548 #
mshr miss ratio for overall accesses (Ratio)
system.cpu.icache.demandAvgMshrMissLatency::writebacks 54047.297297
system.cpu.icache.demandAvgMshrMissLatency::functional 54047.297297
system.cpu.icache.demandAvgMshrMissLatency::interrupt 54047.297297
system.cpu.icache.demandAvgMshrMissLatency::cpu.mmu.dtb.walker 54047.297297
system.cpu.icache.demandAvgMshrMissLatency::cpu.mmu.itb.walker 54047.297297
system.cpu.icache.demandAvgMshrMissLatency::cpu.inst 54047.297297
system.cpu.icache.demandAvgMshrMissLatency::cpu.data 54047.297297
system.cpu.icache.demandAvgMshrMissLatency::total 54047.297297
system.cpu.icache.overallAvgMshrMissLatency::writebacks 54047.297297
system.cpu.icache.overallAvgMshrMissLatency::functional 54047.297297
system.cpu.icache.overallAvgMshrMissLatency::interrupt 54047.297297
system.cpu.icache.overallAvgMshrMissLatency::cpu.mmu.dtb.walker 54047.297297
system.cpu.icache.overallAvgMshrMissLatency::cpu.mmu.itb.walker 54047.297297
system.cpu.icache.overallAvgMshrMissLatency::cpu.inst 54047.297297
system.cpu.icache.overallAvgMshrMissLatency::cpu.data 54047.297297
system.cpu.icache.overallAvgMshrMissLatency::total 54047.297297
system.cpu.icache.replacements 16 #
system.cpu.icache.ReadReq.hits::writebacks 448 #
system.cpu.icache.ReadReq.hits::functional 448 #
system.cpu.icache.ReadReq.hits::interrupt 448 #
system.cpu.icache.ReadReq.hits::cpu.mmu.dtb.walker 448
system.cpu.icache.ReadReq.hits::cpu.mmu.itb.walker 448
system.cpu.icache.ReadReq.hits::cpu.inst 448 #
system.cpu.icache.ReadReq.hits::cpu.data 448 #
system.cpu.icache.ReadReq.hits::total 3136 #
system.cpu.icache.ReadReq.misses::writebacks 183 #
system.cpu.icache.ReadReq.misses::functional 183 #
system.cpu.icache.ReadReq.misses::interrupt 183 #
system.cpu.icache.ReadReq.misses::cpu.mmu.dtb.walker 183
system.cpu.icache.ReadReq.misses::cpu.mmu.itb.walker 183
system.cpu.icache.ReadReq.misses::cpu.inst 183 #
system.cpu.icache.ReadReq.misses::cpu.data 183 #
system.cpu.icache.ReadReq.misses::total 1281 #
system.cpu.icache.ReadReq.missLatency::writebacks 9457000
system.cpu.icache.ReadReq.missLatency::functional 9457000
system.cpu.icache.ReadReq.missLatency::interrupt 9457000
system.cpu.icache.ReadReq.missLatency::cpu.mmu.dtb.walker 9457000
system.cpu.icache.ReadReq.missLatency::cpu.mmu.itb.walker 9457000
system.cpu.icache.ReadReq.missLatency::cpu.inst 9457000
system.cpu.icache.ReadReq.missLatency::cpu.data 9457000
system.cpu.icache.ReadReq.missLatency::total 66199000 #
number of ReadReq miss ticks (Tick)
system.cpu.icache.ReadReq.accesses::writebacks 631 #
system.cpu.icache.ReadReq.accesses::functional 631 #
system.cpu.icache.ReadReq.accesses::interrupt 631 #
system.cpu.icache.ReadReq.accesses::cpu.mmu.dtb.walker 631
system.cpu.icache.ReadReq.accesses::cpu.mmu.itb.walker 631
system.cpu.icache.ReadReq.accesses::cpu.inst 631 #
system.cpu.icache.ReadReq.accesses::cpu.data 631 #
system.cpu.icache.ReadReq.accesses::total 4417 #
system.cpu.icache.ReadReq.missRate::writebacks 0.290016 #
system.cpu.icache.ReadReq.missRate::functional 0.290016 #
system.cpu.icache.ReadReq.missRate::interrupt 0.290016 #
system.cpu.icache.ReadReq.missRate::cpu.mmu.dtb.walker 0.290016
system.cpu.icache.ReadReq.missRate::cpu.mmu.itb.walker 0.290016
system.cpu.icache.ReadReq.missRate::cpu.inst 0.290016 #
system.cpu.icache.ReadReq.missRate::cpu.data 0.290016 #
system.cpu.icache.ReadReq.missRate::total 0.290016 # miss
rate for ReadReq accesses (Ratio)
system.cpu.icache.ReadReq.avgMissLatency::writebacks 51677.595628
system.cpu.icache.ReadReq.avgMissLatency::functional 51677.595628
system.cpu.icache.ReadReq.avgMissLatency::interrupt 51677.595628
system.cpu.icache.ReadReq.avgMissLatency::cpu.mmu.dtb.walker 51677.595628
system.cpu.icache.ReadReq.avgMissLatency::cpu.mmu.itb.walker 51677.595628
system.cpu.icache.ReadReq.avgMissLatency::cpu.inst 51677.595628
system.cpu.icache.ReadReq.avgMissLatency::cpu.data 51677.595628
system.cpu.icache.ReadReq.avgMissLatency::total 51677.595628
system.cpu.icache.ReadReq.mshrHits::writebacks 35 #
system.cpu.icache.ReadReq.mshrHits::functional 35 #
system.cpu.icache.ReadReq.mshrHits::interrupt 35 #
system.cpu.icache.ReadReq.mshrHits::cpu.mmu.dtb.walker 35
system.cpu.icache.ReadReq.mshrHits::cpu.mmu.itb.walker 35
system.cpu.icache.ReadReq.mshrHits::cpu.inst 35 #
system.cpu.icache.ReadReq.mshrHits::cpu.data 35 #
system.cpu.icache.ReadReq.mshrHits::total 245 #
system.cpu.icache.ReadReq.mshrMisses::writebacks 148
system.cpu.icache.ReadReq.mshrMisses::functional 148
system.cpu.icache.ReadReq.mshrMisses::interrupt 148
system.cpu.icache.ReadReq.mshrMisses::cpu.mmu.dtb.walker 148
system.cpu.icache.ReadReq.mshrMisses::cpu.mmu.itb.walker 148
system.cpu.icache.ReadReq.mshrMisses::cpu.inst 148 #
system.cpu.icache.ReadReq.mshrMisses::cpu.data 148 #
system.cpu.icache.ReadReq.mshrMisses::total 1036 #
system.cpu.icache.ReadReq.mshrMissLatency::writebacks 7999000
system.cpu.icache.ReadReq.mshrMissLatency::functional 7999000
system.cpu.icache.ReadReq.mshrMissLatency::interrupt 7999000
system.cpu.icache.ReadReq.mshrMissLatency::cpu.mmu.dtb.walker 7999000
system.cpu.icache.ReadReq.mshrMissLatency::cpu.mmu.itb.walker 7999000
system.cpu.icache.ReadReq.mshrMissLatency::cpu.inst 7999000
system.cpu.icache.ReadReq.mshrMissLatency::cpu.data 7999000
system.cpu.icache.ReadReq.mshrMissLatency::total 55993000
system.cpu.icache.ReadReq.mshrMissRate::writebacks 0.234548
system.cpu.icache.ReadReq.mshrMissRate::functional 0.234548
system.cpu.icache.ReadReq.mshrMissRate::interrupt 0.234548
system.cpu.icache.ReadReq.mshrMissRate::cpu.mmu.dtb.walker 0.234548
system.cpu.icache.ReadReq.mshrMissRate::cpu.mmu.itb.walker 0.234548
system.cpu.icache.ReadReq.mshrMissRate::cpu.inst 0.234548
system.cpu.icache.ReadReq.mshrMissRate::cpu.data 0.234548
system.cpu.icache.ReadReq.mshrMissRate::total 0.234548 #
mshr miss rate for ReadReq accesses (Ratio)
system.cpu.icache.ReadReq.avgMshrMissLatency::writebacks 54047.297297
system.cpu.icache.ReadReq.avgMshrMissLatency::functional 54047.297297
system.cpu.icache.ReadReq.avgMshrMissLatency::interrupt 54047.297297
system.cpu.icache.ReadReq.avgMshrMissLatency::cpu.mmu.dtb.walker 54047.297297
system.cpu.icache.ReadReq.avgMshrMissLatency::cpu.mmu.itb.walker 54047.297297
system.cpu.icache.ReadReq.avgMshrMissLatency::cpu.inst 54047.297297
system.cpu.icache.ReadReq.avgMshrMissLatency::cpu.data 54047.297297
system.cpu.icache.ReadReq.avgMshrMissLatency::total 54047.297297
system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 28931000
system.cpu.icache.power_state.pwrStateResidencyTicks::ON 28931000
system.cpu.icache.power_state.pwrStateResidencyTicks::CLK_GATED 28931000
system.cpu.icache.power_state.pwrStateResidencyTicks::SRAM_RETENTION 28931000
system.cpu.icache.power_state.pwrStateResidencyTicks::OFF 28931000
system.cpu.icache.tags.tagsInUse 29.072072 #
system.cpu.icache.tags.totalRefs 596 # Total
number of references to valid blocks. (Count)
system.cpu.icache.tags.sampledRefs 148 #
system.cpu.icache.tags.avgRefs 4.027027 #
system.cpu.icache.tags.warmupTick 77000 # The
tick when the warmup percentage was hit. (Tick)
system.cpu.icache.tags.occupancies::writebacks 29.072072 #
system.cpu.icache.tags.occupancies::functional 29.072072 #
system.cpu.icache.tags.occupancies::interrupt 29.072072 #
system.cpu.icache.tags.occupancies::cpu.mmu.dtb.walker 29.072072
system.cpu.icache.tags.occupancies::cpu.mmu.itb.walker 29.072072
system.cpu.icache.tags.occupancies::cpu.inst 29.072072 #
system.cpu.icache.tags.occupancies::cpu.data 29.072072 #
system.cpu.icache.tags.avgOccs::writebacks 0.113563 #
system.cpu.icache.tags.avgOccs::functional 0.113563 #
system.cpu.icache.tags.avgOccs::interrupt 0.113563 #
system.cpu.icache.tags.avgOccs::cpu.mmu.dtb.walker 0.113563
system.cpu.icache.tags.avgOccs::cpu.mmu.itb.walker 0.113563
system.cpu.icache.tags.avgOccs::cpu.inst 0.113563 #
system.cpu.icache.tags.avgOccs::cpu.data 0.113563 #
system.cpu.icache.tags.avgOccs::total 0.794939 #
system.cpu.icache.tags.occupanciesTaskId::0 132 #
system.cpu.icache.tags.ageTaskId_0::0 132 #
system.cpu.icache.tags.ratioOccsTaskId::0 0.515625 #
system.cpu.icache.tags.tagAccesses 1410 #
system.cpu.icache.tags.dataAccesses 1410 #
system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 28931000
system.cpu.icache.tags.power_state.pwrStateResidencyTicks::ON 28931000
system.cpu.icache.tags.power_state.pwrStateResidencyTicks::CLK_GATED 28931000
system.cpu.icache.tags.power_state.pwrStateResidencyTicks::SRAM_RETENTION
(Tick)
system.cpu.icache.tags.power_state.pwrStateResidencyTicks::OFF 28931000
system.cpu.itb_walker_cache.blockedCycles::no_mshrs 0
system.cpu.itb_walker_cache.blockedCycles::no_targets 0
system.cpu.itb_walker_cache.blockedCauses::no_mshrs 0
system.cpu.itb_walker_cache.blockedCauses::no_targets 0
system.cpu.itb_walker_cache.avgBlocked::no_mshrs nan
system.cpu.itb_walker_cache.avgBlocked::no_targets nan
system.cpu.itb_walker_cache.replacements 0 #
system.cpu.itb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED
(Tick)
system.cpu.itb_walker_cache.power_state.pwrStateResidencyTicks::ON 28931000
system.cpu.itb_walker_cache.power_state.pwrStateResidencyTicks::CLK_GATED
(Tick)
system.cpu.itb_walker_cache.power_state.pwrStateResidencyTicks::SRAM_RETENTION
(Tick)
system.cpu.itb_walker_cache.power_state.pwrStateResidencyTicks::OFF 28931000
system.cpu.itb_walker_cache.tags.tagsInUse 0 #
system.cpu.itb_walker_cache.tags.totalRefs 0 #
Total number of references to valid blocks. (Count)
system.cpu.itb_walker_cache.tags.sampledRefs 0 #
system.cpu.itb_walker_cache.tags.avgRefs nan #
system.cpu.itb_walker_cache.tags.warmupTick 0 #
The tick when the warmup percentage was hit. (Tick)
system.cpu.itb_walker_cache.tags.tagAccesses 0 #
system.cpu.itb_walker_cache.tags.dataAccesses 0 #
system.cpu.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED
(Tick)
system.cpu.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::ON
(Tick)
system.cpu.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::CLK_GATED
(Tick)
system.cpu.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::SRAM_RETENTION
(Tick)
system.cpu.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::OFF
(Tick)
system.cpu.lsq0.forwLoads 3 #
Number of loads that had data forwarded from stores (Count)
system.cpu.lsq0.squashedLoads 166 #
Number of loads squashed (Count)
system.cpu.lsq0.ignoredResponses 1 #
Number of memory responses ignored because the instruction is squashed (Count)
system.cpu.lsq0.memOrderViolation 1 #
Number of memory ordering violations (Count)
system.cpu.lsq0.squashedStores 145 #
Number of stores squashed (Count)
system.cpu.lsq0.rescheduledLoads 0 #
Number of loads that were rescheduled (Count)
system.cpu.lsq0.blockedByCache 1 #
Number of times an access to memory failed due to the cache being blocked (Count)
system.cpu.lsq0.loadToUse::samples 437 #
Distribution of cycle latency between the first time a load is issued and its
completion (Unspecified)
system.cpu.lsq0.loadToUse::mean 13.983982 #
system.cpu.lsq0.loadToUse::stdev 33.968175 #
system.cpu.lsq0.loadToUse::0-9 395 90.39% 90.39% #
system.cpu.lsq0.loadToUse::min_value 2 #
system.cpu.lsq0.loadToUse::max_value 142 #
system.cpu.lsq0.loadToUse::total 437 #
system.cpu.mmu.dtb.readHits 0 # read
hits (Count)
system.cpu.mmu.dtb.readMisses 0 # read
misses (Count)
system.cpu.mmu.dtb.readAccesses 0 # read
accesses (Count)
system.cpu.mmu.dtb.writeHits 0 # write
hits (Count)
system.cpu.mmu.dtb.writeMisses 0 # write
misses (Count)
system.cpu.mmu.dtb.writeAccesses 0 # write
accesses (Count)
system.cpu.mmu.dtb.hits 0 # Total
TLB (read and write) hits (Count)
system.cpu.mmu.dtb.misses 0 # Total
TLB (read and write) misses (Count)
system.cpu.mmu.dtb.accesses 0 # Total
TLB (read and write) accesses (Count)
system.cpu.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED
(Tick)
system.cpu.mmu.dtb.walker.power_state.pwrStateResidencyTicks::ON 28931000
system.cpu.mmu.dtb.walker.power_state.pwrStateResidencyTicks::CLK_GATED
(Tick)
system.cpu.mmu.dtb.walker.power_state.pwrStateResidencyTicks::SRAM_RETENTION
(Tick)
system.cpu.mmu.dtb.walker.power_state.pwrStateResidencyTicks::OFF 28931000
system.cpu.mmu.itb.readHits 0 # read
hits (Count)
system.cpu.mmu.itb.readMisses 0 # read
misses (Count)
system.cpu.mmu.itb.readAccesses 0 # read
accesses (Count)
system.cpu.mmu.itb.writeHits 0 # write
hits (Count)
system.cpu.mmu.itb.writeMisses 0 # write
misses (Count)
system.cpu.mmu.itb.writeAccesses 0 # write
accesses (Count)
system.cpu.mmu.itb.hits 0 # Total
TLB (read and write) hits (Count)
system.cpu.mmu.itb.misses 0 # Total
TLB (read and write) misses (Count)
system.cpu.mmu.itb.accesses 0 # Total
TLB (read and write) accesses (Count)
system.cpu.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED
(Tick)
system.cpu.mmu.itb.walker.power_state.pwrStateResidencyTicks::ON 28931000
system.cpu.mmu.itb.walker.power_state.pwrStateResidencyTicks::CLK_GATED
(Tick)
system.cpu.mmu.itb.walker.power_state.pwrStateResidencyTicks::SRAM_RETENTION
(Tick)
system.cpu.mmu.itb.walker.power_state.pwrStateResidencyTicks::OFF 28931000
system.cpu.power_state.pwrStateResidencyTicks::UNDEFINED 28931000
system.cpu.power_state.pwrStateResidencyTicks::ON 28931000
system.cpu.power_state.pwrStateResidencyTicks::CLK_GATED 28931000
system.cpu.power_state.pwrStateResidencyTicks::SRAM_RETENTION 28931000
system.cpu.power_state.pwrStateResidencyTicks::OFF 28931000
system.cpu.rename.squashCycles 286 #
Number of cycles rename is squashing (Cycle)
system.cpu.rename.idleCycles 3656 #
Number of cycles rename is idle (Cycle)
system.cpu.rename.blockCycles 66 #
Number of cycles rename is blocking (Cycle)
system.cpu.rename.serializeStallCycles 314 # count
of cycles rename stalled for serializing inst (Cycle)
system.cpu.rename.runCycles 43657 #
Number of cycles rename is running (Cycle)
system.cpu.rename.unblockCycles 9 #
Number of cycles rename is unblocking (Cycle)
system.cpu.rename.renamedInsts 53262 #
Number of instructions processed by rename (Count)
system.cpu.rename.LQFullEvents 5 #
Number of times rename has blocked due to LQ full (Count)
system.cpu.rename.SQFullEvents 6 #
Number of times rename has blocked due to SQ full (Count)
system.cpu.rename.renamedOperands 43571 #
Number of destination operands rename has renamed (Count)
system.cpu.rename.lookups 78710 #
Number of register rename lookups that rename has made (Count)
system.cpu.rename.intLookups 78710 #
Number of integer rename lookups (Count)
system.cpu.rename.committedMaps 42356 #
Number of HB maps that are committed (Count)
system.cpu.rename.undoneMaps 1215 #
Number of HB maps that are undone due to squashing (Count)
system.cpu.rename.serializing 13 # count
of serializing insts renamed (Count)
system.cpu.rename.tempSerializing 13 # count
of temporary serializing insts renamed (Count)
system.cpu.rename.skidInsts 27 # count
of insts added to the skid buffer (Count)
system.cpu.rob.reads 100139 # The
number of ROB reads (Count)
system.cpu.rob.writes 105650 # The
number of ROB writes (Count)
system.cpu.thread_0.numInsts 51443 #
Number of Instructions committed (Count)
system.cpu.thread_0.numOps 51443 #
Number of Ops committed (Count)
system.cpu.thread_0.numMemRefs 0 #
Number of Memory References (Count)
system.cpu.workload.numSyscalls 10 #
Number of system calls (Count)
system.cpu_clk_domain.clock 500 # Clock
period in ticks (Tick)
system.cpu_voltage_domain.voltage 1 #
Voltage in Volts (Volt)
system.mem_ctrls.avgPriority_writebacks::samples 206.00
# Average QoS priority value for accepted requests
system.mem_ctrls.avgPriority_functional::samples 206.00
system.mem_ctrls.avgPriority_interrupt::samples 206.00
system.mem_ctrls.avgPriority_cpu.mmu.dtb.walker::samples 206.00
system.mem_ctrls.avgPriority_cpu.mmu.itb.walker::samples 206.00
system.mem_ctrls.avgPriority_cpu.inst::samples 206.00 #
Average QoS priority value for accepted requests
system.mem_ctrls.avgPriority_cpu.data::samples 206.00 #
Average QoS priority value for accepted requests
system.mem_ctrls.priorityMinLatency 0.000000018750 # per
QoS priority minimum request to response latency (Second)
system.mem_ctrls.priorityMaxLatency 0.000000575500 # per
QoS priority maximum request to response latency (Second)
system.mem_ctrls.numReadWriteTurnArounds 0 #
Number of turnarounds from READ to WRITE (Count)
system.mem_ctrls.numWriteReadTurnArounds 0 #
Number of turnarounds from WRITE to READ (Count)
system.mem_ctrls.numStayReadState 402 #
Number of times bus staying in READ state (Count)
system.mem_ctrls.numStayWriteState 0 #
Number of times bus staying in WRITE state (Count)
system.mem_ctrls.readReqs 196 #
Number of read requests accepted (Count)
system.mem_ctrls.writeReqs 16 #
Number of write requests accepted (Count)
system.mem_ctrls.readBursts 196 #
Number of controller read bursts, including those serviced by the write queue
(Count)
system.mem_ctrls.writeBursts 16 #
Number of controller write bursts, including those merged in the write queue
(Count)
system.mem_ctrls.servicedByWrQ 6 #
Number of controller read bursts serviced by the write queue (Count)
system.mem_ctrls.mergedWrBursts 0 #
Number of controller write bursts merged with an existing one (Count)
system.mem_ctrls.neitherReadNorWriteReqs 0 #
Number of requests that are neither read nor write (Count)
system.mem_ctrls.avgRdQLen 1.15 #
Average read queue length when enqueuing ((Count/Tick))
system.mem_ctrls.avgWrQLen 1.05 #
Average write queue length when enqueuing ((Count/Tick))
system.mem_ctrls.numRdRetry 0 #
Number of times read queue was full causing retry (Count)
system.mem_ctrls.numWrRetry 0 #
Number of times write queue was full causing retry (Count)
system.mem_ctrls.readPktSize::0 196 # Read
request sizes (log2) (Count)
system.mem_ctrls.writePktSize::0 16 # Write
system.mem_ctrls.rdQLenPdf::0 190 # What
read queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::0 16 # What
write queue length does an incoming req see (Count)
system.mem_ctrls.bytesReadWrQ 384 # Total
number of bytes read from write queue (Byte)
system.mem_ctrls.bytesReadSys 12544 # Total
read bytes from the system interface side (Byte)
system.mem_ctrls.bytesWrittenSys 1024 # Total
written bytes from the system interface side (Byte)
system.mem_ctrls.avgRdBWSys 433583353.49624968 #
Average system read bandwidth in Byte/s ((Byte/Second))
system.mem_ctrls.avgWrBWSys 35394559.46908160 #
Average system write bandwidth in Byte/s ((Byte/Second))
system.mem_ctrls.totGap 28799000 # Total
gap between requests (Tick)
system.mem_ctrls.avgGap 135844.34 #
Average gap between requests ((Tick/Count))
system.mem_ctrls.requestorReadBytes::writebacks 12160
# Per-requestor bytes read from memory (Byte)
system.mem_ctrls.requestorReadBytes::functional 12160
system.mem_ctrls.requestorReadBytes::interrupt 12160 #
Per-requestor bytes read from memory (Byte)
system.mem_ctrls.requestorReadBytes::cpu.mmu.dtb.walker 12160
system.mem_ctrls.requestorReadBytes::cpu.mmu.itb.walker 12160
system.mem_ctrls.requestorReadBytes::cpu.inst 12160 #
system.mem_ctrls.requestorReadBytes::cpu.data 12160 #
system.mem_ctrls.requestorReadRate::writebacks 420310393.695344090462
# Per-requestor bytes read from memory rate ((Byte/Second))
system.mem_ctrls.requestorReadRate::functional 420310393.695344090462
system.mem_ctrls.requestorReadRate::interrupt 420310393.695344090462
system.mem_ctrls.requestorReadRate::cpu.mmu.dtb.walker 420310393.695344090462
system.mem_ctrls.requestorReadRate::cpu.mmu.itb.walker 420310393.695344090462
system.mem_ctrls.requestorReadRate::cpu.inst 420310393.695344090462
system.mem_ctrls.requestorReadRate::cpu.data 420310393.695344090462
system.mem_ctrls.requestorReadAccesses::writebacks 196
# Per-requestor read serviced memory accesses (Count)
system.mem_ctrls.requestorReadAccesses::functional 196
system.mem_ctrls.requestorReadAccesses::interrupt 196
system.mem_ctrls.requestorReadAccesses::cpu.mmu.dtb.walker 196
system.mem_ctrls.requestorReadAccesses::cpu.mmu.itb.walker 196
system.mem_ctrls.requestorReadAccesses::cpu.inst 196
system.mem_ctrls.requestorReadAccesses::cpu.data 196
system.mem_ctrls.requestorWriteAccesses::writebacks 16
# Per-requestor write serviced memory accesses (Count)
system.mem_ctrls.requestorWriteAccesses::functional 16
system.mem_ctrls.requestorWriteAccesses::interrupt 16
system.mem_ctrls.requestorWriteAccesses::cpu.mmu.dtb.walker 16
system.mem_ctrls.requestorWriteAccesses::cpu.mmu.itb.walker 16
system.mem_ctrls.requestorWriteAccesses::cpu.inst 16
system.mem_ctrls.requestorWriteAccesses::cpu.data 16
system.mem_ctrls.requestorReadTotalLat::writebacks 4611000
# Per-requestor read total memory access latency (Tick)
system.mem_ctrls.requestorReadTotalLat::functional 4611000
system.mem_ctrls.requestorReadTotalLat::interrupt 4611000
system.mem_ctrls.requestorReadTotalLat::cpu.mmu.dtb.walker 4611000
system.mem_ctrls.requestorReadTotalLat::cpu.mmu.itb.walker 4611000
system.mem_ctrls.requestorReadTotalLat::cpu.inst 4611000
system.mem_ctrls.requestorReadTotalLat::cpu.data 4611000
system.mem_ctrls.requestorReadAvgLat::writebacks 23525.51
# Per-requestor read average memory access latency ((Tick/Count))
system.mem_ctrls.requestorReadAvgLat::functional 23525.51
system.mem_ctrls.requestorReadAvgLat::interrupt 23525.51
system.mem_ctrls.requestorReadAvgLat::cpu.mmu.dtb.walker 23525.51
system.mem_ctrls.requestorReadAvgLat::cpu.mmu.itb.walker 23525.51
system.mem_ctrls.requestorReadAvgLat::cpu.inst 23525.51 #
Per-requestor read average memory access latency ((Tick/Count))
system.mem_ctrls.requestorReadAvgLat::cpu.data 23525.51 #
Per-requestor read average memory access latency ((Tick/Count))
system.mem_ctrls.requestorWriteAvgLat::writebacks 0.00
# Per-requestor write average memory access latency ((Tick/Count))
system.mem_ctrls.requestorWriteAvgLat::functional 0.00
system.mem_ctrls.requestorWriteAvgLat::interrupt 0.00
system.mem_ctrls.requestorWriteAvgLat::cpu.mmu.dtb.walker 0.00
system.mem_ctrls.requestorWriteAvgLat::cpu.mmu.itb.walker 0.00
system.mem_ctrls.requestorWriteAvgLat::cpu.inst 0.00
system.mem_ctrls.requestorWriteAvgLat::cpu.data 0.00
system.mem_ctrls.dram.bytesRead::writebacks 12544 #
Number of bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesRead::functional 12544 #
system.mem_ctrls.dram.bytesRead::interrupt 12544 #
system.mem_ctrls.dram.bytesRead::cpu.mmu.dtb.walker 12544
# Number of bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesRead::cpu.mmu.itb.walker 12544
# Number of bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesRead::cpu.inst 12544 #
system.mem_ctrls.dram.bytesRead::cpu.data 12544 #
system.mem_ctrls.dram.bytesRead::total 87808 #
system.mem_ctrls.dram.bytesInstRead::writebacks 9472
# Number of instructions bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesInstRead::functional 9472
system.mem_ctrls.dram.bytesInstRead::interrupt 9472 #
Number of instructions bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesInstRead::cpu.mmu.dtb.walker 9472
system.mem_ctrls.dram.bytesInstRead::cpu.mmu.itb.walker 9472
system.mem_ctrls.dram.bytesInstRead::cpu.inst 9472 #
system.mem_ctrls.dram.bytesInstRead::cpu.data 9472 #
system.mem_ctrls.dram.bytesInstRead::total 66304 #
system.mem_ctrls.dram.numReads::writebacks 196 #
Number of read requests responded to by this memory (Count)
system.mem_ctrls.dram.numReads::functional 196 #
system.mem_ctrls.dram.numReads::interrupt 196 #
system.mem_ctrls.dram.numReads::cpu.mmu.dtb.walker 196
# Number of read requests responded to by this memory (Count)
system.mem_ctrls.dram.numReads::cpu.mmu.itb.walker 196
# Number of read requests responded to by this memory (Count)
system.mem_ctrls.dram.numReads::cpu.inst 196 #
system.mem_ctrls.dram.numReads::cpu.data 196 #
system.mem_ctrls.dram.numReads::total 1372 #
system.mem_ctrls.dram.bwTotal::writebacks 433583353 #
Total bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::functional 433583353 #
Total bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::interrupt 433583353 # Total
bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::cpu.mmu.dtb.walker 433583353
# Total bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::cpu.mmu.itb.walker 433583353
# Total bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::cpu.inst 433583353 # Total
system.mem_ctrls.dram.bwTotal::cpu.data 433583353 # Total
system.mem_ctrls.dram.bwTotal::total 3035083474 # Total
system.mem_ctrls.dram.readBursts 190 #
Number of DRAM read bursts (Count)
system.mem_ctrls.dram.writeBursts 0 #
Number of DRAM write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::0 190 # Per
bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::0 0 # Per
system.mem_ctrls.dram.totQLat 1048500 # Total
ticks spent queuing (Tick)
system.mem_ctrls.dram.totBusLat 950000 # Total
ticks spent in databus transfers (Tick)
system.mem_ctrls.dram.totMemAccLat 4611000 # Total
ticks spent from burst creation until serviced by the DRAM (Tick)
system.mem_ctrls.dram.avgQLat 5518.42 #
Average queueing delay per DRAM burst ((Tick/Count))
system.mem_ctrls.dram.avgBusLat 5000.00 #
Average bus latency per DRAM burst ((Tick/Count))
system.mem_ctrls.dram.avgMemAccLat 24268.42 #
Average memory access latency per DRAM burst ((Tick/Count))
system.mem_ctrls.dram.readRowHits 163 #
Number of row buffer hits during reads (Count)
system.mem_ctrls.dram.writeRowHits 0 #
Number of row buffer hits during writes (Count)
system.mem_ctrls.dram.readRowHitRate 85.79 # Row
buffer hit rate for reads (Ratio)
system.mem_ctrls.dram.writeRowHitRate nan # Row
buffer hit rate for writes (Ratio)
system.mem_ctrls.dram.bytesPerActivate::samples 18
# Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::mean 519.111111 #
Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::gmean 382.189705 #
system.mem_ctrls.dram.bytesPerActivate::stdev 359.292260 #
system.mem_ctrls.dram.bytesPerActivate::0-127 1 5.56% 5.56% #
system.mem_ctrls.dram.bytesPerActivate::128-255 4 22.22% 27.78%
system.mem_ctrls.dram.bytesPerActivate::1024-1151 4 22.22%
100.00% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::total 18 #
system.mem_ctrls.dram.bytesRead 12160 # Total
number of bytes read from DRAM (Byte)
system.mem_ctrls.dram.bytesWritten 0 # Total
number of bytes written to DRAM (Byte)
system.mem_ctrls.dram.avgRdBW 420.310394 #
Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
system.mem_ctrls.dram.avgWrBW 0 #
Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
system.mem_ctrls.dram.peakBW 12800.00 #
Theoretical peak bandwidth in MiByte/s ((Byte/Second))
system.mem_ctrls.dram.busUtil 3.28 # Data
bus utilization in percentage (Ratio)
system.mem_ctrls.dram.busUtilRead 3.28 # Data
bus utilization in percentage for reads (Ratio)
system.mem_ctrls.dram.busUtilWrite 0.00 # Data
bus utilization in percentage for writes (Ratio)
system.mem_ctrls.dram.pageHitRate 85.79 # Row
buffer hit rate, read and write combined (Ratio)
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::UNDEFINED 28931000
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::ON 28931000
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::CLK_GATED 28931000
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::SRAM_RETENTION
(Tick)
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::OFF 28931000
system.mem_ctrls.dram.rank0.actEnergy 121380 #
Energy for activate commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.preEnergy 45540 #
Energy for precharge commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.readEnergy 949620 #
Energy for read commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.writeEnergy 0 #
Energy for write commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.refreshEnergy 1843920.000000 #
Energy for refresh commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.actBackEnergy 7122720 #
Energy for active background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.preBackEnergy 5111520 #
Energy for precharge background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.actPowerDownEnergy 0 #
Energy for active power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.prePowerDownEnergy 0 #
Energy for precharge power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.selfRefreshEnergy 0 #
Energy for self refresh per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.totalEnergy 15194700 # Total
energy per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.averagePower 525.204798 # Core
power per rank (mW) (Watt)
system.mem_ctrls.dram.rank0.totalIdleTime 0 #
Total Idle time Per DRAM Rank (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::IDLE 28931000 #
Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::REF 28931000 #
system.mem_ctrls.dram.rank0.pwrStateTime::SREF 28931000 #
system.mem_ctrls.dram.rank0.pwrStateTime::PRE_PDN 28931000
# Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::ACT 28931000 #
system.mem_ctrls.dram.rank0.pwrStateTime::ACT_PDN 28931000
system.mem_ctrls.dram.rank1.actEnergy 71400 #
Energy for activate commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.preEnergy 22770 #
Energy for precharge commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.readEnergy 406980 #
Energy for read commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.writeEnergy 0 #
Energy for write commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.refreshEnergy 1843920.000000 #
Energy for refresh commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.actBackEnergy 6895860 #
Energy for active background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.preBackEnergy 5302560 #
Energy for precharge background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.actPowerDownEnergy 0 #
Energy for active power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.prePowerDownEnergy 0 #
Energy for precharge power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.selfRefreshEnergy 0 #
Energy for self refresh per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.totalEnergy 14543490 # Total
energy per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.averagePower 502.695724 # Core
power per rank (mW) (Watt)
system.mem_ctrls.dram.rank1.totalIdleTime 0 #
Total Idle time Per DRAM Rank (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::IDLE 28931000 #
system.mem_ctrls.dram.rank1.pwrStateTime::REF 28931000 #
system.mem_ctrls.dram.rank1.pwrStateTime::SREF 28931000 #
system.mem_ctrls.dram.rank1.pwrStateTime::PRE_PDN 28931000
system.mem_ctrls.dram.rank1.pwrStateTime::ACT 28931000 #
system.mem_ctrls.dram.rank1.pwrStateTime::ACT_PDN 28931000
system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 28931000
system.mem_ctrls.power_state.pwrStateResidencyTicks::ON 28931000
system.mem_ctrls.power_state.pwrStateResidencyTicks::CLK_GATED 28931000
system.mem_ctrls.power_state.pwrStateResidencyTicks::SRAM_RETENTION 28931000
system.mem_ctrls.power_state.pwrStateResidencyTicks::OFF 28931000
system.membus.transDist::InvalidCmd 408 #
Transaction distribution (Count)
system.membus.transDist::ReadReq 408 #
system.membus.transDist::ReadResp 408 #
system.membus.transDist::ReadRespWithInvalidate 408
# Transaction distribution (Count)
system.membus.transDist::WriteReq 408 #
system.membus.transDist::WriteResp 408 #
system.membus.transDist::WriteCompleteResp 408 #
system.membus.transDist::WritebackDirty 408 #
system.membus.transDist::WritebackClean 408 #
system.membus.transDist::WriteClean 408 #
system.membus.transDist::CleanEvict 408 #
system.membus.transDist::SoftPFReq 408 #
system.membus.transDist::SoftPFExReq 408 #
system.membus.transDist::HardPFReq 408 #
system.membus.transDist::SoftPFResp 408 #
system.membus.transDist::HardPFResp 408 #
system.membus.transDist::WriteLineReq 408 #
system.membus.transDist::UpgradeReq 408 #
system.membus.transDist::SCUpgradeReq 408 #
system.membus.transDist::UpgradeResp 408 #
system.membus.transDist::SCUpgradeFailReq 408 #
system.membus.transDist::UpgradeFailResp 408 #
system.membus.transDist::ReadExReq 408 #
system.membus.transDist::ReadExResp 408 #
system.membus.transDist::ReadCleanReq 408 #
system.membus.transDist::ReadSharedReq 408 #
system.membus.transDist::LoadLockedReq 408 #
system.membus.transDist::StoreCondReq 408 #
system.membus.transDist::StoreCondFailReq 408 #
system.membus.transDist::StoreCondResp 408 #
system.membus.transDist::SwapReq 408 #
system.membus.transDist::SwapResp 408 #
system.membus.transDist::Deprecated_MessageReq 408 #
system.membus.transDist::Deprecated_MessageResp 408
# Transaction distribution (Count)
system.membus.transDist::MemFenceReq 408 #
system.membus.transDist::MemSyncReq 408 #
system.membus.transDist::MemSyncResp 408 #
system.membus.transDist::MemFenceResp 408 #
system.membus.transDist::CleanSharedReq 408 #
system.membus.transDist::CleanSharedResp 408 #
system.membus.transDist::CleanInvalidReq 408 #
system.membus.transDist::CleanInvalidResp 408 #
system.membus.transDist::InvalidDestError 408 #
system.membus.transDist::BadAddressError 408 #
system.membus.transDist::FunctionalReadError 408 #
system.membus.transDist::FunctionalWriteError 408 #
system.membus.transDist::PrintReq 408 #
system.membus.transDist::FlushReq 408 #
system.membus.transDist::InvalidateReq 408 #
system.membus.transDist::InvalidateResp 408 #
system.membus.transDist::HTMReq 408 #
system.membus.transDist::HTMReqResp 408 #
system.membus.transDist::HTMAbort 408 #
system.membus.pktCount_system_port::system.mem_ctrls.port 408
# Packet count per connected requestor and responder (Count)
system.membus.pktCount_system.cpu.icache.mem_side_port::system.mem_ctrls.port
408 # Packet count per connected requestor and responder
(Count)
system.membus.pktCount_system.cpu.dcache.mem_side_port::system.mem_ctrls.port
408 # Packet count per connected requestor and responder
(Count)
system.membus.pktCount_system.cpu.itb_walker_cache.mem_side_port::system.mem_ctrls.
port 408 # Packet count per connected requestor and
responder (Count)
system.membus.pktCount_system.cpu.dtb_walker_cache.mem_side_port::system.mem_ctrls.
port 408 # Packet count per connected requestor and
responder (Count)
system.membus.pktCount::total 2040 #
Packet count per connected requestor and responder (Count)
system.membus.pktSize_system_port::system.mem_ctrls.port 13568
# Cumulative packet size per connected requestor and responder (Byte)
system.membus.pktSize_system.cpu.icache.mem_side_port::system.mem_ctrls.port
13568 # Cumulative packet size per connected requestor and
responder (Byte)
system.membus.pktSize_system.cpu.dcache.mem_side_port::system.mem_ctrls.port
13568 # Cumulative packet size per connected requestor and
responder (Byte)
system.membus.pktSize_system.cpu.itb_walker_cache.mem_side_port::system.mem_ctrls.p
ort 13568 # Cumulative packet size per connected
requestor and responder (Byte)
system.membus.pktSize_system.cpu.dtb_walker_cache.mem_side_port::system.mem_ctrls.p
ort 13568 # Cumulative packet size per connected
requestor and responder (Byte)
system.membus.pktSize::total 67840 #
Cumulative packet size per connected requestor and responder (Byte)
system.membus.snoops 0 # Total
snoops (Count)
system.membus.snoopTraffic 0 # Total
snoop traffic (Byte)
system.membus.snoopFanout::samples 196 #
Request fanout histogram (Count)
system.membus.snoopFanout::mean 0 #
system.membus.snoopFanout::stdev 0 #
system.membus.snoopFanout::underflows 0 0.00% 0.00% #
system.membus.snoopFanout::0 196 100.00% 100.00% #
system.membus.snoopFanout::overflows 0 0.00% 100.00% #
system.membus.snoopFanout::min_value 0 #
system.membus.snoopFanout::max_value 0 #
system.membus.snoopFanout::total 196 #
system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 28931000
system.membus.power_state.pwrStateResidencyTicks::ON 28931000
system.membus.power_state.pwrStateResidencyTicks::CLK_GATED 28931000
system.membus.power_state.pwrStateResidencyTicks::SRAM_RETENTION 28931000
system.membus.power_state.pwrStateResidencyTicks::OFF 28931000
system.membus.reqLayer0.occupancy 323000 # Layer
occupancy (ticks) (Tick)
system.membus.reqLayer0.utilization 0.0 # Layer
utilization (Ratio)
system.membus.respLayer1.occupancy 779250 # Layer
system.membus.respLayer1.utilization 0.0 # Layer
utilization (Ratio)
system.membus.respLayer2.occupancy 254250 # Layer
system.membus.respLayer2.utilization 0.0 # Layer
utilization (Ratio)
system.membus.snoop_filter.totRequests 212 # Total
number of requests made to the snoop filter. (Count)
system.membus.snoop_filter.hitSingleRequests 16 #
Number of requests hitting in the snoop filter with a single holder of the
requested data. (Count)
system.membus.snoop_filter.hitMultiRequests 0 #
Number of requests hitting in the snoop filter with multiple (>1) holders of the
system.membus.snoop_filter.totSnoops 0 # Total
number of snoops made to the snoop filter. (Count)
system.membus.snoop_filter.hitSingleSnoops 0 #
Number of snoops hitting in the snoop filter with a single holder of the requested
data. (Count)
system.membus.snoop_filter.hitMultiSnoops 0 #
Number of snoops hitting in the snoop filter with multiple (>1) holders of the
system.voltage_domain.voltage 1 #
Voltage in Volts (Volt)
system.workload.inst.arm 0 #
number of arm instructions executed (Count)
system.workload.inst.quiesce 0 #
number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------

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---------- Begin Simulation Statistics ----------

---------- End Simulation Statistics ----------

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