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OPA334

OPA3
35
OPA2
335
OPA2334
OPA2
334
OPA23
35

OPA335
OPA2335
SBOS245D – JUNE 2002 – REVISED JULY 2003

0.05µV/°C max, SINGLE-SUPPLY


CMOS OPERATIONAL AMPLIFIERS
Zerø-Drift Series
FEATURES DESCRIPTION
● LOW OFFSET VOLTAGE: 5µV (max) The OPA334 and OPA335 series of CMOS operational
amplifiers use auto-zeroing techniques to simultaneously
● ZERO DRIFT: 0.05µV/°C (max)
provide very low offset voltage (5µV max), and near-zero drift
● QUIESCENT CURRENT: 285µA over time and temperature. These miniature, high-precision,
● SINGLE-SUPPLY OPERATION low quiescent current amplifiers offer high input impedance
and rail-to-rail output swing. Single or dual supplies as low as
● SINGLE AND DUAL VERSIONS
+2.7V (±1.35V) and up to +5.5V (±2.75V) may be used.
● SHUTDOWN These op amps are optimized for low-voltage, single-supply
● MicroSIZE PACKAGES operation.
The OPA334 family includes a shutdown mode. Under logic
control, the amplifiers can be switched from normal operation
APPLICATIONS to a standby current of 2µA. When the Enable pin is con-
● TRANSDUCER APPLICATIONS nected high, the amplifier is active. Connecting Enable low
disables the amplifier, and places the output in a high-
● TEMPERATURE MEASUREMENT impedance state.
● ELECTRONIC SCALES The OPA334 (single version with shutdown) comes in
● MEDICAL INSTRUMENTATION MicroSIZE SOT23-6. The OPA335 (single version without
● BATTERY-POWERED INSTRUMENTS shutdown) is available in SOT23-5, and SO-8. The OPA2334
(dual version with shutdown) comes in MicroSIZE MSOP-10.
● HANDHELD TEST EQUIPMENT The OPA2335 (dual version without shutdown) is offered in
the MSOP-8 and SO-8 packages. All versions are specified
for operation from –40°C to +125°C.

OFFSET VOLTAGE PRODUCTION DISTRIBUTION OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION


Population

Population

Absolute Value;
Centered Around Zero
–3.0
–2.7
–2.4
–2.1
–1.8
–1.5
–1.2
–0.9
–0.6
–0.3
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0

0.005

0.010

0.015

0.020

0.025

0.030

0.035

0.040

0.045

0.050

Offset Voltage (µV)


Offset Voltage Drift (µV/°C)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2002-2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
Supply Voltage .................................................................................... +7V
Signal Input Terminals, Voltage(2) ........................... –0.5V to (V+) + 0.5V DISCHARGE SENSITIVITY
Current(2) .................................................. ±10mA
Output Short Circuit(3) .............................................................. Continuous This integrated circuit can be damaged by ESD. Texas
Operating Temperature .................................................. –40°C to +150°C Instruments recommends that all integrated circuits be handled
Storage Temperature ..................................................... –65°C to +150°C with appropriate precautions. Failure to observe proper han-
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C dling and installation procedures can cause damage.

NOTES: (1) Stresses above these ratings may cause permanent damage. ESD damage can range from subtle performance degrada-
Exposure to absolute maximum conditions for extended periods may de- tion to complete device failure. Precision integrated circuits
grade device reliability. These are stress ratings only, and functional opera-
may be more susceptible to damage because very small
tion of the device at these, or any other conditions beyond those specified,
is not implied. (2) Input terminals are diode-clamped to the power-supply parametric changes could cause the device not to meet its
rails. Input signals that can swing more than 0.5V beyond the supply rails published specifications.
should be current-limited to 10mA or less. (3) Short-circuit to ground, one
amplifier per package.

PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD DESIGNATOR(1) RANGE MARKING NUMBER MEDIA, QUANTITY

Shutdown Version
OPA334 SOT23-6 DBV –40°C to +125°C OAOI OPA334AIDBVT Tape and Reel, 250
" " " " " OPA334AIDBVR Tape and Reel, 3000
OPA2334 MSOP-10 DGS –40°C to +125°C BHE OPA2334AIDGST Tape and Reel, 250
" " " " " OPA2334AIDGSR Tape and Reel, 2500
Non-Shutdown Version
OPA335 SOT23-5 DBV –40°C to +125°C OAPI OPA335AIDBVT Tape and Reel, 250
" " " " " OPA335AIDBVR Tape and Reel, 3000
OPA335 SO-8 D –40°C to +125°C OPA335 OPA335AID Rails, 100
" " " " " OPA335AIDR Tape and Reel, 2500
OPA2335 SO-8 D –40°C to +125°C OPA2335 OPA2335AID Rails, 100
" " " " " OPA2335AIDR Tape and Reel, 2500
OPA2335 MSOP-8 DGK –40°C to +125°C BHF OPA2335AIDGKT Tape and Reel, 250
" " " " " OPA2335AIDGKR Tape and Reel, 2500

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

PIN CONFIGURATIONS

OPA335 OPA335 OPA2334

Out 1 5 V+ NC(1) 1 8 NC(1) Out A 1 10 V+

V– 2 –In 2 7 V+ –In A 2 9 Out B


A
+In 3 4 –In +In 3 6 Out +In A 3 8 –In B
B
V– 4 5 NC(1) V– 4 7 +In B
SOT23-5
Enable A 5 6 Enable B
SO-8
MSOP-10

OPA334(2) OPA2335
OAOI

Out 1 6 V+ Out A 1 8 V+

–In A 2 A 7 Out B
V– 2 5 Enable

+In A 3 B 6 –In B
+In 3 4 –In

V– 4 5 +In B
SOT23-6

SO-8, MSOP-8

NOTES: (1) NC indicates no internal connection. (2) Pin 1 of the SOT23-6 is


determined by orienting the package marking as indicated in the diagram.

2
OPA334, OPA2334, OPA335, OPA2335
www.ti.com SBOS245D
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, VS = +5V, RL = 10kΩ connected to VS /2, and VOUT = VS /2, unless otherwise noted.

OPA334AI, OPA335AI
OPA2334AI, OPA2335AI

PARAMETER CONDITION MIN TYP MAX UNITS


OFFSET VOLTAGE
Input Offset Voltage VOS VCM = VS /2 1 5 µV
vs Temperature dVOS /dT ±0.02 ±0.05 µV/°C
vs Power Supply PSRR VS = +2.7V to +5.5V, VCM = 0, Over Temperature ±1 ±2 µV/V
Long-Term Stability(1) See Note (1)
Channel Separation, dc 0.1 µV/V
INPUT BIAS CURRENT
Input Bias Current IB VCM = VS /2 ±70 ±200 pA
Over Temperature 1 nA
Input Offset Current IOS ±120 ±400 pA
NOISE
Input Voltage Noise, f = 0.01Hz to 10Hz en 1.4 µVPP
Input Current Noise Density, f = 10Hz in 20 fA/ √Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range VCM (V–) – 0.1 (V+) – 1.5 V
Common-Mode Rejection Ratio CMRR (V–) – 0.1V < VCM < (V+) – 1.5V, Over Temperature 110 130 dB
INPUT CAPACITANCE
Differential 1 pF
Common-Mode 5 pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain, Over Temperature AOL 50mV < VO < (V+) – 50mV, RL = 100kΩ, VCM = VS /2 110 130 dB
Over Temperature 100mV < VO < (V+) – 100mV, RL = 10kΩ, VCM = VS /2 110 130 dB
FREQUENCY RESPONSE
Gain-Bandwidth Product GBW 2 MHz
Slew Rate SR G = +1 1.6 V/µs
OUTPUT
Voltage Output Swing from Rail RL = 10kΩ, Over Temperature 15 100 mV
Voltage Output Swing from Rail RL = 100kΩ, Over Temperature 1 50 mV
Short-Circuit Current ISC ±50 mA
Capacitive Load Drive CLOAD See Typical Characteristics
SHUTDOWN
tOFF 1 µs
tON(2) 150 µs
VL (shutdown) 0 +0.8 V
VH (amplifier is active) 0.75 (V+) 5.5 V
Input Bias Current of Enable Pin 50 pA
IQSD 2 µA
POWER SUPPLY
Operating Voltage Range 2.7 5.5 V
Quiescent Current: OPA334, OPA335 IQ IO = 0 285 350 µA
Over Temperature 450 µA
OPA2334, OPA2335 (total—two amplifiers) IO = 0 570 700 µA
Over Temperature 900 µA
TEMPERATURE RANGE
Specified Range –40 +125 °C
Operating Range –40 +150 °C
Storage Range –65 +150 °C
Thermal Resistance θJA °C/W
SOT23-5, SOT23-6 Surface-Mount 200 °C/W
MSOP-8, MSOP-10, SO-8 Surface-Mount 150 °C/W

NOTES: (1) 500-hour life test at 150°C demonstrated randomly distributed variation approximately equal to measurement repeatability of 1µV. (2) Device requires
one complete cycle to return to VOS accuracy.

OPA334, OPA2334, OPA335, OPA2335 3


SBOS245D www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, RL = 10kΩ connected to VS /2, and VOUT = VS /2, unless otherwise noted.

OFFSET VOLTAGE PRODUCTION DISTRIBUTION OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION


Population

Population
Absolute Value;
Centered Around Zero
–3.0
–2.7
–2.4
–2.1
–1.8
–1.5
–1.2
–0.9
–0.6
–0.3
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0

0.005

0.010

0.015

0.020

0.025

0.030

0.035

0.040

0.045

0.050
Offset Voltage (µV)
Offset Voltage Drift (µV/°C)

OUTPUT VOLTAGE SWING vs OUTPUT CURRENT INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
(V+) 1200
+125°C
5.5V
2.7V 1000
+125°C
Output Voltage Swing (V)

Input Bias Current (pA)

(V+) – 1 +25°C
800
–40°C
600
+25°C
(V–) + 1 400
–40°C
–40°C
+125°C +25°C
200

(V–) 0
0 2 4 6 8 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Output Current (mA) Common-Mode Voltage (V)

QUIESCENT CURRENT (per channel)


INPUT BIAS CURRENT vs TEMPERATURE vs TEMPERATURE
1000 400

350
VS = +5.5V
Input Bias Current (pA)

Quiescent Current (µA)

300

250

100 200
VS = +2.7V
150

100

50

10 0
–40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120
Temperature (°C) Temperature (°C)

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OPA334, OPA2334, OPA335, OPA2335
www.ti.com SBOS245D
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, RL = 10kΩ connected to VS /2, and VOUT = VS /2, unless otherwise noted.

OPEN-LOOP GAIN/PHASE vs FREQUENCY LARGE-SIGNAL RESPONSE


140 –80
G = –1
120 –90 CL = 300pF
Phase

Output Voltage (1V/div)


100 –100

80 –110

Phase (°)
AOL (dB)

60 –120
Gain
40 –130

20 –140

0 –150

–20 –160
0.1 1 10 100 1k 10k 100k 1M 10M Time (5µs/div)
Frequency (Hz)

SMALL-SIGNAL RESPONSE POSITIVE OVER-VOLTAGE RECOVERY

G = +1

200mV/div
CL = 50pF
Output Voltage (50mV/div)

0
Input

10kΩ

+2.5V
1V/div

100Ω Output
0
OPA335

–2.5V

Time (5µs/div) Time (25µs/div)

NEGATIVE OVER-VOLTAGE RECOVERY COMMON-MODE REJECTION vs FREQUENCY


140

120
200mV/div

Common-Mode Rejection (dB)

Input
100
0
80
0
10kΩ 60
+2.5V
1V/div

100Ω 40
Output
OPA335
20
–2.5V
0
Time (25µs/div) 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz)

OPA334, OPA2334, OPA335, OPA2335 5


SBOS245D www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, RL = 10kΩ connected to VS /2, and VOUT = VS /2, unless otherwise noted.

POWER-SUPPLY REJECTION RATIO vs FREQUENCY SAMPLING FREQUENCY vs SUPPLY VOLTAGE


140 11.0
Power-Supply Rejection Ratio (dB)

10.9
120
+PSRR 10.8
100 10.7

Frequency (kHz)
80 10.6
10.5
60
10.4
40 10.3
–PSRR
10.2
20
10.1
0 10.0
10 100 1k 10k 100k 1M 2.7 3.2 3.7 4.2 4.7 5.2 5.5
Frequency (Hz) Supply Voltage (V)

NOISE vs FREQUENCY 0.01Hz TO 10Hz NOISE


1000
Noise (nV/√Hz)

400nV/div

100

10
1 10 100 1k 10k 100k 10s/div
Frequency (Hz)

SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE


SAMPLING FREQUENCY vs TEMPERATURE (VS = 2.7V to 5V)
13 50
RL = 10kΩ
45
Sampling Frequency (kHz)

12 40
35
Overshoot (%)

11 30
25
10 20
15
9 10
5
8 0
–40 –10 20 50 80 110 125 10 100 1000
Temperature (°C) Load Capacitance (pF)

6
OPA334, OPA2334, OPA335, OPA2335
www.ti.com SBOS245D
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, RL = 10kΩ connected to VS /2, and VOUT = VS /2, unless otherwise noted.

SETTLING TIME vs CLOSED-LOOP GAIN COMMON-MODE RANGE vs SUPPLY VOLTAGE


100 4.5
Unity-gain 4.0
requires one

Common-Mode Range (V)


complete Auto-Zero 3.5
Maximum Common-Mode
Cycle—see text.
Settling Time (µs)

3.0

0.01% 2.5
10 2.0
1.5

0.1% 1.0
0.5
Minimum Common-Mode
0
1 –0.5
1 10 100 2.7 3.2 3.7 4.2 4.7 5.2 5.5
Gain (V/V) Supply Voltage (V)

APPLICATIONS INFORMATION OPA334 ENABLE FUNCTION


The enable/shutdown digital input is referenced to the V–
The OPA334 and OPA335 series op amps are unity-gain
supply voltage of the amp. A logic high enables the op amp. A
stable and free from unexpected output phase reversal. They
valid logic high is defined as > 75% of the total supply voltage.
use auto-zeroing techniques to provide low offset voltage
The valid logic high signal can be up to 5.5V above the negative
and very low drift over time and temperature.
supply, independent of the positive supply voltage. A valid
Good layout practice mandates use of a 0.1µF capacitor logic low is defined as < 0.8V above the V– supply pin. If dual
placed closely across the supply pins. or split power supplies are used, be sure that logic input signals
For lowest offset voltage and precision performance, circuit are properly referred to the negative supply voltage. The
layout and mechanical conditions should be optimized. Avoid Enable pin must be connected to a valid high or low voltage, or
temperature gradients that create thermoelectric (Seebeck) driven, not left open circuit.
effects in thermocouple junctions formed from connecting The logic input is a high-impedance CMOS input, with sepa-
dissimilar conductors. These thermally-generated potentials rate logic inputs provided on the dual version. For battery-
can be made to cancel by assuring that they are equal on operated applications, this feature can be used to greatly
both input terminals. reduce the average current and extend battery life.
• Use low thermoelectric-coefficient connections (avoid dis- The enable time is 150µs, which includes one full auto-zero
similar metals). cycle required by the amplifier to return to VOS accuracy.
• Thermally isolate components from power supplies or Prior to this time, the amplifier functions properly, but with
other heat-sources. unspecified offset voltage.
• Shield op amp and input circuitry from air currents, such as Disable time is 1µs. When disabled, the output assumes a
cooling fans. high-impedance state. This allows the OPA334 to be oper-
Following these guidelines will reduce the likelihood of junc- ated as a gated amplifier, or to have the output multiplexed
tions being at different temperatures, which can cause ther- onto a common analog output bus.
moelectric voltages of 0.1µV/°C or higher, depending on
materials used. INPUT VOLTAGE
The input common-mode range extends from (V–) – 0.1V to
OPERATING VOLTAGE (V+) – 1.5V. For normal operation, the inputs must be limited
The OPA334 and OPA335 series op amps operate over a to this range. The common-mode rejection ratio is only valid
power-supply range of +2.7V to +5.5V (±1.35V to ±2.75V). within the valid input common-mode range. A lower supply
Supply voltages higher than 7V (absolute maximum) can voltage results in lower input common-mode range; there-
permanently damage the amplifier. Parameters that vary fore, attention to these values must be given when selecting
over supply voltage or temperature are shown in the Typical the input bias voltage. For example, when operating on a
Characteristics section of this data sheet. single 3V power supply, common-mode range is from 0.1V
below ground to half the power-supply voltage.

OPA334, OPA2334, OPA335, OPA2335 7


SBOS245D www.ti.com
Normally, input bias current is approximately 70pA; however, swing limit of a single-supply op amp. A good single-supply
input voltages exceeding the power supplies can cause op amp may swing close to single-supply ground, but will not
excessive current to flow in or out of the input pins. Momen- reach ground. The output of the OPA334 or OPA335 can be
tary voltages greater than the power supply can be tolerated made to swing to ground, or slightly below, on a single-
if the input current is limited to 10mA. This is easily accom- supply power source. To do so requires use of another
plished with an input resistor, as shown in Figure 1. resistor and an additional, more negative, power supply than
the op amp’s negative supply. A pull-down resistor may be
connected between the output and the additional negative
supply to pull the output down below the value that the output
Current-limiting resistor
would otherwise achieve, as shown in Figure 2.
required if input voltage
exceeds supply rails by
≥ 0.5V.
+5V
V+ = +5V
IOVERLOAD
10mA max
OPA335 VOUT
VIN OPA335 VOUT
5kΩ VIN
RP = 40kΩ

Op Amp’s V– = Gnd
FIGURE 1. Input Current Protection. –5V
Additional
Negative
Supply
INTERNAL OFFSET CORRECTION
The OPA334 and OPA335 series op amps use an auto-zero
FIGURE 2. Op Amp with Pull-Down Resistor to Achieve
topology with a time-continuous 2MHz op amp in the signal
VOUT = Ground.
path. This amplifier is zero-corrected every 100µs using a
proprietary technique. Upon power-up, the amplifier requires
one full auto-zero cycle of approximately 100µs to achieve The OPA334 and OPA335 have an output stage that allows
specified VOS accuracy. Prior to this time, the amplifier the output voltage to be pulled to its negative supply rail, or
functions properly but with unspecified offset voltage. slightly below using the above technique. This technique only
works with some types of output stages. The OPA334 and
This design has remarkably little aliasing and noise. Zero
OPA335 have been characterized to perform well with this
correction occurs at a 10kHz rate, but there is virtually no
technique. Accuracy is excellent down to 0V and as low as
fundamental noise energy present at that frequency. For all
–2mV. Limiting and non-linearity occurs below –2mV, but
practical purposes, any glitches have energy at 20MHz or
excellent accuracy returns as the output is again driven
higher and are easily filtered, if required. Most applications
above –2mV. Lowering the resistance of the pull-down resis-
are not sensitive to such high-frequency noise, and no
tor will allow the op amp to swing even further below the
filtering is required.
negative rail. Resistances as low as 10kΩ can be used to
Unity-gain operation demands that the auto-zero circuitry achieve excellent accuracy down to –10mV.
correct for common-mode rejection errors of the main ampli-
fier. Because these errors can be larger than 0.01% of a full- LAYOUT GUIDELINES
scale input step change, one calibration cycle (100µs) can be
Attention to good layout practices is always recommended.
required to achieve full accuracy. This behavior is shown in
Keep traces short. When possible, use a PCB ground plane
the typical characteristic section, see Settling Time vs Closed-
with surface-mount components placed as close to the de-
Loop Gain.
vice pins as possible. Place a 0.1µF capacitor closely across
the supply pins. These guidelines should be applied through-
ACHIEVING OUTPUT SWING TO THE OP AMP’S out the analog circuit to improve performance and provide
NEGATIVE RAIL benefits such as reducing the EMI (electromagnetic-interfer-
Some applications require output voltage swing from 0V to a ence) susceptibility.
positive full-scale voltage (such as +2.5V) with excellent
accuracy. With most single-supply op amps, problems arise
when the output signal approaches 0V, near the lower output

8
OPA334, OPA2334, OPA335, OPA2335
www.ti.com SBOS245D
4.096V
+5V REF3040
+
0.1µF
R9
R1 150kΩ
6.04kΩ
R5
31.6kΩ +5V
D1
0.1µF

+
R2 R2
2.94kΩ 549Ω
– –

+ + OPA335 VO
R6
K-Type 200Ω
Thermocouple Zero Adj.
R4 R3
40.7µV/°C
6.04kΩ 60.4Ω

FIGURE 3. Temperature Measurement Circuit.

IIN R1 IIN R1

+5V
+2.5V

Photodiode Photodiode
OPA343 OPA343

–2.5V

C1 1MΩ C1
1MΩ

+2.5V +5V

R2 R2

OPA335 NOTE: (1) Optional pull-down OPA335


resistor to allow below C2
C2 40kΩ(1)
ground output swing.
–2.5V

–5V
a. Split Supply. b. Single Supply.

FIGURE 4. Auto-Zeroed Transimpedance Amplifier.

VEX = +2.5V

VEX
R1 = 105Ω
R1
Select R1 so bridge R2
output ≤ VCMmax.
+5V
@ VS = 2.7V, +2.7V
R R
300Ω VCMmax = 1.2V
R R
OPA335 VOUT Bridge
OPA335 VOUT

R1
R2
VREF
VREF
a. 5V Supply Bridge Amplifier. b. 2.7V Supply Bridge Amplifier.

FIGURE 5. Single Op Amp Bridge Amplifier Circuits.

OPA334, OPA2334, OPA335, OPA2335 9


SBOS245D www.ti.com
R2 R1 R1 R2

VREF +5V R2
G=1+
+5V R1

1/2
OPA2335 1/2
R R
OPA2335 VOUT
R R
R3(1)
40kΩ

–5V
NOTE: (1) Optional pull-down resistor
to allow accurate swing to 0V.

FIGURE 6. Dual Op Amp IA Bridge Amplifier.

11.5kΩ

+5V 5V
V

FS = 0.63V
Load
OPA335
R3(1) ADS1100 I2C
40kΩ
50mV
RS 1kΩ
Shunt G = 12.5 –5V
(PGA Gain = 8)
5V FS

NOTE: (1) Pull-down resistor


to allow accurate swing to 0V.

FIGURE 7. Low-Side Current Measurement.

10
OPA334, OPA2334, OPA335, OPA2335
www.ti.com SBOS245D
R1
4.12kΩ

C1
56pF

+5V
C2
0.1µF

R3
Photodiode 100Ω
≈ 2pF OPA353 VOUT
C3
R2(1) 1nF ≈ 1MHz Bandwidth
2kΩ VOS ≈ 10µV

–5V

C4
10nF

R7 +5V
Photodiode 1kΩ C6
Bias 0.1µF
C7 R4
1µF 100kΩ R6
49.9kΩ
OPA335
C5
R5(1) 10nF
40kΩ

–5V
NOTE: (1) Pull-down resistors to allow accurate swing to 0V.

FIGURE 8. High Dynamic Range Transimpedance Amplifier.

OPA334, OPA2334, OPA335, OPA2335 11


SBOS245D www.ti.com
PACKAGE DRAWINGS

DBV (R-PDSO-G6) PLASTIC SMALL-OUTLINE

0,50
0,95 6X 0,20 M
0,25
6 4

0,15 NOM
1,70 3,00
1,50 2,60

1 3
Gage Plane
3,00
2,80
0,25
0 –8
0,55
0,35

Seating Plane

1,45
0,05 MIN 0,10
0,95

4073253-5/G 01/02

NOTES: A. All linear dimensions are in millimeters.


B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation.

12
OPA334, OPA2334, OPA335, OPA2335
www.ti.com SBOS245D
PACKAGE DRAWINGS (Cont.)

DGS (S-PDSO-G10) PLASTIC SMALL-OUTLINE PACKAGE

0,27
0,50 0,08 M
0,17
10 6

0,15 NOM
3,05 4,98
2,95 4,78

Gage Plane

0,25

1 5 0°– 6°
0,69
3,05 0,41
2,95

Seating Plane

0,15
1,07 MAX 0,10
0,05

4073272/B 08/01

NOTES: A. All linear dimensions are in millimeters.


B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
A. Falls within JEDEC MO-187

OPA334, OPA2334, OPA335, OPA2335 13


SBOS245D www.ti.com
PACKAGE DRAWINGS (Cont.)

DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE

0,50 0,20 M
0,95
0,30
5 4

0,15 NOM
1,70 3,00
1,50 2,60

1 3
Gage Plane
3,00
2,80
0,25

0° – 8° 0,55
0,35

Seating Plane

1,45
0,05 MIN 0,10
0,95

4073253-4/G 01/02

NOTES: A. All linear dimensions are in millimeters.


B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-178

14
OPA334, OPA2334, OPA335, OPA2335
www.ti.com SBOS245D
PACKAGE DRAWINGS (Cont.)

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE


8 PINS SHOWN

0.020 (0,51)
0.050 (1,27) 0.010 (0,25)
0.014 (0,35)
8 5

0.244 (6,20) 0.008 (0,20) NOM


0.228 (5,80)
0.157 (4,00)
0.150 (3,81)

Gage Plane

1 4 0.010 (0,25)

A 0°– 8°
0.044 (1,12)
0.016 (0,40)

Seating Plane

0.010 (0,25)
0.069 (1,75) MAX 0.004 (0,10)
0.004 (0,10)

PINS **
8 14 16
DIM

0.197 0.344 0.394


A MAX
(5,00) (8,75) (10,00)
0.189 0.337 0.386
A MIN
(4,80) (8,55) (9,80)

4040047/E 09/01

NOTES: A. All linear dimensions are in inches (millimeters).


B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

OPA334, OPA2334, OPA335, OPA2335 15


SBOS245D www.ti.com
PACKAGE DRAWINGS (Cont.)

DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE

0,38
0,65 0,08 M
0,25
8 5

0,15 NOM
3,05 4,98
2,95 4,78

Gage Plane

0,25

1 4 0°– 6°
0,69
3,05 0,41
2,95

Seating Plane

0,15
1,07 MAX 0,10
0,05

4073329/C 08/01

NOTES: A. All linear dimensions are in millimeters.


B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187

16
OPA334, OPA2334, OPA335, OPA2335
www.ti.com SBOS245D
PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA2334AIDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BHE

OPA2334AIDGST ACTIVE VSSOP DGS 10 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BHE

OPA2334AIDGSTG4 ACTIVE VSSOP DGS 10 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BHE

OPA2335AID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA
2335
OPA2335AIDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BHF

OPA2335AIDGKRG4 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BHF

OPA2335AIDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BHF

OPA2335AIDGKTG4 ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BHF

OPA2335AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA
2335
OPA334AIDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OAOI

OPA334AIDBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OAOI

OPA334AIDBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OAOI

OPA335AID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA
335
OPA335AIDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 OAPI

OPA335AIDBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 OAPI

OPA335AIDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 OAPI

OPA335AIDBVTG4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 OAPI

OPA335AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA
335

(1)
The marketing status values are defined as follows:

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

ACTIVE: Product device recommended for new designs.


LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF OPA2335 :

• Military: OPA2335M

NOTE: Qualified Version Definitions:

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 20-Oct-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2334AIDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2334AIDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2335AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2335AIDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2335AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA334AIDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
OPA334AIDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
OPA335AIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA335AIDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA335AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 20-Oct-2020

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2334AIDGSR VSSOP DGS 10 2500 853.0 449.0 35.0
OPA2334AIDGST VSSOP DGS 10 250 210.0 185.0 35.0
OPA2335AIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
OPA2335AIDGKT VSSOP DGK 8 250 366.0 364.0 50.0
OPA2335AIDR SOIC D 8 2500 853.0 449.0 35.0
OPA334AIDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
OPA334AIDBVT SOT-23 DBV 6 250 180.0 180.0 18.0
OPA335AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
OPA335AIDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
OPA335AIDR SOIC D 8 2500 853.0 449.0 35.0

Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/F 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.

www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE


EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN


ARROUND ARROUND

NON SOLDER MASK SOLDER MASK


DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/F 06/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.


6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/F 06/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA

1
6

2X 0.95
3.05
2.75
1.9 5
2

4
3
0.50
6X
0.25
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214840/C 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.

www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE


EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN


ARROUND ARROUND

NON SOLDER MASK SOLDER MASK


DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214840/C 06/2021

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.


7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214840/C 06/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
DGS0010A SCALE 3.200
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP SEATING PLANE
4.75

A PIN 1 ID 0.1 C
AREA

8X 0.5
10
1

3.1
2.9 2X
NOTE 3 2

5
6
0.27
10X
0.17
3.1 0.1 C A B 1.1 MAX
B
2.9
NOTE 4

0.23
TYP
SEE DETAIL A 0.13

0.25
GAGE PLANE

0.7 0.15
0 -8 0.05
0.4

DETAIL A
TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.

www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
10X (0.3) SYMM (R0.05)
1 TYP
10

SYMM

8X (0.5) 5 6

(4.4)

LAND PATTERN EXAMPLE


SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK


METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN


ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK


DEFINED DEFINED

SOLDER MASK DETAILS


NOT TO SCALE

4221984/A 05/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.


7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
SYMM (R0.05) TYP
10X (0.3)
1
10

SYMM
8X (0.5)

5 6

(4.4)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221984/A 05/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE


EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK


METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK


DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.


7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE


BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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