CE/EE270 Introduction to Digital System Design

Chapter 5
Synchronous Sequential Logic

Part a
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Sequential Circuits
 Asynchronous

Inputs Outputs
Combinational
Circuit
Memory
Elements
 Synchronous

Inputs Outputs
Combinational
Circuit
Flip-flops
Clock
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Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0

R
0 0
Q

S Q
0 1

Initial Value
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Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

R
0 1
Q

S Q
0 0
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Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0

R
1 0
Q

S Q
0 1
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Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0

R
1 1 0 1 1 0 1 Q=0
Q

S Q
0 0
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Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 0 0 1 1 0 1
Q=0

Q 1 0 0 1 0 Q=1

S Q
1 1
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Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 1 0 1 1 0 1
Q=0

Q 1 0 0 1 0 Q=1

1 0 1 1 0 Q=1

S Q
1 0
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Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 0 0 1 1 0 1
Q=0

Q 1 0 0 1 0 Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

S Q
1 10
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Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 10 0 1 1 0 1
Q=0

Q 1 0 0 1 0 Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’

S Q
1 0
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Latches
 SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S’ R’ Q
Q Invalid
0 0 Q=Q’=1
0 1 1 Set
Q 1 0 0 Reset
R Q0 No change
1 1
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Controlled Latches
 SR Latch with Control Input

R R S S
Q Q
C C
S Q R Q
S R

C S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q=Q’ Invalid
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Controlled Latches
 D Latch (D = Data) Timing Diagram

S
C
D
Q
C D
R Q
Q

t
C D Q
Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set
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Flip-Flops
 Controlled latches are level-triggered

C
 Flip-Flops are edge-triggered

CLK Positive Edge

CLK Negative Edge

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 Master-Slave D

D D Q D Q Q
D Latch D Latch
(Master) (Slave)
C C
Master Slave

CLK
CLK

D
Looks like it is negative
edge-triggered QMaster

QSlave
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Flip-Flops
 JK Flip-Flop

J
D Q Q
K
CLK Q Q

J Q
D = JQ’ + K’Q
K Q
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Flip-Flop Characteristic Equations

 Analysis / Derivation

J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 Reset
0 1 1
K Q
1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1
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Flip-Flop Characteristic Equations

 Analysis / Derivation

J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
K Q
1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1
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Flip-Flop Characteristic Equations

 Analysis / Derivation

J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
K Q
1 0 0 1 Set
1 0 1 1
1 1 0 Toggle
1 1 1
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Flip-Flop Characteristic Equations

 Analysis / Derivation

J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
K Q
1 0 0 1 Set
1 0 1 1
1 1 0 1 Toggle
1 1 1 0
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Flip-Flop Characteristic Equations

 Analysis / Derivation

J K Q(t) Q(t+1)
0 0 0 0
J Q 0 0 1 1 K
0 1 0 0 0 1 0 0
0 1 1 0 J 1 1 0 1
K Q Q
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Q(t+1) = JQ’ + K’Q

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Flip-Flop Characteristic Equations

D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)

T Q T Q(t+1)
0 Q(t) Q(t+1) = T  Q
Q
1 Q’(t)
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Flip-Flop Characteristic Tables

D Q D Q(t+1)
0 0 Reset
Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q’(t) Toggle

T Q T Q(t+1)
0 Q(t) No change
Q
1 Q’(t) Toggle
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Flip-Flops
 Edge-Triggered D Flip-Flop
D Q

Q Positive Edge
CLK

Q
D Q

D Negative Edge
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Flip-Flops
 T Flip-Flop

T J Q T D Q

Q
K Q

T Q
D = JQ’ + K’Q
D = TQ’ + T’Q = T  Q Q
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Flip-Flops with Direct Inputs

 Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 x x 0
Q 1 0 ↑ 0
R 1 1 ↑ 1
Reset
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Flip-Flops with Direct Inputs

 Asynchronous Preset and Clear

Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0
0 1 x x 1
Q 1 1 0 ↑ 0
CLR 1 1 1 ↑ 1
Reset
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Analysis of Clocked Sequential Circuits

 The State
 State = Values of all Flip-Flops

Example
x
AB=00 D Q A

D Q B

CLK Q

y
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Analysis of Clocked Sequential Circuits

 State Equations
x
A
A(t+1) = DA D Q

= A(t) x(t)+B(t) x(t) Q

=Ax+Bx
D Q B
B(t+1) = DB
CLK Q
= A’(t) x(t)
y
= A’ x
y(t) = [A(t)+ B(t)] x’(t)
= (A + B) x’
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Analysis of Clocked Sequential Circuits

 State Table (Transition Table)
x
Present Next D Q A
Input Output
State State
Q
A B x A B y
0 0 0 0 0 0 B
D Q
0 0 1 0 1 0
CLK Q
0 1 0 0 0 1
0 1 1 1 1 0 y

1 0 0 0 0 1
1 0 1 1 0 0
A(t+1) = A x + B x
1 1 0 0 0 1
1 1 1 1 0 0 B(t+1) = A’ x
y(t) = (A + B) x’
t t+1 t
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Analysis of Clocked Sequential Circuits

 State Table (Transition Table)
x
Present Next State Output D Q A

State x=0 x=1 x=0 x=1 Q

A B A B A B y y
0 0 0 0 0 1 0 0 D Q B
0 1 0 0 1 1 1 0
CLK Q
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0 y

t t+1 t A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
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Analysis of Clocked Sequential
Circuits
 State Diagram Present Next State Output
State x=0 x=1 x=0 x=1
A B A B A B y y
AB input/output
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
0/0 1/0
1 0 0 0 1 0 1 0
0/1 1 1 0 0 1 0 1 0
00 10
x
D Q A
0/1
Q
1/0 0/1 1/0
D Q B

CLK Q
01 11
y
1/0
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Analysis of Clocked Sequential Circuits

 D Flip-Flops
Example:
x D Q A
Present Next
y
Input
State State CLK Q
A x y A
0 0 0 0
0 0 1 1 A(t+1) = DA = A  x  y
0 1 0 1
0 1 1 0
1 0 0 1 01,10
1 0 1 0
00,11 0 1 00,11
1 1 0 0
1 1 1 1 01,10
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Analysis of Clocked Sequential Circuits

 JK Flip-Flops J Q A

Example: x K Q

Present Next Flip-Flop

I/P J Q B
State State Inputs
A B x A B JA KA JB KB K Q

0 0 0 0 1 0 0 1 0 CLK
0 0 0 0 0 1
0 0 1 JA = B KA = B x’
0 1 0 1 1 1 1 1 0
JB = x’ KB = A  x
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1 A(t+1) = JA Q’A + K’A QA
1 0 1 1 0 0 0 0 0 = A’B + AB’ + Ax
1 1 0 0 0 1 1 1 1 B(t+1) = JB Q’B + K’B QB
1 1 1 1 1 1 0 0 0 = B’x’ + ABx + A’Bx’
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Analysis of Clocked Sequential Circuits

 JK Flip-Flops J Q A

Example: x K Q

Present Next Flip-Flop J Q B

I/P
State State Inputs
A B x A B JA KA JB KB K Q

0 0 0 0 1 0 0 1 0 CLK

0 0 1 0 0 0 0 0 1 1 0 1
0 1 0 1 1 1 1 1 0 00 11
0 1 1 1 0 1 0 0 1
0
1 0 0 1 1 0 0 1 1 0 0
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1 01 10
1 0 0 0
1
1 1 1 1 1 1
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Analysis of Clocked Sequential Circuits

x A
 T Flip-Flops T Q y

Example: R Q

Present Next F.F

I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0
TA = B x TB = x
0 1 1 1 0 1 1 0
y =AB
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0
A(t+1) = TA Q’A + T’A QA
= AB’ + Ax’ + A’Bx
1 1 0 1 1 0 0 1
1 1
B(t+1) = TB Q’B + T’B QB
1 1 1 0 0 1
=xB
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Analysis of Clocked Sequential Circuits

x A
 T Flip-Flops T Q y

Example: R Q

Present Next F.F

I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0 0/0 0/0
0 1 1 1 0 1 1 0 00 1/0 01
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0 1/1 1/0
1 1 0 1 1 0 0 1 11 10
1 1
0/1 0/0
1 1 1 0 0 1 1/0