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 Nanotechnology

Nanotechnology 29 (2018) 134003 (8pp) https://doi.org/10.1088/1361-6528/aaaacb

NRAM: a disruptive carbon-nanotube

resistance-change memory
D C Gilmer1,4 , T Rueckes2 and L Cleveland3
1
Nantero, Inc., Austin, TX, United States of America
2
Nantero, Inc., Woburn, MA, United States of America
3
Nantero, Inc., Sunnyvale, CA, United States of America

E-mail: David.Gilmer@Nantero.com

Received 4 December 2017, revised 16 January 2018

Accepted for publication 26 January 2018
Published 13 February 2018

Abstract
Advanced memory technology based on carbon nanotubes (CNTs) (NRAM) possesses desired
properties for implementation in a host of integrated systems due to demonstrated advantages of its
operation including high speed (nanotubes can switch state in picoseconds), high endurance (over a
trillion), and low power (with essential zero standby power). The applicable integrated systems for
NRAM have markets that will see compound annual growth rates (CAGR) of over 62% between
2018 and 2023, with an embedded systems CAGR of 115% in 2018–2023 (http://bccresearch.com/
pressroom/smc/bcc-research-predicts:-nram-(finally)-to-revolutionize-computer-memory). These
opportunities are helping drive the realization of a shift from silicon-based to carbon-based (NRAM)
memories. NRAM is a memory cell made up of an interlocking matrix of CNTs, either touching or
slightly separated, leading to low or higher resistance states respectively. The small movement of
atoms, as opposed to moving electrons for traditional silicon-based memories, renders NRAM with a
more robust endurance and high temperature retention/operation which, along with high speed/low
power, is expected to blossom in this memory technology to be a disruptive replacement for the
current status quo of DRAM (dynamic RAM), SRAM (static RAM), and NAND flash memories.
Keywords: nanotubes, CNT, RRAM, NRAM

(Some figures may appear in colour only in the online journal)

1. Introduction FETs to store a bit of information, dynamic random access

The future of Moore’s law [1, 2] has been an engaging debate
topic continually reduced to moot points for more than a decade.
However, as the difficulty for continued shrinking of the relative
electronic components has dramatically increased, the end to this
debate, and Moore’s law, may actually have occurred with the
focus rapidly gravitating toward the many emerging technolo-
gies that have promise for improved performance and more cost-
effective integration of large amounts of memory with logic [3].
The increasing difficulty for improved performance with further
miniaturization of established memory devices is an opportunity
for the emerging memory technology based on carbon nano-
tubes (CNTs) (NRAM®) [4]. Regarding scalability and device
footprints for the current status quo; static random-access
memory (SRAM) (is fast but takes up a lot of area) uses six
4
Author to whom any correspondence should be addressed.
memory (DRAM) (is slower but higher density so less area) uses
one FET and one capacitor to store a bit, and NAND flash
memory (with very dense and slow memory that stores data
when the power is off) uses one FET [3]. In contrast, an NRAM
storage element is integrated in the back of the line (BEOL) and
depending on applications can be in a 1 transistor-1 resistor
(1T1R) or a cross-point configuration with optional 3D scal-
ability through multiple NRAM layers with the minimum
dimension for the CNT element or ‘puck’ (see figure 1) deter-
mined by the width of the underlying via (bottom electrode)
defined by the process node photolithographic/alignment toler-
ances. Beyond competitive scaling, NRAM has demonstrated
performance advantages against the incumbents, as well as with
its peers in the emerging memory technology space, by showing
remarkable device characteristics including low 20 μA program
current at low voltage, trillion+ (>1012) program endurance,
fast <5 ns program time, excellent retention (?10 yrs @85C),

0957-4484/18/134003+08$33.00 1 © 2018 IOP Publishing Ltd Printed in the UK

Nanotechnology 29 (2018) 134003
Figure 1. Schematic (and SEM) of an NRAM cell.
and multilevel cell potential [5–7]. As the physical operation
understanding of the CNT resistance switching continues to
improve, NRAM device performance advantages are expected
increase even further.
2. What is NRAM®
2.1. NRAM= CNTs for resistance switching memory
2.1.1. Carbon nanotubes. CNTs can be understood by
beginning with graphene’s atomic structure of repeating units
of hexagonal rings, which have sp2 bonding structure, and the
CNT is formed by rolling up a graphene sheet into a tube. Thus,
CNTs are seamless cylinders of one or more layers of graphene
(denoted single-wall, SWNT, or multiwall, MWNT), with open
or closed ends [8, 9]. The diameters of SWNTs and MWNTs are
typically 0.9–2 nm and 5–20 nm respectively and CNT lengths
can range from ∼10 nm to several hundred microns. With the
many unique properties of CNTs (strength (Youngs Modulus
∼TPa), thermal stability (to ∼2700 °C in vacuum), current
density (∼109 A cm−2), thermal conductivity (>2× that of
diamond)), it is tempting to just think of them as discrete well-
defined entities, and that has often been the case with the
‘bottom-up’ type assembly researched for large scale CNT
integration at the nanoscale. However, after over 20 years of
intense research there is still no method available for precision
assembly of CNTs at nanometer pitch and/or with repeatability
required for today’s production devices (billions of identical
devices across a 200 or 300 mm wafer). The breakthrough
toward feasible implementation in production that NRAM
utilizes, is the use of a random CNT fabric, with no
orientation or alignment requirements, which can be spun onto
wafers using standard coating tools found in all semiconductor
manufacturing facilities.
2.1.2. Converting raw CNT materials to semiconductor-grade
formulation. Although CNTs having all carbons bonded in a
hexagonal lattice except at their ends may be called ‘perfect’,
mass produced CNTs introduce pentagons, heptagons, and other
imperfections in the sidewalls that generally may degrade or
change the CNTs properties. In addition, the formed CNT raw
2
D C Gilmer et al
Figure 2. SEM image of raw CNT materials which are a mixture of
CNTs, metal catalysts, and amorphous carbon.
materials are not discrete molecular entities, but are a mixture of
CNTs, metal catalysts, and amorphous carbons (figure 2).
There may be a perception that these raw CNT materials
are hard to control, in part due to the materials properties
depending on the CNT manufacturing details (e.g., catalyst
variations, reactor design and conditions, etc), and these all
impact fundamentally different approaches to refining a final
CNT product. The CNT refinement process used for NRAM
was to develop a CNT based formulation, which may be spun
onto a substrate, much like a photo resist [10, 11]. However,
CNT formulations differ from photo resist and other sacrificial
materials in that they remain on the substrate and are used
as a primary functioning component of the intended device.
Thus, potential contaminate sources such as trace-metals and
particulates must be tightly controlled to ‘semiconductor grade
quality’ before deposition. The thin-film structure of deposited
CNT formulations is also markedly different than the dense,
homogenous photo-resist films. Experience gained over many
years with developing CNT formulation has shown that
numerous subtle details make the difference between success
and failure, and that reproducible processes can be created
and controlled.
The solution processing model for NRAM CNT
materials can be subdivided into five main components:
raw materials selection and acid functionalization, metals
removal, amorphous carbon removal, and defect removal.
Nanotechnology 29 (2018) 134003
Figure 3. Raw CNT materials are a mixture of CNTs, metal catalysts, and amorphous carbon which after careful refinement and subsequent
spin-coating on a wafer become a uniform CNT fabric (with randomly orientated CNTs) which can be used as a resistance change material
for memory devices.
Final formulations are then submitted for quality control (QC)
[10] (see figure 3).
In general, the raw material CNTs, from various
manufacturers who have controlled processes for CNT
production, are acid functionalization to promote CNT
colloidal stability while also liberating catalyst metal and
amorphous-carbon which are removed in subsequent proces-
sing steps. Before submitting to the QC process, solutions
undergo an intense particulate removal process. The CNT
formulation’s wet chemistry is defined by four primary
metrics: pH, [NO-], CNT concentration, and trace metals.
The pH, ionic strength, and colloid concentration are the
governing parameters in colloidal science, and our formula-
tions are optimized on these factors. Once in QC, the
formulation’s wet chemical profile is examined along with the
coat quality parameters and the passing solutions are then
packaged and sent for device processing. In addition to the
solution phase examinations, CNT coated wafers from each
CNT solution lot are characterized for sheet resistance, film
adhesion and the frequency of particulate defects found
within the film. In addition to trace metals reduction, the
suppression of particulate defects is a critical prerequisite for
high volume semiconductor manufacturing yield enhance-
ments. With careful CNT processing parameter identification,
suitable measurement development, and watchful data
collection and analysis, CNT solution formulations for
coating CNT fabrics onto silicon wafers can be prepared,
improved, and controlled to semiconductor-grade acceptable
purity at the multi-liter scale, like traditional thin film
precursors [10].
2.1.3. The CNT memory cell. A CNT memory cell (see
figure 1) consists of ‘semiconductor fab-friendly’ TiN top and
3
D C Gilmer et al
bottom electrodes sandwiching a ∼30 nm thick layer of a
mostly conductive CNT fabric. The CNTs are spin coated,
analogous to photoresist coating, onto the wafer and bottom
electrode and then the top electrode is deposited. Then
standard lithographic pattern and etch are used to define the
cell or ‘puck’ and also to complete isolation/backend
processing. Thus, NRAM technology is fully compatible
with current CMOS fabrication processing and semiconductor
fabs. By applying an electrical bias across the CNT memory
cell, an electrical induced resistance change can occur
resulting from a movement of atoms in the CNT cell, where
both mechanical and electrical CNT properties are of interest.
The output from the CNT memory cells has been fed back to
the CNT selection and refinement process in a loop ‘linking
the process’ allowing for continued CNT solution refinement
and process integration improvements resulting in the current
state of the art NRAM performance (see figure 4).
2.1.4. CNT mechanical properties. The CNT fabric spun
onto a wafer is a quasi-elastic, porous fiber of CNTs. The
CNTs are bound to each other in disordered network of points
and lines with van der Waals (vdW) forces. The movement
and subsequent rearrangement-contact of this network of
CNTs leads to either high resistance (∼1 MΩ; Reset), or low
resistance (∼100 kΩ; Set) states, resulting in CNT-based
resistance switching (NRAM®) as shown in a simplistic
rendering in figure 5.
2.1.5. CNT electrical properties and switching. Electron
movement through the CNT fabric can take different
mechanisms. It can be inter-CNT transport via tunnel coupling
of CNTs bound by vdW, or it can be more like a tunnel junction
often described by a parallel resistor and capacitor (leaky
Nanotechnology 29 (2018) 134003 D C Gilmer et al

Figure 4. The output from the CNT memory cells has been fed back to the CNT selection and refinement process in a loop ‘linking the
process’ allowing for continued CNT solution refinement and process integration improvements resulting in the current state of the art
NRAM performance.

Figure 5. RESET (ON→OFF): CNT–CNT are not in physical

contact=high resistance. SET (OFF→ON): CNT are in physical
contact=low resistance. *SET is an electrostatic operation while
RESET is current driven operation.

capacitor), and there can be transport within CNTs with a

combination of ballistic and sequential transport. The DC-IV
measurements displayed in figure 6 show that SET behavior
(top graph) is gradual and it is observed in performing the
measurement that up to some voltage, it is reversible. The
RESET displayed in the lower panel of figure 6 in contrast to
set, occurs suddenly. The charts in figures 7 and 8 detail a model
to explain this observation. For the SET operation (figure 7),
application of positive bias to the bottom electrode causes a
capacitive Coulomb attraction across switching gaps in the CNT
fabric where the CNT fabric material and individual CNT
elasticity allow the fabric to stretch and close some of the gaps.
This gap closure can continue reversibly with applied voltage
until it is within the vdW binding distance where the CNTs then
become ‘trapped’ together in a vdW well. For a RESET
operation (figure 8), the application of a positive bias pulse from
the top electrode initiates feedback between CNT vibrational
modes in a vdW well and Coulomb attraction. For sufficiently
high voltage the bound CNTs can become free of their vdW
‘trap’ and relax to an elastic minimum.
The CNT resistance in the untested Virgin state will
typically be relatively high, but also variable since the CNT
Figure 6. Cascade (abrupt) behavior of RESET with applied-voltage
as opposed to the gradual action of SET with applied-voltage (device
sizes are 0.36 mm×0.36 mm top electrode CDs, and bottom
electrode area of 0.015 mm2).
connections are purely random. Through the application of a
first reset bias, gaps or voids are introduced in the CNT fabric
nearer the bottom electrode which can subsequently allow for
small deflections of some of the CNTs to move between the
set and reset states. The strategic placement of different CNT
types (size, resistance, dopants, etc) in the coated fabric help
dictate the choice for reset/set bipolar biasing and this
asymmetric CNT fabric engineering, along with nature of the
CNT bonding to the lower electrode, promote lower voltages/
currents for a bipolar mode of operation. Although the set and
reset process is aided by passing a current (moving electrons)
across the CNT fabric, it is the ability of the CNT fabric to
allow for molecular movement from the CNTs that result in
the differentiable and repeatable resistance states constituting

4
Nanotechnology 29 (2018) 134003
Figure 7. Set operation dynamics.
Figure 8. Reset operation dynamics.
a resistance memory device. In addition, it can be postulated
that the reason for the good uniformity/repeatability of the
CNT electromechanical switch is due to the CNTs movement
being very small, where the ‘moving parts’ of the CNTs
are confined between two ‘wells’, the vdW well and an
electrostatic minimum, which have boundaries influenced by
the initial reset biasing, and the CNT fabric intertwining and
cross-linking that essentially immobilize many parts of the
‘long’ CNTs (compared to contact points) leaving limited
gaps or voids for free moving parts in confined areas.
3. Potential of NRAM (CNT memory)
3.1. Time to market for emerging technologies takes decades
In general, research on CNTs has been underway well before
Moore’s law was drafted [9, 12], but demonstrated use of
CNTs for the active element in electronic devices, such as
5
D C Gilmer et al
field-effect transistors and resistance change switching has
been underway for only a couple decades [13–15], with
development work of the current NRAM cell ongoing for less
than a decade. Although incremental changes, such as for
Moore’s law scaling, have taken ∼18 months (and now take
years) [1]; the introduction of new technologies to market
more often has taken decades or more. High-K dielectrics
were under research and development for over a decade
before their induction into products near 2007 [16]. Ferro-
electric RAM, also took decades of research before Fujitsu
was successful in bringing it to market in the late 1990s [17].
Phase-change had been studied for near half-century (even by
Gordon Moore) before recently finding niche markets [18]
and magnetic-RAM (MRAM) application, discovered near
1989, took almost two decades to make it to market [19]. So,
relatively speaking, NRAM® is young as reports of its
introduction toward products start to appear [20]. As a new
emerging technology, the research and development path for
NRAM has been sprinkled with seeds of continued learning
and advancements to improved CNT solution refinement,
improved performance of individual and isolated cells, and
also improvements in integration and multi-arrays that are
all appropriate for manufacturability in modern electronic
products which are now on a path to bloom with NRAM®
technology inside.
3.2. NRAM® device performance
One advantage for NRAM technology, is low power opera-
tion (with essentially zero standby power). The device size in
the arrays for electrical data shown in graphs below (and
figure 1) is 0.36 mm×0.36 mm for top electrode CDs, with a
bottom electrode area of 0.015 mm2. In figure 9 the DC-IV
low write voltage and low currents for devices along the bit
line (few kbits) of the array indicate the low power potential
for NRAM.
With resistive-RAM (RRAM) technologies such as
NRAM, the small movement of atoms, as opposed to moving
electrons for traditional memories, renders NRAM with a
more robust high temperature retention/operation as shown in
figure 10 for devices along a bit-line (few kbits). The dis-
played 24 h 150 °C stable retention and operation window at
1 × 106 cycles leads to an extrapolated >5000 years at 85 °C.
In addition, the ON/OFF distribution observed after 24 h/
150 °C bake—measured up to 48 h/150 °C indicates no
change between the 24 and 48 h bake at 150 °C.
Over 10 year retention for 32 kbit/die NRAM at 300 °C
(3σ) is demonstrated in figure 11 with extracted activation
energies of 5.4 eV (median) and 4.5 eV (3σ) indicating robust
operation can be expected from NRAM in a variety of
environmental conditions [21].
Read and write distributions are also shown to be stable
from low to high temperatures with no change from −25 to
85 °C for a 200 ms read stress per bit/cycle (see figure 12).
The bit error rate has been reduced to 0.76 ppm average
(all errors are hard defects and repairable and relatively cheap
to correct with redundancy in RRAM technologies such
as NRAM).
Nanotechnology 29 (2018) 134003 D C Gilmer et al

Figure 9. CNT write current DC-IV. Median set current ∼14 mA and median reset current ∼7 mA.

Figure 10. NRAM array bit-line data for 150 °C retention (few kbits) indicates stable window at 1 × 106 cycles (>5000 years at 85 °C).

Fast switching along with high endurance is a pre-
requisite for any emerging memory trying to replace the
current incumbents. In figure 13 below, NRAM array fast
switching performance at 5 or 40 ns look similar in write or
bit-line distributions after write. In addition, figure 14 shows
bit-line distribution to be stable for high endurance perfor-
mance cycles for the 1T1R read Vref sweep distribution
across cycling of 4 × 109 (without any error correction
control).
NRAM single cell endurance has also recently demon-
strated to a trillion+ cycles [22] so the multi-cell Mbit array
data of multiple billions of cycles endurance already, is
expected to improve even more.
4. Summary
Advanced NRAM® memory technology, based on CNTs for
resistive switching, can be integrated into memory devices on
large (300 mm+) or small wafers in standard backend CMOS
processing as a random fabric (spun-coat) without the need
for any special alignment of the CNTs. The NRAM memory

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Nanotechnology 29 (2018) 134003 D C Gilmer et al

Figure 11. Retention data for 85–300 °C on 32 kbit/die at each temperature. T0=before bake, T48=48 h bake, T168=168 h bake.
Retention data indicates >300 years at 300 °C (3σ). Extracted activation energies are 5.4 eV (median) and 4.5 eV (3σ) [21]. Reproduced with
permission from [21].

Figure 12. Read and write distributions do not change at high and low temperature along the bit line (few kbits). Data for 200 ms read stress
per bit/cycle. Blank area between the set (green) and reset (red) distributions represents the read Vref margin (window).

devices are shown to possess desired properties for imple-
mentation in a host of integrated systems due to demonstrated
advantages of operation including high speed (single cell
nanotubes can switch state in picoseconds and large arrays
switch in nanoseconds [15]), high endurance (over a trillion
for single cell operation, and billions of endurance cycles for
large arrays), and low power (array cell switching operations
at low voltage with <25 mA currents in ns time frame, and
essential zero standby power).
The impressive potential demonstrated by NRAM device
operational characteristics along with a competitive scaling
render NRAM technology to be faster and denser than
DRAM while consuming substantially less power compared
to DRAM or flash. Thus, there is considerable momentum to
continue research and development with NRAM to allow not
only its disruptive replacement of these technologies soon,
but also to replace SRAM and ultimately hard disk storage,
and for NRAM to become a truly universal memory.

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Nanotechnology 29 (2018) 134003
Figure 13. The 1T1R read sweep distribution for 5 versus 40 ns
pulse width (without ECC). Switching pulse for 5 or 40 ns look
similar in write or bit distributions after write.
Figure 14. The 1T1R read Vref sweep distribution across cycling
(w/o ECC) (1–4) × 109 cycles. All Ones (set), and all Zeroes (reset)
data pattern; bit distribution stable across cycling of 4 × 109 cycles
and looks good.
Acknowledgments
Thank you to the CNT-chemistry/synthesis teams, the Nan-
tero process integration teams, and the Nantero e-test teams.
ORCID iDs
D C Gilmer https://orcid.org/0000-0001-6148-8079
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