NRAM Status and Prospects
D.C. Gilmer, T. Rueckes, L. Cleveland, D. Viviani
Nantero, Inc.
Austin, TX / Sunnyvale, CA / Woburn, MA, USA
Abstract—Advanced memory technology based on carbon
nanotubes (NRAM) has been shown to possess desired properties
for implementation in a host of integrated systems due to
demonstrated advantages of its operation including high speed
(Nanotubes can switch state in picoseconds), high endurance
(over a trillion), and low power (with essential zero standby
power). The applicable integrated systems have markets that will
see compound annual growth rates (CAGR) of over 62% between
2018 and 2023, with an embedded systems CAGR of 115% in
2018 to 2023 [1]. These opportunities for NRAM technology are
helping drive the realization of a shift from silicon to a carbon-
based memory. NRAM is made up of an interlocking matrix of
carbon nanotubes, either touching or slightly separated, leading
to low or higher resistance states respectively. The small
movement of atoms, as opposed to electrons for traditional
memories, renders NRAM with a more robust endurance and
high temperature retention/operation which, along with high
speed/low power, is expected to blossom in this memory
technology to be a disruptive replacement for the current status
quo of DRAM (dynamic RAM), SRAM (static RAM), and NAND
flash memories.
Keywords—NRAM; Carbon Nanotubes; Emerging Memory;
RRAM; ReRAM
I. INTRODUCTION
The future of Moore’s law [2,3] has been an engaging
debate topic continually reduced to moot points for decades.
However, as the difficulty for continually shrinking the relative
electronic components has dramatically increased, the end to
this debate, and Moore’s law, may actually have occurred with
the focus rapidly gravitating toward the many emerging
technologies that have promise for improved performance and
more cost-effective integration of large amounts of memory
with logic [4]. This increasing difficulty for improved
performance with further miniaturization of established
memory devices is an opportunity for the emerging memory
technology based on carbon nanotubes (NRAM®) [5].
Regarding scalability and device footprints for the current
status quo; Static random access memory (SRAM) [fast but
takes up a lot of area] uses six FETs to store a bit of
information, Dynamic random access memory (DRAM)
[slower but higher density so less area] uses one FET and one
capacitor to store a bit, and NAND flash memory [the very
dense and slow memory that stores data when the power is off]
uses one FET [4]. In contrast, the NRAM storage element is
integrated in the back of the line (BEOL) and depending on
applications can be in a 1 transistor-1resistor (1T1R) or cross-
point configuration with optional 3D scalability through
multiple NRAM layers with the minimum dimension for the
carbon nanotube (CNT) element or ‘puck’ (see Fig. 1)
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determined by the width of the underlying Via (bottom
electrode) defined by the process node photolithographic and
alignment tolerances. Beyond competitive scaling, NRAM has
demonstrated performance advantages against these
incumbents, as well as with its peers in the emerging memory
technology space, by showing remarkable characteristics
including low 20μA program current at low voltage, Trillion+
(>1012) program endurance, fast <5ns program time, excellent
retention (>>10 yrs @85C), and multilevel cell potential
[6,7,8]. As the physical understanding of the CNT resistance
switching continues to improve, NRAM device performance
advantages are expected to grow even larger.
Fig.1. Schematic (and SEM) of an NRAM cell
II. WHAT IS NRAM®
A. Carbon Nanotubes for Resistance Switching Memory
1) The CNT memory cell
A CNT memory cell, as shown in Fig. 1, consists of “Fab-
friendly” TiN top and bottom electrodes sandwiching a ~30 nm
thick layer of a mostly conductive CNT fabric. The CNTs are
spin coated, analogously to photoresist, onto the wafer and
bottom electrode and then the top electrode is deposited.
Essentially standard pattern and etch are used to define the cell
or ‘puck’ and also to complete isolation\backend processing.
Thus, NRAM technology is fully compatible with current
CMOS fabrication process and FABs. With an electrical
induced resistance change resulting from a movement of atoms
in the CNT cell, both mechanical and electrical CNT properties
are of interest.
2) CNT Mechanical properties
The CNT fabric spun onto a wafer is a quasi-elastic, porous
fiber of CNTs. The CNTs are bound to each other in disordered
network of points and lines with van der Waals (vdW) forces.
The movement and subsequent rearrangement-contact of this
network of CNTs leads to either high (~1 MΩ) resistance
(Reset), or low (~100 kΩ) resistance (Set) states, resulting in
CNT-based resistance switching (NRAM®). (See Fig. 2)
 3) CNT Electrical properties and switching
Electron movement can be inter-CNT transport via tunnel
coupling of CNTs bound by vdW. This is like a tunnel junction
often described by a parallel resistor and capacitor (leaky
capacitor). The transport within CNTs in a low resistance state
is a combination of ballistic and sequential transport. The DC-
IV measurements (Fig. 3) show that SET behavior (top graph)
is gradual and, up to some voltage reversible. The RESET
(lower panel Fig. 3), in contrast to set, occurs suddenly (in the
figure around V=1.1 V). The charts in Figs. 4 and 5 show the
model explaining this observation. For a SET operation (Fig.
4), application of bias to the bottom electrode causes capacitive
Coulomb attraction across switching gaps where the CNT
fabric material and individual CNT elasticity allow the fabric to
stretch and close the gap. This gap can continue to close
reversibly with applied voltage until it is within the van der
Waals binding distance where the CNTs then become ‘trapped’
together. For a RESET operation (Fig. 5), application of a
pulse from the top electrode initiates feedback between CNT Fig.4. Set operation dynamics
vibrational modes in a vdW well and Coulomb attraction. For
sufficiently high voltages the bound CNTs can become free of
their vdW ‘trap’ and relax to an elastic minimum. This process
is aided by noise from hot electrons and is therefore direction
dependent.

Fig. 2. RESET (ON  OFF): CNT-CNT are not in physical contact =

high resistance
SET (OFF  ON): CNT are in physical contact = low resistance Fig.5. Reset operation dynamics
*SET is an electrostatic operation while RESET is current driven
operation

III. POTENTIAL OF NRAM (CARBON NANOTUBE MEMORY)

A. Time to market for emerging technologies takes decades

Fig. 3. Cascade (abrupt) behavior of RESET with applied-Voltage as
opposed to the gradual action of SET with applied-Voltage.
In general, research on carbon nanotubes has been
underway well before Moore’s law was drafted, but
demonstrated use of CNTs for the active element in electronic
devices, such as field-effect transistors and resistance change
switching has been underway for only a couple decades [9,10,
11]. Although incremental changes, such as for Moore’s law
scaling, have taken ~18 months (and now take years) [2]; the
introduction of new technologies to market has taken decades
or more. High-K dielectrics were under research and
development for over a decade before their induction into
products near 2007 [12]. Ferro-electric RAM (FRAM), also
took decades of research before Fujitsu was successful in
bringing it to market in the late 1990’s [13]. Phase-change
(PCRAM) had been studied for near half-century (even by
Gordon Moore) before recently finding niche markets [14] and
magnetic-RAM (MRAM) application, discovered near 1989,
did not make it to market until the mid-2000’s [15]. So,
relatively speaking, NRAM® is young as reports of its

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introduction toward products begin to appear [16]. As with
near all new emerging technologies, the research and
development road for NRAM has been sprinkled with seeds of
continued learning and advancements to both improve
performance of individual or isolated cells, and also to improve
integration and multi-arrays that are appropriate for
manufacturability in modern electronic products and which are
now on a path to bloom with NRAM® technology inside.
B. NRAM® Device Performance
One advantage for NRAM technology, is low power
operation (and essentially zero standby power). In Fig. 6 the
write voltage & current are demonstrated to be ~1V & <25uA
respectively for devices along the bit line (few Kbits) of the
array. Note, for 1T1R configuration this allows for use of the
lower voltage core transistors.
Fig.6. CNT write current DC-IV. Median Set current ~14uA and median reset
current ~7uA.
With resistive-RAM (RRAM) technologies such as
NRAM, the small movement of atoms, as opposed to only
electrons for traditional memories, renders NRAM with a more
robust high temperature retention/operation as shown in Fig. 7
for devices along a bit-line (few Kbits). The 24 hour 150C
stable retention and operation window at 1E6 cycles leads to an
extrapolated >5000 years at 85C. The ON/OFF distribution
observed after 24h/150C bake – measured up to 48h/150C
indicates no change between the 24hrs and 48hrs bake at 150C.
Fig.7. NRAM array bit-line data for 150C retention (few kbits) indicates
stable window at 1E6 cycles (>5000 years at 85C)
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Over 10year retention for 32kbit/die NRAM at 300C (3σ)
is demonstrated in Fig. 8 with extracted activation energies of
5.4eV (median) and 4.5eV (3σ) indicating robust operation is
expected from NRAM in a variety of environmental conditions
[17].
Read and write distributions are also shown to be stable at
high (and low) temperature with no change from -25C to 85C
for a 200ms read stress per bit / cycle (see Fig. 9). The Bit
error rate (all errors are hard defects and repairable) has been
reduced to 0.76 ppm average (relatively cheap to correct with
redundancy in resistive-RAM (RRAM) technologies such as
NRAM).
Fig. 8. Retention data for 85 to 300C on 32kbit/die at each temperature.
T0=before bake, T48=48 hour bake, T168=168 hour bake. Retention
data indicates >300 years at 300C (3σ). Extracted activation energies are
5.4eV (median) and 4.5eV (3 σ) [17].
Read & write at -25C Read & write at 25C Read & write at 85C
Fig. 9. Read and write distributions do not change at high and low
temperature along the bit line (few kbits). Data for 200ms read stress per
bit / cycle. Blank area between the set (green) and reset (red) distributions
represents the read Vref margin (window).
Fast switching with high endurance is a requirement for any
emerging memory trying to replace the current incumbents. In
Fig. 10 below, NRAM array switching performance at 5ns or
40ns look similar in write or bit-line distributions after write.
In addition, Fig. 11 shows bit-line distribution to be stable for
high endurance performance cycles for the 1T1R read Vref
sweep distribution across cycling of 4e9 (w/o ECC).
NRAM single cell endurance has also recently demonstrated
to a trillion+ cycles (see Fig. 12) [18] so the multi-cell MBit
array data, at multiple billions of cycles endurance already, is
expected to improve even more.

Fig.10. The 1T1R Read Sweep Distribution for 5ns vs 40ns pulse width
(without ECC). Switching pulse for 5ns or 40ns look similar in write or
bit distributions after write.
Fig.11. The 1T1R Read Vref Sweep Distribution Across Cycling (w/o
ECC) 1-4e9 cycles. All Ones (set) , and all Zeroes (reset) data pattern; Bit
distribution stable across cycling of 4e9 cycles and looks good.
Fig.12. Single cell endurance data showing trillions endurance cycles
IV. SUMMARY
Advanced memory technology based on carbon nanotubes
(NRAM®) has been shown to possess desired properties for
implementation in a host of integrated systems due to
demonstrated advantages of its operation including high speed
(single cell Nanotubes can switch state in picoseconds and
large arrays switch in nanoseconds [11]), high endurance (over
a trillion for single cell operation, and billions of endurance
cycles for large arrays), and low power (Array cell switching
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operations at ~1V with <25uA currents in ns time frame, and
essential zero standby power).
The impressive potential demonstrated by the NRAM
operation characteristics along with its competitive scaling
render NRAM technology to be faster and denser than DRAM
while consuming substantially less power compared to DRAM
or flash. Thus, there is considerable momentum to continue
NRAM research and development to allow not only its
disruptive replacement of these technologies soon, but also to
replace SRAM and ultimately hard disk storage, for NRAM to
become a truly universal memory.
ACKNOWLEDGMENT
“Thank you to the CNT-Chemistry/synthesis teams, the
Nantero process integration teams, and the Nantero e-test
teams”.
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