A 3D Stackable Carbon Nanotube-based Nonvolatile

Memory (NRAM)
Sohrab Kianian, Glen Rosendale, Monte Manning, Darlene Hamilton, X. M. Henry Huang, Karl Robinson, Young
Weon Kim, Thomas Rueckes
Nantero, Inc.
25D Olympia Ave.
Woburn, MA 01801
glen@nantero.com

Abstract—A 4Mbit nonvolatile memory with a Carbon

Nanotube (CNT) storage element has been manufactured in a
0.25 µm CMOS process at a production fab. The CNT storage
element is integrated in BEOL, requires minimal additional
processing steps, and only a single additional mask. The memory
can be RESET in 50 nanoseconds and SET in 500 nanoseconds.
Demonstrated read access time of the development vehicle is 50
nanoseconds. Write endurance is in excess of 10,000 cycles, and
robust data retention has been demonstrated. The CNT storage
element is scalable to <5 nm, and voltage and current
consumption during write operations are low. As intrinsic
NRAM SET & RESET times are < 1 nanosecond, improvements
in performance are anticipated.

I. INTRODUCTION
The world’s first publicly disclosed Nanotube RAM
(NRAM) product is described. This memory device is
fabricated in 0.25 µm CMOS, and the Carbon Nanotube
(CNT) memory element is integrated in the Back End of Line
(BEOL) portion of the process1. NOR architecture is chosen
over NAND to take greater advantage of higher NRAM
performance, although NRAM is suitable for NAND as well
as NOR. The use of a 0.25 µm foundry was strictly for cost
reasons.
The memory test chip is organized as a 4Mb×1, and the
target application is nonvolatile storage. The CNT memory
element is a 2-terminal variable resistance device, and is
selected with a single NMOS transistor. Device performance
shows clear advantages compared to Flash memory.
Previous implementations of carbon related semiconductor
devices have focused on replacing the silicon substrate (e.g.,
graphene); or have emphasized novel devices manually
assembled in small quantity, in a laboratory environment.
These implementations suffer from either the need to overhaul
a significant portion of semiconductor manufacturing
capability (e.g. elimination or modification of silicon wafers)
or do not support manufacturability. The NRAM described
here follows a novel approach, emphasizing the use of existing
semiconductor manufacturing equipment and processes while
achieving the gains of incorporating NRAM as the memory
1
While numerous implementations are possible, in this implementation
(4Mb×1) the CNT switch is integrated between Metal 3 and Metal 4 and the
access device consists of an NMOS transistor
Figure 1. AFM of patterned CNT on silicon
storage element of an NVM. As a result it is not necessary
to significantly change the manufacturing flow. Most
significantly NRAM relies on utilizing an IC-grade (i.e. ppb
level purity) suspended CNT solution, deposited and patterned
via standard fab tools and processes resulting in a consistent
film of controlled quality, uniformity, resistance and thickness
of CNT. The CNT film formation process is thus key to a
controlled manufacturability of NRAM and its integration into
base-line process thereby. Fig. 1 is an AFM image of
patterned and etched carbon nanotube on a silicon surface
overlaying W vias.
II. DEVICE AND OPERATION
Fig. 2 is a diagram of the NRAM bitcell, where the 2–
terminal CNT is represented as a switch. Terminals WL
(Wordline), BL (Bitline), and SL (Sourceline), respectively,
connect the bitcell within the array. The sense of these terms is
conventional, with the exception that the Sourceline terminal
SL is a common return line for the CNT switch on the
opposite side from its connection to the select transistor, rather
than the connection to an MOS source junction. The NMOS
transistor acts as the selector for the CNT data storage element
in this design, although many active elements (diode, BJT,
etc) could serve equally as well. Fig. 3 is a chip micro-
photograph of the 4Mb characterization vehicle.

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 BL SL
WL
Figure 2. NRAM Bitcell
Figure 3. 4Mb NRAM microphotograph
A. Definition of SET and RESET States
The CNT bitcell as described in this paper has 2 states,
SET (logical ‘1’) and RESET (logical ‘0’); although multiple
levels are possible (the CNT element can be programmed to a
very wide range of resistances). The circuits described in this
paper consider a SET cell to have a resistance in the KΩ
range, and a RESET cell to have a resistance in the MΩ range.
B. Write Operation
A system of CNT film produces multiple CNT junctions
(i.e., one CNT touching another) which provide for a
conductive path. These junctions have nano–size surface area
and require very small currents to experience Joule heating. A
CNT junction (CNT–CNT space <3Å) requires energy of <~1
picojoule to separate (>10Å) and form a non-conducting path
(Fig. 4).
Figure 4. Relative energy states of CNT vs. distance
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ELECTRODE ELECTRODE
ELECTRODE ELECTRODE
RESET STATE SET STATE
Figure 5. Electrical equivalent of CNT network in RESET and SET states.
Resistors represent intrinsic CNT resistance, and circled switches represent
‘junctions’ between adjacent touching nanotubes.
The CNT bitcell is written to a RESET state by applying a
voltage pulse of <5V to terminal BL of the memory element
(Fig. 2) while the other terminal (SL) is grounded. Driver
current and bias on transistor M are such that an arbitrarily
large current (a few tens of microamps) is allowed to pass
through the CNT switch. The pulse is 50 nanoseconds in
duration, and results in a high resistance state (RESET, or ‘0’)
due to transformation of the CNT network from one of closely
touching nanotubes to a network of separated nanotube
junctions (Fig. 5).
The bitcell is written to the complementary SET state by
applying a similar bias (<5V on BL, 0V on SL) but modifying
the driver and bias on device M such that current through the
switch is limited to a much smaller current during the 500
nanosecond SET pulse.
Fig. 5 illustrates the resulting electrical equivalent of the
CNT network, with a reduced resistance due to the increased
number of CNT junctions which have been ‘closed’ by
electrostatic attraction (“closed” switches). Table I
summarizes voltage and time requirements for RESET and
SET operations.
TABLE I. EXAMPLE PROGRAM AND READ CONDITIONS
RESET SET READ TIME
VPP: 4.5V VPP: 5.0V “1”, 50 nSec
Pulse Width: 50 nSec Pulse Width: 500 nSec “0”, 30 nSec
* SET is differentiated from RESET by current control. The NRAM
CNT is unipolar and bilateral; the same potential is used for both
SET & RESET, and can be reversed in either case with no difference
in result.
C. Read Operation
The 4Mb NRAM bitcell is read in NOR fashion with
terminal SL at ground potential, and terminal BL at about 1V.
Under these bias conditions a cell current (ICELL) of a few
µA is typical for a SET bit, and < 10 nA for a RESET bit. The
4Mb NRAM uses a current comparison sense amplifier with
an internal reference level of 800nA, adjustable from 100 nA
to 10 µA.
 A[0]

W PLUG ►
D
TiN ►
CNT ►
W PLUG ►

Figure 7. tACC = 49.8 nSec

Figure 6. CNT Bitcell Integration

IV. ELECTRICAL RESULTS

III. INTEGRATION
The NRAM bitcell is comprised of the 2-terminal CNT
element and a select device. In this design an NMOS transistor
is used as the selector, and the CNT element is integrated
between METAL3 and METAL 4 (Fig. 6, transistor not
shown).
The CNT element is composed of carbon nanotubes which
have been placed in solution and deposited on the wafer
surface via spin coat. An electrode is then deposited on top of
the CNT layer, then both the CNT and Metal layers are
patterned with photoresist to define the desired geometry (all
steps are compatible with CMOS fab equipment and the CNT
solution can be applied with a standard spin coat track). The
resultant structure is a vertical stack of metal (W plugs and
TiN metal cladding in this case) interconnects above and
below a CNT layer. A standard planarized oxide is deposited
as a passivation barrier around the structure. A single extra
photomask is required, and only those additional steps
necessary to add the CNT layer (depositions, photo patterning,
etch & clean). The resulting structure is a vertical stack
connecting the metal layers above and below, which are
unaffected by this step. In this implementation the metal layers
are Al, but there is no barrier to implementing the CNT bitcell
in a process with a Cu back end.
The resulting structure has a variable, unipolar resistance
from one electrode (W pillar, in this design) to the other. It is
electrically identical in either direction, and SET & RESET
operations can be identically performed with either polarity.
The CNT layer provides the varying resistance (KΩ – GΩ)
A. Access Time
The NRAM development test chip has a single data pin D.
Fig. 7 shows a single random read access of the NRAM,
illustrating 50 nSec random address access time (tACC) at
room temperature. Although this design is organized as
4Mb×1, any organization (e.g. ×8, ×16, ×32) is possible; as
well as pipelining techniques to boost sequential throughput to
CMOS clock speeds.
B. Endurance
NRAM has no known intrinsic wear mechanism. Fig. 8
shows ICELL over 10,000 cycles of SET/RESET on a typical
array bit from the 4Mb NRAM. Read points are at every cycle
for the first 10, then every 50 cycles to completion (10K). The
bit passed verify on every cycle, including those whose values
are not shown on the graph.
C. Current Consumption
The NRAM described here has a NOR architecture, and
current consumption of the 4Mb NRAM during READ is
comparable to high-performance random access NOR
memory (e.g. NOR Flash, ROM, etc). As individual bitcell
current measurement can be complex, current during SET and
K201 Lot GAK35929.4 Wafer Q07NTA0 DIE 5,4 ICELL vs Cycle
10.000
1.000
ICELL (µA)

depending on the stimulus, as described in the “Write

Operation” section above. 0.100

This integration method makes NRAM particularly

suitable for 3-D structures, in which successive layers of 0.010
bitcells can be fabricated vertically – ideally with an integrated
selector. The CNT material is also electrically unaffected by
manufacturing temperatures to >700°C. 0.001
0 2000 4000 6000 8000 10000
Cycle
Figure 8. ICELL over 10,000 SET/RESET cycles

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RESET are inferred from bias conditions on a series transistor
100%
during write operations as described below.

D. Measuring ISET, IRESET: 80%

The NRAM SET and RESET transitions are intrinsically

fast (< 1nSec) and difficult to measure directly, particularly in
an array. In order to determine current flow through the CNT
element, array selector M (see Fig. 2) can be biased so as to
limit the series current to the CNT during SET and RESET.
The current required to write data to the CNT can then be
determined from the bias voltages on M (WL, BL, SL) and
from measured characterization data of device M in a test
structure.
Using this configuration, typical current required for
RESET of a 4Mb NRAM bit is measured for the operation
condition outlined in Table I at ~15 µA and typical current
required for SET of a bit is measured at ~1 µA. In addition,
the RESET current is intrinsically self-limiting: once the bit
goes to the RESET state, current drops to <<1 µA regardless
of bias voltages. Table II compares NRAM current
consumption during RESET (the higher-current operation) to
existing and emerging NVM technologies.
TABLE II. PROGRAM AND READ CONDITIONS
Max I during WRITE/PGM
Flash* ~200 µA
MRAM** ~170 µA/~625 µ (1mSec/2nSec)
PCRAM ~200 µA
NRAM ~15 µA
* Flash, ETOX using hot carrier injection
** MRAM, current is inverse to write time
E. Retention
NRAM has demonstrated 24 hours of data retention at
125°C. Fig. 9 shows before and after distribution of RESET
and SET bits. In neither case is failure seen.
100%
60%
40%
20%
0%
100E-6 1E-3 10E-3 100E-3 1E+0 10E+0 100E+0 1E+3
ICELL (µA)
Figure 10. 20nm CNT Bitcell ICELL distribution
V. SCALING
NRAM has been fabricated in our Woburn laboratory
using EBL (E-Beam Lithography) at dimensions smaller than
available Fab capability. Fig. 10 illustrates the SET/RESET
current distributions of an array of 20nm bitcells.
VI. CONCLUSION
The first publicly disclosed CNT-based NVM has been
demonstrated. It is manufactured in a CMOS production fab,
provides write and read performance superior to existing Flash
memory, low power consumption during read and write, and
is scalable to <5 nm. Endurance and data retention show no
wear or failure and are intrinsically expected to surpass that of
Flash. The memory storage element (the CNT material) can be
paired with any choice of select device (various diode, N/P
MOSFET, BJT, etc) and due to its temperature tolerance is
suitable for 3-D manufacturing techniques with multiple levels
of ‘stacked’ CNT switches in a monolithic structure as
opposed to a multi-die stack approach to 3-D with its
associated assembly and interconnect requirements.

80%
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