IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO.
5, MAY 2019
Demonstration and Understanding of Nano-RAM
Novel One-Time Programmable
Memory Application
Sheyang Ning , Member, IEEE , and Jia Luo
Abstract — In prior researches, carbon nanotube (CNT)-
based nano-random access-memory (NRAM) uses reset
initialization which obtains >1011 high write endurance for
large-time programmable (LTP) application. In this paper, for
the first time, NRAM one-time programmable (OTP) applica-
tion is proposed by using set initialization for data archive.
Specifically, virgin NRAM cells are all in high resistance
state (HRS) for storing bit “0.” In contrast, set initialization
uses reversed polarity voltage to obtain low resistance
state (LRS) for bit “1.” Furthermore, physical models of
set initialization and retention current degradation are pro-
posed for the first time. The current increment during set
initialization can be attributed to electron tunneling and
CNT deformation. Retention current degradation may be due
to variation of paralleled CNT contacts in bottleneck zone.
As for OTP performance, median NRAM bit and 1% tail bit
demonstrate more than 1 billion years and 15 years data
retentions, respectively, on 150 °C. The tail bit activation
energy is 2.41 eV. Finally, no LRS read disturb is found after
10 s 0.5-V stress on both polarities. The virgin NRAM cells in
HRS should be more stable than set initialized NRAM cells
in LRS for both retention time and read disturb.
Index Terms — Carbon nanotube (CNT), data retention,
digital archive, emerging memory, error correcting code
(ECC), nano-random access memory (NRAM), nonvolatile
memory, one-time programmable (OTP) memory.
I. I NTRODUCTION
C ARBON nanotube (CNT)-based nonvolatile nano-
random access-memory (NRAM) is one of the promis-
ing candidates of emerging memories. It has demonstrated
high performances, such as fast write and read speeds, 1011
high endurance, good data retention, and low program cur-
rent [1]–[4]. Reset initialization is needed on virgin cell
by applying positive voltage on top electrode (TE) while
grounding the bottom electrode (BE). It is called reset ini-
tialization because it uses the same voltage polarity as reset
program. In addition, the term large-time programmable (LTP)
Manuscript received December 30, 2018; revised March 4, 2019 and
March 19, 2019; accepted March 20, 2019. Date of publication April 10,
2019; date of current version April 22, 2019. The review of this paper
was arranged by Editor P. Du. (Corresponding author: Sheyang Ning.)
The authors are with the Nantero Inc., Sunnyvale, CA 94085 USA
(e-mail: sning@nantero.com).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2019.2907140
0018-9383 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
2179
is used for this conventional high endurance application in
order to differentiate with the one-time programmable (OTP)
application proposed in this paper.
Different from the conventional LTP NRAM, for the first
time, NRAM OTP application is demonstrated and analyzed
which uses the same virgin cell as LTP. Specifically, virgin
NRAM cells are all in HRS which can be used to store bit “0.”
In contrast to LTP NRAM, OTP requires set initialization with
reversed voltage polarity to reduce cell resistance to low resis-
tance state (LRS) for storing bit “1.” The HRS is more stable
than LRS on data retention and read disturb because the virgin
NRAM cells have been through high temperature in back-
end-of-line (BEOL) and plasma etching caused voltage stress
during manufacture. Extensions of measured retention results
demonstrate that the median bit and 1% tail bit obtain more
than 1 billion years and 15 years data retentions, respectively,
on 150 °C. No read disturb is found after 10 s 0.5-V stress.
OTP is widely used on applications such as boot code,
encryption keys, and configuration parameters for analog,
sensor, and display circuitry[5]–[10]. In addition, high capac-
ity, long retention, or permanent retention data archive in
specific applications becomes a hot topic [11], [12]. However,
conventional OTP devices may not be suitable for the archive
application. Specifically, fuse and antifuse OTPs have large
cell size which limits memory capacity [9], [10]. In addi-
tion, though NAND flash obtains the highest cell density and
capacity, it shows limited data retention time and radiation
sensitivity [13], [14]. In contrast, OTP NRAM demonstrates
potential for data archive application because of its small
cell size, long data retention time, and radiation-resistant
characteristic [15].
The rest of this paper is organized as follows. NRAM OTP
is proposed for the first time in Section II. Measured NRAM
reset and set initialization currents and proposed physical mod-
els are demonstrated and discussed. Then, Section III shows
OTP data retention performance. A physical model is also pro-
posed to understand HRS and LRS degradations. In addition,
OTP NRAM read disturb performance and the comparison
with other OTP devices are discussed in this section.
II. OTP S ET I NITIALIZATION AND P HYSICAL M ODEL
In this section, reset and set initialization currents are
measured on single virgin NRAM cells. Novel NRAM OTP
2180
Fig. 1. Photographs of a planar-type NRAM cell after (a) set program and
(b) reset program [4]. The variation of spacing between CNTs decides
NRAM cell tunneling current.
application is proposed for the first time. Physical models of
reset and set initializations are discussed.
A. NRAM Photograph and Process
Fig. 1(a) and (b) shows photographs of a planar-type NRAM
cell after set and reset programs, respectively [4]. This NRAM
cell is different from the vertically placed 140-nm single
NRAM cells which are measured in the rest of this paper [3].
However, the cell resistance switching mechanism can be
considered the same. Specifically, more CNTs are placed on
one electrode than the other after initialization. A void, or say
a bottleneck zone with less CNT contacts, can be found in the
lower middle part between two electrodes. Set program for
LTP application applies positive voltage on the electrode with
less CNTs, as illustrated in Fig. 1(a). It reduces the spacing
between CNTs so that decreases NRAM cell resistance. On the
other hand, CNT contacts are separated in Fig. 1(b) after
reset program with reversed voltage polarity. The spacing
between CNTs decides NRAM cell current due to electron
tunneling. Moreover, a simplified NRAM process is shown in
Fig. 2 [2]. In detail, CNT layer is spin-coated between two
metal layers [3]. Conventional dry etching and postetching
cleaning are used for fabricating NRAM cells [3]. The virgin
NRAM cell in HRS has been through standard 425 °C BEOL
temperature and plasma etching caused voltage stress during
manufacture [3]. So, HRS’s data retention and read disturb
should be more stable than LRS after set initialization.
B. Physical Model of Reset Initialization
Conventional NRAM developments and researches focus
on high endurance LTP application. It requires reset initial-
ization by applying positive voltage on TE. In contrast, set
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 5, MAY 2019
Fig. 2. Simplified NRAM process [2].
Fig. 3. Comparison of measured set and reset initialization currents by
using (a) graph with linear X- and Y-axes and (b) FN plot.
initialization uses reversed voltage polarity and provides stable
cell resistance for OTP application. At beginning, all virgin
NRAM cells are in HRS which can be used for bit “0.”
Then, set initialization is applied to program NRAM cells to
LRS for bit “1.” Fig. 3(a) shows the comparison of measured
current versus voltage during reset and set initializations on
two discreate NRAM cells. For set initialization, a current
compliance is applied to prevent NRAM cell break.
To understand the physical mechanisms during reset and
set initializations, Simmons’s tunneling current equation for
metal–insulator–metal (MIM) system is showed in (1) [16].
J is current density. D is the spacing between CNTs. V is the
external voltage applied on CNT. ∅ is insulator average
√ barrier
height. q is electron charge. In addition, A = 4πβ 2m/ h and
B = q/(2πβ 2 h) can be considered as constants. In A and B,
h is Planck constant. β is correction coefficient and usually
β ≈ 1 [16]. m is electron mass
B √ √
−AD ∅
J= 2
[(∅e − (∅ + q V )e−AD ∅+q V ]. (1)
D
To simplify this equation, (2) shows an approximation in
direct tunneling region when low bias voltage is applied
√ and
∅  q V [16]. C is a constant which equals q 2 2m/ h 2 .
Equation (2) shows that the junction is ohmic in direct
tunneling region when the spacing D is fixed
√
√ − AD ∅
3C ∅V β
J= e . (2)
2D
Furthermore, (3) shows another approximation of (1) in
Fowler–Nordheim (FN) tunneling region by using large bias
voltage so that ∅ < q V [16]. C  = 2.2q 3 /(8πh) and
NING AND LUO: NRAM NOVEL OTP MEMORY APPLICATION 2181

Fig. 4. Proposed physical mechanism for set initialization.

√
C  = 8π 2m/(2.96 ∗ hq) are both constants in the following
equation [16]:
Fig. 5. Validation of the set initialization model which combines electron
√ 3 tunneling and CNT elastic deformation.
V 2 −C  D ∅0
J = C e V . (3)
∅0 D 2
To understand the mechanism of reset initialization,
Fig. 3(b) shows a well-known FN plot by adjusting Fig. 3(a)’s
X- and Y -axes. The reset initialization shows log-like curve in
low-voltage region and negatively sloped curve in high-voltage
region which match with (2) and (3), respectively. This result
can also be found frequently in other MIM solid materials.
So, it suggests that during reset initialization, the spacing
between CNTs does not have obvious variation on direct
tunneling and FN tunneling regions until a higher voltage
Fig. 6. (a) Photograph of 4-Mbit 140-nm NRAM cell array [3], [19].
causes separation. In prior publications, the separation of (b) Array structure and voltage applied for set initialization.
CNTs is attributed to phonon vibration [1]–[4].

C. Physical Model of Set Initialization
In Fig. 3(b), set initialization has higher current on low
bias which cannot be explained by using direct tunneling
or FN tunneling. Naturally, the CNT spacing reduction as
shown in Fig. 1 should also be considered for explanation
because the cell resistance is converted from high resistance
to low resistance after set initialization. A cartoon figure in
Fig. 4 provides a clear demonstration of this phenomenon. The
occurrence of CNT deformation is on the current bottleneck
because it has the largest voltage drop and electrostatic force.
To analyze this assumption, electrostatic force caused CNT
approaching is calculated in (4). The left side is electrostatic
force when voltage V is applied on CNTs [17]. It equals to
elastic force due to CNT or CNT network deformation [18].
ε is relative permittivity. S is effective CNTs overlap area.
K is elastic modulus. D0 is initial CNT spacing before set
initialization
εSV 2
= −K (D0 − D). (4)
2D 2
To give a qualitative analysis, (5) shows derived relationship
between D and V
 tograph of 140-nm NRAM cell array and the schematic of
3
D ∝ V 2. (5)
Then, (5) is brought to (2) for finding the I –V correlation
in low bias region as shown in the following equation:
√ √
√
3 −A
3
V2 ∅
I ∝ Ve β . (6)
Fig. 5 shows the validation of (6) by adjusting X- and
Y -axes from Fig. 3(a). Linear curve is expected in low bias
region. The result in Fig. 5 shows that this assumption has a
reasonable match from measured set initialization current.
III. OTP R ETENTION P ERFORMANCES
AND P HYSICAL M ODEL
In this section, OTP NRAM data retention performances
are measured on NRAM array. Then, a physical model for
data retention is proposed. Next, read disturb performance is
demonstrated and discussed. Finally, OTP NRAM is compared
with other devices for data archive application.
A. Improvement of NRAM Array Set Initialization
Higher voltage and longer pulse width can be used on
the set initialization for larger cell current and better data
retention. The strong initialization stress may further reduce
the spacing between CNTs or increase the number of carbon
atoms in contact. In this subsection, NRAM cell resistance
after set initialization is compared to find the best set ini-
tialization scheme. First, Fig. 6(a) and (b) shows the pho-
one-transistor one-resistor (1T1R) structure, respectively [19].
High voltage is applied on bitline (BL) and NRAM BE for set
initialization. The word line uses higher voltage for passing BL
voltage.
By using this array, Fig. 7(a) and (b) shows the compari-
son of the performance of four set initialization conditions.
2182
Fig. 7. (a) Comparison of set initialization conditions. (b) Comparison
of measured median cell current of 2-Kbit per condition after set initial-
ization.
The first one uses single 100-μs pulse with fixed voltage.
The second one reduces the pulsewidth by 10 times. The
third condition separates the stress time into 1000 pulses with
100-ns per pulse. The program voltage V used in these three
conditions equals to the maximum voltage that this process
can tolerate. Finally, the last set initialization reduces the
program voltage by 0.5-V. For each condition, set initialization
is applied on 2-Kbit. Then, the median cell’s read current
is compared in Fig. 7(b). Though the conditions 1 and 3
have same program voltage and total stress time, multiple
pulse programs in condition 3 obtain the highest cell current.
This can be attributed to prior published NRAM characteristic
that set and reset programs have higher success rate on
leading edge of program pulse [2]. In addition, the comparison
between conditions 3 and 4 also shows that high voltage is the
key for NRAM program. Finally, higher cell current and longer
data retention can be expected by further increasing the set
initialization voltage. However, higher voltage than V is pro-
hibited in our test, due to transistor limitation in control circuit.
B. Measured Data Retention Performances
By using the best set initialization scheme, Fig. 8(a) and (b)
shows measured 4-Kbit OTP cell current distribution percentile
when applying retention on 85 °C and 150 °C, respectively.
In Fig. 8(a) and (b), HRS resistance does not move because the
virgin NRAM cell has been through much higher temperature
in manufacture. On LRS side, NRAM cell current degradation
saturates quickly during 150 °C baking. By using low-density-
parity-check (LDPC) error correcting code (ECC), more than
1% raw bit error rate (RBER) can be corrected by using
0.89 high code rate and soft decoding [20]. So, this paper
uses 1% RBER margin and evenly split to 0.5% for LRS and
0.5% for HRS in the following analyses.
In this section, more efforts and analyses are applied on LRS
side because it shows faster retention degradation. In specific,
Fig. 9(a)–(c) shows 10 days data retention on 85 °C, 125 °C,
and 150 °C, respectively. In total, nine NRAM dies (parts) and
4-Kbit per die are measured. In each figure, the three black
curves with higher current show the median cell current of the
three dies with 4-Kbit measured per die. The gray curves in the
background are the 1% tail bits of the three dies. The definition
of tail bit is having the shortest data retention time when the
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 5, MAY 2019
Fig. 8. Measured cell current distribution when baking at (a) 85 °C
and (b) 150 °C.
extension of current degradation reaches the sensing criteria.
Furthermore, the red curves are the median cell current of the
1% tail bits in three dies. So, the red curve is considered as
cell current degradation at 0.5% tail bit. From these figures,
both median current and tail bit current have linear degradation
when retention time is in log scale.
The data retention times for median bit and tail bit are
then compared in Fig. 10(a) and (b), respectively. The raw
data from Fig. 9(a)–(c) are used in these analyses. Each
LRS curve shows a combined result from three dies with
4-Kbit per die. In addition, for each HRS curve, 2-Kbit are
measured on virgin NRAM die. In both figures, LRS cell
current degradation shows larger slope when applying data
retention on higher temperature. In Fig. 10(a), HRS median
bit does not find current variation when baking on 85 °C
or 150 °C. In addition, the extended 150 °C LRS and HRS
curves still keep large sensing margin even after 1 billion years
retention. Furthermore, Fig. 10(b) shows 1% tail bit current
degradations including 0.5% for HRS and 0.5% for LRS. The
sensing criteria are decided by the cross point of 150 °C LRS
and HRS extensions. More than 15 years data retention time
can be obtained on 150 °C. In addition, the retention times on
125 °C and 85 °C are decided by LRS current degradation.
Though no margin is assigned in Fig. 10(b), the assumption
and calculation are practical and agree with industry standard
data retention time projection. In detail, normally the margin
is reserved after program verify for compensating margin
loss due to program disturb, read disturb, data retention
NING AND LUO: NRAM NOVEL OTP MEMORY APPLICATION
Fig. 9. Measured LRS NRAM cell current degradation during 10 days baking by using (a) 85 °C, (b) 125 °C, and (c) 150 °C. In all figures, both
median bit and 0.5% tail-bit show linear current degradation when data retention time is in log scale.
Fig. 10. Measured (a) median cell current and (b) 1% tail-bit current
(0.5% HRS and 0.5% LRS) degradations on different temperatures. For
each temperature, data from three parts are combined.
degradation, and sensing noise. In NRAM OTP application,
there is no program disturb concern due to the 1T1R structure,
and the user data are written only once. The read disturb
is also not a concern as show in the following analyses.
Furthermore, the data retention caused margin degradation is
closely monitored in Fig. 10(b). Finally, the sensing noise
is already included in Fig. 10 because the data is read out
from our on-die sense amplifier. In addition, during the data
retention test, sensing circuit is also baked with memory cells.
2183
So, the sensing circuit baking caused margin loss is also
included in this figure.
Besides using LDPC, the data retention time is also cal-
culated by using Bose–Chaudhuri–Hocquenghen (BCH) ECC
which is another popular ECC scheme for nonvolatile memory.
It has smaller circuit size but the correctable RBER is reduced
to about 0.4% [20]. At 150 °C, retention time is largely
reduced from more than 15 years by using LDPC to 1 year
by using BCH. Similarly, at 85 °C, retention time is reduced
from 2 × 106 years to 2 × 105 years by using BCH.
Arrhenius equation (7) is commonly used to calculate data
retention times and active energy on resistive RAM (RRAM),
phase change RAM (PRAM), and conductive bridge RAM
(CBRAM) [21]–[24]. For example, it is suitable for RRAM
cell current degradation which is due to oxygen vacancy
diffusion [21], [24]. Similarly, NRAM retention degradation
can be attributed to displacement and diffusion of CNT–CNT
contacts. So, the Arrhenius equation is also used in this
paper for calculating OTP NRAM retention degradation and
activation energy
t = t0 e Ea / k B T . (7)
In (7), T is absolute temperature. t is data retention time
on temperature T . t0 is retention time on infinite temperature.
k B is Boltzmann’s constant. E a is activation energy for 1% tail
bit data retention. By using data retention time on 85 °C and
150 °C, the calculated activation energy is 2.41eV. Further-
more, extended curve in Fig. 11 shows more than 1020 seconds
retention time on 25 °C.
C. Data Retention Physical Model
According to Ohm’s law, the bottleneck of current flow on
the CNT sparse region should make key contribution to cell
current variation during retention. Based on the photographs
in Fig. 1, the bottleneck is made from paralleled CNT contact
pairs. Then, by considering measured results in Figs. 9 and 10,
a physical model of NRAM OTP data retention is proposed
as below.
First, the NRAM LRS current reduction and HRS current
growth during data retention clearly suggest an equilibrium
2184 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 5, MAY 2019

Fig. 12. Comparison of NRAM cell current distributions before and after
0.5-V, 10-s read stress by using (a) TE read and (b) BE read.

Fig. 11. Arrhenius plot of data retention time. TABLE I

C OMPARISON OF M EMORIES FOR D IGITAL A RCHIVE A PPLICATION
state with moderate number of paralleled CNT contact pairs
or contact atoms in the bottleneck region. Equation (8)
demonstrates measured linear-log relation of current and reten-
tion time for HRS and LRS approaching to the equilibrium
state. In (8), A is the slope of retention curve as shown
in Figs. 9 and 10
I ∝ Aln(t). (8)
Then, (9) calculates the current variation rate dI/dt in each
NRAM cell by adding or removing part of paralleled CNT
contacts which have resistance R. The result shows that it
changes the NRAM cell resistance by 1/R. In (9), R0 is
initial cell resistance before data retention
 
dI 1 1 V
=V − = . (9)
dt R0 //R R0 R
E. Comparison With Other OTP Devices
Finally, the retention current degradation as shown in (8)
matches with measured result. It can be derived by solving Table I shows the comparison of NRAM performances with
the integration in (9) if V /R can be replaced by V × A/t other nonvolatile memories for OTP data archive application.
as shown in (10). The n in (10) is the number of reduced or In detail, antifuse demonstrates stable data retention after
increased CNT contacts in bottleneck zone which cause 1/R 150 °C, 450-h without degradation [26]. In addition, EEPROM
resistance variation on NRAM cell can obtain 10-year data retention time on 150 °C [27]. How-
ever, both antifuse and EEPROM have limited capacity due
1 A
= ∝ n. (10) to large cell size. For example, at 10-nm technology node,
R t 2T antifuse needs 144-nm × 192-nm cell size [28]. On the
In conclusion, the model shows that during data retention, other hand, 3-D NAND flash obtains the highest capacity due to
the increase or decrease of paralleled CNT contacts n in bot- 3-D array structure and multiple bits per cell. However, it has
tleneck zone is inversely proportional to retention time t. The limited data retention time and radiation sensitivity [13], [14].
reduction of LRS current during retention can be considered Furthermore, emerging memories such as RRAM, PRAM, and
as recover of the CNT deformation during set initialization. NRAM have potential of high array capacity because they
On the other hand, the increase of HRS current may be also all support 3-D array structure, and have less limitation for
due to unbalanced CNT net, from mechanical stress or plasma cell etching [29]–[30]. For example, Rueckes [3] demonstrated
etching caused voltage stress on virgin NRAM cell. 22-nm NRAM cell resistance switching. Among these emerg-
ing memories, OTP NRAM shows the best data retention
D. Read Disturb
performance. In addition, NRAM also has advantage of
Fig. 12(a) and (b) shows OTP read disturb performances by radiation-resistant characteristic [15].
applying read voltage on TE and BE, respectively. LRS read
disturb is demonstrated because it is less stable than HRS.
IV. C ONCLUSION
Specifically, one second 0.5-V stress is applied 10 times on
three NRAM dies. No obvious cell resistance shift is found in A novel NRAM OTP application is proposed for the first
both figures. From prior publication, NRAM array requires time. Virgin NRAM cells in HRS are used for data “0,”
only 13.5-ns access time [25]. So, the applied total 10-s whereas set initialization is needed to program NRAM cells
read stress shows no read disturb concern on NRAM OTP to LRS for data “1.” Two physical models are also proposed
application. for understanding set initialization current and LRS, HRS
NING AND LUO: NRAM NOVEL OTP MEMORY APPLICATION
retention current degradation. OTP NRAM is suitable for data
archive application because it has long data retention on high
temperature, potential of high capacity, and radiation-resistant
characteristic.
ACKNOWLEDGMENT
The authors would like to thank W. Wong, M. Kwan,
M. Ramsbey, T. Gallagher, N. Leong, and L. Cleveland for
their supports and discussions.
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