Roll No:

KAKATIYA INSTITUTE OF TECHNOLOGY & SCIENCE, WARANGAL-15

VLSI DESIGN
IV/IV B. Tech. (ECE & EIE) I-Semester, II-Mid Examination
Date: 28.10.2015 Max. Marks: 50
Time: 2 Hours
Note: Answer the following questions.
PART A

1. (a) Define the terms sheet resistance and standard unit of capacitance. (3)
(b) Draw the stick diagram and lay out of a CMOS inverter. (3)
(c) Write a brief note on Floor Planning. (2)
(d) Differentiate between pass transistors and transmission gates. (2)
(e) Explain how the pull up – pull down ratio affects the time delays of nMOS (2½)
circuits.
PART B
2. (a) Explain Lambda based design rules. (6)
(b) What are different types of scaling models? Explain the effect of scaling on (6½)
various device parameters of a MOSFET.
(OR)
(c) Draw the stick diagram and lay out of a 2 input NAND gate. (6)
(d) Discuss the architectural issues and guide lines for a Subsystem design. (3)
(e) Derive expressions for rise time and fall time of CMOS inverter. (3½)
3. (a) Discuss the Switch logic implementation of a four way Multiplexer. (4 ½)
(b) What is Bus arbitration logic? Show the structured design and stick (8)
diagram for the same.
(OR)
(c) Explain the structured design of a Parity Generator and show the circuit (6½ )
and stick diagrams.
(d) Elaborate on various forms of CMOS circuits. (6)
4. (a) Write short notes on programmable logic structures. (6½)
(b) Write short notes on the following design verification tools (6 )
(OR)
(c) Elaborate on CMOS chip design options and design methods. (6 )
(d) Write short notes on CMOS test methods. (6½ )
*******
Paper set by:

Dr. K. Sivani
Syed Zaheeruddin
Sri. B.Raju