U18EI503 VLSI DESIGN

Class: B.Tech. V-Semester Branch: Electronics & Instrumentation Engineering (EIE)

Teaching Scheme: Examination Scheme:
L T P C Continuous Internal Evaluation 40 marks
3 - - 3 End Semester Examination 60 marks

Course Learning Objectives(LOs):

This course will develop students‟ knowledge in/on…
LO1: fabrication process and electrical properties of MOS transistors
LO2: stick diagrams, design rules, layout diagrams and MOS transistor circuit concepts
LO3: scaling models, scaling factors & limitations of scaling and subsystem design
LO4: behavioral, dataflow, gate and switch level abstractions of Verilog HDL

UNIT–I (9)
Review of Microelectronics and Introduction to MOS Technology: Introduction to IC
technology, MOS technology and VLSI, Basic MOS transistor, Photolithographic process, Etches,
Deposition techniques, Fabrication process of nMOS, CMOS and BiCMOS transistors, Production
of E-Beam masks
Basic Electrical Properties of MOS Transistor: Derivation of drain to source current, Threshold
voltage, Transconductance, Pass transistor, nMOS inverter, Pull up/Pull down ratios, Alternate
forms of pull up, CMOS inverter, BiCMOS inverters, Latch-up in CMOS circuits

UNIT–II (9)
MOS Circuit Design Processes: MOS layers, Stick diagrams and symbolic diagrams, nMOS
design style, CMOS design style, Layout and Lambda based design rules, Contact cuts, Layout
diagrams
Basic Circuit Concepts: Sheet resistance, Area capacitances of layers and calculations, Delay unit,
Inverter delays, Rise and Fall time estimation

UNIT–III (9)
Scaling of MOS Circuits: Scaling models, Scaling factors for device parameters and limitations
of scaling
Subsystem Design and Layout: Architectural issues, Switch logic, Gate logic, Examples of
structured design, Clocked sequential circuits and system considerations

UNIT–IV (9)
Verilog HDL: Hierarchical modeling concepts, Basic concepts - Data types, Modules and ports;
Gate level modeling, Dataflow modeling, Behavioral modeling, Design examples of
combinational and sequential circuits , Switch level modeling

KITSW-Syllabi for III to VI Semester B. Tech. EIE 4 – year Degree Programme Page 86 of 127
 Text Books:

[1] Douglas A Pucknell and Kamran Eshraghian, Basic VLSI Design, 3rd ed. New Delhi:
Prentice Hall of India, 2008. (Chapters 1 to 6)
[2] Samir Palnitkar, Verilog HDL – A Guide to Digital Design and Synthesis, 2nd ed. New
Delhi: Pearson Education, 2003. (PART-I: Chapters 2 to 8)

Reference Books:

[1] Neil H. E. Weste, David Harris and Ayan Banerjee, CMOS VLSI Design, 3rd ed.New
Delhi: Pearson Education, 2006.
[2] John P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and Simulation, 2nd ed.
Thomson/Nelson, 2010.

Course Learning Outcomes(COs):

On completion of this course, students will be able to…
CO1: illustrate fabrication steps for nMOS, pMOS& CMOS circuits and determine aspect ratios
of MOS transistors using electrical properties
CO2: construct the stick diagrams & mask layouts using design rules and estimate transistor &
interconnect delays
CO3: determine the scaling factors for device parameters and illustrate structured design
approach for typical example circuits
CO4: develop Verilog HDL programs in behavioral, dataflow, gate and switch level modeling

Course Articulation Matrix (CAM):U18EI503 VLSI DESIGN

CO PO PO PO PO PO PO PO PO PO PO PO PO PS PS
1 2 3 4 5 6 7 8 9 10 11 12 O1 O2
CO1 U18EI503.1 1 1 -- -- -- -- -- -- -- -- -- 1 2 2
CO2 U18EI503.2 1 2 1 1 1 -- -- -- -- -- -- 1 2 2
CO3 U18EI503.3 1 2 1 1 1 -- -- -- -- -- -- 1 2 2
CO4 U18EI503.4 1 2 2 2 2 -- -- -- -- -- -- 1 2 2
1. 1.
1.7 1.3
U18EI503 1 3 3 -- -- -- -- -- -- 1 2 2
5 3
3 3

KITSW-Syllabi for III to VI Semester B. Tech. EIE 4 – year Degree Programme Page 87 of 127