Jerome S.

Del Castillo: BS ECE: 17-21514

WEEK 8:

Microprocessors plays a relevant role on our computers and electronic devices. It is regarded as the main brain
of system and always branded to be the most important part needed to be improved in order to make your system
faster and better. The evolution of microprocessors’ speed and performance pioneered the enhancement of
technology specifically in the application of computing, gaming, display and rendering. The microprocessor was
assigned to carry out the computations needed to perform basic functions, and it works by following a simple cycle
called “fetch-execute cycle”.
Figure 1 presents the Fetch execute cycle
done by any system containing microprocessors.
The fetch execute cycle happens between the
Central processing unit (CPU) and Random-
Access Memory. CPU is a single integrated
circuit that contains all the electronics needed to
perform and execute a program. The CPU
contains the designed circuitry that performs
fetching, interpreting/decoding instructions,
processing and writing data (Stallings, 2010).
Figure 1. Fetch-execute cycle.

The RAM is a hardware device that allows information to be stored and retrieved on a computer. In the figure,
the CPU have a clock responsible for setting the cycle along the CPU. The CPU contains three (3) registers needed
for the cycle. The program counter keeps tracks of the instruction cycle; instruction register loads the instruction
form the memory and the accumulator stores the computed value from the RAM. While the RAM contains and
stores the instructions, address and values calculated.

Figure 2 clearly shows the loop of execute, fetch and

decode cycle per each CPU parts. Fetching, decoding
and executing will be mainly dependent on the clock
cycle. At every tick of the clock, either of the three will
be implemented simultaneously. The instructions and
values that are stored in the RAM will be fetched by
assigning address from the program counter. After
fetching the instruction from the RAM, the instruction
will be store on an instruction register, that will be soon
decoded. Then control unit decodes the instruction and
Figure 2. Fetch, decode and
executes the instruction and accumulates the resulting
execute (BBC, 2021)
value based from the instruction and memory location.
 The fetch-decode-execute loop continuously progresses dependent to the series of instructions
loaded to the RAM. This is the main reason why RAM size, clock speed and even the CPU itself gravely
affects the performance of the system. If the RAM have higher size, then the size of succeeding instruction
loaded will be plenty. But in order to cater the huge amount of RAM size with huge amount of loaded
instruction, the device must also have a powerful CPU (multi-cores) with multiple ALU to compensate
with the instructions, boosting the speed and performance of the system. Clock speed also plays a huge
part in the system, since clock speed dictates the speed of the looping. The faster the clock speed the faster
the loaded information to the buses.

A bus architecture constitutes of the wires connected/ or the pathways the connects each part and
components of the system in order to communicate and function in unison. A single bus architecture is
only connected to a common bus. It has the main advantage of low cost and flexibility for connecting
peripheral devices (Mueller , 2015). But the single bus architecture is limited to communication between
only two (2) units. Every single bus represents a single bit, it means if the processors can process 32 bits,
the bus architecture has 32 multiplexed buses connecting every single component.

Figure 3. Single Bus Architecture.

Figure 3 illustrates the Single bus Architecture, in which all of the four components (input, output,
memory and processor) are only connected on a single common bus. All of the components are connected,
in which results to the creation of a conflict called bus contention; which some components need to wait for
other components to finish processing, that further results to the deceleration of the systems speed (Bethea,
2021).

Figure 4. Double Bus architecture

Figure 4 shows the double bus structure, in contrast with single bus architecture, double bus has
two (2) independent buses, the first one is use for the input and output (peripherals), while the other one
is used on the processor and memory. With its application multiple advantages came into light such as
the process execution and performance increases. With more expanded bus capacity, several components
could do work simultaneously, reducing time spent waiting and improving the processing speed.
 The development of faster computers can be
accounted to the number of cores or processors.
And with more cores requires more buses to carry
out the instructions and values. The Dual
independent bus structured to the double bus
architecture on figure 4 was first implemented on
Pentium Pro Processor to aid the processors’ bus
bandwidth (Erdei & Luther, 2021). Based on the
double bus architecture, the DIB has two (2)
independent bus; the first one is Frontside bus
(FSB). FSB is connected to the main memory (L1
cache).
Figure 5. Dual Independent Bus

The second independent bus refers to the backside bus (BSB) which is connected to the Level 2 (L2)
cache of the microprocessor. With separate bus used for the peripherals and processor, DIB associate more
registers than single bus architecture. The execution process is faster, since the number of cycles needed for
execution are lesser. So, for example, if the execution process of a computer with a clock speed of 2.4 GHz
using a single bus architecture is .20 millisecond, then computer with similar clock speed but implemented
DIB architecture can have an execution process lesser than .20 millisecond. The faster execution of the
instructions can also be accounted with the existence of caches. With caches, a buffering or a filtering system
was implemented to ease out the flow of data from FSB towards the processor. It gives way for the processor
to furtherly improve its scope while increasing its performance.

The Dual independent bus architecture gives more option on the data to flow accordingly. Providing
more data flow on the fetch and execute stage of the cycle. DIB provides more avenues for the system to
extract and send data from the peripherals, CPU and RAM. Moreover, the DIB architecture highlights the
significant of separate and specific paths to harness more productivity. Putting into analogy, the fetch -
execute cycle, Single bus architecture, and DIB architecture to a building with identified fire exits.

The fetch-execute cycle represents the flow of evacuation, in which a building with no fire exits is
represented with single bus architecture, while buildings with fire exit represents the DIB architecture.
Building with no or unusable fire exits, hinders the flow of evacuation forcing all the building occupants to
use the single path or door in the entrance of the ground floor.
 The flow of evacuation is slow and inefficient causing possible deaths and injuries. But with buildings
with multiple functional fire exits, represented as DIB, the occupants are offered with different proper option
to escape. The flow and speed of evacuation could be increase and more occupants could be saved.

Personal Insights

The DIB architecture is a good testament of how humans strive to make everything efficient
starting from theories and junks up to applications that could be called game-changers. The DIB
architecture pioneered the ideas of stepping up the capabilities of the microprocessor. And I can’t wait to
see more hardware architectural design that evolves and always dreams to make everything better.

References
BBC. (2021). The CPU and the fetch-execute cycle. Retrieved from BBC:
https://www.bbc.co.uk/bitesize/guides/zws8d2p/revision/3
Bethea, A. (2021, January 30). What Are the Benefits of Using Multiple-Bus Architecture Compared to Single-Bus
Architecture? Retrieved from Chron: https://smallbusiness.chron.com/benefits-using-multiplebus-
architecture-compared-singlebus-architecture-72173.html
Erdei, J., & Luther, S. (2021). ptechguide. Retrieved from Dual Independent Bus (DIB) – frontside and
backside data bus CPU architecture: https://www.pctechguide.com/
Mueller , S. M. (2015). Upgrading and Repairing. Pearson Educaition Inc.
Stallings, W. (2010). CPU Structure and Function Chapter 12. In W. Stallings, CPU Structure and Function.
Computer Organization and Architecture .