SiI 141

®
PanelLink Digital Receiver July 1999

General Description Features

The SiI 141 uses PanelLink Digital technology to support displays ranging • Scaleable Bandwidth: 25-86 MHz (VGA to High Refresh
from VGA to High Refresh XGA (25-86 MHz), which is ideal for LCD desktop XGA)
monitor applications. With a flexible single or dual pixel out interface and • Low Power: 3.3V core operation & power-down mode
selectable output drive, the SiI 141 receiver supports up to true color panels (24 • High Skew Tolerance: 1 full input clock cycle (15ns at 65
bit/pixel, 16.7M colors) in 1 pixel/clock mode (18 bit/pixel in 2 pixel/clock mode). MHz)
PanelLink also features an inter-pair skew tolerance up to 1 full input clock cycle • Pin-compatible with SiI101
and a highly jitter tolerant PLL design. Since all PanelLink products are • Sync Detect: for Plug & Display “Hot Plugging”
designed on scaleable CMOS architecture to support future performance • Cable Distance Support: over 5m with twisted-pair, fiber-
requirements while maintaining the same logical interface, system designers can optics ready
be assured that the interface will be fixed through a number of technology and • Compliant with DVI 1.0 (DVI is backwards compatible
TM
performance generations. with VESA® P&D and DFP)
PanelLink Digital technology simplifies PC design by resolving many of the
system level issues associated with high-speed digital design, providing the
system designer with a digital interface solution that is quicker to market and
lower in cost.

SiI141 Pin Diagram Functional Block Diagram

ST
24-bit Input Data for 1-pixel/clock mode PIXS
DFO
8-bit Channel 2 Data 8-bit Channel 1 Data 8-bit Channel 0 Data
1-pixel/clock OCK_INV
1-pixel/clock 1-pixel/clock
PDO
18-bit Even Data for 2-pixel/clock mode
Termination
EXT_RES
6-bit Odd Channel 0 6-bit Even Channel 2 6-bit Even Channel 1 Control
Data 2-pixel/clock Data 2-pixel/clock Data 2-pixel/clock 8
OGND
ODCK

OVCC

24/36
GND
VCC

DATA CLT3
Q19

Q18

Q17
Q16
Q15
Q14
Q13
Q12
Q11

Q10

RX2+ Q[35:0/23:0]
Q9
Q8
Q7
Q6
Q5

VCR RECOVERY
CLT2
RX2- CH2 ODCK
6-bit Even Channel 0

DE2
DE
Data 2-pixel/clock
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
18-bit Odd Data for 2-pixel/clock mode

DE 41 20 Q4 HSYNC
8 PANEL VSYNC
Q20 42 19 Q3 INTER-
RX1+ DATA INTER- CLT1 FACE
Q21 43 18 Q2 RECOVERY
VCR CHANNEL DECODER PLL_SYNC LOGIC
Q22 44 17 Q1 RX1- CH1 SYNC.
DE1
Q23 45 16 Q0 SCDT

OGND 46 15 OVCC
8
CONTROL

Q24 47 14 VSYNC CLT1

VSYNC
RX0+ DATA CLT2
OVCC 48 13 OGND
6-bit Odd Channel 1

VCR RECOVERY HSYNC

Data 2-pixel/clock

CLT3
Q25 49
SiI141 12 HSYNC RX0- CH0 DE0
VCC 50 11 GND
80-Pin TQFP
CONTROL
GENERAL
PURPOSE

Q26 51 10 CTL3
(Top View)
Q27 52 9 CTL2
RXC+
Q28 53 8 CTL1 VCR PLL
RXC-
Q29 54 7 SCDT
Q30 55 6 DFO
6-bit Odd Channel 2
Data 2-pixel/clock

Q31 56 5 PIXS
Q32 57 4 OGND
Q33 58 3 PDO
Q34 59 2 PD
Q35 60 1 RESERVED
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
OCK_INV
AGND

AGND

PGND
EXT_RES
GND

RESERVED
AVCC

AVCC

RXC+
RX2+

RX1+

RX0+

PVCC
RXC-
RX2-

RX1-

RX0-

ST
VCC

DIFFERENTIAL SIGNAL MISC.

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Silicon Image, Inc. SiI141 SiI/DS-0004-D

Absolute Maximum Conditions

Note: Permanent device damage may occur if absolute maximum conditions are exceeded.
Functional operation should be restricted to the conditions described under Normal Operating Conditions.
Symbol Parameter Min Max Units
VCC Supply Voltage 3.3V -0.3 4.0 V
VI Input Voltage -0.3 VCC+ 0.3 V
VO Output Voltage -0.3 VCC+ 0.3 V
TA Ambient Temperature (with power applied) -25 105 °C
TSTG Storage Temperature -40 125 °C
PPD Package Power Dissipation 1 W

Normal Operating Conditions

Symbol Parameter Min Typ Max Units
VCC Supply Voltage 3.00 3.3 3.6 V
VCCN Supply Voltage Noise 100 mVP-P
TA Ambient Temperature (with power applied) 0 25 70 °C
1
Note: Guaranteed by design.

DC Digital I/O Specifications

Under normal operating conditions unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
VIH High-level Input Voltage 2 V
VIL Low-level Input Voltage 0.8 V
VOH High-level Output Voltage 2.4 V
VOL Low-level Output Voltage 0.4 V
1
VCINL Input Clamp Voltage ICL = -18mA GND -0.8 V
1
VCIPL Input Clamp Voltage ICL = 18mA IVCC + 0.8 V
1
VCONL Output Clamp Voltage ICL = -18mA GND -0.8 V
1
VCOPL Output Clamp Voltage ICL = 18mA OVCC + 0.8 V
IIL Input Leakage Current -10 10 µA
1
Note: Guaranteed by design.

DC Specifications
Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are shown in brackets.
Symbol Parameter Conditions Min Typ Max Units
IOHD Output High Drive VOUT = VOH
Data and Controls ST=1 5.0 10.3 17.6 mA
ST=0 2.51 5.15 8.8
IOLD Output Low Drive VOUT = VOL
Data and Controls ST=1 -5.5 -8.3 -11.2 mA
ST=0 -2.8 -4.2 -5.6
IOHC ODCK High Drive VOUT = VOH
ST=1 10.1 20.6 35.1 mA
ST=0 5.0 10.3 17.6
IOLC ODCK Low Drive VOUT = VOL
ST=1 -11.1 -16.7 -22.4 mA
ST=0 -5.5 -8.3 -11.2
VID Differential Input Voltage 75 1000 mV
Single Ended Amplitude
µA
1
IPD Power-down Current 25
IPDL Output leakage current to ground in 10 uA
high impedance mode (PD, PDO =
LOW)
ICCR Receiver Supply Current CLOAD = 10pF
REXT_SWING = 680 Ω
2
DCLK=86MHz, 1-pixel/clock mode 157 182 mA
3
Typical Pattern
CLOAD = 10pF
REXT_SWING = 680 Ω
2
DCLK=86MHz, 1-pixel/clock mode 172 194 mA
4
Worst Case Pattern
1
Notes: The transmitter must be in power-down mode, powered off, or disconnected for the current to be under this maximum.
2
For worst case I/O power consumption.
3
The Typical Pattern contains a gray scale area, checkerboard area, and text.
4
Black and white checkerboard pattern, each checker is one pixel wide.

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Silicon Image, Inc. SiI141 SiI/DS-0004-D

AC Specifications
Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are given below.
Symbol Parameter Conditions Min Typ Max Units
TDPS Intra-Pair (+ to -) Differential Input Skew 86 MHz 470 ps
One pixel / clock
TCCS Channel to Channel Differential Input Skew 86 MHz 7 ns
One pixel / clock
1,2
TIJIT Worst Case Differential Input Clock Jitter tolerance
65 MHz, One Pixel / Clock 465 ps
86 MHz, One Pixel / Clock 350 ps
DLHT Low-to-High Transition Time: Data and Controls CL = 10pF, ST=1 5.2
CL = 5pF, ST=0 4.4 ns
ODCK CL = 10pF, ST=1 2.3 ns
CL = 5pF, ST=0 1.8
DHLT High-to-Low Transition Time: Data and Controls CL = 10pF, ST=1 3.8
CL = 5pF, ST=0 3 ns
ODCK CL = 10pF, ST=1 2 ns
CL = 5pF, ST=0 1.5
4
TSOF Data/Control Setup Time to ODCK falling (OCK_INV=0): CL = 10pF, ST=1 2
65 MHz, One Pixel / Clock, PIXS = 0 CL = 5pF, ST=0 1.6 ns
43 MHz, Two Pixel / Clock, PIXS = 1 CL = 10pF, ST=1 5 ns
CL = 5pF, ST=0 5
4
THOF Data/Control Hold Time to ODCK falling (OCK_INV=0): CL = 10pF, ST=1 6
65 MHz, One Pixel / Clock, PIXS = 0 CL = 5pF, ST=0 6 ns
43 MHz, Two Pixel / Clock, PIXS = 1 CL = 10pF, ST=1 12 ns
CL = 5pF, ST=0 12
RCIP ODCK Cycle Time (1 pixel/clock) 11.6 50 ns
FCIP ODCK Frequency (1 pixel/clock) 20 86 MHz
RCIP ODCK Cycle Time (2 pixels/clock) 23.3 100 ns
FCIP ODCK Frequency (2 pixels/clock) 10 43 MHz
RCIH ODCK High Time CL = 10pF, ST=1 5
3
65 MHz, One Pixel / Clock, PIXS = 0 CL = 5pF, ST=0 4.4 ns
3
43 MHz, Two Pixel / Clock, PIXS = 1 CL = 10pF, ST=1 9 ns
CL = 5pF, ST=0 8.2
RCIL ODCK Low Time CL = 10pF, ST=1 6
3
65 MHz, One Pixel / Clock, PIXS = 0 CL = 5pF, ST=0 5 ns
3
43 MHz, Two Pixel / Clock, PIXS = 1 CL = 10pF, ST=1 9 ns
CL = 5pF, ST=0 9
1
THSC Link disabled (DE inactive) to SCDT low 160 ms
5
Link disabled (Tx power down) to SCDT low 200 250 ms
TFSC Link enabled (DE active) to SCDT high 40 Falling DE
edges
TPDL Delay from PD/ PDO Low to high impedance outputs 8 ns
1
Notes: Jitter defined as per DVI 1.0 Specification, Section 4.6 Jitter Specification.
2
Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electrical Measurement Procedures.
3
Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.
4
The setup and hold timing for the data and controls relative to the ODCK rising edge (OCK_INV=1) is by design the same
as the falling edge timing.
5
Measured when transmitter was powered down (see SiI/AN-0005 “PanelLink Basic Design /Application Guide,” Section 2.4).

Timing Diagrams

80% 80%

SiI141 10pF (5pF)

20% 20%

DLHT DHLT

Figure 1. Digital Output Transition Times

3 Subject to Change without Notice

Silicon Image, Inc. SiI141 SiI/DS-0004-D

RCIP
RCIH
VIH VIH

VIL VIL
RCIL

Figure 2. Receiver Clock Cycle/High/Low Times

RX0
VDIFF=0V

RX1

TCCS VDIFF=0V

RX2

Figure 3. Channel-to-Channel Skew Timing

Output Timing

VOH
ODCK VOL
TSOF THOF
Q[35:0], VOH VOH
VSYNC,
HSYNC, VOL VOL
CTL[3:1]
DE

Figure 4. Output Data Setup/Hold Times to ODCK

PD VIL
TPDL
Q[35:0],DE,
VSYNC,HSYNC,
CTL[3:1]

Figure 5. Output Signals Disabled Timing from PD Active

THSC
DE

SCDT

TFSC

DE

SCDT

Figure 6. SCDT Timing from DE Inactive/Active

4 Subject to Change without Notice

Silicon Image, Inc. SiI141 SiI/DS-0004-D

Output Pin Description

Pin Name Pin # Type Description
Q35 – Q0 See Out Output Data [35:0].
SiI141 Output data is synchronized with output data clock (ODCK).
Pin When PIXS is low Q35-Q24 are low and Q23-Q0 output 24-bit/pixel data.
Diagram When PIXS is high Q17-Q0 output the even numbered pixels (pixel 0, 2, 4, ... , etc.) and Q35-Q18 output the
odd numbered pixels (pixel 1, 3, 5, ... , etc.).
Refer to the TFT Signal Mapping (SiI/AN-0008) and DSTN Signal Mapping (SiI/AN-0007) application notes
which tabulate the relationship between the input data to the transmitter and output data from the receiver.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal
pull-down device brings each output to ground.
ODCK 36 Out Output Data Clock.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal
pull-down device brings each output to ground.
DE 41 Out Output Data Enable.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal
pull-down device brings each output to ground.
HSYNC 12 Out Horizontal Sync output control signal.
VSYNC 14 Out Vertical Sync output control signal.
CTL1 8 Out General output control signal 1. This pin is not controlled by PDO.
CTL2 9 Out General output control signal 2
CTL3 10 Out General output control signal 3.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal
pull-down device brings each output to ground.

Configuration Pin Description

Pin Name Pin # Type Description
OCK_INV 80 In ODCK Polarity. A low level selects normal ODCK output, which enables data latching on the falling edge. A high
level (3.3V) selects inverted ODCK output, which enables data latching on the rising edge. Both conditions are for
color TFT panel support. For color 24-bit DSTN panel support, please refer to the DSTN Signal Mapping
(SiI/AN-0008-A) application note.
PIXS 5 In Pixel Select. A low level indicates that output data is one pixel (up to 24-bit) per clock and a high level (3.3V)
indicates that output data is two pixels (up to 36-bit) per clock.
DF0 6 In Output Data Format. This pin controls clock and data output format. A low level indicates that ODCK runs
continuously for color TFT panel support and a high level (3.3V) indicates that ODCK is stopped (LOW) for color
24-bit DSTN panel support when DE is low. Refer to the TFT Signal Mapping (SiI/AN-0007-A) and DSTN
Signal Mapping (SiI/AN-0008-A) application notes for a table on TFT or DSTN panel support.
ST 79 In Output Driver Strength. A low level indicates low drive. A high level indicates high drive.

Power Management Pin Description

Pin Name Pin # Type Description
SCDT 7 Out SyncDetect. A high level is output when DE is toggling. A low level is output when DE is inactive.
PD 2 In Power Down (active low). A high level (3.3V) indicates normal operation and a low level indicates power down
mode. During power down mode all internal circuitry is powered down and digital I/O are set the same as when
PDO is asserted. (see PDO pin description).
PDO 3 In Power Down Output (active low). A high level indicates normal operation. A low level puts the output drivers only into
a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. There is an
internal pull-up resistor on PDO that defaults the chip to normal operation if left unconnected. SCDT and CTL1 are
not tri-stated by this pin.

Differential Signal Data Pin Description

Pin Name Pin # Type Description
RX0+ 70 Analog TMDS Low Voltage Differential Signal input data pairs.
RX0- 71
RX1+ 67
RX1- 68
RX2+ 64
RX2- 65
RXC+ 74 Analog TMDS Low Voltage Differential Signal input clock pair.
RXC- 73
EXT_RES 76 Analog Impedance Matching Control. Resistor value should be ten times the characteristic impedance of the cable. In the
common case of 50Ω transmission line, an external 500Ω resistor must be connected between AVCC and this
pin.

5 Subject to Change without Notice

Silicon Image, Inc. SiI141 SiI/DS-0004-D

Reserved Pin Description

Pin Name Pin # Type Description
RSVD 1 Out This signal must be left unconnected.
RSVD 75 In This pin must be tied high.

Power and Ground Pin Description

Pin Name Pin # Type Description
VCC 39 Power Core VCC, must be set to 3.3V.
50
61
GND 11 Ground Digital GND.
37
62
OVCC 15 Power Output VCC, must be set to 3.3V.
28
48
OGND 4 Ground Output GND.
13
26
46
AVCC 63 Power Analog VCC, must be set to 3.3V.
69
AGND 66 Ground Analog GND.
72
PVCC 77 Power PLL VCC, must be set to 3.3V.
PGND 78 Ground PLL GND.

Application Information
To obtain the most updated Application Notes and other useful information for your design application, please
visit the Silicon Image web site at www.siimage.com, or contact your local Silicon Image sales office.

Ordering Information
Part Number: SiI141CT80

6 Subject to Change without Notice

Silicon Image, Inc. SiI141 SiI/DS-0004-D

Package Dimensions
80-pin TQFP Package Dimensions

Lead Length
1.00mm
80-pin Plastic TQFP
Lead Width
0.22mm

Lead Pitch
0.50mm

Body Size 12.00mm

Footprint 14.00mm
Device # SiI141CT80
Lot # LNNNNN.NLLL
Date Code # XXYY
SiI Rev. # X.XX

Package Height Body Thickness

1.0mm max. Clearance 1.0mm
0.15mm max.
Body Size 12.00mm

Footprint 14.00mm

Copyright Notice
This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or send/transmit any part of this documentation
without the express written permission of Silicon Image, Inc.

Trademark Acknowledgment
PanelLink and the PanelLink Digital logo are registered trademarks of Silicon Image, Inc. Silicon Image, the Silicon Image logo and TMDS are
trademarks of Silicon Image, Inc. VESA is a registered trademark of Video Electronics Standards Association. TMDS is a licensed trademark of
VESA. All other trademarks are the property of their respective holders.

Disclaimer
This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the information in this document as
necessary. The customer should make sure that they have the most recent data sheet version. Silicon Image, Inc. holds no responsibility for any
errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any
patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights.

Ordering Information
Part Number: SiI141CT80

© 1999 Silicon Image, Inc. 7/99 SiI/DS-0004-D

Silicon Image, Inc. Tel: 408-873-3111

10131 Bubb Road Fax: 408-873-0446
Cupertino, CA 95014 E-Mail: salessupport@siimage.com
USA Web: www.siimage.com
www.panellink.com

7 Subject to Change without Notice