Department of ECE, Anna University, Chennai

Internal Assessment – II
Sem : III Programme : B.E Mon/Year : Oct 2020
Subject : EC5303 DIGITAL SYSTEM DESIGN
Time : 90 mins Answer All Questions Max Mark: 50

CO1 Use Boolean algebra and simplification procedures relevant to digital

logic.

CO2 Design various combinational digital circuits using logic gates.

CO3 Ability to analyse and design synchronous sequential circuits.

CO4 Ability to analyse and design asynchronous sequential circuits.

CO5 Ability to build logic gates and use programmable devices

S.No Questions Marks BL CO

PART – A 7 X 2 = 14

1 Implement the following Boolean function with a MUX 2 L3 2

F(A,B,C,D)= ∑ (0,1,3,4,8,9,15)
2 The serial adder of the given Figure uses two four bit registers. 2 L3 2
Register A holds the binary number 0101 and register B holds 0111.
The carry flip flop is initially reset to 0. List the binary
values in register A and the carry flip flop after each shift.

3 What is the function of priority Encoder. 2 L1 2

4 Write the function table of SR latch using NAND gate with control 2 L1 3
input.
5 Write the characteristic equation of all Flipflops 2 L1 3
6 A flip flops has a 5 ns delay from the time the clock edge occurs to 2 L2 3
the time the output is complemented. What is the maximum delay in a
10bit binary ripple counter that uses these flip flops? What is the
maximum frequency at which the counter can operate reliably?

7 How many states are possible for a K-bit Ring counter and K-bit 2 L1 3
Johnson Counter.

PART – B 2 X 12 = 24

8a (i). Construct a 5 to 32 line decoder with four 3 to 8 line 12 L2,L3 2

decoders with enable and a 2 to 4 line decoder. Use block
Diagram for the Component. (4)
(ii). Design a Decimal Adder circuit. (8)
Or
8b (i). Construct a 16x1 MUX with two 8x1 and 2x1 MUX. 12 L2,L3 2
Use block Diagram for the Component. (4)
(ii). Design a 3-bit Magnitude Comparator Circuit. (8)
9 .a Design a 3-bit synchronous counter using JK FF. 12 L3 3
Or
9.b A Sequential circuit has two JK FF's A and B, two inputs x and y and 12 L2,L3 3
one output z. The FF input equations and circuit output equations are:
JA=Bx+B'y' KA= B'xy' JB= A'x KB= A+xy'
Z=Ax'y'+Bx'y'
(i). Derive the state equations for A and B.
(ii). Tabulate the State table.
(iii). Draw the logic diagram of the circuit.

PART – C 1 X 12 =1 2

10 The counter of given Figure has two control inputs—Load (L) and 12 L4 3
Count (C)—and a data input, (I).
a. Obtain the characteristic table and equation
b. Derive the flip‐flop input equations for J and K of the first
stage in terms of L, C, and I