Digital System Design

LAB Report#01

Submitted By Taha Saeed

Registration No. FA18-EEE-032

Class EEE-7

Submitted To Dr. Fasil Sadiqi

Date 9/30/2021
 LAB # 01 Introduction to Verilog, ModelSim, Xilinx ISE
Design Suite and FPGA

In-Lab Task:
Verilog Code:
module Lab1_T1(
input A,
input B,
output S,
output C );
xor G1(S,A,B);
and G2(C,A,B);
endmodule

Test Bench:
module DUT_LAB1;

// Inputs
reg A;
reg B;

// Outputs
wire S;
wire C;

integer a;
integer b;

// Instantiate the Unit Under Test (UUT)

Lab1_T1 uut (
.A(A),
.B(B),
.S(S),
.C(C)
);

initial begin
// Initialize Inputs

for(a=0; a<=1; a=a+1)

 begin
for(b=0; b<=1; b=b+1)
begin
A=a; B=b;
#100;
end
end

$finish;

// Add stimulus here

end

endmodule

UCF File:
NET "A" LOC=H18;
NET "B" LOC=G18;
NET "S" LOC=J15;
NET "C" LOC=J14;
Simulation:

Post Lab Task:

Verilog Code:
module BinToBcd(A,Unit,Ten,Hund);
output reg [3:0]Hund;
output reg [3:0]Ten;
output reg [3:0]Unit;
input [9:0]A;
integer i;
always @ (*)
begin
Hund = 4'd0;
Ten = 4'd0;
Unit = 4'd0;
for (i=9; i>=0; i=i-1)
begin
if (Hund >= 5)
begin
Hund = Hund + 3;
end
if (Ten >= 5)
begin
Ten=Ten+3;
end
if (Unit >= 5)
begin
Unit=Unit+3;
end
Hund=Hund<<1;
Hund[0]=Ten[3];
Ten=Ten<<1;
Ten[0]=Unit[3];
Unit=Unit<<1;
Unit[0]=A[i];
end
end
endmodule

Test Bench Code:

module DUT_BinToBCD;

// Inputs
reg [9:0] A;

// Outputs
wire [3:0] Unit;
wire [3:0] Ten;
wire [3:0] Hund;
integer i=0;

// Instantiate the Unit Under Test (UUT)

BinToBcd uut (
.A(A),
.Unit(Unit),
.Ten(Ten),
.Hund(Hund)
);
 initial begin
// Initialize Inputs
for(i=0;i<=999;i=i+1)
begin
A=i;
#10;
end

// Add stimulus here

end

endmodule

Simulation:
Conclusion:
In this lab I revised how to use Xilinx ISE Design suite software to write Verilog code,
simulate it and burn code on the Nexys 2 board. There are three types of coding levels in
Verilog which are as follows:
1. Gate Level:
We make individual gates and connect the according to our circuit.
2. Data Flow:
We write the final equation of our circuit and the CAD tool makes the circuit according
to the equation.
3. Behavioral Level:
We use this when we don’t know the circuit diagram or final equation of our circuit but
know the output for each input. We tell the CAD tool the behavior of our circuit and ot
develops the circuit itself.

Verilog is a non-sequential programming language meaning that all the lines in our code are
executed at the same time. Therefore we avoid using Loops in our code as there is no hardware
representation of Loop.