Name:_________________ Roll No:__________

Lab: Computer Architecture (8th Term)

LAB # 5
Strengthening of concepts of behavioural modelling with deep
familiarization with FPGA board.
Continued…

Note : All modules are attached at the end of manual.

Procedure:
1. Launch the Xilinx ISE 7.1 software as follows:

Start >> Programs >> Xilinx ISE 7.1 >> Project Navigator

2. Start a new project as follows:

File >> New Project

3. Give the project name as: Disp

4. Select the project location as follows:

C:\CA05\2005_E_205

5. Select the top level module type as : HDL

6. Click Next.
7. In the next window of ‘Select Device and Design Flow for the Project’:
Select the simulator as : ISE simulator
In the Device Family option,
Select Spartan3
In the Device option
Select xc3s200
In the Package option
Select ft256
In the Speed Grade option
Select -5
In the Top Level Module Type option
Select HDL
In the Synthesis Tool option
Select XST(VHDL/Verilog)
In the Simulator option
Select ISE Simulator
In the Generated Simulation Language option
Select Verilog

Then, select Next.

8. In the next window of ‘Create a new source’:

Simply click Next. We shall not use this option for the time
being.
9. In the next window of ‘Add Existing Sources’:
Simply click Next. We shall not use this option for the time
being.
10. In the next window, click Finish.
11. Just right click in the “sources in project” space and select “add copy
of Source”.

And copy all the files present in Lab5 folder present in desktop.
Synthesis the code and see its behavioural simulation on test bench.

Implement the counter on FPGA using the following instructions.

1) See the attached file for pin configuration of seven segment display.
2) Assign the pin package in user constraints according to the above
configuration.
3) Assign clk (input) to T9 pin in the package.

After saving the pin package assignment. Just implement the design and generate
programming file and see the output.

Note : You will be graded only if you are able to run the implement the program on
the FPGA Board.
 Module Definition:

Controller:
Connectivity:

Code:
//Interface
module Interface(a , b ,clk , c_i, rst, u_d ,disp_ind, disp_sel);

input clk, c_i, rst, u_d ;

input [3:0] a ,b;
output [6:0] disp_ind;
output [3:0] disp_sel;
wire clk_div;
wire [1:0] clk_div2;

controller f1 (clk ,disp_sel ,clk_div ,clk_div2);

connectivity f2 (clk_div2 ,a ,b, c_i ,rst, u_d, clk_div, disp_ind);

endmodule

//connectivity
module connectivity(sel, a, b, c_i, rst, u_d, clk, out);
input [1:0] sel;
input [3:0] a, b;
input c_i, rst, u_d, clk;
output [6:0] out;

wire [3:0] sum, out_c1, out_c2, dec_in ;

wire o_c;

bcd_adder ba(a, b, c_i, sum, o_c);

counter c1(rst, u_d, clk, out_c1);
arbitrary_count_sequence c2(clk, out_c2);
 mux_4to1_4bit m({3'b0, o_c}, sum, out_c1, out_c2, sel, dec_in);
binary_to_7seg_decoder bd(dec_in, out);

endmodule

// controller
module controller(clk, out_anode, clk_div2, clk_div);

input clk;
output [1:0]clk_div2;
output clk_div;
output [3:0]out_anode;

crude_clock_div2 f1(clk, clk_div2);

crude_clock_divider f2 (clk,clk_div);
dec_for_anode_cntrl f3(clk_div2 , out_anode);

endmodule

// arbitrary_count_sequence
module arbitrary_count_sequence(clk, out);
input clk;
output reg [3:0] out = 0;
reg [2:0] count = 0;

always @ (posedge clk)

if (count == 5)
count <= 0;
else
count <= count + 1;

always @ (count)
case (count)
0 : out = 4'hA;
1 : out = 4'h1;
2 : out = 4'hE;
3 : out = 4'h9;
4 : out = 4'h6;
5 : out = 4'h3;
default : out = 4'hA;
endcase
endmodule

// bcd_adder
module bcd_adder(addend, augend, carry_in, S, output_carry);

input [3:0] addend, augend;

input carry_in;
 output reg [3:0] S;
output output_carry;

wire carry;
reg K;
reg [3:0] Z;

always @ (addend or augend or carry_in)

{K,Z} = addend + augend + carry_in;

always @ (Z or carry)
S = {1'b0, carry, carry, 1'b0} + Z;

assign carry = K | (Z[3] & Z[2]) | (Z[3] & Z[1]);

assign output_carry = carry;

endmodule

// counter
module counter(rst, up_down, clk, out);
input rst, up_down, clk;
output reg [3:0] out = 0;

always @ (posedge clk)

begin
if (rst)
out <= 0;
if (~ rst && ~up_down)
out <= out + 1;
if (~ rst && up_down)
out <= out - 1;
end

endmodule

// mux_4to1_4bit
module mux_4to1_4bit(a, b, c, d, sel, out);
input [3:0] a, b, c, d;
input [1:0] sel;
output reg [3:0] out;

always @ (a or b or c or d or sel)
case (sel)
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
 default : out = a;
endcase

endmodule

// binary_to_7seg_decoder
module binary_to_7seg_decoder(in, out);
input [3:0] in;
output reg [6:0] out;

always @ (in)
case (in)
4'h0 : out = 7'b0000001;
4'h1 : out = 7'b1001111;
4'h2 : out = 7'b0010010;
4'h3 : out = 7'b0000110;
4'h4 : out = 7'b1001100;
4'h5 : out = 7'b0100100;
4'h6 : out = 7'b0100000;
4'h7 : out = 7'b0001111;
4'h8 : out = 7'b0000000;
4'h9 : out = 7'b0000100;
4'hA : out = 7'b0001000;
4'hB : out = 7'b1100000;
4'hC : out = 7'b0110001;
4'hD : out = 7'b1000010;
4'hE : out = 7'b0110000;
4'hF : out = 7'b0111000;
endcase

endmodule

// crude_clock_div2
module crude_clock_div2(clk, clk_out2);
input clk;
output [1:0] clk_out2;

reg [31:0] count =

32'b00000000000000000000000000000000;

always @ (posedge clk)

begin
count <= count + 1;
end

assign clk_out2 = count[18:17];

endmodule
// crude_clock_divider
module crude_clock_divider(clk_in, clk_out);
input clk_in;
output clk_out;

reg [31:0] count = 32'b00000000000000000000000000000000;

always @ (posedge clk_in)

begin
count <= count + 1;
end

assign clk_out = count[23];

endmodule

// dec_for_anode_cntrl
module dec_for_anode_cntrl(sel ,out);

input [1:0] sel;

output reg [3:0] out;

always @ (sel)
begin
case(sel)
0: out = 4'b1110;
1: out = 4'b1101;
2: out = 4'b1011;
3: out = 4'b0111;
endcase
end

endmodule