ISET DE GABES AU 2015/2016 sem 1

II N5
EXAMEN
ENSEIGNANT
CLASSE
: M. TAYARI LASSAAD
: AII51
FPGA
DATE : Le 05 /01/2016 NOM :………….………….
DUREE :1 h 30 mn PRENOM :……………………..
DOCUMENTS :Non autorisés

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Exercice n°1 : (03 points) …………………………………………………………………………

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Ecrire la description VHDL du circuit …………………………………………………………………………
ci-dessous (convertisseur code binaire …………………………………………………………………………
-> code de Gray) sur 3 bits: …………………………………………………………………………
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Exercice n°2 : (05 points) …………………………………………………………………………
Soit la tranche d'UAL représentée ci-dessous : …M S1 S0 Opération
0 0 0 Fi=Ai+Bi+Ci
Ci+1=Retenu
0 0 1 Fi =Ai-Bi-Ci
Ci+1=Signe
(1 :négatif,0 :positif)
0 1 0 Fi = Ai+1+Ci
Ci+1=Signe
0 1 1 Fi =Ai-1
Ci+1=Signe
1 0 0 Fi=Ai and Bi
1 0 1 Fi=Ai or Bi
1 1 0 Fi=Ai xor Bi
1 1 1 Fi=not Ai

et correspondant à l'entity suivante :

entity slice is port(ai,bi,ci,s0,s1,m: in std_logic;
ciplus1,fi: out std_logic);
end slice;

Ecrire (completer) sa description VHDL dans le style structurel en suivant le modèle ci-
dessous :
entity arithmetic_unit is
port(a,b,c,s0,s1: in std_logic;
cout,res: out std_logic);
end arithmetic_unit;

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 Ne rien écrire ici

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architecture dataflow of arithmetic_unit is
begin
...
.
.
.
.
end dataflow;
entity logic_unit is
port(a,b,s0,s1: in std_logic;
res: out std_logic);
end logic_unit;
architecture dataflow of logic_unit is
begin
....
.
.
.
.
.
.
end dataflow;
entity mux is
port(i1,i2,sel: in std_logic;
res: out std_logic);
end mux;
architecture arch1 of mux is
begin
....
.
.
.
end arch1;
architecture ual of slice is
.
.
begin
..
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
end ual;

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Exercice n°3 : (06 points)
Soit le programme ci-contre.
Entity prog is
port(
A: in std_logic_vector(7 downto 0);
B: in std_logic_vector(7 downto 0);
S: in std_logic_vector(1 downto 0);
R: out std_logic_vector(7 downto 0) );
End prog;
Architecture behv of prog is
process(A,B,S)
begin
case S is
when "00" =>
R <= A + B;
when "01" =>
R <= A - B;
when "10" =>
R <= A and B;
when "11" =>
R <= A or B;
when others =>
R <= "XXXXXXXX ";
end case;
End process;
End behv;

1) Dessiner un schéma synoptique pour ce circuit.

2) Quel est selon vous la fonction de ce circuit?

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Exercice n°4 :(05 points)
Soit le système défini par le schéma ci-dessous

1- compléter le programme VHDL correspondant ci-dessous.

Library ieee ;
Use ieee.std_logic_1164.all ;

Entity exercice4 is
port( A: ………………………………..;
B:………………………………...;
SEL:……………………………...;
CLK :……………………………. ;
O: ………………………………....);
End exercice4;

Architecture behv of exercice4 is

Signal S1,S2,S3 ………………………….;
begin
…………………………
…………………………
process(SEL)
begin
if SEL=’1’ then
…………………………
else
…………………………
end if ;
end process;

process(CLK,S3)
begin
if (CLK'event and …………) then
…………………………
end if;
end process;
end behv;

2- Retrouver l’équation logique du système.

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3- Implanter le système dans le PAL20R8 suivant :

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NOM :………….………….
PRENOM :……………………..
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Bonne Chance
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