Schematics Laptop Lenovo b490 La4801126410106

5 4 3 2 1
http://laptopblue.vn
UMA & Optimus Schematics Document
D D
IVY Bridge(rPGA989)
C
Intel PCH(Panther Point) C
DY :NotInstalled
UMA:UMA platform installed
OPS:Optimus
B
HR:Huron River B
CR:Chief River
V: V-Series installed
<Core Design>
Wistron Corporation
A 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C
Title
Cover Page
Size Document Number Rev
A4 SD
LA480
Date: Friday, January 06, 2012 Sheet 1 of 103
5 ##OnMainBoard
4 3 2 1
Block Diagram
http://laptopblue.vn CPU DC/DC
INPUTS
TPS51640
OUTPUTS
42~43
VRAM
(UMA/Optimus co-lay) DCBATOUT
SYSTEM DC/DC
VCC_CORE
TPS51219 45
2GB/1GB/512MB4 LA480 LA580 INPUTS OUTPUTS
D 88,89,90,91
DCBATOUT 1D05V_VTT
D
Project Code 91.4TD01.001 91.4TE01.001
DDR3 SYSTEM DC/DC
800MHz Intel CPU PCB P/N 11264 11273 TPS51225 41
Revision SC SC INPUTS OUTPUTS

3D3V_AUX_S5
NVIDIA PCIe x 16
IVY Bridge DCBATOUT 5V_S5
3D3V_S5
DDRIII 1066/1333/1600 Channel A DDRIII Slot 0

(Discrete only) SYSTEM DC/DC
N13P-GL (V) 1066/1333/1600 14
DDRIII: 1066/1333/1600 MHz RT8207M 46
N13M-GE1 (B) INPUTS OUTPUTS
4,5,6,7,8,9,10
DDRIII 1066/1333/1600 Channel B DDRIII Slot 1 0D75V_S0
83.84,85,86,87
1066/1333/1600 15 DCBATOUT 1D5V_S3
DDR_VREF_S3
FDI x 4 x 2 SYSTEM DC/DC

HDMI DMI x 4 TPS51640 44
(UMA only) 71.08111.N03, IC PCIE CTRL RTL8111F-CGT QFN 48P
C 51
HDMI
INPUTS OUTPUTS C
GLAN DCBATOUT VCC_GFXCORE
LCD LVDS PCIE x 1
RJ45
49 REALTEK
CONN 59 VGA
RGB CRT
Intel RTL8111F 31
TPS51728 92
CRT INPUTS OUTPUTS
50 PCH PCIE x 1/USB2.0 x 1
Mini-Card DCBATOUT VGA_CORE
Bluetooth USB2.0 x 3 Panther Point WLAN 65

TI CHARGER
63 BQ24737 40
USB 3.0/2.0 ports (14) Mini-Card
SATA x 1/USB2.0 x 1 INPUTS OUTPUTS
ETHERNET (10/100/1000Mb) 66
CAMERA +DC_IN_S5
49 High Definition Audio +PBATT DCBATOUT
26
SATA ports (6) SYSTEM DC/DC
USB 3.0 x 2 USB x 2
Finger Print BD Finger Print 64 PCIE ports (8) RT8068A 47
LPC I/F INPUTS OUTPUTS
CardReader ACPI 1.1
SD/MMC+/MS/ USB 2.0 x 1 USB 2.0 x 2 USB x 2 3D3V_S5 1D8V_S0
B MS Pro/xD ALCOR B
AU6435B52
LDO
74 RT8207 46
17,18,19,20,21,22,23,24,25
AZALIA INPUTS
26 OUTPUTS
SATA x 2 HDD
56 5V_S5 0D75V_S0
PCB LAYER
SPI
(V only)
ODD
LPC Bus
Internal DMIC 56 L1:Top L5:VCC

Azalia
L2:GND L6:Signal
CODEC L3:Signal L7:GND
(B only) Analog DMIC
REALTEK Flash ROM LPC debug port L4:Signal L8:Signal
71
8MB 60
Combo ALC269Q-VC2
Jack 29
KBC SMBus
NUVOTON
NPCE885G 27
A <Core Design>
A
2CH SPEAKER
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
G-Sensor Touch Int. Thermal Fan Title

PAD KB EMC2103-2-AP 28 Block Diagram
(V only) 79 69 69 2528 Size Document Number Rev
A3 SD
LA480
5 4 3 2 1
PCH Strapping Chief River Schematic Checklist Rev0.72 Processor Strapping Chief River Schematic Checklist Rev0.72
Name
SPKR
Schematics Notes
Reboot option at power-up
http://laptopblue.vn Pin Name Strap Description Configuration (Default value for each bit is
1 unless specified otherwise)
Default
Value
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ CFG[2] PCI-Express Static 1: Normal Operation.
- 10-kΩ weak pull-up resistor. Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1
Lane Reversal 0:
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
Disabled - No Physical Display Port attached to
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. CFG[4] 1: Embedded DisplayPort.
D GNT2#/GPIO53 Mobile: Used as GPIO only 0 D
GNT1#/GPIO51 Pull-up resistors are not required on these signals. Enabled - An external Display Port device is
0: connectd to the EMBEDDED display Port
If pull-ups are used, they should be tied to the Vcc3_3power rail.
CFG[6:5] PCI-Express 11 : x16 - Device 1 functions 1 and 2 disabled
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. Port Bifurcation 10 : x8, x8 - Device 1 function 1 enabled ;
SPI_MOSI function 2 disabled
Straps 11
Disable Danbury:Left floating, no pull-down required. 01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm enabled
weak pull-up resistor [CRB has it pulled up
NV_ALE with 1-kohm no-stuff resistor] CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training 1
Disable Danbury: Leave floating (internal pull-down)
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features. Voltage Rails
HAD_DOCK_EN# High (1) - Security measure defined in the Flash Descriptor will be enabled. POWER PLANE VOLTAGE DESCRIPTION
Platform design should provide appropriate pull-up or pull-down depending on ACTIVE IN
C
/GPIO[33] 5V_S0 5V C
the desired settings. If a jumper option is used to tie this signal to GND as 3D3V_S0 3.3V
required by the functional strap, the signal should be pulled low through a weak 1D8V_S0 1.8V
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. 1D5V_S0 1.5V
1D05V_VTT 1.05V
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal 1D0V_S0 1.0V S0 CPU Core Rail
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for VCCSA 0.9 - 0.675V Graphics Core Rail
strapping functions. 0D75V_S0 0.75V
VCC_CORE 0.35V to 1.5V
VCC_GFXCORE 0.4 to 1.25V
1D8V_VGA_S0 1.8V
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. 3D3V_VGA_S0 3.3V
1V_VGA_S0 1V
HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low(0) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no
GPIO15 5V_USBX_S3 5V
confidentiality. High(1) - Intel ME Crypto Transport Layer Security (TLS) cipher 1D5V_S3 1.5V S3
suite with confidentiality. DDR_VREF_S3 0.75V
Note : This is an un-muxed signal.
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. BT+ 6V-14.1V
Sampled at rising edge of RSMRST#. DCBATOUT 6V-14.1V
CRB has a 1-kohm pull-up on this signal to +3.3VA rail. 5V_S5 5V
5V_AUX_S5 5V All S states AC Brick Mode only
3D3V_S5 3.3V
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down 3D3V_AUX_S5 3.3V
GPIO8 using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled. 1D05V_LAN 1.05V S0/M0, SX/M3 ON whenever iAMT is active
B B
Default = Do not connect (floating)

3D3V_M 3.3V
High(1) = Enables the internal VccVRM to have a clean supply for 1D05V_M 1.05V S0/M0, SX/M3, WOL_EN ON for iAMTLegacy WOL
GPIO27 analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails. 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states
SATA Table
3D3V_AUX_S5 3.3V G3, Sx Powered by Li Coin Cell in G3 SATA
USB Table port9 is debug port and 3D3V_S5 in Sx
Pair Device
PCIe Routing Pair Device SMBus ADDRESSES 0 HDD1
0 USB3.0 ext port 1
LANE1 X 1 mSATA
1 USB3.0 ext port 2 I 2 C / SMBus Addresses Ref Des Chief River CRV
2 N/A
2 USB3.0 ext port 3 Device Address Hex Bus
LANE2 Mini Card2(WWAN) 3 N/A
3 USB3.0 ext port 4
EC SMBus 1 BAT_SCL/BAT_SDA 4 ODD
LANE3 Card Reader 4 BLUETOOTH (USB1.1) Battery BAT_SCL/BAT_SDA
CHARGER BAT_SCL/BAT_SDA 5 ESATA
LANE4 Mini Card1(WLAN) 5 Fingerprint (USB1.1)
6 X
EC SMBus 2 SML1_CLK/SML1_DATA
A
LANE5 X 7 X PCH SML1_CLK/SML1_DATA
<Core Design> A
eDP SML1_CLK/SML1_DATA
LANE6 Intel GBE LAN / LAN 8 Mini Card2 (WWAN) Wistron Corporation
9 USB ext. port 4 / E-SATA /USB CHARGER PCH SMBus PCH_SMBDATA/PCH_SMBCLK 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
SO-DIMMA (SPD) PCH_SMBDATA/PCH_SMBCLK Taipei Hsien 221, Taiwan, R.O.C.
LANE7 X 10 CARD READER SO-DIMMB (SPD)
Digital Pot
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK Title
G-Sensor PCH_SMBDATA/PCH_SMBCLK
LANE8 Express Card 11 Mini Card1 (WLAN) MINI PCH_SMBDATA/PCH_SMBCLK Table of Content
12 CCD Size Document Number Rev
A3 SD
13 New Card LA480
5 4 3 2 1
5 4 3 2 1
SSID = CPU http://laptopblue.vn

01.00IVY.000 IVY BRIDGE ORCAD SYMBOL.
Signal Routing Guideline:
Note: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
Intel DMI supports both Lane PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap. 1D05V_VTT
CPU1A 1 OF 9 NOTE.
J22 PEG_IRCOMP_R R401 1 2
PEG_ICOMPI If PEG is not implemented, the RX&TX pairs can be left as No Connect
D 19 DMI_TXN[3:0]
DMI_TXN0 B27
SANDY PEG_ICOMPO J21
H22
24D9R2F-L-GP D
DMI_TXN1 DMI_RX#0 PEG_RCOMPO
B25 DMI_RX#1
DMI_TXN2 A25 DMI_RX#2 PEG_RXN[0..15] 83
DMI_TXN3 B24 K33 PEG_RXN15
DMI_RX#3 PEG_RX#0 PEG_RXN14
19 DMI_TXP[3:0] PEG_RX#1 M35
DMI_TXP0 B28 L34 PEG_RXN13
DMI_TXP1 DMI_RX0 PEG_RX#2 PEG_RXN12
B26 DMI_RX1 PEG_RX#3 J35
DMI
DMI_TXP2 A24 J32 PEG_RXN11
DMI_TXP3 DMI_RX2 PEG_RX#4 PEG_RXN10
B23 DMI_RX3 PEG_RX#5 H34
H31 PEG_RXN9
19 DMI_RXN[3:0] PEG_RX#6
DMI_RXN0 G21 G33 PEG_RXN8
DMI_RXN1 DMI_TX#0 PEG_RX#7 PEG_RXN7
E22 DMI_TX#1 PEG_RX#8 G30
DMI_RXN2 F21 F35 PEG_RXN6
DMI_RXN3 DMI_TX#2 PEG_RX#9 PEG_RXN5
D21 DMI_TX#3 PEG_RX#10 E34
E32 PEG_RXN4
19 DMI_RXP[3:0] PEG_RX#11
DMI_RXP0 G22 D33 PEG_RXN3
DMI_RXP1 DMI_TX0 PEG_RX#12 PEG_RXN2
D22 DMI_TX1 PEG_RX#13 D31
PCI EXPRESS* - GRAPHICS

DMI_RXP2 F20 B33 PEG_RXN1
DMI_RXP3 DMI_TX2 PEG_RX#14 PEG_RXN0
C21 DMI_TX3 PEG_RX#15 C32
PEG_RXP[0..15] 83
J33 PEG_RXP15
PEG_RX0 PEG_RXP14
PEG_RX1 L35
K34 PEG_RXP13
19 FDI_TXN[7:0] PEG_RX2
FDI_TXN0 A21 H35 PEG_RXP12
FDI_TXN1 FDI0_TX#0 PEG_RX3 PEG_RXP11
Note: H19 FDI0_TX#1 PEG_RX4 H32
Intel FDI supports both Lane FDI_TXN2 E19 G34 PEG_RXP10
F18 G31
Intel(R) FDI
Reversal and polarity inversion FDI_TXN4 B21
FDI0_TX#3 PEG_RX6
F33 PEG_RXP8
but only at PCH side. This is FDI1_TX#0 PEG_RX7
C enabled via a soft strap.
FDI_TXN5
FDI_TXN6
C20
D18
FDI1_TX#1 PEG_RX8 F30
E35
PEG_RXP7
PEG_RXP6 C
E17 FDI1_TX#3 PEG_RX10 E33
F32 PEG_RXP4
PEG_RX11 PEG_RXP3
19 FDI_TXP[7:0] PEG_RX12 D34
FDI_TXP0 A22 E31 PEG_RXP2
FDI_TXP1 FDI0_TX0 PEG_RX13 PEG_RXP1
G19 FDI0_TX1 PEG_RX14 C33
FDI_TXP2 E20 B32 PEG_RXP0 PEG Static Lane Reversal
FDI0_TX2 PEG_RX15 PEG_TXN[0..15] 83
FDI_TXP3 G18
FDI_TXP4 FDI0_TX3 PEG_C_TXN15 C401 SCD22U10V2KX-1GP PEG_TXN15
FDI_TXP5
B20 FDI1_TX0 PEG_TX#0 M29
PEG_C_TXN14 C402
1 2 OPS SCD22U10V2KX-1GP PEG_TXN14
FDI_TXP6
C19 FDI1_TX1 PEG_TX#1 M32
PEG_C_TXN13 C403
FDI_TXP7
D19 FDI1_TX2 PEG_TX#2 M31
PEG_C_TXN12 C404
F17 FDI1_TX3 PEG_TX#3 L32
PEG_C_TXN11 C405
PEG_TX#4 L29
PEG_C_TXN10 C406
19 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#5 K31
PEG_C_TXN9 C407
19 FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#6 K28
PEG_C_TXN8 C408
Note: PEG_TX#7 J30 1 2 OPS
Lane reversal does not apply to H20 J28 PEG_C_TXN7 C409 1 2 OPS SCD22U10V2KX-1GP PEG_TXN7
19 FDI_INT FDI_INT PEG_TX#8
H29 PEG_C_TXN6 C410 1 2 OPS SCD22U10V2KX-1GP PEG_TXN6
FDI sideband signals. PEG_TX#9 PEG_C_TXN5 C411 SCD22U10V2KX-1GP PEG_TXN5
19 FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#10 G27
PEG_C_TXN4 C412
19 FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#11 E29
PEG_C_TXN3 C413
PEG_TX#12 F27
PEG_C_TXN2 C414
1D05V_VTT PEG_TX#13 D28
PEG_C_TXN1 C415
PEG_TX#14 F26
PEG_C_TXN0 C416
R402 1 PEG_TX#15 E25 1 2 OPS
2 24D9R2F-L-GP DP_COMP A18 EDP_COMPIO PEG_TXP[0..15] 83
A17 M28 PEG_C_TXP15 C417 1 2 OPS SCD22U10V2KX-1GP PEG_TXP15
R403 1 EDP_ICOMPO PEG_TX0
2 10KR2J-3-GP eDP_HPD B16 EDP_HPD PEG_TX1 M33 PEG_C_TXP14 C418 1 2 OPS SCD22U10V2KX-1GP PEG_TXP14
DY M30 PEG_C_TXP13 C419 1 2 OPS SCD22U10V2KX-1GP PEG_TXP13
PEG_TX2 PEG_C_TXP12 C420 SCD22U10V2KX-1GP PEG_TXP12
B PEG_TX3 L31
PEG_C_TXP11 C421
1 2 OPS SCD22U10V2KX-1GP PEG_TXP11 B
C15 EDP_AUX PEG_TX4 L28
PEG_C_TXP10 C422
1 2 OPS SCD22U10V2KX-1GP PEG_TXP10
D15 EDP_AUX# PEG_TX5 K30 1 2 OPS
eDP
K27 PEG_C_TXP9 C423 1 2 OPS SCD22U10V2KX-1GP PEG_TXP9

PEG_TX6 PEG_C_TXP8 C424 SCD22U10V2KX-1GP PEG_TXP8
PEG_TX7 J29
PEG_C_TXP7 C425
C17 EDP_TX0 PEG_TX8 J27
PEG_C_TXP6 C426
F16 EDP_TX1 PEG_TX9 H28
PEG_C_TXP5 C427
C16 EDP_TX2 PEG_TX10 G28
PEG_C_TXP4 C428
G15 EDP_TX3 PEG_TX11 E28
PEG_C_TXP3 C429
PEG_TX12 F28
PEG_C_TXP2 C430
C18 EDP_TX#0 PEG_TX13 D27
PEG_C_TXP1 C431
E16 EDP_TX#1 PEG_TX14 E26
PEG_C_TXP0 C432
D16 EDP_TX#2 PEG_TX15 D25 1 2 OPS
F15 EDP_TX#3
SANDY SKT-BGA989C470395-1H180
62.10055.421
NOTE: 2nd = 62.10040.771
Select a Fast FET similar to 2N7002E whose rise/
fall time is less than 6 ns. If HPD on eDP interface is
disabled, connect it to CPU VCCIO via a 10-kΩ pull-Up
resistor on the motherboard.

EDP_ICOMPO keep W/S=12/15 mils and routing NOTE.
A length less than 500 mils. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.
<Core Design>
A
EDP_COMPIO keep W/S=4/15 mils and routing
length less than 500 mils.
Wistron Corporation
Title
CPU (PCIE/DMI/FDI)
A3 SD
LA480
5 4 3 2 Disabling Guidelines: 1
SSID = CPU
C26: PROC_SELECT#
CPU1B
SANDY
2 OF 9
Need Add Test Point

If motherboard only supports external graphics:
Connect DPLL_REF_SSCLK on Processor to GND through
1K +/- 5% resistor.
Connect DPLL_REF_SSCLK# on Processor to VCCP
BCLK A28 CLK_EXP_P 20 through 1K +/- 5% resistorpower (~15 mW) may be
MISC
CLOCKS
22 H_SNB_IVB# C26 A27 CLK_EXP_N 20
SNB_IVB# BCLK# wasted.
1D05V_VTT
TP501 1 SKTOCC#_R AN34
H_PROCHOT# SKTOCC# CLK_DP_P_R
1 2 DPLL_REF_SSCLK A16
R501 A15 CLK_DP_N_R
62R2J-GP
1 DPLL_REF_SSCLK# RN502 1D05V_VTT
D Intel
C502
SC47P50V2JN-3GP TP502 1 H_CATERR# AL33 CLK_DP_N_R 1
SRN1KJ-7-GP
4
D
CATERR# SM_DRAMRST# 37
recommends CLK_DP_P_R 2 3
2
43pf
THERMAL
0511-CHECK
AN33 R8 SM_DRAMRST# 2 1
22,27 H_PECI PECI SM_DRAMRST# R502 4K99R2F-L-GP
DDR3
MISC
1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R506 1 2 140R2F-GP In order to minimize resistance, use thick traces to
27,42 H_PROCHOT# PROCHOT# SM_RCOMP0 route all COMP signals, use 10-mils wide trace for
R513 56R2J-4-GP A5 SM_RCOMP_1 R507 1 2 25D5R2F-GP
SM_RCOMP1 SM_RCOMP_2 R508 1 routing less than 500 mils, or 20-mils wide trace
SM_RCOMP2 A4 2 200R2F-L-GP
Connect EC to PROCHOT# through inverting OD buffer. for routing between 500 mils and 1000 mils. Keep
20-mils spacing to any other signals in order to
22,36 H_THERMTRIP# AN32 THERMTRIP#
Signal Routing Guideline: minimize crosstalk.
SM_RCOMP keep routing length less than 500 mils.
If PROCHOT# is not used, then it must
be terminated with a 68ohm ±5% 1D05V_VTT
pull-up resistor to VTT. AP29 XDP_PRDY# 1 TP511
PRDY# XDP_PREQ# TP512
PREQ# AP27 1
XDP_TDO R523 1 2 51R2J-2-GP
AR26 XDP_TCLK 1 TP513
TCK
PWR MANAGEMENT
XDP_TMS
JTAG & BPM

TMS AR27
AM34 AP30 XDP_TRST# RN501
19 H_PM_SYNC PM_SYNC TRST# XDP_TMS 1 8
AR28 XDP_TDI 1 TP516 XDP_TDI 2 7
TDI
22,97 H_CPUPW RGD 1 2 H_CPUPW RGD_R TDO AP26 XDP_TDO XDP_TCLK 3 6
R504 0R0402-PAD AP33 XDP_TRST# 4 5
UNCOREPWRGOOD
1 2
C R503 10KR2J-3-GP
AL35 XDP_DBRESET#
SRN51J-1-GP
C
DBR#
37 VDDPW RGOOD V8 SM_DRAMPWROK
BPM#0 AT28
BPM#1 AR29
BPM#2 AR30
1 2 BUF_CPU_RST# AR33 AT30
18,27,31,36,65,66,71,80,82,83,97 PLT_RST# RESET# BPM#3
R510 AP32
1K5R2F-2-GP BPM#4
BPM#5 AR31
1
BPM#6 AT31
R509 C501 AR32
BPM#7
1
750R2F-GP SC220P50V2KX-3GP
DY
2
0511-CHECK
62.10055.421
2nd = 62.10040.771
3D3V_S0
DEL U501 19 XDP_DBRESET#

XDP_DBRESET# 1
R516
2
1KR2J-1-GP
DEL R519
B DEL C503 B
DEL R517
DEL R515
ASM R510
ASM R509
A <Core Design>
A
Wistron Corporation
Title
CPU (THERMAL/CLOCK/PM )
A3 SD
LA480
5 4 3 2 1

CPU1C 3 OF 9 CPU1D 4 OF 9
SANDY
AB6
SANDY AE2
SA_CLK0 M_A_DIM0_CLK_DDR0 14 SB_CLK0 M_B_DIM0_CLK_DDR0 15
14 M_A_DQ[63:0] SA_CLK#0 AA6 M_A_DIM0_CLK_DDR#0 14 15 M_B_DQ[63:0] SB_CLK#0 AD2 M_B_DIM0_CLK_DDR#0 15
M_A_DQ0 C5 V9 M_B_DQ0 C9 R9
SA_DQ0 SA_CKE0 M_A_DIM0_CKE0 14 SB_DQ0 SB_CKE0 M_B_DIM0_CKE0 15
D M_A_DQ1 D5 M_B_DQ1 A7 D
M_A_DQ2 SA_DQ1 M_B_DQ2 SB_DQ1
D3 SA_DQ2 D10 SB_DQ2
M_A_DQ3 D2 M_B_DQ3 C8
D6 SA_DQ4 SA_CLK1 AA5 M_A_DIM0_CLK_DDR1 14 A9 SB_DQ4 SB_CLK1 AE1 M_B_DIM0_CLK_DDR1 15
M_A_DQ5 C6 AB5 M_B_DQ5 A8 AD1
SA_DQ5 SA_CLK#1 M_A_DIM0_CLK_DDR#1 14 SB_DQ5 SB_CLK#1 M_B_DIM0_CLK_DDR#1 15
M_A_DQ6 C2 V10 M_B_DQ6 D9 R10
SA_DQ6 SA_CKE1 M_A_DIM0_CKE1 14 SB_DQ6 SB_CKE1 M_B_DIM0_CKE1 15
M_A_DQ7 C3 M_B_DQ7 D8
F10 SA_DQ8 G4 SB_DQ8
M_A_DQ9 F8 M_B_DQ9 F4
G10 SA_DQ10 SA_CLK2 AB4 F1 SB_DQ10 SB_CLK2 AB2
M_A_DQ11 G9 AA4 M_B_DQ11 G1 AA2
M_A_DQ12 SA_DQ11 SA_CLK#2 M_B_DQ12 SB_DQ11 SB_CLK#2
F9 SA_DQ12 SA_CKE2 W9 G5 SB_DQ12 SB_CKE2 T9
M_A_DQ13 F7 M_B_DQ13 F5
G8 SA_DQ14 F2 SB_DQ14
M_A_DQ15 G7 M_B_DQ15 G2
K4 SA_DQ16 SA_CLK3 AB3 J7 SB_DQ16 SB_CLK3 AA1
M_A_DQ17 K5 AA3 M_B_DQ17 J8 AB1
M_A_DQ18 SA_DQ17 SA_CLK#3 M_B_DQ18 SB_DQ17 SB_CLK#3
K1 SA_DQ18 SA_CKE3 W10 K10 SB_DQ18 SB_CKE3 T10
M_A_DQ19 J1 M_B_DQ19 K9
J5 SA_DQ20 J9 SB_DQ20
M_A_DQ21 J4 M_B_DQ21 J10
J2 SA_DQ22 SA_CS#0 AK3 M_A_DIM0_CS#0 14 K8 SB_DQ22 SB_CS#0 AD3 M_B_DIM0_CS#0 15
M_A_DQ23 K2 AL3 M_B_DQ23 K7 AE3
SA_DQ23 SA_CS#1 M_A_DIM0_CS#1 14 SB_DQ23 SB_CS#1 M_B_DIM0_CS#1 15
M_A_DQ24 M8 AG1 M_B_DQ24 M5 AD6
M_A_DQ25 SA_DQ24 SA_CS#2 M_B_DQ25 SB_DQ24 SB_CS#2
N10 SA_DQ25 SA_CS#3 AH1 N4 SB_DQ25 SB_CS#3 AE6
M_A_DQ26 N8 M_B_DQ26 N2
N7 SA_DQ27 N1 SB_DQ27
M_A_DQ28 M10 M_B_DQ28 M4
M9 SA_DQ29 SA_ODT0 AH3 M_A_DIM0_ODT0 14 N5 SB_DQ29 SB_ODT0 AE4 M_B_DIM0_ODT0 15
DDR SYSTEM MEMORY B

C M_A_DQ30 N9 AG3 M_B_DQ30 M2 AD4 C
DDR SYSTEM MEMORY A
SA_DQ30 SA_ODT1 M_A_DIM0_ODT1 14 SB_DQ30 SB_ODT1 M_B_DIM0_ODT1 15
M_A_DQ31 M7 AG2 M_B_DQ31 M1 AD5
M_A_DQ32 SA_DQ31 SA_ODT2 M_B_DQ32 SB_DQ31 SB_ODT2
AG6 SA_DQ32 SA_ODT3 AH2 AM5 SB_DQ32 SB_ODT3 AE5
M_A_DQ33 AG5 M_B_DQ33 AM6
AK6 SA_DQ34 AR3 SB_DQ34
M_A_DQ35 AK5 M_B_DQ35 AP3
AH5 SA_DQ36 M_A_DQS#[7:0] 14 AN3 SB_DQ36 M_B_DQS#[7:0] 15
M_A_DQ37 AH6 C4 M_A_DQS#0 M_B_DQ37 AN2 D7 M_B_DQS#0
M_A_DQ38 SA_DQ37 SA_DQS#0 M_A_DQS#1 M_B_DQ38 SB_DQ37 SB_DQS#0 M_B_DQS#1
AJ5 SA_DQ38 SA_DQS#1 G6 AN1 SB_DQ38 SB_DQS#1 F3
M_A_DQ39 AJ6 J3 M_A_DQS#2 M_B_DQ39 AP2 K6 M_B_DQS#2
AJ8 SA_DQ40 SA_DQS#3 M6 AP5 SB_DQ40 SB_DQS#3 N3
M_A_DQ41 AK8 AL6 M_A_DQS#4 M_B_DQ41 AN9 AN5 M_B_DQS#4
AJ9 SA_DQ42 SA_DQS#5 AM8 AT5 SB_DQ42 SB_DQS#5 AP9
M_A_DQ43 AK9 AR12 M_A_DQS#6 M_B_DQ43 AT6 AK12 M_B_DQS#6
AH8 SA_DQ44 SA_DQS#7 AM15 AP6 SB_DQ44 SB_DQS#7 AP15
M_A_DQ45 AH9 M_B_DQ45 AN8
AL9 SA_DQ46 AR6 SB_DQ46
M_A_DQ47 AL8 M_B_DQ47 AR5
AP11 SA_DQ48 M_A_DQS[7:0] 14 AR9 SB_DQ48 M_B_DQS[7:0] 15
M_A_DQ49 AN11 D4 M_A_DQS0 M_B_DQ49 AJ11 C7 M_B_DQS0
M_A_DQ50 SA_DQ49 SA_DQS0 M_A_DQS1 M_B_DQ50 SB_DQ49 SB_DQS0 M_B_DQS1
AL12 SA_DQ50 SA_DQS1 F6 AT8 SB_DQ50 SB_DQS1 G3
M_A_DQ51 AM12 K3 M_A_DQS2 M_B_DQ51 AT9 J6 M_B_DQS2
AM11 SA_DQ52 SA_DQS3 N6 AH11 SB_DQ52 SB_DQS3 M3
M_A_DQ53 AL11 AL5 M_A_DQS4 M_B_DQ53 AR8 AN6 M_B_DQS4
AP12 SA_DQ54 SA_DQS5 AM9 AJ12 SB_DQ54 SB_DQS5 AP8
M_A_DQ55 AN12 AR11 M_A_DQS6 M_B_DQ55 AH12 AK11 M_B_DQS6
AJ14 SA_DQ56 SA_DQS7 AM14 AT11 SB_DQ56 SB_DQS7 AP14
M_A_DQ57 AH14 M_B_DQ57 AN14
AL15 SA_DQ58 AR14 SB_DQ58
B M_A_DQ59 M_B_DQ59 B
AK15 SA_DQ59 AT14 SB_DQ59
M_A_DQ60 AL14 M_B_DQ60 AT12
SA_DQ60 M_A_A[15:0] 14 SB_DQ60 M_B_A[15:0] 15
M_A_DQ61 AK14 AD10 M_A_A0 M_B_DQ61 AN15 AA8 M_B_A0
M_A_DQ62 SA_DQ61 SA_MA0 M_A_A1 M_B_DQ62 SB_DQ61 SB_MA0 M_B_A1
AJ15 SA_DQ62 SA_MA1 W1 AR15 SB_DQ62 SB_MA1 T7
M_A_DQ63 AH15 W2 M_A_A2 M_B_DQ63 AT15 R7 M_B_A2
SA_DQ63 SA_MA2 M_A_A3 SB_DQ63 SB_MA2 M_B_A3
SA_MA3 W7 SB_MA3 T6
V3 M_A_A4 T2 M_B_A4
SA_MA4 M_A_A5 SB_MA4 M_B_A5
SA_MA5 V2 SB_MA5 T4
W3 M_A_A6 T3 M_B_A6
14 M_A_BS0 AE10 SA_BS0 SA_MA7 W6 15 M_B_BS0 AA9 SB_BS0 SB_MA7 R2
AF10 V1 M_A_A8 AA7 T5 M_B_A8
14 M_A_BS1 SA_BS1 SA_MA8 15 M_B_BS1 SB_BS1 SB_MA8
V6 W5 M_A_A9 R6 R3 M_B_A9
14 M_A_BS2 SA_BS2 SA_MA9 15 M_B_BS2 SB_BS2 SB_MA9
AD8 M_A_A10 AB7 M_B_A10
SA_MA11 V4 SB_MA11 R1
W4 M_A_A12 T1 M_B_A12
14 M_A_CAS# AE8 SA_CAS# SA_MA13 AF8 15 M_B_CAS# AA10 SB_CAS# SB_MA13 AB10
AD9 V5 M_A_A14 AB8 R5 M_B_A14
14 M_A_RAS# SA_RAS# SA_MA14 15 M_B_RAS# SB_RAS# SB_MA14
AF9 V7 M_A_A15 AB9 R4 M_B_A15
14 M_A_W E# SA_WE# SA_MA15 15 M_B_W E# SB_WE# SB_MA15
SANDY SANDY
62.10055.421 62.10055.421
2nd = 62.10040.771 2nd = 62.10040.771
A <Core Design> A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU (DDR)
A3 SD
LA480
5 4 3 2 1
5 4 3 2 1
SSID = CPU http://laptopblue.vn CPU1E 5 OF 9
RSVD#L7 L7
RSVD#AG7 AG7
CFG2 TP717 1 CFG0 AK28 AE7
TP702 1 CFG1 AK29
CFG0 SANDY RSVD#AE7
AK2
CFG1 RSVD#AK2
1 PEG Static Lane Reversal - CFG2 is for the 16x CFG2 AL26 CFG2 RSVD#W8 W8
R702 TP703 1 CFG3 AL27
1KR2J-1-GP 1: Normal Operation; Lane # CFG4 CFG3
CFG2 AK26 CFG4
D OPS definition matches socket pin map definition CFG5 AL29 AT26 D
CFG6 CFG5 RSVD#AT26
AL30 AM33
2
0:Lane Reversed CFG7 CFG6 RSVD#AM33

AM31 CFG7 RSVD#AJ27 AJ27
AM32 CFG8
AM30 CFG9
AM28 CFG10
AM26 CFG11
AN28 CFG12
AN31 CFG13 RSVD#T8 T8
CFG4 AN26 J16
CFG14 RSVD#J16
AM27 CFG15 RSVD#H16 H16
1
Display Port Presence Strap TP704 1 CFG16 AK31 G16

R703 CFG16 RSVD#G16
AN29 CFG17
1KR2J-1-GP CFG4 1: Disabled; No Physical Display Port
DY attached to Embedded Display Port
2
0: Enabled; An external Display Port device is AR35

RSVD#AR35
connected to the Embedded Display Port AJ31 RSVD#AJ31 RSVD#AT34 AT34
AH31 RSVD#AH31 RSVD#AT33 AT33
AJ33 RSVD#AJ33 RSVD#AP35 AP35
AH33 RSVD#AH33 RSVD#AR34 AR34
AJ26 RSVD#AJ26
RESERVED
RSVD#B34 B34
12 DDR_W R_VREF01 B4 RSVD#B4 RSVD#A33 A33
12 DDR_W R_VREF02 D1 RSVD#D1 RSVD#A34 A34
C B35 C
RSVD#B35
RSVD#C35 C35
F25 RSVD#F25
F24 RSVD#F24
F23 RSVD#F23
D24 RSVD#D24 RSVD#AJ32 AJ32
G25 RSVD#G25 RSVD#AK32 AK32
G24 RSVD#G24
E23 RSVD#E23
D23 RSVD#D23
C30 AH27 TP713 1 TP720
RSVD#C30 RSVD#AH27
A31 RSVD#A31
B30 RSVD#B30
B29 RSVD#B29
D30 AN35 CLK_XDP_ITP_P 1 TP718
RSVD#D30 RSVD#AN35 CLK_XDP_ITP_N TP719
B31 RSVD#B31 RSVD#AM35 AM35 1
A30 RSVD#A30
C29 RSVD#C29
J20 RSVD#J20
B18 RSVD#B18 RSVD#AT2 AT2
TP705 1 H_VCCP_SEL A19 AT1
RSVD#A19 RSVD#AT1
RSVD#AR1 AR1
J15 RSVD#J15
B B
62.10055.421
CFG5 2nd = 62.10040.771
CFG6
PCIE Port Bifurcation Straps
1
R701 R704
1KR2J-1-GP
1KR2J-1-GP
DY DY CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
2
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG7
A <Core Design> A
1
PEG DEFER TRAINING

R705
1KR2J-1-GP
DY 1: PEG Train immediately following xxRESETB de assertion Wistron Corporation
CFG7
0: PEG Wait for BIOS for training 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2
Title
CPU (RESERVED)
A3 SD
LA480
5 4 3 2 1
5 4 3 2 1
0511-CHECK CAP. VCC CORE:53A http://laptopblue.vn

POWER CPU1F 6 OF 9
0511-CHECK CAP. VCCIO:8.5A

VCC_CORE
SANDY 0511-CHECK
VCC_CORE 1D05V_VTT
AG35 VCC
AG34 VCC VCCIO AH13
C801 C802 C803 C804 C811 AG33 AH10 C805 C806 C807 C808 C809 C810 C838 C839 C840 C841
VCC VCCIO
D DY DY AG32 VCC VCCIO AG10 DY D
1
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AG31 VCC VCCIO AC10
AG30 VCC VCCIO Y10
AG29 U10
2
2
VCC VCCIO
AG28 VCC VCCIO P10
AG27 VCC VCCIO L10
AG26 VCC VCCIO J14
AF35 VCC VCCIO J13
AF34 VCC VCCIO J12
AF33 VCC VCCIO J11
AF32 VCC VCCIO H14
AF31 VCC VCCIO H12
C815 C817 C818 C819 C820 AF30 H11
VCC VCCIO
AF29 VCC VCCIO G14
1
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AF28 VCC VCCIO G13
PEG AND DDR

AF27 VCC VCCIO G12
AF26 F14
2
2 VCC VCCIO
AD35 VCC VCCIO F13
AD34 VCC VCCIO F12
AD33 VCC VCCIO F11
AD32 E14
AD31
VCC
VCC
VCCIO
VCCIO E12 Reserve C846 & C847 1D05V_VTT
AD30 VCC
AD29 VCC VCCIO E11
AD28 D14 C812 C813 C814 C829 C830 C842 C843 C844 C845
C816 C821 C822 C823 C824 C825 C826 C827 VCC VCCIO
AD27 VCC VCCIO D13 DY
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY AD26 VCC VCCIO D12
1
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AC35 VCC VCCIO D11
AC34 C14
2
VCC VCCIO
AC33 C13
2
2
VCC VCCIO
AC32 VCC VCCIO C12
C AC31 VCC VCCIO C11 C
AC30 VCC VCCIO B14
AC29 VCC VCCIO B12
AC28 VCC VCCIO A14
AC27 VCC VCCIO A13
AC26 VCC VCCIO A12
AA35 VCC VCCIO A11
C837 C836 C835 C834 C833 C832 C831 C828 AA34 VCC
DY AA33 VCC VCCIO J23
1
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AA32 VCC
AA31 VCC
AA30
2
VCC
AA29 VCC
AA28 VCC
AA27 VCC
AA26 VCC
CORE SUPPLY
Y35 VCC For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7
Y34
Y33
VCC For CRB VIDALERT# need to pull high 75 ohm close to CPU
VCC
Y32 VCC
Y31 VCC
Y30 VCC
Y29 VCC
Y28 VCC 1 2 1D05V_VTT
Y27 R807 75R2F-2-GP
VCC
Y26 VCC
V35 VCC
SVID
V34 AJ29 H_CPU_SVIDALRT# 1 2
VCC VIDALERT# VR_SVID_ALERT# 42
V33 AJ30 H_CPU_SVIDCLK R803 43R2J-GP
VCC VIDSCLK H_CPU_SVIDCLK 42
V32 AJ28 H_CPU_SVIDDAT
VCC VIDSOUT H_CPU_SVIDDAT 42
V31 VCC
B V30 VCC B
V29 VCC
V28 VCC 1 2 1D05V_VTT
V27 R804 130R2F-1-GP
VCC 0511-CHECK
V26 VCC
U35 VCC
U34 VCC
U33 check
VCC Place neer PCU pin.
U32 VCC
U31 1D05V_VTT
VCC
U30 VCC
U29 VCC
1
U28 VCC
U27 R808
VCC 10R2F-L-GP
U26 VCC
R35 VCC_CORE
VCC
R34
2
VCC VCCIO_SENSE
R33 VCC
1
R32 VCC
R31 R801 VSSIO_SENSE
VCC 100R2F-L1-GP-U
R30 VCC
1
R29 VCC
SENSE LINES
R28 R809
2
VCC 10R2F-L-GP
R27 VCC VCC_SENSE AJ35 VCCSENSE 42
R26 VCC VSS_SENSE AJ34 VSSSENSE 42
P35
2
VCC
1
P34 VCC
P33 R802
VCC 100R2F-L1-GP-U
P32 VCC VCCIO_SENSE B10 VCCIO_SENSE 45
P31 VCC VSSIO_SENSE A10 VSSIO_SENSE 45
P30
2
VCC
A P29 VCC A
P28 VCC <Core Design>
P27 VCC
P26 VCC
Wistron Corporation
Title
CPU (VCC_CORE)
SANDY Size Document Number Rev
62.10055.421 Custom SD
LA480
2nd = 62.10040.771 Date: Friday, January 06, 2012 Sheet 8 of 103
5 4 3 2 1
5 4 3 2 1
0511-CHECK CAP VCC_GFXCORE
POWER
1
R906
CPU1G 7 OF 9 100R2F-L1-GP-U
VCC_GFXCORE
0511-CHECK
D PROCESSOR VAXG: 24A D
2
SENSE
LINES
AT24 AK35 VCC_AXG_SENSE
VAXG VAXG_SENSE VCC_AXG_SENSE 42
C901 C902 C903 C904 C905 C906 RC901 AT23 AK34 VSS_AXG_SENSE
VAXG VSSAXG_SENSE VSS_AXG_SENSE 42
AT21 VAXG SANDY
1
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC33P50V2JN-3GP
AT20 VAXG
AT18 Refer to the latest Huron River Mainstream PDG R907
VAXG 100R2F-L1-GP-U
DY AT17 (Doc# 436735) for more details on S3 power
2
2
VAXG
AR24 VAXG reduction implementation.
AR23
2
VAXG
AR21 VAXG
AR20 +V_SM_VREF_CNT should have 10 mil trace width
VAXG
VREF
AR18 VAXG
AR17 VAXG
AP24 VAXG SM_VREF AL1 +V_SM_VREF_CNT 37
AP23 VAXG
AP21 VAXG
AP20 VAXG
Routing Guideline:
C907 C908 C918 C919 C920 C921 RC902 AP18 Power from DDR_VREF_S3 and +V_SM_VREF_CNT
VAXG
AP17 VAXG should have 10 mils trace width.
1
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC33P50V2JN-3GP
AN24 VAXG
DY AN23 VAXG
AN21
2
2
VAXG
AN20 VAXG 1D5V_S0
DDR3 -1.5V RAILS

AN18 VAXG VDDQ:5A
AN17 VAXG
GRAPHICS
AM24 VAXG VDDQ AF7
AM23 AF4 C909 C910 C911 C912 C913 C914
VAXG VDDQ
AM21 VAXG VDDQ AF1 DY
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AM20 VAXG VDDQ AC7
C AM18 AC4 C
VAXG VDDQ
AM17 AC1
2
VAXG VDDQ
AL24 VAXG VDDQ Y7
AL23 VAXG VDDQ Y4
AL21 VAXG VDDQ Y1
AL20 VAXG VDDQ U7
AL18 VAXG VDDQ U4
AL17 VAXG VDDQ U1
AK24 VAXG VDDQ P7
AK23 VAXG VDDQ P4
AK21 VAXG VDDQ P1
AK20 VAXG
AK18 VAXG
AK17 VCCSA
AJ24
VAXG VCCA:6A
VAXG
AJ23 VAXG
AJ21 C916 C915 C917
VAXG
AJ20 VAXG
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AJ18 VAXG
AJ17 VAXG
AH24
SA RAIL
2
VAXG
AH23 VAXG
AH21 VAXG VCCSA M27
AH20 VAXG VCCSA M26
AH18 VAXG VCCSA L26
AH17 VAXG VCCSA J26
VCCSA J25
VCCSA J24
B VCCSA H26 +V0.85S - VCCSA - System Agent rail voltage can be B
H25
VCCSA [0.9, 0.725, 0.8, 0.675] V for IVB
1.8V RAIL
[0.9, 0.8] V for SNB

1D8V_S0
VCCPLL:1.2A
B6 VCCPLL VCCSA_SENSE H23 VCCSA_SENSE 48
MISC
C926 C923 C922 C924 A6 VCCPLL

A2 VCCPLL
1
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
FC_C22 C22 VCCSA_SELECT0 48

C24
2
VCCSA_VID1 VCCSA_SELECT1 48
4
3
SANDY
62.10055.421 RN901
SRN1KJ-7-GP
2nd = 62.10040.771
1
2
A <Core Design> A
Wistron Corporation
Title
CPU (VCC_GFXCORE)
A3 SD
LA480
5 4 3 2 1
5 4 3 2 1

CPU1H 8 OF 9 CPU1I 9 OF 9
AT35 VSS VSS AJ22

AT32 VSS VSS AJ19
AT29 VSS VSS AJ16 T35 VSS SANDY VSS F22
AT27 VSS VSS AJ13 T34 VSS VSS F19
AT25 VSS VSS AJ10 T33 VSS VSS E30
D AT19 VSS VSS AJ4 T31 VSS VSS E24 D
AT13 VSS SANDY VSS AJ2 T29 VSS VSS E18
AT7 VSS VSS AH35 T27 VSS VSS E13
AT4 VSS VSS AH34 T26 VSS VSS E10
AT3 VSS VSS AH32 P9 VSS VSS E9
AR25 VSS VSS AH30 P8 VSS VSS E8
AR10 VSS VSS AH22 N35 VSS VSS E3
AR2 VSS VSS AH7 N32 VSS VSS D35
AP34 VSS VSS AH4 N31 VSS VSS D32
AP31 VSS VSS AG9 N30 VSS VSS D29
AP22 VSS VSS AF6 N27 VSS VSS D17
AP19 VSS VSS AF5 N26 VSS VSS C34
AP16 VSS VSS AF3 M34 VSS VSS C31
AP13 VSS VSS AF2 L33 VSS VSS C28
AP10 VSS VSS AE35 L30 VSS VSS C27
AN30 VSS VSS AE31 L6 VSS VSS C1
C AN27 AE30 L5 B22 C
VSS VSS VSS VSS
AN25 AE29 L4 B19
AN22
AN19
VSS
VSS
VSS
VSS VSS
VSS
VSS
AE28
AE27
L3
L2
VSS
VSS
VSS
VSS VSS
VSS
VSS
B17
B15
AN16 VSS VSS AE26 L1 VSS VSS B13
AN13 VSS VSS AE9 K35 VSS VSS B11
AN10 VSS VSS AD7 K32 VSS VSS B9
AN7 VSS VSS AC9 K29 VSS VSS B8
AN4 VSS VSS AC8 K26 VSS VSS B7
AM29 VSS VSS AC6 J34 VSS VSS B5
AM25 VSS VSS AC5 J31 VSS VSS B3
AM22 VSS VSS AC3 H33 VSS VSS B2
AM19 VSS VSS AC2 H30 VSS VSS A35
AM16 VSS VSS AB35 H27 VSS VSS A32
AM2 VSS VSS AB29 H10 VSS
AM1 VSS VSS AB28 H9 VSS
AL34 VSS VSS AB27 H8 VSS
AL31 VSS VSS AB26 H7 VSS
AL28 VSS VSS Y9 H6 VSS
B B
AL10 VSS VSS W35 G35 VSS
AK33 VSS VSS W31 G23 VSS
AK22 VSS VSS W27 F34 VSS
AK19 VSS VSS W26 F31 VSS
AK16 VSS VSS U9 F29 VSS
AK13 VSS VSS U8
AK10 VSS VSS U6
AK7 VSS VSS U5
AK4 VSS VSS U3
AJ25 VSS VSS U2
SANDY SANDY
62.10055.421 62.10055.421
2nd = 62.10040.771 2nd = 62.10040.771
A <Core Design> A
Wistron Corporation
Title
CPU (VSS)
A3 SD
LA480
5 4 3 2 1
5 4 3 2 1
D D
C
BLANK C
B B
<Core Design>
Wistron Corporation
Title
<Title>

A4 LA480 SD

5 4 3 2 1
VREF circuit -M1 (Voltage Driver Network) & M3 (Driven by Processor) Implementation
CAD Note: All VREF traces should have 20:20 mil trace geometry. Note that while 20 mil trace width is optimal, short violations is acceptable if
required due to tight routing constraints.
SA_DIMM_VREFDQ R1226
1 DY 2
0R2J-2-GP
SB_DIMM_VREFDQ 1
R1208
DY 2
0R2J-2-GP
D Driven by process (PIN#B4) Driven by process (PIN#D1) D
U1201 U1202
7 DDR_W R_VREF01 S 7 DDR_W R_VREF02 S
1
D DDR_W R_VREF01_B4 D DDR_W R_VREF01_D1
R1228 R1227
1KR2F-3-GP DY G 1KR2F-3-GP DY G
2N7002K-2-GP 2N7002K-2-GP
2
84.2N702.J31 84.2N702.J31
2ND = 84.2N702.031 2ND = 84.2N702.031
20,37 DRAMRST_CNTRL_PCH 20,37 DRAMRST_CNTRL_PCH
DDR_W R_VREF01_B4
DDR_VREF_S3 DDR_VREF_S3
1
2
R1204 SODDIM0 R1232
0R0402-PAD 0R0402-PAD
CLOSE PIN1
2
1
C C
1 2 M_VREF_DQ_DIMM0 M_VREF_CA_DIMM0 1 2 +V_SM_VREF 37

R1203 R1222
0R0402-PAD 0R0402-PAD
1
1
R1209 C1201 C1203
0R2J-2-GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP
2
2
DY
1
2
CLOSE PIN R1218

+V_VREF_PATH1
0R0402-PAD
2
1+V_VREF_PATH3
1 DY 2 DDR_W R_VREF01_D1
R1219
0R2J-2-GP
1
R1221
0R0402-PAD
R1217
2
0R0402-PAD
2
1
B B
DDR_VREF_S3 R1225 DDR_VREF_S3
0R2J-2-GP
DY
2
1
R1216
DY2
1 2 M_VREF_DQ_DIMM1
R1207 0R2J-2-GP
0R0402-PAD SODDIM1
1
1
C1202 M_VREF_CA_DIMM1
R1210 SCD1U10V2KX-4GP
2
0R0402-PAD
1
C1204
2
SCD1U10V2KX-4GP
2
CLOSE PIN
CLOSE PIN
+V_VREF_PATH2
A <Core Design> A
Wistron Corporation
Title
M3
A3 SD
LA480
5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
Wistron Corporation
Title
<Title>

A4 LA480 SD

5 4 3 2 1
DIMM1
SSID = MEMORY M_A_A[15:0] 6
M_A_A0
M_A_A1
M_A_A2
M_A_A3
98
97
96
95
A0
A1
A2
NP1
NP2
NP1
NP2
110 M_A_RAS# 6
SA0_DIM0
SA1_DIM0
1
M_A_A4 A3 RAS#
92 113 M_A_WE# 6
M_A_A5 A4 WE# R1401 R1402
91 115 M_A_CAS# 6
M_A_A6 A5 CAS# 10KR2J-3-GP 10KR2J-3-GP
90
M_A_A7 A6
86 114 M_A_DIM0_CS#0 6
M_A_A8 A7 CS0#
89 121
2
A8 CS1# M_A_DIM0_CS#1 6
M_A_A9 85
M_A_A10 A9
107 73 M_A_DIM0_CKE0 6
M_A_A11 A10/AP CKE0
84 74 M_A_DIM0_CKE1 6
M_A_A12 A11 CKE1
83
M_A_A13 A12
119 101 M_A_DIM0_CLK_DDR0 6
M_A_A14 A13 CK0
80 103 M_A_DIM0_CLK_DDR#0 6
M_A_A15 A14 CK0#
78
A15 Note:
D 6 M_A_BS2 79 102 M_A_DIM0_CLK_DDR1 6 D
A16/BA2 CK1 If SA0 DIM0 = 0, SA1_DIM0 = 0
104 M_A_DIM0_CLK_DDR#1 6
CK1#
6 M_A_BS0 109 SO-DIMMA SPD Address is 0xA0
BA0
6 M_A_BS1 108 11
BA1 DM0
6 M_A_DQ[63:0] DM1
28 SO-DIMMA TS Address is 0x30
M_A_DQ0 5 46
M_A_DQ1 DQ0 DM2
7 63
DQ1 DM3
M_A_DQ2 15
DQ2 DM4
136 If SA0 DIM0 = 1, SA1_DIM0 = 0
M_A_DQ3 17 153
M_A_DQ4 4
DQ3 DM5
170 SO-DIMMA SPD Address is 0xA2
M_A_DQ5 DQ4 DM6
M_A_DQ6
6
DQ5 DM7
187 SO-DIMMA TS Address is 0x32
16
M_A_DQ7 DQ6
18 200 PCH_SMBDATA 15,20,65,66
M_A_DQ8 DQ7 SDA
21 202 PCH_SMBCLK 15,20,65,66
M_A_DQ9 DQ8 SCL
23
M_A_DQ10 DQ9 3D3V_S0
33 198 TS#_DIMM0_1 15
M_A_DQ11 DQ10 EVENT#
35
M_A_DQ12 DQ11
22 199
M_A_DQ13 DQ12 VDDSPD
24
1
M_A_DQ14 DQ13 SA0_DIM0 C1401 C1402
34 197
M_A_DQ15 36
DQ14
DQ15
SA0
SA1
201 SA1_DIM0 SCD1U10V2KX-5GP SC2D2U10V3KX-1GP Thermal EVENT 3D3V_S0
M_A_DQ16 39 DY
2
M_A_DQ17 DQ16
41 77
M_A_DQ18 DQ17 NC#77 TS#_DIMM0_1
51 122 1 2
M_A_DQ19 DQ18 NC#122 1D5V_S3 R1403
53 125
M_A_DQ20 DQ19 NC#125/TEST 10KR2J-3-GP
40
M_A_DQ21 DQ20
42 75
M_A_DQ22 DQ21 VDD
50 76
M_A_DQ23 DQ22 VDD
52 81
M_A_DQ24 DQ23 VDD
57 82
M_A_DQ25 DQ24 VDD
59 87
M_A_DQ26 DQ25 VDD
67 88
M_A_DQ27 DQ26 VDD
69 93
M_A_DQ28 DQ27 VDD
56 94
M_A_DQ29 DQ28 VDD
58 99
M_A_DQ30 DQ29 VDD
68 100
M_A_DQ31 DQ30 VDD
70 105
M_A_DQ32 DQ31 VDD
129 106
M_A_DQ33 DQ32 VDD SODIMM A DECOUPLING
131 111
M_A_DQ34 DQ33 VDD
141 112
M_A_DQ35 DQ34 VDD 1D5V_S3
143 117
M_A_DQ36 DQ35 VDD
C 130 118 C
M_A_DQ37 DQ36 VDD 0511-CHECK
132 123
M_A_DQ38 DQ37 VDD
140 124
M_A_DQ39 DQ38 VDD TC1401 C1403 C1404 C1405 C1406 C1407 C1408 C1409 C1410
142
M_A_DQ40 DQ39
147 2
1
DQ40 VSS
ST330U2VDM-4-GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
M_A_DQ41 149 3
M_A_DQ42 DQ41 VSS
157
DQ42 VSS
8 DY DY DY DY DY
M_A_DQ43 159 9
2
M_A_DQ44 DQ43 VSS
146 13
M_A_DQ45 DQ44 VSS
Place these caps M_A_DQ46
148
DQ45 VSS
14
158 19
close to VTT1 and M_A_DQ47 DQ46 VSS
160 20
0D75V_S0 M_A_DQ48 DQ47 VSS
VTT2. 163 25
M_A_DQ49 DQ48 VSS
165 26
M_A_DQ50 DQ49 VSS
175 31
C1419 C1420 C1421 C1422 C1418 M_A_DQ51 DQ50 VSS C1414 C1415 C1416 C1417
177 32
M_A_DQ52 DQ51 VSS
164 37
1
1
DQ52 VSS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_A_DQ53 166 38 Layout Note:
M_A_DQ54 DQ53 VSS
DY DY DY M_A_DQ55
174
DQ54 VSS
43
Place these Caps near
176 44
2
2
M_A_DQ56 DQ55 VSS
181 48 SO-DIMMB.
M_A_DQ57 DQ56 VSS
183 49
M_A_DQ58 DQ57 VSS
191 54
M_A_DQ59 DQ58 VSS
193 55
M_A_DQ60 DQ59 VSS
180 60
M_A_DQ61 DQ60 VSS
182 61
M_A_DQ62 DQ61 VSS
192 65
M_A_DQ63 DQ62 VSS
194 66
DQ63 VSS
71
M_A_DQS#0 VSS
10 72
M_A_DQS#1 DQS0# VSS
27 127
M_A_DQS#2 DQS1# VSS
45 128
M_A_DQS#3 DQS2# VSS
62 133
M_A_DQS#4 DQS3# VSS
135 134
M_A_DQS#5 DQS4# VSS
152 138
M_A_DQS#6 DQS5# VSS
M_A_DQS#[7:0] 6 169 139
M_A_DQS#7 DQS6# VSS
186 144
DQS7# VSS
M_A_DQS[7:0] 6 145
M_A_DQS0 VSS
12 150
M_A_DQS1 DQS0 VSS
29 151
M_A_DQS2 DQS1 VSS
47 155
B M_A_DQS3 DQS2 VSS B
64 156
M_A_DQS4 DQS3 VSS
137 161
M_A_DQS5 DQS4 VSS
154 162
M_A_DQS6 DQS5 VSS
171 167
M_A_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
6 M_A_DIM0_ODT0 116 173
ODT0 VSS
6 M_A_DIM0_ODT1 120 178
ODT1 VSS
179
VSS
M_VREF_CA_DIMM0 126 184
VREF_CA VSS
M_VREF_DQ_DIMM0 1 185
VREF_DQ VSS
189
VSS
15,37 DDR3_DRAMRST# 30 190
RESET# VSS
195
VSS
196
VSS
0D75V_S0 203 205
VTT1 VSS
204 206
VTT2 VSS
DDR3-204P-96-GP-U1
62.10017.V61
2ND = *62.10017.X51
3RD = *62.10017.V61
(H=8mm)
A A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
DDR3-SODIMM1
A2
LA480 SD
5 4 3 2 1
5 4 3 2 1
SSID = MEMORY DIMM2
M_B_A[15:0] 6
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
98
97
96
95
92
A0
A1
A2
A3
A4
NP1
NP2
RAS#
WE#
NP1
NP2
110
113
M_B_RAS#
M_B_WE#
6
6
M_B_A5 91 115
A5 CAS# M_B_CAS# 6
M_B_A6 90
M_B_A7 A6
86 114 M_B_DIM0_CS#0 6
M_B_A8 A7 CS0#
89 121 M_B_DIM0_CS#1 6
M_B_A9 A8 CS1#
85
M_B_A10 A9
107 73 M_B_DIM0_CKE0 6
M_B_A11 A10/AP CKE0
84 74 M_B_DIM0_CKE1 6
M_B_A12 A11 CKE1
83
M_B_A13 A12
119 101 M_B_DIM0_CLK_DDR0 6
M_B_A14 A13 CK0
80 103 M_B_DIM0_CLK_DDR#0 6
M_B_A15 A14 CK0#
78
A15
D 6 M_B_BS2 79 102 M_B_DIM0_CLK_DDR1 6 D
A16/BA2 CK1
104 M_B_DIM0_CLK_DDR#1 6
CK1#
6 M_B_BS0 109
BA0
6 M_B_BS1 108 11
BA1 DM0
6 M_B_DQ[63:0] 28
M_B_DQ0 DM1
5 46
M_B_DQ1 DQ0 DM2
7 63
M_B_DQ2 DQ1 DM3
15 136
M_B_DQ3 DQ2 DM4
17 153
M_B_DQ4 DQ3 DM5
4 170
M_B_DQ5 DQ4 DM6
6 187
M_B_DQ6 DQ5 DM7
16
M_B_DQ7 DQ6
18 200 PCH_SMBDATA 14,20,65,66
M_B_DQ8 DQ7 SDA 3D3V_S0
21 202 PCH_SMBCLK 14,20,65,66
M_B_DQ9 DQ8 SCL
23
M_B_DQ10 DQ9 3D3V_S0
33 198 TS#_DIMM0_1 14
1
M_B_DQ11 DQ10 EVENT#
35
M_B_DQ12 DQ11 R1501
22 199
M_B_DQ13 DQ12 VDDSPD 10KR2J-3-GP
24
1
M_B_DQ14 DQ13 SA0_DIM1 C1501 C1502
34 197
M_B_DQ15 DQ14 SA0 SA1_DIM1 SCD1U10V2KX-5GP SC2D2U10V3KX-1GP
36 201 DY
2
M_B_DQ16 DQ15 SA1 SA1_DIM1
39
2
M_B_DQ17 DQ16
41 77
M_B_DQ18 DQ17 NC#1 0511-CHECK SA0_DIM1
51 122
M_B_DQ19 DQ18 NC#2 1D5V_S3
53 125
1
M_B_DQ20 DQ19 NC#/TEST
40
M_B_DQ21 DQ20 R1502
42 75
M_B_DQ22 DQ21 VDD1 10KR2J-3-GP
50 76
M_B_DQ23 DQ22 VDD2
52 81
M_B_DQ24 DQ23 VDD3
57 82
2
M_B_DQ25 DQ24 VDD4
59 87
M_B_DQ26 DQ25 VDD5
67 88
M_B_DQ27 DQ26 VDD6
69 93
M_B_DQ28 DQ27 VDD7
56 94
M_B_DQ29 DQ28 VDD8
58 99
M_B_DQ30 DQ29 VDD9
M_B_DQ31
68
DQ30 VDD10
100 Note:
70 105
M_B_DQ32 DQ31 VDD11 SO-DIMMB SPD Address is 0xA4
129 106
M_B_DQ33 DQ32 VDD12
131 111 SO-DIMMB TS Address is 0x34
M_B_DQ34 DQ33 VDD13
141 112
M_B_DQ35 DQ34 VDD14
143 117
M_B_DQ36 DQ35 VDD15
C 130 118 C
M_B_DQ37 DQ36 VDD16
M_B_DQ38
132
DQ37 VDD17
123 SO-DIMMB is placed farther from
140 124
M_B_DQ39 DQ38 VDD18 the Processor than SO-DIMMA
142
M_B_DQ40 DQ39
147 2
M_B_DQ41 DQ40 VSS
149 3
M_B_DQ42 DQ41 VSS
157 8
M_B_DQ43 DQ42 VSS
159 9
M_B_DQ44 DQ43 VSS
146 13
M_B_DQ45 DQ44 VSS
148 14
M_B_DQ46 DQ45 VSS
158 19 1D5V_S3
M_B_DQ47 DQ46 VSS
M_B_DQ48
160
DQ47 VSS
20 SODIMM B DECOUPLING
163 25
M_B_DQ49 DQ48 VSS
165 26
M_B_DQ50 DQ49 VSS
175 31
M_B_DQ51 DQ50 VSS C1503 C1504 C1505 C1506 C1507 C1508 C1509 C1510
177 32
M_B_DQ52 DQ51 VSS
164 37
1
DQ52 VSS
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
M_B_DQ53 166 38
M_B_DQ54 DQ53 VSS
M_B_DQ55
174
DQ54 VSS
43 DY DY DY DY
Place these caps 176 44
2
M_B_DQ56 DQ55 VSS
181 48
close to VTT1 and M_B_DQ57 DQ56 VSS
183 49
0D75V_S0 M_B_DQ58 DQ57 VSS
VTT2. 191 54
M_B_DQ59 DQ58 VSS
193 55
M_B_DQ60 DQ59 VSS
180 60
C1518 C1519 C1520 C1521 M_B_DQ61 DQ60 VSS
182 61
M_B_DQ62 DQ61 VSS
192 65
1
DQ62 VSS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
M_B_DQ63 194 66
DQ63 VSS
DY DY M_B_DQS#0 VSS
71
C1511 C1512 C1513 C1514
10 72
2
M_B_DQS#1 DQS0# VSS

27 127
1
DQS1# VSS
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_B_DQS#2 45 128
M_B_DQS#3 DQS2# VSS
62 133
M_B_DQS#4 DQS3# VSS
135 134
2
M_B_DQS#5 DQS4# VSS
152 138
M_B_DQS#6 DQS5# VSS
169 139
M_B_DQS#7 DQS6# VSS
186 144
DQS7# VSS
145
M_B_DQS0 VSS
12 150
M_B_DQS1 DQS0 VSS
M_B_DQS#[7:0] 6 29 151
M_B_DQS2 DQS1 VSS
47 155
B M_B_DQS3 DQS2 VSS B
M_B_DQS[7:0] 6 64 156
M_B_DQS4 DQS3 VSS
137 161
M_B_DQS5 DQS4 VSS
154 162
M_B_DQS6 DQS5 VSS
171 167
M_B_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
6 M_B_DIM0_ODT0 116 173
ODT0 VSS
6 M_B_DIM0_ODT1 120 178
ODT1 VSS
179
VSS
M_VREF_CA_DIMM1 126 184
VREF_CA VSS
M_VREF_DQ_DIMM1 1 185
VREF_DQ VSS
189
VSS
14,37 DDR3_DRAMRST# 30 190
RESET# VSS
195
VSS
196
VSS
0D75V_S0 203 205
VTT1 VSS
204 206
VTT2 VSS
DDR3-204P-144-GP-U1
(H=4mm) 62.10024.G21
2nd = *62.10017.X41
3rd = *62.10017.V51
62.10017.X41
3RD:62.10017.V51
A A
<Core Design>
Wistron Corporation
Title
DDR3-SODIMM2
A2
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Wistron Corporation A
Title
DDR3-SODIMM2
A4
LA480 SD
5 4 3 2 1
A B C D E
3D3V_S0
RN1701
1 4 L_CTRL_DATA
2 3 L_CTRL_CLK
PCH1D 4 OF 10
SRN2K2J-1-GP 3D3V_S0
49 L_BKLT_EN J47 L_BKLTEN SDVO_TVCLKINN AP43
49 LVDS_VDD_EN M45 L_VDD_EN SDVO_TVCLKINP AP45
4 L_DDC_DATA(K47): DDI Port B Detect:(SDVO_CTRL_ DATA) 4
49 L_BKLT_CTRL P45 L_BKLTCTL SDVO_STALLN AM42 1: Port B detected
3
4
This signal is on the LVDS interface. SDVO_STALLP AM40 0: Port B not detected
T40 RN1706
This signal needs to be left NC if eDP is 49 LVDS_DDC_CLK_R
K47
L_DDC_CLK
AP39 SRN2K2J-1-GP
49 LVDS_DDC_DATA_R L_DDC_DATA SDVO_INTN
used for the local flat panel display SDVO_INTP AP40
L_CTRL_CLK T45
L_CTRL_DATA L_CTRL_CLK
P39
2
1
L_CTRL_DATA
LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK PCH_HDMI_CLK 51
RN1702 AF36 M39
LVD_VBG SDVO_CTRLDATA PCH_HDMI_DATA 51
1
2 3 L_BKLT_EN RN1704
1 4 LVDS_VDD_EN R1701 2 3 LVDS_VREFH AE48
2K37R2F-GP LVDS_VREFL LVD_VREFH
1 4 AE47 LVD_VREFL DDPB_AUXN AT49
SRN100KJ-6-GP
Close to PCH SRN0J-6-GP DDPB_AUXP AT47
AT40 HDMI_PCH_DET 51
2
DDPB_HPD
49 LVDSA_CLK# AK39 LVDSA_CLK#
LVDS
49 LVDSA_CLK AK40 LVDSA_CLK DDPB_0N AV42 HDMI_DATA2_R# 51
Close to PCH and keep 20mil AV40
away from other signal. DDPB_0P HDMI_DATA2_R 51
49 LVDSA_DATA0# AN48 LVDSA_DATA#0 DDPB_1N AV45 HDMI_DATA1_R# 51 HDMI
49 LVDSA_DATA1# AM47 LVDSA_DATA#1 DDPB_1P AV46 HDMI_DATA1_R 51
Digital Display Interface

49 LVDSA_DATA2# AK47 LVDSA_DATA#2 DDPB_2N AU48 HDMI_DATA0_R# 51
AJ48 LVDSA_DATA#3 DDPB_2P AU47 HDMI_DATA0_R 51
DDPB_3N AV47 HDMI_CLK_R# 51
49 LVDSA_DATA0 AN47 LVDSA_DATA0 DDPB_3P AV49 HDMI_CLK_R 51
0511-CHECK AM49 0511-CHECK
49 LVDSA_DATA1 LVDSA_DATA1
49 LVDSA_DATA2 AK49 LVDSA_DATA2
CRT_RED AJ47 P46
CRT_BLUE LVDSA_DATA3 DDPC_CTRLCLK
DDPC_CTRLDATA P42
3 CRT_GREEN 3
AF40 LVDSB_CLK#
AF39 AP47 DDI PCH Pin HDMI/DVI
LVDSB_CLK DDPC_AUXN PORT Names Mapping
DDPC_AUXP AP49
5
6
7
8
AH45 LVDSB_DATA#0 DDPC_HPD AT38

RN1705 AH47
SRN150F-1-GP LVDSB_DATA#1 DDPB_[0]P TMDSB_DATA2
AF49 LVDSB_DATA#2 DDPC_0N AY47
AF45 AY49 DDPB_[0]N TMDSB_DATA2#
LVDSB_DATA#3 DDPC_0P DDPB_[1]P TMDSB_DATA1
DDPC_1N AY43
DDPB_[1]N TMDSB_DATA1#
AH43 AY45
4
3
2
1
LVDSB_DATA0 DDPC_1P DDPB_[2]P TMDSB_DATA0

Close to PCH AH49 LVDSB_DATA1 DDPC_2N BA47 DDPB_[2]N TMDSB_DATA0#
AF47 LVDSB_DATA2 DDPC_2P BA48 DDPB_[3]P TMDSB_CLK
AF43 LVDSB_DATA3 DDPC_3N BB47 DDPB_[3]N TMDSB_CLK#
DDPC_3P BB49 DDPB_AUXP NA
DDPB_AUXN NA
PORT-B DDPB_HPD HDMIB_HPD
50 CRT_BLUE N48 CRT_BLUE DDPD_CTRLCLK M43 SDVO_CTRLCLK HDMIB_CTRLCLK
P49 M36 SDVO_CTRLDATA HDMIB_CTRLDATA
50 CRT_GREEN CRT_GREEN DDPD_CTRLDATA
50 CRT_RED T49 CRT_RED
CRT_BLUE
CRT_GREEN AT45
DDPD_AUXN
CRT
CRT_RED T39 AT43
50 CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
EC1701 EC1702 EC1703 M40 BH41
50 CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD
1
1
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
DDPD_0N BB43
DY DY DY 50 CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
50 CRT_VSYNC M49 BF44
2
CRT_VSYNC DDPD_1N
DDPD_1P BE44
DDPD_2N BF42
2 DAC_IREF_R 2
T43 DAC_IREF DDPD_2P BE42
T42 CRT_IRTN DDPD_3N BJ42
1
DDPD_3P BG42
R1702
1KR2D-1-GP PANTHER-GP-NF
2
The recommended value for this external resistor is 1.0 k ±0.5%. The CRT DAC outputs may be
Notes: measured when the display is completely white. If CRT DAC signal voltage value is between 665
mV to 770 mV, then the video level is within VESA specification and the reference resistor
1K 0.5% 0402 value is optimal for the motherboard design.
1 <Core Design> 1
Wistron Corporation
Title
PCH : LVDS/CRT/DDI
A3 SD
LA480
A B C D E
A B C D E
4 4
PCH1E 5 OF 10
SSID = PCH RSVD1
RSVD2
AY7
AV7
BG26 AU3
TP1 RSVD3
BJ26 BG4
TP2 RSVD4
BH25
TP3
BJ16 AT10
TP4 RSVD5 BBS_BIT1
RN1801 BG16 BC8 1 DY 2 R1802
INT_PIRQH# TP5 RSVD6 1KR2J-1-GP
1 10 3D3V_S0 AH38
INT_PIRQB# INT_PIRQD# TP6
2 9 AH37 AU2 1 DY 2 R1803 BBS_BIT0 21
INT_PIRQF# LCD_DET# TP7 RSVD7 1KR2J-1-GP
3 8 AK43 AT4
INT_PIRQA# INT_PIRQC# TP8 RSVD8
4 7 AK45 AT3
INT_PIRQG# TP9 RSVD9
3D3V_S0 5 6 C18 AT1
TP10 RSVD10 BOOT BIOS Strap
N30 AY3
TP11 RSVD11
SRN8K2J-2-GP-U H3 AT5
TP12 RSVD12
AH12
TP13 RSVD13
AV3 GNT1#/GPIO51 SATA1GP/GPIO19 BOOT BIOS Location
AM4 AV1
TP14 RSVD14
AM5
TP15 RSVD15
BB1 0 0 LPC
Y13 BA3
TP16 RSVD16
2 1 PCI_GNT3# K24 BB5 0 1 Reserved
R1801 TP17 RSVD17
DY 4K7R2J-2-GP L24
TP18 RSVD18
BB3
AB46
TP19 RSVD19
BB7 1 0 Reserved
AB45 BE8
TP20 RSVD20
RSVD
A16 swap override Strap/Top-Block RSVD21
BD4 1 1 SPI(Default)
Swap Override jumper BF6
RSVD22
PCI_GNT#3 Low = A16 swap B21 AV5 NV_ALE 1 TP1814
TP21 RSVD23 NV_RCOMP TP1812
override/Top-Block M20 AV10 1
TP22 RSVD24
Swap Override enabled AY16
TP23
BG46 AT8
High = Default For PPT USB3.0 feature TP24 RSVD25
RSVD26
AY5 Mini Card2 (WWAN)
BA2
RSVD27
BE28
USB3RN1
62 USB3_RX1_N BC30 AT12
USB3RN2 RSVD28
BE32 BF3
DGPU_HOLD_RST# USB3RN3 RSVD29
1 2 BJ32
R1819 10KR2J-3-GP
62 USB3_RX3_N
62 USB3_RX1_P
BC28
BE30
USB3RN4
USB3RP1
USB3RP2 Utilize Port 9 for USB debug
Gx8 USB Table
BF32
USB3RP3 USB_PN0 TP1819
3
62 USB3_RX3_P BG32
USB3RP4 USBP0N
C24 1 Pair Device 3
AV26 A24 USB_PP0 1 TP1820
USB3TN1 USBP0P
62 USB3_TX1_N BB26
USB3TN2 USBP1N
C25 USB_PN1 62 0 X
AU28
USB3TN3 USBP1P
B25 USB_PP1 62 USB3.0 ext port 1
3D3V_S0 62 USB3_TX3_N AY30
USB3TN4 USBP2N
C26 USB_PN2 82 1 USB3.0, ext port1
AU26
USB3TP1 USBP2P
A26 USB_PP2 82 USB2.0 ext port 4
62 USB3_TX1_P AY26
USB3TP2 USBP3N
K28 USB_PN3 62 2 USB2.0, ext port4
AV28
USB3TP3 USBP3P
H28 USB_PP3 62 USB3.0 ext port 2
62 USB3_TX3_P AW30 E28 USB_PN4 63 3 USB3.0, ext port2
2
USB3TP4 USBP4N
3D3V_S0 USBP4P
D28 USB_PP4 63 BLUETOOTH
R1814 C28 4 Bluetooth
USBP5N USB_PN5 82
10KR2F-2-GP USBP5P
A28 USB_PP5 82 CARD READER
DY USBP6N
C29 5 CARD READER
R1818 B29
1
INT_PIRQA# USBP6P
8K2R2J-3-GP K40
PIRQA# USBP7N
N28 6 X
DGPU_PWR_EN# INT_PIRQB# K38 M28
PIRQB# USBP7P
PCI
INT_PIRQC# X
DY INT_PIRQD#
H38
PIRQC# USBP8N
L30 USB_PN8 66 7
G38 K30 USB_PP8 66
2
PIRQD# USBP8P
G30 USB_PN9 82 8 3G
1
R1815 DGPU_HOLD_RST# USBP9N

83 DGPU_HOLD_RST# C46
REQ1#/GPIO50 USBP9P
E30 USB_PP9 82 USB2.0 ext port 3
USB
10KR2F-2-GP TP1805 1 DGPU_SELECT# C44 C30 9 USB2.0, ext. port 3
REQ2#/GPIO52 USBP10N USB_PN10 64
DGPU_PWR_EN# E40 A30 Fingerprint
93 DGPU_PWR_EN# REQ3#/GPIO54 USBP10P USB_PP10 64
L32 10 Finger Print
1
USBP11N USB_PN11 65
BBS_BIT1 D47 K32 Mini Card1 (WLAN)
GNT1#/GPIO51 USBP11P USB_PP11 65
DGPU_PWM_SELECT# E42 G32 11 Mini Card1 (WLAN)
PCI_GNT3# GNT2#/GPIO53 USBP12N USB_PN12 49
F46
GNT3#/GPIO55 USBP12P
E32 USB_PP12 49 CAMERA
USBP13N
C32 12 CAMERA
A32
USBP13P
49 LCD_DET# G42
PIRQE#/GPIO2 13 X
3D3V_S0 1 2 INT_PIRQF# G40
27,56 SATA_ODD_DA# PIRQF#/GPIO3
R1813 INT_PIRQG# C42 C33 USB_RBIAS 1 2
0R2J-2-GP INT_PIRQH# PIRQG#/GPIO4 USBRBIAS# R1811
D44
PIRQH#/GPIO5 22D6R2F-L1-GP USB 2.0 Overcurrent Pin Default Usage
R1817
2
B33
8K2R2J-3-GP TP1813 PCI_PME# USBRBIAS Pin Default Port Pin Default Port
1 K10
PME# Mapping Mapping
DY PCI_PLTRST# C6 A14 USB_OC#0_1
PLTRST# OC0#/GPIO59 USB_OC#0_1 62
K20 USB_OC#2_3 OC0# Port 0, Port 1 OC4# Port 8, Port 9
OC1#/GPIO40 USB_OC#2_3 61
USB_OC#4_5 OC1# Port 2, Port 3 OC5# Port 10, Port 11
1
B17 USB_OC#4_5 62
R1804 CLK_PCI_LPC_R H49 OC2#/GPIO41 USB_OC#6_7 OC2# Port 4, Port 5 OC6# Port 12, Port 13
65,71 CLK_PCI_LPC 1 2 22R2J-2-GP C16
DGPU_PWM_SELECT# R1805 CLK_PCI_FB_R H43 CLKOUT_PCI0 OC3#/GPIO42 USB_OC#8_9 OC3# Port 6, Port 7 OC7# Not Used
20 CLK_PCI_FB 1 2 22R2J-2-GP L16 USB_OC#8_9 82
2 R1806 CLK_PCI_KBC_R J48 CLKOUT_PCI1 OC4#/GPIO43 USB_OC#10_11 2
27 CLK_PCI_KBC 1 2 22R2J-2-GP A16
CLKOUT_PCI2 OC5#/GPIO9 USB_OC#12_13
K42 D14
CLKOUT_PCI3 OC6#/GPIO10 PCH_GPIO14
H40 C14
CLKOUT_PCI4 OC7#/GPIO14
PANTHER-GP-NF
OC[3:0]# for Device 29 (Ports 0-7)
OC[7:4]# for Device 26 (Ports 8-13)
Reserve Buffer or not? RN1802

USB_OC#2_3 1 10 3D3V_S5
PCH_GPIO14 2 9 USB_OC#12_13
USB_OC#6_7 3 8 USB_OC#8_9
1 2 PCI_PLTRST# USB_OC#0_1 4 7 USB_OC#10_11
5,27,31,36,65,66,71,80,82,83,97 PLT_RST#
R1807 5 6 USB_OC#4_5
3D3V_S5
0R2J-2-GP
SRN8K2J-2-GP-U
1
R1816 C1801
1
100KR2J-1-GP SC220P50V2KX-3GP
DY DY
2
2
1 1
<Core Design>
Wistron Corporation
Title
PCH : PCI/USB/NVRAM/RSVD
A2 SD
LA480
A B C D E
A B C D E
SSID = PCH
For platforms not supporting Deep S4/S5
1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)
4 2.DPWROK and RSMRST# will rise at the same time (connected on board) 4
3.SLP_SUS# and SUSACK# are left as ‘no connect’
4.SUSWARN# used as SUSPWRDNACK/GPIO30
PCH1C 3 OF 10
4 DMI_RXN[3:0] FDI_TXN[7:0] 4
DMI_ZCOMP keep W=4 mils and DMI_RXN0 BC24 BJ14 FDI_TXN0
routing length less than 500 DMI_RXN1 DMI0RXN FDI_RXN0 FDI_TXN1
BE20 AY14
mils. DMI_RXN2 DMI1RXN FDI_RXN1 FDI_TXN2
BG18 BE14
DMI_IRCOMP keep W=4 mils and DMI_RXN3 DMI2RXN FDI_RXN2 FDI_TXN3
BG20 BH13
routing length less than 500 DMI3RXN FDI_RXN3 FDI_TXN4
4 DMI_RXP[3:0] BC12
mils. DMI_RXP0 FDI_RXN4 FDI_TXN5
BE24 BJ12 DSWODVREN - On Die DSW VR Enable
DMI_RXP1 DMI0RXP FDI_RXN5 FDI_TXN6
BC20 BG10
DMI_RXP2 DMI1RXP FDI_RXN6 FDI_TXN7
BJ18 BG9 HIGH Enabled (DEFAULT)
DMI_RXP3 DMI2RXP FDI_RXN7
BJ20 FDI_TXP[7:0] 4
DMI3RXP FDI_TXP0
4 DMI_TXN[3:0] BG14
DMI_TXN0 FDI_RXP0 FDI_TXP1 LOW Disabled
AW24 BB14
DMI_TXN1 DMI0TXN FDI_RXP1 FDI_TXP2
AW20 BF14
SYS_PWROK DMI_TXN2 DMI1TXN FDI_RXP2 FDI_TXP3
1
R1926
DY 2
10KR2J-3-GP DMI_TXN3
BB18
DMI2TXN FDI_RXP3
BG13
FDI_TXP4
AV18 BE12
DMI3TXN FDI_RXP4 RTC_AUX_S5
DMI
FDI
BG12 FDI_TXP5
4 DMI_TXP[3:0] FDI_RXP5
1 2 PWROK DMI_TXP0 AY24 BJ10 FDI_TXP6
R1904 100KR2J-1-GP DMI_TXP1 DMI0TXP FDI_RXP6 FDI_TXP7
AY20 BH9
DMI_TXP2 DMI1TXP FDI_RXP7 R1917
AY18 1 2 330KR2J-L1-GP
DMI_TXP3 DMI2TXP
AU18
DMI3TXP
AW16 FDI_INT 4
FDI_INT DSWODVREN R1918 1 DY 2 330KR2J-L1-GP
1D05V_VTT BJ24 AV12
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 4
R1905 1 SYS_RESET# R1901
3D3V_S0
Platforms supporting Deep S4/S5, but not wishing
10KR2J-3-GP
DY 2
DMI_COMP_R
1 2 49D9R2F-GP BG25 BC10 FDI_FSYNC1 4
to participate in the handshake during wake and Deep S4/S5 DMI_IRCOMP FDI_FSYNC1
entry may tie SUSACK# to SUSWARN#. 1 2 R1902 RBIAS_CPY BH21 AV14
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 4
750R2F-GP
BB10 FDI_LSYNC1 4
FDI_LSYNC1 3D3V_S0
3 3
SUS_ACK#: For non-DWS platforms, this signal can be left unconnected.

Due to the internal pull-up on this signal it will be pulled high A18 DSWODVREN PM_CLKRUN# R1919 1 2 8K2R2J-3-GP
DSWVRMEN
in order for the boot sequence to proceed. 1 2 PM_RSMRST#
R1992 0R0402-PAD
System Power Management

SUS_PWR_ACK SUSACK# PCH_DPWROK
1
R1915
DY 2
0R2J-2-GP
C12
SUSACK# DPWROK
E22 1
R1911
DY 2 RTC_AUX_S5
10KR2J-3-GP
R1916 1 2 0R0402-PAD SYS_RESET# K3 B9
5 XDP_DBRESET# SYS_RESET# WAKE# PCIE_WAKE# 31,65,66
SYS_PWROK: the system is ready to start the exit from P12 N3

reset (de-asserts PLT_RST# to the processor) 36 SYS_PWROK SYS_PWROK CLKRUN#/GPIO32 PM_CLKRUN# 27
1 DY 2
R1923 0R2J-2-GP
PWROK: it indicates to PCH that 1 2 PWROK L22 G8 PM_SUS_STAT# 1 TP1901
its CORE well power is stable. 27 S0_PWR_GOOD PWROK SUS_STAT#/GPIO61
R1914 0R0402-PAD
Active Sleep Well 1 2 MEPWROK L10 N14 SUS_CLK 1 R1913 2

(ASW) Power OK APWROK SUSCLK/GPIO62 PCH_SUSCLK_KBC 27
R1930 0R2J-2-GP 0R0402-PAD
45 MPWROK 1 2 Non-SBA
R1931 0R2J-2-GP B13 D10 PM_SLP_S5# 1 TP1902
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms 37 PM_DRAM_PWRGD DRAMPWROK SLP_S5#/GPIO63
SBA
PM_RSMRST# C21 H4
RSMRST# SLP_S4# PM_SLP_S4# 27,46,97
SUS_PWR_ACK K16 F4 This signal is used to control power planes to the IntelR ME
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# 27,36,37,47 sub-system. This signal will be asserted in M-off state. If M3
is not supported then SLP_A# will have the same timings as
PM_PWRBTN# E20 G10 SLP_S3#.
27,97 PM_PWRBTN# PWRBTN# SLP_A# PM_SLP_A# 27,45
H20 G16 PM_SLP_SUS# 1 TP1904

27 AC_PRESENT ACPRESENT/GPIO31 SLP_SUS# For platforms supporting DEEP S4/S5 state, a low on this
signal indicates that PCH is in Deep Sleep state and that
BATLOW# E10 AP14 EC/platform logic does not need to keep the Suspend Rails
BATLOW#/GPIO72 PMSYNCH H_PM_SYNC 5 ON.
If high means EC must keep SUS rails ON.
PM_RI# A10 K14 PM_SLP_LAN# 1 TP1905 If DEEP S4/S5 is not supported, then this pin can be left
RI# SLP_LAN#/GPIO29 unconnected.
2 2
3D3V_S5 PANTHER-GP-NF
RN1901
8 1 BATLOW#
7 2 PM_RI#
SUSPWRDNACK : No longer requires a 10-K pull-up to VccSUS 6 3 SUS_PWR_ACK
(3.3 V). 5 4 PCIE_WAKE#
SRN10KJ-6-GP
PCH_WAKE# 3D3V_AUX_S5
CRB : 1K
R1909 2 1 10KR2J-3-GP AC_PRESENT 2 1
CHKLIST: 10K R1925 100KR2J-1-GP
2
R1922
DY PM_PWRBTN#
2 1 10KR2J-3-GP R1924
10KR2J-3-GP Q1901
4 3 PM_RSMRST# 1 2 RSMRST#_KBC 27
R1921
1
3V_5V_POK_# 5 2 1KR2J-1-GP
PM_RSMRST# 3V_5V_POK 41
R1908 2 1
10KR2J-3-GP 6 1
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
1 1
<Core Design>
Wistron Corporation
Title
PCH : DMI/FDI/PM
A2 SD
LA480
A B C D E
A B C D E
3D3V_S5
4 SSID = PCH 0511-CHECK 3D3V_S5
SMB_CLK 4 1 RN2003
4
1
SMB_DATA 3 2 SRN2K2J-1-GP
R2004
10KR2J-3-GP SML0_DATA 4 1 RN2004
PCH1B 2 OF 10 SML0_CLK 3 2 SRN2K2J-1-GP
If PCIE port 1 is disabled, it will
2
BG34 PEG_CLKREQ#_R SML1_CLK 2 3 RN2005
cause all PCIE port disabled BJ34
PERN1
E12 EC_SWI# SML1_DATA 1 4 SRN2K2J-1-GP
1
PERP1 SMBALERT#/GPIO11
AV32 WWAN
PETN1 SMB_CLK R2005 PCIE_CLK_RQ6#
AU32 H14 SMB_CLK 80 1 4 RN2006
PETP1 SMBCLK 10KR2J-3-GP PCH_GPIO74
DY 2 3 SRN10KJ-5-GP
BE34 C9 SMB_DATA
65 PCIE_RXN2 PERN2 SMBDATA SMB_DATA 80
BF34
2
65 PCIE_RXP2 PERP2
C2016 1 2 SCD1U10V2KX-5GP PCIE_TXN2_C BB32 DRAMRST_CNTRL_PCH 1 2 R2009
65 PCIE_TXN2
C2015 1 2 SCD1U10V2KX-5GP PCIE_TXP2_C AY32
PETN2 WLAN 1KR2J-1-GP
65 PCIE_TXP2 PETP2
SMBUS
A12 DRAMRST_CNTRL_PCH
SML0ALERT#/GPIO60 DRAMRST_CNTRL_PCH 12,37
BG36
PERN3 SML0_CLK
BJ36 C8
PERP3 SML0CLK 3D3V_S0
AV34 Card Reader
PETN3 SML0_DATA RN2007
AU34 G12
PETP3 SML0DATA
2 3
31 PCIE_RXN4 BF36 1 4
PERN4
31 PCIE_RXP4
C2005 1 2 SCD1U10V2KX-5GP PCIE_TXN4_C
BE36
AY34
PERP4 LAN C13 PCH_GPIO74 SRN2K2J-1-GP
31 PCIE_TXN4 PETN4 SML1ALERT#/PCHHOT#/GPIO74
C2006 1 2 SCD1U10V2KX-5GP PCIE_TXP4_C BB34
31 PCIE_TXP4 PETP4
E14 SML1_CLK
SML1CLK/GPIO58 SML1_CLK 27
PCI-E*
BG37 Q2001
PERN5 SML1_DATA SMB_DATA
BH37 M16 SML1_DATA 27 6 1 PCH_SMBDATA 14,15,65,66
PERP5 SML1DATA/GPIO75
AY36
PETN5
BB36 5 2
PETP5
BJ38 4 3
PERN6
BG38
PERP6
Controller
AU36 M7 CL_CLK 1 TP2001 2N7002KDW-GP
PETN6 CL_CLK1
AV36
PETP6 84.2N702.A3F PCH_SMBCLK 14,15,65,66
2nd = 84.DM601.03F
Link
BG40 T11 CL_DATA 1 TP2002 SMB_CLK
PERN7 CL_DATA1
BJ40
PERP7
AY40
PETN7 CL_RST# TP2003
BB40 P10 1
PETP7 CL_RST1# XTAL25_IN
3 2 1 3
BE38 X2001
PERN8 C2008
BC38
PERP8 SC15P50V2JN-2-GP
AW38 1 4
2
PETN8
AY38
PETP8 0511-CHECK R2006
M10 PEG_CLKREQ#_R 1 2 PEG_CLKREQ# 83
1M1R2J-GP
PEG_A_CLKRQ#/GPIO47 R2003 0R0402-PAD
Y40 2 3
CLKOUT_PCIE0N C2007
Y39
1
CLKOUT_PCIE0P SC15P50V2JN-2-GP
AB37 CLK_PCIE_VGA# 83
PCIE_CLK_RQ0# CLKOUT_PEG_A_N XTAL25_OUT XTAL-25MHZ-155-GP
CLOCKS
J2 AB38 CLK_PCIE_VGA 83 2 1
PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P
82.30020.D41
RN2012 SRN0J-6-GP serial 0ohm RN? 2nd = 82.30020.G71
WLAN CLK 65 CLK_PCIE_WLAN# 1 4 CLK_PCH_SRC1_N AB49
CLKOUT_PCIE1N CLKOUT_DMI_N
AV22 CLK_EXP_N 5 3rd = 82.30020.G61
2 3 CLK_PCH_SRC1_P AB47 AU22
65 CLK_PCIE_WLAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_EXP_P 5
PCIE_CLK_WLAN_REQ# M1
65 PCIE_CLK_WLAN_REQ# PCIECLKRQ1#/GPIO18
AM12 CLK_DP_N 1 TP2006
CLKOUT_DP_N CLK_DP_P 3D3V_S0 3D3V_S0
CLKOUT_DP_P
AM13 1 TP2007 UMA_DISCRETE#
AA48 UMA: 1 1
CLKOUT_PCIE2N
AA47 DIS :0 1
1
CLKOUT_PCIE2P CLK_BUF_EXP_N
BF18
PCIE_CLK_CR_REQ# CLKIN_DMI_N CLK_BUF_EXP_P R2012 R2013 SG(PX) : 0 0
V10 BE18
PCIECLKRQ2#/GPIO20 CLKIN_DMI_P 10KR2J-3-GP 10KR2J-3-GP Optimus(Muxless) : 1 0
RN2016 SRN0J-6-GP RN2008 Non-SBA UMA
1 4 CLK_PCH_SRC3_N Y37 BJ30 CLK_BUF_CPYCLK_N 2 3
2
31 CLK_PCIE_LAN# CLK_PCH_SRC3_P CLKOUT_PCIE3N CLKIN_GND1_N CLK_BUF_CPYCLK_P
2 3 Y36 BG30 1 4
LAN CLK 31 CLK_PCIE_LAN CLKOUT_PCIE3P CLKIN_GND1_P DGPU_PRSNT#
SBA_Support# 22
PCIE_CLK_LAN_REQ# A8 SRN10KJ-5-GP
31 PCIE_CLK_LAN_REQ#
1
PCIECLKRQ3#/GPIO25 CLK_BUF_DOT96_N
G24
CLKIN_DOT_96N CLK_BUF_DOT96_P R2010 R2011
E24
CLKIN_DOT_96P 10KR2J-3-GP 10KR2J-3-GP
Y43
CLKOUT_PCIE4N PL 10K FOR Integrated CLOCK GEN mode.
Y45
CLKOUT_PCIE4P CLK_BUF_CKSSCD_N
SBA OPS
AK7 RN2020 SRN10KJ-5-GP
2
PCIE_CLK_RQ4# CLKIN_SATA_N CLK_BUF_CKSSCD_P CLK_BUF_DOT96_N 1
L12 AK5 4
PCIECLKRQ4#/GPIO26 CLKIN_SATA_P CLK_BUF_DOT96_P 2 3
V45 K45 CLK_BUF_REF14

PCIE_CLK_LAN_REQ# PCIE_CLK_WLAN_REQ# CLKOUT_PCIE5N REFCLK14IN RN2021 SRN10KJ-5-GP 3D3V_S5
V46
CLKOUT_PCIE5P CLK_BUF_CKSSCD_N 1 RN2001
4
PCIE_CLK_RQ5# L14 H45 CLK_PCI_FB CLK_BUF_CKSSCD_P 2 3 1 8 CLK_PCIE_NEW_REQ#
PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK CLK_PCI_FB 18
2 2 7 PCIE_CLK_LAN_REQ# 2
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1
3 6 PCIE_CLK_RQ5#
EC2001 EC2002 AB42 V47 XTAL25_IN RN2019 SRN10KJ-5-GP 4 5 PCIE_CLK_RQ4#
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT CLK_BUF_EXP_N
DY DY AB40 V49 1 4
2
CLKOUT_PEG_B_P XTAL25_OUT CLK_BUF_EXP_P SRN10KJ-6-GP

2 3
PEG_B_CLKRQ# E6 +VCCDIFFCLKN RN2002
PEG_B_CLKRQ#/GPIO56
1 8 EC_SWI#
Y47 XCLK_RCOMP 1 2 CLK_BUF_REF14 1 2 2 7 PCIE_CLK_RQ0#
XCLK_RCOMP R2007 R2008
V40 3 6
CLKOUT_PCIE6N
V42 90D9R2F-1-GP 10KR2J-3-GP 4 5 PEG_B_CLKRQ#
CLKOUT_PCIE6P
PCIE_CLK_RQ6# T13 SRN10KJ-6-GP
PCIECLKRQ6#/GPIO45
V38 K43 JTAG_TCK 1 TP2004
FLEX CLOCKS
CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64
V37
CLKOUT_PCIE7P
DY
F47 CLK_PCH_48M_L 1 2
CLKOUTFLEX1/GPIO65 CLK_PCH_48M 82
CLK_PCIE_NEW_REQ# K12 R2016 22R2J-2-GP
PCIECLKRQ7#/GPIO46 CLK_27M_VGA_R TP2005
H47 1
TP2010 PCIE_CLK_XDP_N CLKOUTFLEX2/GPIO66
1 AK14
TP2011 PCIE_CLK_XDP_P CLKOUT_ITPXDP_N DGPU_PRSNT#
1 AK13 K49
SCD1U16V2KX-3GP
1
3D3V_S0 CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 EC2003
RN2018
PCIE_CLK_CR_REQ# PANTHER-GP-NF
1 4 DY
2
2 3 PCIE_CLK_WLAN_REQ#
SRN10KJ-5-GP – Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3

PCIECLKRQ1# and PCIECLKRQ2# – Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2
Support S0 power only if more than 2 PCI clocks + PCI loopback are routed.
1 1
<Core Design>
Wistron Corporation
Title
PCH : PCIE/SMBUS/CLK
A2 SD
LA480
A B C D E
A B C D E
SSID = PCH
1 2
RTC_X1
RTC_X2
RTC_AUX_S5
SRN20KJ-GP-U
1
2
4
3
INTVRMEN- Integrated SUS
1.05V VRM Enable
1
R2101 10MR2J-L-GP RN2104 C2103 High - Enable internal VRs
SC1U6D3V2KX-GP Low - Enable external VRs
2
X2101
0511-CHECK
1 2 PCH1A 1 OF 10
Check with SW
C2101 C2102 3D3V_S0
LPC_AD[0..3] 27,65,71
RTC_X1 A20 C38 LPC_AD0_TPM R2111 1 2 22R2F-1-GP LPC_AD0
Q2102
1
1
RTCX1 FWH0/LAD0
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
XTAL-32D768KHZ-15-GP A38 LPC_AD1_TPM R2118 1 2 22R2F-1-GP LPC_AD1
FWH1/LAD1
LPC
82.30001.C21 G RTC_X2 C20 B37 LPC_AD2_TPM R2119 1 2 22R2F-1-GP LPC_AD2
27 RTCRST_ON
2
RTCX2 FWH2/LAD2 LPC_AD3_TPM R2120 22R2F-1-GP LPC_AD3
C37 1 2
2
2
RTC_RST# FWH3/LAD3 R2128
4 D D20 4
RTCRST#
D36 LPC_FRAME#_L R2121 1 2 22R2F-1-GP LPC_FRAME# 27,65,71 10KR2J-3-GP
SRTC_RST# FWH4/LFRAME#
S G22 DY
2
G2101 SRTCRST#
E36
1
1
LDRQ0#
RTC
C2104 GAP-OPEN 2 1 SM_INTRUDER# K22 K36
2N7002K-2-GP INTRUDER# LDRQ1#/GPIO23 APS_LED 68
SC1U6D3V2KX-GP R2104 1M1R2J-GP
84.2N702.J31 RTC_AUX_S5 1 2 PCH_INTVRMEN C17 V5 APS_LED
2
INTVRMEN SERIRQ INT_SERIRQ 27
2ND = 84.2N702.031 R2105 330KR2F-L-GP
1
1
R2131
DY 0R2J-2-GP
2
AM3 SATA_RXN0 66
HDA_BITCLK SATA0RXN
N34 AM1
HDA_BCLK SATA0RXP SATA_RXP0 66 m-SATA
SATA 6G
AP7 SATA_TXN0 66
2
HDA_SYNC SATA0TXN
L34 AP5 SATA_TXP0 66
2
0511-CHECK ADD BLOCK FET IN CODEC PAGE. R2130 HDA_SYNC SATA0TXP
0R2J-2-GP D2130 T10 AM10
29 HDA_SPKR SPKR SATA1RXN SATA_RXN1 56
33R2J-2-GP2 DY 1 R2122 HDA_SYNC AM8
29 HDA_CODEC_SYNC BAS16-6-GP
83.00016.K11 HDA_RST# K34
SATA1RXP
AP11
SATA_RXP1 56 HDD1
1
HDA_RST# SATA1TXN SATA_TXN1 56
33R2J-2-GP2 1 R2123 HDA_SDOUT 2nd = 83.00016.M11
29 HDA_CODEC_SDOUT DY SATA1TXP
AP10 SATA_TXP1 56
3rd = 83.00016.N11
3
29 HDA_SDIN0 E34 AD7
HDA_SDIN0 SATA2RXN
AD5
SATA2RXP mSATA, CRV USE PORT2
G34 AH5
33R2J-2-GP2 HDA_RST# HDA_SDIN1 SATA2TXN
29 HDA_CODEC_RST# 1 R2126 KBC_RTCRST# 27 AH4
33R2J-2-GP2 HDA_BITCLK SATA2TXP
29 HDA_CODEC_BITCLK 1 R2129 Notes: C34
HDA_SDIN2
IHDA
AB8
ME_UNLOCK (HDA_SDO) connect to EC. SATA3RXN
A34 AB10
HDA_SDIN3 SATA3RXP
Make sure EC drive this pin "low" all the time. AF3
SATA3TXN
AF1
HDA_SDOUT SATA3TXP
Flash Descriptor Security Overide A36
HDA_SDO
+3VS_+1.5VS_HDA_IO
SATA
R2107 1 2 1KR2J-1-GP Y7
27 ME_UNLOCK SATA4RXN SATA_RXN4 56
Low = Default Y5
1 2 HDA_SDOUT
DY 1KR2J-1-GP HDA_SDOUT High = Enable TP2105 1 PCH_GPIO33 C36
HDA_DOCK_EN#/GPIO33
SATA4RXP
SATA4TXN
AD3
SATA_RXP4
SATA_TXN4
56
56
ODD
R2102 AD1
SATA4TXP SATA_TXP4 56
N32
HDA_DOCK_RST#/GPIO13
Y3
SATA5RXN
Y1
NO REBOOT STRAP
SATA5RXP
SATA5TXN
AB3 E-SATA
PCH_JTAG_TCK_BUF J3 AB1
3D3V_S0 JTAG_TCK SATA5TXP
No Reboot Strap
TP2102 1 PCH_JTAG_TMS H7 Y11 1D05V_VTT
JTAG_TMS SATAICOMPO
JTAG
1 HDA_SPKR
DY 1KR2J-1-GP
2 Low = Default
3 R2106 HDA_SPKR High = No Reboot TP2103 1 PCH_JTAG_TDI K5 Y10 SATA_COMP R2112 1 2 37D4R2F-GP 3
JTAG_TDI SATAICOMPI
TP2104 1 PCH_JTAG_TDO H1
JTAG_TDO 1D05V_VTT
AB12
SATA3RCOMPO
AB13 SATA3_COMP R2113 1 2 49D9R2F-GP
SATA3COMPI
1 2 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 R2114 1 2 750R2F-GP

27,60 SPI_CLK_R SPI_CLK SATA3RBIAS
R2108 33R2J-2-GP
27,60 SPI_CS0#_R 1 2 PCH_SPI_CS0# Y14
SPI_CS0#
R2109 0R2J-2-GP OD
60 SPI_CS1#_R 1 2 PCH_SPI_CS1# T1
SPI_CS1#
SPI
R2117 SBA 0R2J-2-GP P3 SATA_LED#
SATALED# SATA_LED# 68
1 2 PCH_SPI_SI V4 V14 SATA_DET#0
27,60 SPI_SI_R SPI_MOSI SATA0GP/GPIO21
R2110 33R2J-2-GP
+3VS_+1.5VS_HDA_IO U3 P1
27,60 SPI_SO_R SPI_MISO SATA1GP/GPIO19 BBS_BIT0 18
R2103 1 2 1KR2J-1-GP HDA_SYNC
PANTHER-GP-NF
This signal has a weak internal pull down.
On Die PLL VR is supplied by 1.5V when
sampled high, 1.8 V when sampled low.
Needs to be pulled High for Huron River platform. CHECK CHECK 4.7K PD
co-operate with R2310
PCH_JTAG_TCK_BUF 1 2
R2134 51R2J-2-GP
PLL ODVR VOLTAGE

Low = 1.8V (Default) CHECK
HDA_SYNC High = 1.5V
3D3V_S0
RN2103
This signal has a weak internal pull-down. SATA_LED# 1 8
SATA_DET#0 2 7
On Die PLL VR is supplied by 1.5 V from VccVRM when 3 6
sampled high, 1.8 V from VccVRM when sampled low. 22 S_GPIO
PCH_SPI_CLK HDA_CODEC_BITCLK HDA_CODEC_SDOUT SPI_CS0#_R 4 5
2 2
2E EC2102
C2102 EC2103
C2103 EC2101
C2101 SRN10KJ-6-GP
2E
2E
SCD1U16V2KX-3GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
1
EC2104
DY DY DY
1
1
DY
2
R2125
HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to INT_SERIRQ 1 2 8K2R2J-3-GP 10K?
sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this
signal on the board. Signal may have leakage paths via powered off devices (Audio
Codec) and hence contend with the external pull-up. A blocking FET is
recommended in such a case to isolate HDA_SYNC from the Audio Codec device
until after the Strap sampling is complete.
84.2N702.J31
2ND = 84.2N702.031
Q2101
HDA_CODEC_SYNC 2 1 HDA_CODEC_SYNC_L S
R2124
1
33R2J-2-GP D HDA_SYNC
R2127
1MR2F-GP G
2N7002K-2-GP Vth?
2
5V_S0
1 1
<Core Design>
Wistron Corporation
Title
PCH : HDA/JTAG/SATA
A2 SD
LA480
A B C D E
A B C D E
R2202
HR:200K (64.20035.6DL) 1D8V_S0
3D3V_S0 CRV:10K (63.10334.1DL) Note:
4 For PCH debug with XDP, need to NO STUFF R2218 4
1
1 2 SATA_ODD_PRSNT#
R2202 10KR2J-3-GP PCH1F 6 OF 10 R1808
2K2R2J-2-GP
1 2 GPIO0 T7 C40
21 S_GPIO BMBUSY#/GPIO0 TACH4/GPIO68 SATA_ODD_PWRGT 56
R2218 100R2J-2-GP
2
3D3V_S0 EC_SMI# A42 B41 NV_CLE 1 2
TACH1/GPIO1 TACH5/GPIO69 SBA_Support# 20 H_SNB_IVB# 5
RN2203 R1809 1KR2J-1-GP
2 3 H_A20GATE DGPU_HPD_INTR# H36 C41 VRAM_SIZE1
H_RCIN# TACH2/GPIO6 TACH6/GPIO70
1 4
EC_SCI# E38 A40 VRAM_SIZE2 DMI & FDI Termination Voltage
27 EC_SCI# TACH3/GPIO7 TACH7/GPIO71
SRN10KJ-5-GP
ICC_EN# C10 Set to Vss when LOW
GPIO27 has a weak[20K] internal pull up. GPIO8
NV_CLE Set to Vcc when HIGH
To enable on-die PLL Voltage regurator, 60 RTC_DET# C4
LAN_PHY_PWR_CTRL/GPIO12
should not place external pull down. PCH_GPIO15 G2 P4 H_A20GATE 27
GPIO15 A20GATE
AU16 H_PECI_R 1 DY 0R2J-2-GP
2
PECI H_PECI 5,27
SATA_ODD_PRSNT# 1 2PCH_GPIO16 U2 R2203
56 SATA_ODD_PRSNT# SATA4GP/GPIO16
R2215 0R2J-2-GP P5
RCIN# H_RCIN# 27
GPIO
1 2 DGPU_PWROK_C D40 AY11 PROCPWRGD (PCH) --> UNCOREPOWRGOOD (CPU)
92,93 DGPU_PWROK TACH0/GPIO17 PROCPWRGD H_CPUPWRGD 5,97
CPU/MISC
R2216 0R2J-2-GP Indicates that VccSA, VDDQ, VccA (1.8V) and VccIO power
G-Sensor ST KIXNOK PCH_GPIO22 T5 AY10 PCH_THERMTRIP_R 1 2 supplies are stable. This signal will be asserted only after
SCLOCK/GPIO22 THRMTRIP# H_THERMTRIP# 5,36 PWROK assertion.
DY R2204
Gsensor_ID E8 T14 INIT3_3V# 1 390R2J-1-GP
R2226 DY 10K GPIO24 INIT3_3V# TP2201
A K
PCH_GPIO27 E16 AY1 NV_CLE
R2221 10K DY D2201 GPIO27 DF_TVS
CH751H-40-1-GP PLL_ODVR_EN P8
GPIO28
AH8
3D3V_S0 PSW_CLR# TS_VSS1
K1
3D3V_S5 G2201 STP_PCI#/GPIO34
TS_VSS2
AK11 TS Signal Disable Guideline:
FP_DET# K4 TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4
2
GPIO35
GAP-OPEN
AH10 should not float on the motherboard. They
2
DMI_OVRVLTG TS_VSS3
V8
PCH_GPIO48 R2221 SATA2GP/GPIO36 TS_VSS 1 should be tied to GND directly.
1 2 AK10 2
R2220 10KR2J-3-GP FDI_OVRVLTG TS_VSS4 R2219
10KR2J-3-GP M5
FP_DET# SATA3GP/GPIO37 0R0402-PAD
1 DY 2
1
R2224 10KR2J-3-GP MFG_MODE N2 P37
1
PCH_TEMP_ALERT# 1 SLOAD/GPIO38 NC_1

3 2 3
R2222 10KR2J-3-GP Gsensor_ID GFX_CRB_DET M3
RN2201 SDATAOUT0/GPIO39 3D3V_S0
2
EC_SMI# 1 8 PCH_GPIO48 V13 BG2

EC_SCI# R2226 SDATAOUT1/GPIO48 VSS_NCTF_15#BG2
2 7
1
DGPU_HPD_INTR# 3 6 10KR2J-3-GP PCH_TEMP_ALERT# V3 BG48 FDI TERMINATION VOLTAGE OVERRIDE
PCH_GPIO22 SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16#BG48 R2207
4 5 DY
USB3_PWR_ON D6 BH3 DY 10KR2J-3-GP
1
SRN10KJ-6-GP GPIO57 VSS_NCTF_17#BH3

GPIO37 LOW - Tx, Rx terminated to same voltage
R2225 BH47 (FDI_OVRVLTG) (DC Coupling Model DEFAULT)
2
PSW_CLR# VSS_NCTF_18#BH47 FDI_OVRVLTG
1 2 10KR2J-3-GP
MFG_MODE 1 2 TP2206 1 PCH_NCTF_1 A4 BJ4
1
R2228 10KR2J-3-GP VSS_NCTF_1#A4 VSS_NCTF_19#BJ4
NCTF
A44 BJ44 R2208
PCH_GPIO27 VSS_NCTF_2#A44 VSS_NCTF_20#BJ44 10KR2J-3-GP
1 2
R2229 10KR2J-3-GP TP2212 1 PCH_NCTF_7 A45 BJ45 PCH_NCTF_9 1 TP2214
3D3V_S5 FP_DET# VSS_NCTF_3#A45 VSS_NCTF_21#BJ45
2
A46 BJ46 PCH_NCTF_10 1 TP2215
VSS_NCTF_4#A46 VSS_NCTF_22#BJ46
1
RN2204 SRN10KJ-5-GP A5 BJ5 PCH_NCTF_5 1 TP2210

R2223 VSS_NCTF_5#A5 VSS_NCTF_23#BJ5
RTC_DET# 4 1 10KR2J-3-GP
USB3_PWR_ON 3 2 A6 BJ6
VSS_NCTF_6#A6 VSS_NCTF_24#BJ6
A4,A44,A45,A46,A5,A6,B3,B47,
BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
3D3V_S0
BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
2
B3 C2
PCH_GPIO15 VSS_NCTF_7#B3 VSS_NCTF_25#C2
1 2
1
R2201 1KR2J-1-GP B47 C48 DMI TERMINATION VOLTAGE OVERRIDE
VSS_NCTF_8#B47 VSS_NCTF_26#C48 R2209
D49,E1,E49,F1,F49
PLL_ODVR_EN
BD1
VSS_NCTF_9#BD1 VSS_NCTF_27#D1
D1 DY 10KR2J-3-GP
1 2 GPIO36 LOW - Tx, Rx terminated to same voltage
NCTF TEST PIN:

R2234 DY 10KR2J-3-GP BD49 D49 PCH_NCTF_8 1 TP2213 (DMI_OVRVLTG) (DC Coupling Model DEFAULT)
2
VSS_NCTF_10#BD49 VSS_NCTF_28#D49 DMI_OVRVLTG
TP2207 1 PCH_NCTF_2 BE1 E1 PCH_NCTF_6 1 TP2211
1
VSS_NCTF_11#BE1 VSS_NCTF_29#E1
TP2208 1 PCH_NCTF_3 BE49 E49 R2210
VSS_NCTF_12#BE49 VSS_NCTF_30#E49 10KR2J-3-GP
BF1 F1
VSS_NCTF_13#BF1 VSS_NCTF_31#F1
2
TP2209 1 PCH_NCTF_4 BF49 F49
VSS_NCTF_14#BF49 VSS_NCTF_32#F49
INTERNAL GFX EXTERNAL GFX PANTHER-GP-NF

2 2
R2205 DY 10K
3D3V_S0 Integrated Clock Enable functionality is achieved
R2206 100K DY
via soft-strap. The default is integrated clock
enable.
1
3D3V_S0 R2230 R2232

10KR2J-3-GP 10KR2J-3-GP DY Integrated Clock Chip Enable
DY DY
1
ICC_EN# 1 2 HIGH (R2211 DY)- DISABLED [DEFAULT]

2
R2205 VRAM_SIZE1 R2211 ICC_EN#

DY 10KR2J-3-GP VRAM_SIZE2 1KR2J-1-GP LOW (R2211)- ENABLED
PLL ON DIE VR ENABLE
R2211 BOM CTRL
2
GFX_CRB_DET GPIO8 has a weak[20K] internal pull up.

NOTE:This signal has a weak internal pull-up 20K
HR:1K Integrated Clock Enable functionality is achieved
1
ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT

CRV:DY via soft-strap. The default is integrated clock
R2206 DISABLED -- LOW (R2212 STUFFED)
100KR2J-1-GP
enable.
2
PLL_ODVR_EN 1
R2212
DY 2
1KR2J-1-GP
1 1
<Core Design>
Wistron Corporation
Title
PCH : GPIO/NTCF/MISC
A2 SD
LA480
A B C D E
5 4 3 2 1
SSID = PCH http://laptopblue.vn

3D3V_DAC_S0
6A 1
DY
2
+VCCA_DAC_3V
R2301 0R2J-2-GP
D
1D05V_VTT
PCH1G POWER 7 OF 10
3D3V_S0
D
0.001A L2301
1.3A(Total current of VCCCORE)
AA23 VCCCORE1 VCCADAC U48 +VCCA_DAC_1_2 1 2 1 2
C2311 C2312 C2302 C2304 C2303 AC23 C2313 C2314 C2315 C2333 BLM18PG181SN1D-GP R2302 0R2J-2-GP
VCCCORE2
1
AD21 C2326
CRT
VCCCORE3
1
1
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD01U50V2KX-1GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
AD23 VCCCORE4 VSSADAC U47
AF21
2
VCC CORE
VCCCORE5
AF23
2
2
VCCCORE6
AG21 VCCCORE7 0.001A
AG23 VCCCORE8
AG24 VCCCORE9 VCCALVDS AK36
AG26 VCCCORE10
AG27 AK37 3D3V_S0
VCCCORE11 VSSALVDS
AG29 VCCCORE12
AJ23 +3VS_VCCA_LVDS 1 2
VCCCORE13
LVDS
AJ26 AM37 R2304
VCCCORE14 VCCTX_LVDS1 0R0603-PAD
AJ27 VCCCORE15
(0.01uF x2) 1D8V_S0
AJ29 VCCCORE16 VCCTX_LVDS2 AM38 0.06A
AJ31 VCCCORE17
(22uF x1)
AP36 +1.8VS_VCCTX_LVDS 1 2
1D05V_VTT VCCTX_LVDS3 R2305 C2330 C2329
AP37 C2316 C2317 0R0603-PAD
VCCTX_LVDS4
1
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
AN19 SCD01U50V2KX-1GP SCD01U50V2KX-1GP
VCCIO28
2
TP2301 1 VCCAPLLEXP BJ22
1D05V_VTT VCCAPLLEXP
(10uF x1)
2.925A(Total current of VCCIO) VCC3_3_6 V33
HVCMOS
C AN16 C
C2327 C2328 C2306 C2307 C2308 C2309 VCCIO15 3D3V_S0
AN17 VCCIO16 0.266A (0.1uFx1)
1
1
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
VCC3_3_7 V34
C2319 Reserve 0ohm for power measurement?
1
AN21 SCD1U10V2KX-5GP
2
VCCIO17
+VCCAFDI_VRM 1D5V_S0
AN26 0.16A
2
VCCIO18 R2308
AN27 VCCIO19 VCCVRM3 AT16 1 2
0R0402-PAD
1D05V_VTT
AP21 VCCIO20 0.042A 3.3V CRT LDO
AP23 AT20 +1.05VS_VCC_DMI R2306 1 2 0R0402-PAD
VCCIO21 VCCDMI1 5V_S0 3D3V_DAC_S0
1
DMI
AP24 U2302 DY
VCCIO22
VCCIO
C2320 (1uF x1)

AP26 AB36 SC1U6D3V2KX-GP 1 5
2
VCCIO23 VCCCLKDMI IN OUT
2 GND
1D05V_VTT
AT24 VCCIO24 0.02A R2307
3 EN NC#4 4
1
+1.05VS_VCC_DMI_CCI 1 2 DY DY
0.266A (Totally VCC3_3 current) AN33 0R0402-PAD C2325 AME8818BEEV330Z-GP C2324
VCCIO25
1
74.08818.B3F
SC1U10V2KX-1GP
SC1U6D3V2KX-GP
2
2
3D3V_S0 AN34 AG16 C2321 (1uFx1)
VCCIO26 VCCDFTERM1 SC1U6D3V2KX-GP (10uFx1)
2
(0.1uF x1) BH29 VCC3_3_3 VCCDFTERM2 AG17
1
C2310 1D8V_S0
DFT / SPI
B SCD1U10V2KX-5GP B
0.19A
0.159A(Totally current of VCCVRM) AJ16
2
VCCDFTERM3 Reserve 0ohm for power measurement?

+VCCAFDI_VRM AP16 VCCVRM2 1 C2322 (0.1uFx1)
AJ17 SCD1U10V2KX-5GP
VCCDFTERM4 74.09091.J3F GMT OBS REASON:G9091
2
TP2302 1 VCCFDIPLL BG6 series is going to EOL and no room for further cost reduction.
VCCAFDIPLL Pls help to use AME AME8818 , TI TLV702 and GMT G9090 for replacement.
3D3V_S5
1D05V_VTT AP17 0.02A R2309
VCCIO27 VCCSPI_3D3V 74.09198.G7F OBS
V1 1 2
FDI
VCCSPI 0R0402-PAD
1
+1.05VS_VCC_DMI AU20 VCCDMI2 C2323

0.042A (Totally current of VCCDMI)
SC1U6D3V2KX-GP
2
PANTHER-GP-NF (1uFx1)
VCCVRM(Internal PLL and VRMs):

A.1.5V for Mobile
B.1.8 V for Desktop
A Refer to NPCE795 shared SPI flash architecture <Core Design> A
Wistron Corporation
Title
PCH : POWER1
A3 SD
LA480
5 4 3 2 1
A B C D E
SSID = PCH http://laptopblue.vn

POWER
TP2401 1 VCCACLK AD49
PCH1J
VCCACLK
10 OF 10
VCCIO29 N26
1D05V_VTT
3D3V_S5 (1uFx1)
1
0.002A P26 C2423
+VCCPDSW VCCIO30 SCD1U10V2KX-5GP
(0.1uFx1) 1 2 T16 VCCDSW3_3
R2403 P28
2
0R0603-PAD VCCIO31
(10uFx1)
(1uFx1) TP2405 1 DCPSUSBYP V12 T27
3D3V_S0 DCPSUSBYP VCCIO32 3D3V_S5 5V_S5
L2401 T29
+V3.3S_VCC_CLKF33 +V3.3S_VCC_CLKF33 VCCIO33 3D3V_S5 D2401
4 1 2 T38 VCC3_3_5 4
2
IND-10UH-218-GP 1 0.097A (Totally current of VCCSUS3_3) CH751H-40PT-GP
1
68.10050.10Y C2401 C2402 T23 83.R0304.A8F
SC10U6D3V5KX-1GP SC1U10V2KX-1GP TP2404 +VCCAPLL_CPY_PCH BH23 VCCSUS3_3_7
2nd = 68.1001E.10N 1 VCCAPLLDMI2
(0.1uFx1) 2nd = 83.R2004.B8F
1
T24 C2424
2
2
VCCSUS3_3_8 SCD1U10V2KX-5GP
(10uFx1) 1D05V_VTT AL29
1
VCCIO14 R2408 1
V23 2
2
VCCSUS3_3_9
USB
10R2J-2-GP
1
TP2402 1 +VCCSUS1 AL24 V24 3D3V_S5 (0.1uFx1)
DCPSUS3 VCCSUS3_3_10 C2426
P24 SCD1U10V2KX-5GP
2
VCCSUS3_3_6
(0.1uFx1)
1
1D05V_M AA19 C2425
VCCASW1 SCD1U10V2KX-5GP
1.01A (Total current of VCCASW) VCCIO34 T26 1D05V_VTT
AA21
2
C2403 C2436 C2437 C2406 C2407 C2408 VCCASW2
AA24 M26 +5VA_PCH_VCC5REFSUS 0.001A
VCCASW3 V5REF_SUS
1
SC10U6D3V3MX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
AA26 3D3V_S0 5V_S0
Clock and Miscellaneous

VCCASW4 +VCCA_USBSUS TP2403
AN23 1
2
DCPSUS4 D2402
AA27 VCCASW5
2
AN24 3D3V_S5 CH751H-40PT-GP
VCCSUS3_3_1
AA29 VCCASW6 83.R0304.A8F
2nd = 83.R2004.B8F
AA31 VCCASW7
0.001A
1
AC26 P34 +5VS_PCH_VCC5REF R2407 1 2
VCCASW8 V5REF 10R2J-2-GP (1uFx1)
1
AC27 VCCASW9
3 N20 3D3V_S5 C2427 3
1D05V_VTT VCCSUS3_3_2 SC1U10V2KX-1GP
PCI/GPIO/LPC
AC29
2
L2402 VCCASW10
+1.05VS_VCCA_A_DPL
0.08A VCCSUS3_3_3 N22
1 2 AC31 VCCASW11
(1uFx1)
1
IND-10UH-218-GP P20
VCCSUS3_3_4
1
68.10050.10Y C2443 C2409 AD29 C2428

SC10U6D3V3MX-GP SC1U6D3V2KX-GP VCCASW12 SC1U6D3V2KX-GP
2nd = 68.1001E.10N DY P22
2
VCCSUS3_3_5
AD31
2
VCCASW13
(1uFx1)
(220uFx1) W21 AA16 3D3V_S0
VCCASW14 VCC3_3_1
W23 VCCASW15 VCC3_3_8 W16
L2403 0.08A (0.1uFx2)
1
1 2 +1.05VS_VCCA_B_DPL W24 T34
IND-10UH-218-GP VCCASW16 VCC3_3_4 C2430 C2431
1
68.10050.10Y C2444 C2410 W26 SCD1U10V2KX-5GP SCD1U10V2KX-5GP
2
SC10U6D3V3MX-GP SC1U6D3V2KX-GP VCCASW17
2nd = 68.1001E.10N DY
W29 3D3V_S0
2
VCCASW18
(1uFx1)
(220uFx1) W31 VCCASW19 VCC3_3_2 AJ2
(0.1uFx1)
1
W33 VCCASW20
AF13 C2429
VCCIO5 SCD1U10V2KX-5GP
2
+VCCRTCEXT N16 DCPRTC 1D05V_VTT
0.16A (Totally current of VCCVRM VCCIO12 AH13
1
C2411 +VCCAFDI_VRM Y49 AH14

SCD1U10V2KX-5GP VCCVRM4 VCCIO13
(1uFx1)
2
1
2 2
(0.1uFx1)
AF14 C2432
+1.05VS_VCCA_A_DPL VCCIO6 SC1U6D3V2KX-GP
BD47
2
VCCADPLLA
SATA
VCCAPLLSATA AK1
+1.05VS_VCCA_B_DPL BF47
1D05V_VTT VCCADPLLB +V1.05S_VCCAPLL_SATA3 TP2407
1
R2404 AF11 +VCCAFDI_VRM
+VCCDIFFCLK 1D05V_VTT +VCCDIFFCLKN +VCCDIFFCLK VCCVRM1
2 1 AF17 VCCIO7
0R0402-PAD (1uFx1) AF33 VCCDIFFCLKN1
1
1 2 0.055A AF34 VCCDIFFCLKN2 VCCIO2 AC16

C2412 (1uFx1) R2406 AG34 VCCDIFFCLKN3
1
SC1U6D3V2KX-GP 0R0603-PAD AC17 1D05V_VTT

2
C2414 VCCIO3
0.095A
SC1U6D3V2KX-GP +V1.05S_SSCVCC AG33 AD17
2
VCCSSC VCCIO4
(1uFx1) (1uFx1)
1
C2435
1D05V_VTT (0.1uFx1) 2 1 +VCCSST V16 SCD1U10V2KX-5GP
R2405 C2415 DCPSST 1D05V_M
2
2 1 +V1.05S_SSCVCC SCD1U10V2KX-5GP
0R0402-PAD T17 T21
DCPSUS1 VCCASW22
1
(1uFx1) TP2406 1 DCPSUS V19 DCPSUS2

C2413 +3VS_+1.5VS_HDA_IO 3D3V_S5
MISC
SC1U6D3V2KX-GP 1D05V_VTT V21

2
R2413 VCCASW23
1 2
CPU
2 1 C2417 V_PROC_IO_R 0.001A BJ8 R2409

0R0402-PAD V_PROC_IO 0R0603-PAD
VCCASW21 T19
1
1
SC1U6D3V2KX-GP
(0.1uFx2) C2418 C2419

(4.7uFx1_0603) SCD1U10V2KX-5GP SCD1U10V2KX-5GP +3VS_+1.5VS_HDA_IO
1 <Core Design> 1
2
HDA
A22 P32 0.01A (0.1uFx1)

RTC
VCCRTC VCCSUSHDA
1
C2433
RTC_AUX_S5 PANTHER-GP-NF SCD1U10V2KX-5GP Wistron Corporation
2
6uA Taipei Hsien 221, Taiwan, R.O.C.
(0.1uFx2)
1
(1uFx1) C2416 C2421 C2422 Title

SC1U6D3V2KX-GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
PCH : POWER2
2

A3 SD
LA480
A B C D E
A B C D E
SSID = PCH http://laptopblue.vn AY4

PCH1I
VSS159
9 OF 10
VSS259 H46
AY42 VSS160 VSS260 K18
B11 VSS163 VSS263 K46
B15 VSS164 VSS264 K7
B19 VSS165 VSS265 L18
B23 VSS166 VSS266 L2
B27 VSS167 VSS267 L20
4 B31 VSS168 VSS268 L26 4
PCH1H 8 OF 10 B35 L28
VSS169 VSS269
H5 VSS0 B39 VSS170 VSS270 L36
B7 VSS171 VSS271 L48
AA17 VSS1 VSS80 AK38 F45 VSS172 VSS272 M12
AA2 VSS2 VSS81 AK4 BB12 VSS173 VSS273 P16
AA3 VSS3 VSS82 AK42 BB16 VSS174 VSS274 M18
AB11 VSS6 VSS85 AL16 BB24 VSS177 VSS277 M30
AB7 VSS12 VSS91 AL26 BC14 VSS183 VSS283 M46
AC19 VSS13 VSS92 AL27 BC18 VSS184 VSS284 M8
AC2 VSS14 VSS93 AL31 BC2 VSS185 VSS285 N18
AC21 VSS15 VSS94 AL33 BC22 VSS186 VSS286 P30
AC24 VSS16 VSS95 AL34 BC26 VSS187 VSS287 N47
AC33 VSS17 VSS96 AL48 BC32 VSS188 VSS288 P11
AC34 VSS18 VSS97 AM11 BC34 VSS189 VSS289 P18
AC48 VSS19 VSS98 AM14 BC36 VSS190 VSS290 T33
AD10 VSS20 VSS99 AM36 BC40 VSS191 VSS291 P40
AD13 VSS23 VSS102 AM45 BD46 VSS194 VSS294 P7
AD19 VSS24 VSS103 AM46 BD5 VSS195 VSS295 R2
AD24 VSS25 VSS104 AM7 BE22 VSS196 VSS296 R48
3 AD26 AN2 BE26 T12 3
VSS26 VSS105 VSS197 VSS297
AD27 VSS27 VSS106 AN29 BE40 VSS198 VSS298 T31
AD33 VSS28 VSS107 AN3 BF10 VSS199 VSS299 T37
AD34 VSS29 VSS108 AN31 BF12 VSS200 VSS300 T4
AD36 VSS30 VSS109 AP12 BF16 VSS201 VSS301 W34
AD37 VSS31 VSS110 AP19 BF20 VSS202 VSS302 T46
AD4 VSS34 VSS113 AP32 BF26 VSS205 VSS305 V11
AD42 VSS36 VSS115 AP4 BD3 VSS207 VSS307 V26
AD8 VSS40 VSS119 AR2 BF8 VSS211 VSS311 V36
AE2 VSS41 VSS120 AR48 BG17 VSS212 VSS312 V39
AE3 VSS42 VSS121 AT11 BG21 VSS213 VSS313 V43
AF10 VSS43 VSS122 AT13 BG33 VSS214 VSS314 V7
AF12 VSS44 VSS123 AT18 BG44 VSS215 VSS315 W17
AD14 VSS45 VSS124 AT22 BG8 VSS216 VSS316 W19
AD16 VSS46 VSS125 AT26 BH11 VSS217 VSS317 W2
AF16 VSS47 VSS126 AT28 BH15 VSS218 VSS318 W27
AF19 VSS48 VSS127 AT30 BH17 VSS219 VSS319 W48
AF24 VSS49 VSS128 AT32 BH19 VSS220 VSS320 Y12
AF26 VSS50 VSS129 AT34 H10 VSS221 VSS321 Y38
2 2
AF4 VSS55 VSS134 AU24 BH39 VSS226 VSS328 BG29
AF42 VSS56 VSS135 AU30 BH43 VSS227 VSS329 N24
AF46 VSS57 VSS136 AV16 BH7 VSS228 VSS330 AJ3
AF5 VSS58 VSS137 AV20 D3 VSS229 VSS331 AD47
AF7 VSS59 VSS138 AV24 D12 VSS230 VSS333 B43
AF8 VSS60 VSS139 AV30 D16 VSS231 VSS334 BE10
AG19 VSS61 VSS140 AV38 D18 VSS232 VSS335 BG41
AG2 VSS62 VSS141 AV4 D22 VSS233 VSS337 G14
AG31 VSS63 VSS142 AV43 D24 VSS234 VSS338 H16
AG48 VSS64 VSS143 AV8 D26 VSS235 VSS340 T36
AH11 VSS65 VSS144 AW14 D30 VSS236 VSS342 BG22
AH3 VSS66 VSS145 AW18 D32 VSS237 VSS343 BG24
AH36 VSS67 VSS146 AW2 D34 VSS238 VSS344 C22
AH39 VSS68 VSS147 AW22 D38 VSS239 VSS345 AP13
AH40 VSS69 VSS148 AW26 D42 VSS240 VSS346 M14
AH42 VSS70 VSS149 AW28 D8 VSS241 VSS347 AP3
AH46 VSS71 VSS150 AW32 E18 VSS242 VSS348 AP1
AH7 VSS72 VSS151 AW34 E26 VSS243 VSS349 BE16
AJ19 VSS73 VSS152 AW36 G18 VSS244 VSS350 BC16
AJ21 VSS74 VSS153 AW40 G20 VSS245 VSS351 BG28
AJ24 VSS75 VSS154 AW48 G26 VSS246 VSS352 BJ28
AJ33 VSS76 VSS155 AV11 G28 VSS247
AJ34 VSS77 VSS156 AY12 G36 VSS248
AK12 VSS78 VSS157 AY22 G48 VSS249
AK3 VSS79 VSS158 AY28 H12 VSS250
H18 VSS251
PANTHER-GP-NF H22 VSS252
H24 VSS253
1 H26 VSS254 <Core Design> 1
H30 VSS255
H32 VSS256
H34
F3
VSS257
VSS258
Wistron Corporation
PANTHER-GP-NF Title
PCH : VSS
A3 SD
LA480
A B C D E
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Title
Reserved
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
3D3V_AUX_KBC 3D3V_AUX_S5
1 2
R2725
0R0805-PAD
SSID = KBC
3D3V_AUX_KBC 3D3V_S0_KBC 3D3V_S0
1 2 VBAT 1 2
R2702 C2703 R2709
D D
1
0R0603-PAD C2702 SC2D2U10V3KX-1GP 0R0805-PAD
SCD1U10V2KX-5GP DY DY
RC2702 C2701 C2704 C2705 C2706 C2707 C2708 C2709 C2710 RC2701
Code change to Low Active on 8/19
2
SC33P50V2JN-3GP 3D3V_AUX_S5
1
SC33P50V2JN-3GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
R2712
1
3D3V_AUX_KBC AC_IN_KBC
DY DY R2775
1
0R0402-PAD
2 AC_IN# 40
1
1 2 100KR2J-1-GP
3D3V_AUX_KBC R2706
R2743 0R0402-PAD
100KR2J-1-GP
1
1 2 RTC_AUX_S5
2
65W: 1.7V R2707 R2739 0R0402-PAD DY
10KR2F-2-GP HDD_DET#
2
115
102
114
90W: 3.3V
19
46
76
88
75
4
U2701A 1 OF 2 U2701B 2 OF 2
DY
2
KCOL[0..15] 69
1 2
VCC1
VCC2
VCC3
VCC4
VCC5
AVCC
VDD
VSBY
VBKUP
C2711 LPC_AD[0..3] 21,65,71 56 HDD_DET# 31 53 KCOL0
ADT_TYPE SC220P50V2KX-3GP GPIO56/TA1 KBSOUT0/GPOB0/JENK# KCOL1
38 ADT_TYPE 82 USB_AO_SEL0 63 52
C2713 GPIO14/TB1 KBSOUT1/GPIOB1/TCK KCOL2
19,36,37,47 PM_SLP_S3# 64 51
GPIO1/TB2 KBSOUT2/GPIOB2/TMS
1
40 AD_IA 104 7 PLT_RST#_EC 1 2 PLT_RST# 5,18,31,36,65,66,71,80,82,83,97 50 KCOL3

VREF LRESET#/GPIOF7 KBSOUT3/GPIOB3/TDI
1
SCD1U10V2KX-5GP
R2701 2 R2735 0R0402-PAD CLK_PCI_KBC 18 68 DC_BATFULL 32 49 KCOL4

100KR2F-L1-GP LCLK/GPIOF5 LPC_FRAME#_R R2730 1 GPIO15/A_PWM KBSOUT4/GPOB4/JEN0#
1 DY 2 97 3 2 33R2J-2-GP LPC_FRAME# 21,65,71 29 KBC_BEEP 118 48 KCOL5
GPIO90/AD0 LFRAME#/GPIOF6 GPIO21/B_PWM KBSOUT5/GPIOB5/TDO
DY C2714 PCB_VER_AD 98 1 LPC_AD3_R R2740 1 2 0R0402-PAD LPC_AD3 68 PWRLED 62 47 KCOL6
2
GPIO91/AD1 LAD3/GPIOF4 GPIO13/C_PWM KBSOUT6/GPIOB6/RDY#

SCD1U10V2KX-5GP ADT_TYPE 99 128 LPC_AD2_R R2741 1 2 0R0402-PAD LPC_AD2 40 STOP_CHG# 65 43 KCOL7
2
GPIO92/AD2 LAD2/GPIOF3 GPIO32/D_PWM KBSOUT7/GPIOB7

MODEL_ID_AD 100 127 LPC_AD1_R R2742 1 2 0R0402-PAD LPC_AD1 38 AD_DETECT 22 42 KCOL8
GPIO93/AD3 LAD1/GPIOF2 LPC_AD0_R LPC_AD0 GPIO45/E_PWM KBSOUT8/GPIOC0 KCOL9
42 VGA_CURRENT 108 126 1 2 68 NUM_LED 81 41
GPIO5/AD4 LAD0/GPIOF1 R2729 33R2J-2-GP GPIO66/G_PWM KBSOUT9/GPOC1/SDP_VIS# KCOL10
42 CPU_CURRENT 96 125 INT_SERIRQ 21 68 KBC_NOVO_BTN# 66 40
GPIO4/AD5 SERIRQ/GPIOF0 GPIO33/H_PWM KBSOUT10_P80_CLK/GPIOC2 KCOL11
79 GSENSE_X 95 8 PM_CLKRUN# 19 68 CHARGE_LED 16 39
GPIO3/AD6 GPIO11/CLKRUN# GPIO40/F_PWM KBSOUT11_P80_DAT/GPIOC3 KCOL12
79 GSENSE_Y 94 9 PANEL_BLEN 49 38
GPIO7/AD7 GPIO65/SMI# ECSCI#_KBC KBSOUT12/GPIO64 KCOL13
29 37
ECSCI#/GPIO54 SATA_ODD_DA#_R KBSOUT13/GPIO63 KCOL14
49 CAMERA_EN 101 124 1 2 SATA_ODD_DA# 18,56 21 ME_UNLOCK 23 36
GPIO94/DA0 GPIO10/LPCPD# R2738 0R2J-2-GP GPIO46/CIRRXM/TRIST# KBSOUT14/GPIO62 KCOL15
66 -MSATA_DET 105 121 H_A20GATE 22 65 E51_RxD 113 35
3D3V_AUX_S5 TP2704 3G_EN GPIO95/DA1 GPIO85/GA20 GPIO87/CIRRXM/SIN_CR KBSOUT15/GPIO61/XOR_OUT KCOL16 TP2707
1 106 122 H_RCIN# 22 65 E51_TxD 111 34 1
GPIO96/DA2 KBRST#/GPIO86 GP/I/O83/SOUT_CR/TRIST# GPIO60/KBSOUT16 KCOL17 TP2708 3D3V_AUX_KBC
68 CAP_LED 107 33 1
GPIO97/DA3 GPIO57/KBSOUT17
1
KROW[0..7] 69
R2776 19 PCH_SUSCLK_KBC 77 54 KROW0
GPIO0/EXTCLK KBSIN0/GPIOA0/N2TCK
1
100KR2J-1-GP 79 27 30 55 KROW1
65 AOAC_EN GPIO2 GPIO52/PSDAT3/RDY# BLON_OUT 49 29 AMP_MUTE# GPIO55/CLKOUT/IOX_DIN_DIO KBSIN1/GPIOA1/N2TMS
38 AD_OFF 6 25 PM_SLP_A# 19,45 56 KROW2 R2717
GPIO24 GPIO50/PSCLK3/TDO ECRST# KBSIN2/GPIOA2 KROW3 10KR2J-3-GP
82 USB_CHG_EN 109 11 GSENSE_ON# 79 41 ECRST# 85 57
2
GPIO30/F_WP# GPIO27/PSDAT2 VCC_POR# KBSIN3/GPIOA3 KROW4

36,97 S5_ENABLE 14
GPIO34/CIRRXL GPIO26/PSCLK2
10 CHG_USB_OC# 82 KBSIN4/GPIOA4
58 DY
-MSATA_DET 82 ADP_LED 15 71 TPDATA 69 59 KROW5
2
GPIO36 GPIO35/PSDAT1 R2721 KBSIN5/GPIOA5
39 BAT_IN# 80 72 TPCLK 69 <------ TP 5,22 H_PECI 1 2 43R2J-GP PECI 13 60 KROW6 PM_SLP_A#
GPIO41/F_WP# GPIO37/PSCLK1 R2720 PECI KBSIN6/GPIOA6
49,70 LID_CLOSE# 17 1D05V_VTT 1 2 0R2J-2-GP EC_VTT 12 61 KROW7
GPIO42/TCK VTT KBSIN7/GPIOA7
19 RSMRST#_KBC 20
GPIO43/TMS
1
C2716
19,46,97 PM_SLP_S4#
TP2703 1 NC_KBC_GPIO51
21
26
GPIO44/TDI GPIO17/SCL1/N2TCK
70
69
BAT_SCL 39,40 <------ BATTERY / CHARGER NPCE885GA0DX-GP
GPIO51/N2TCK GPIO22/SDA1/N2TMS BAT_SDA 39,40 3D3V_AUX_KBC
SCD1U16V2KX-3GP
65 PCIE_WLAN_WAKE# 123 67 <------PCH / eDP
2
GPIO67N2TMS GPIO73/SCL2 SML1_CLK 20
65 WIFI_RF_EN 82
GPIO75 GPIO74/SDA2
68 SML1_DATA 20 R2720 and C2716
63,65 BLUETOOTH_EN 83 119 LAN_PWR_ON 31 Need very close to EC
GPIO76 GPIO23/SCL3
1
19 S0_PWR_GOOD SBA 84
GPIO77 GPIO31/SDA3
120 RTCRST_ON 21
33R2J-2-GP 2 1 R2744 24 PROCHOT_EC R2714
21,60 SPI_CS1#_R GPIO47/SCL4 10KR2J-3-GP
Non-SBA GPIO53/SDA4
28 CHG_ON# 40
33R2J-2-GP 2 1 R2736 EC_SPI_CS#_C 90
21,60 SPI_CS0#_R F_CS0#
33R2J-2-GP 2 1 R2719 EC_SPI_CLK_C 92
2
21,60 SPI_CLK_R F_SCK
0R2J-2-GP 2 1 R2737 EC_SPI_DI_C 86 74 NC_EC_ENABLE 1 TP2705 KBC_NOVO_BTN#
21,60 SPI_SO_R F_SDI_F_SDIO1 PSL_OUT_GPIO71#
33R2J-2-GP 2 1 R2722 EC_SPI_DO_C 87 93 KBC_PWRBTN_EC#
21,60 SPI_SI_R F_SDI_F_SDIO0 PSL_IN2_GPI6#
21 KBC_RTCRST# 91 73 AC_IN_KBC
GPIO81/F_WP# PSL_IN1_GPI70#
EC_SPI_DI_C
C C
19,97 PM_PWRBTN# 117
GPIO20/TA2/IOX_DIN_DIO
1
19 AC_PRESENT 112
GP/I/O84/IOX_SCLK/XORTR# KBC_VCORF R2773
61,62,82 USB_PWR_EN_R 110 44
GPO82/IOX_LDSH/TEST# VCORF 100KR2J-1-GP
1
AGND
GND1
GND2
GND3
GND4
GND5
GND6
C2712
2
SC1U10V2KX-1GP
2
NPCE885GA0DX-GP
18
45
78
89
116
5
103
EC_AGND
R2711
1 2
0R0402-PAD
Reset IC: Prevent BIOS data loss solution

EC_GPIO47 High Active
3D3V_AUX_S5
ECRST#
1
Q2702
SC1U6D3V2KX-GP
C2715
PROCHOT_EC G R2705
AD_OFF 2 1 10KR2J-3-GP 3D3V_AUX_S5
1
R2770 D H_PROCHOT#_EC 1 2 H_PROCHOT# 5,42 U2702 DY
E
1KR2J-1-GP R2732 R2733 DY
2
100KR2J-1-GP S 0R0402-PAD 28,36,86 PURE_HW_SHUTDOWN# 2 1 ECRST#_B B 1
2
R2723 Q2701 GND
3
2N7002K-2-GP 10KR2J-3-GP MMBT3906-4-GP PURE_HW_SHUTDOWN# VCC
2
C
RESET#
84.2N702.031 84.03906.F11
2ND = 84.2N702.J31 2nd = 84.C3906.A11
G690L293T73UF-GP
74.00690.I7B
1
R2716
DY 0R2J-2-GP
2
D2704
22 EC_SCI# 1
3D3V_AUX_S5
B 3 ECSCI#_KBC
B
1
2
BAS16-6-GP R2704
83.00016.K11 10KR2J-3-GP
2ND = 83.00016.F11
WHY
2
68 KBC_PWRBTN# 2 1 KBC_PWRBTN_EC#
R2703
470R2J-2-GP C2717
1
SC220P50V2KX-3GP
G2701 R2774 DY
GAP-OPEN 100KR2J-1-GP
2
2
2
EC GPIO standard PH/PL
3D3V_AUX_KBC
RN2701
BAT_SCL 3 2
3D3V_AUX_KBC BAT_SDA 4 1
SRN4K7J-8-GP
1
SML1_CLK R2727 RN2703

RN48 47KR2F-GP BAT_IN# 4 1
SMBC_THERM 3 2 BOM CTRL LID_CLOSE# 3 2
SMBD_THERM 4 1 3D3V_S0
2
MODEL_ID_AD SRN100KJ-6-GP
Q2703 SRN10KJ-5-GP
1
4 3
R2728 RN2705
SMBC_THERM 28,86 100KR2F-L1-GP
5 2 S5_ENABLE 4 1 PCB Version A/D Pull-Low Resistor Pull-High Resistor Voltage
ECRST# 3 2 3D3V_AUX_KBC
SML1_DATA 6 1 (Pin98) (3D3V_AUX_S5)
2
SMBD_THERM 28,86
SRN10KJ-5-GP
1
2N7002KDW-GP SA 100.0K 10.0K 3.0V
3D3V_S0 84.2N702.A3F PCIE_WLAN_WAKE# 2 1 R2724
2nd = 84.DM601.03F 10KR2J-3-GP R2715 64K9R2F-1-GP SB 100.0K 20.0K 2.75V
DY BOM CTRL
SC 100.0K 33.0K 2.48V
2
3D3V_S0 PCB_VER_AD
-1 100.0K 47.0K 2.24V
1
R2726 Reserved 100.0K 64.9K 2.0V
MODEL_ID_AD Pull Down Pull High Voltage 100KR2F-L1-GP
(Pin100) Reserved 100.0K 76.8K 1.87V
2
E51_RxD 1 DY2 Reserved 100.0K 100.0K 1.65V
UMA 100.0K 33.0K 2.481V R2708
10KR2J-3-GP
A OPTIMUS 100.0K 47.0K 2.245V
BLUETOOTH_EN 2 DY 1 71.00885.A0G
A
R2710
IC EMB CTRL NPCE885PA0DX LQFP 128P
10KR2J-3-GP
<Core Design>
Wistron Corporation
Title
<Title>

A1 LA480 SD

5 4 3 2 1
SSID = Thermal http://laptopblue.vn

Thermal sensor 20110718_Carrey:
For Vendor suggestion, add 390pF Cap. as closed to pin B/C and E of Q2803
T8
Close to SO-DIMM on top side. 2200p close to smsc2103 chip
H_THERMDA
SA 0905 change to 390p
3 1
1
E
1
D B C2808 C2802 D
1
B C2803 Q2803 SC390P50V2KX-GP SC2200P50V2KX-2GP
2
SC390P50V2KX-GP
2
E
H_THERMDC
2
C
MMBT3904W T1G-GP
Q2802
MMBT3904W T1G-GP
CPU backside or inside the socket
2200p close to smsc2103 chip CPU TEMP:
REMOTE2-
H_THERMDA and H_THERMDC routing 10mil trace width
2 and spacing. Locate Capacity near Thermal diode.
E
1
B C2804 C2805
SC390P50V2KX-GP SC2200P50V2KX-2GP
2 DY
2
C
4 WIRE PWM Fan Control circuit

Q2804 REMOTE2+
MMBT3904W T1G-GP 5V_S0
between CPU, VGA and DIMM on bottom side
C2801 R2803
1
1
SC4D7U6D3V3KX-GP
10KR2J-3-GP
R2802
0R0805-PAD
20110718_Carrey: 3D3V_S0 AFTP2807
2
For Vendor suggestion, add 10k pull high to 3D3V_S0
2
FAN1
1
C C
3D3V_S0 R2801 6
1
6K8R2J-GP
5V_S0_FAN 4
1
FAN_TACH 3
2
R2812 SHDN_SEL 2
10KR2J-3-GP
DY 3D3V_S0 SHDN --> 2N3904 ON External diode FAN_PW M 1 2 FAN_PW M_C 1
R2804 EC2802 EC2801
2
THERM_SCI# 0R0402-PAD 5
1
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
R2805 RN2801 ACES-CON4-GP-U1
1
68R2-GP 2 3 20.F0714.004
3D3V_S0
U2801 1 4 DY DY
2
2
1 2 2103_VDD SRN10KJ-5-GP
C2806 SCD1U10V2KX-4GP 3 4 2103_4 1 TP2802 20100707_EMI CHECK PIN DEFINE
VDD GPIO1 2103_5 TP2803
GPIO2 5 1 D2801
H_THERMDA 2
H_THERMDC DP1 FAN_TACH_1 FAN_TACH
1 DN1 TACH 10 1 2
REMOTE2+ 16 11 FAN_PW M
REMOTE2- DP2/DN3 PWM
15 ND2/DP3
14 TRIP_SET R2806 1 2 649R2F-GP CH551H-30PT-GP
THERM_SYS_SHDN# TRIP_SET SHDN_SEL AFTP2801 FAN_PW M_C
7 SYS_SHDN# SHDN_SEL 13 T8 = 98 83.R5003.C8F 1
THERM_SCI# 6 1st = 83.R5003.J8F AFTP2805 1 FAN_TACH
ALERT# AFTP2806 5V_S0_FAN
TRIP_SET: 649 ohm => 87 dgree C 2ND = 83.R5003.I8F 1
27,86 SMBC_THERM 9 SMCLK GND 12
27,86 SMBD_THERM 8 SMDATA GND 17
B B
EMC2103-2-AP-GP
pin6, ALERT# OD
pin7, SYS_SHDN# OD
3D3V_AUX_S5 3D3V_S0 3D3V_S0

3
D2802 R2808 R2809

BAT54PT-GP 100KR2J-1-GP 10KR2J-3-GP
83.00054.T81 DY
2ND = 83.BAT54.D81 Q2801
2
3rd = 83.BAT54.S81 S THERM_SYS_SHDN#

1
A <Core Design> A
27,36,86 PURE_HW _SHUTDOW N# D
1
IMVP_PW RGD_T
R2810 C2807
G 1
R2811
2 IMVP_PW RGD 36,42
Wistron Corporation
1
10KR2J-3-GP SCD1U10V2KX-5GP 2N7002K-2-GP 0R0402-PAD 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
84.2N702.031 Taipei Hsien 221, Taiwan, R.O.C.
DY DY
2ND = 84.2N702.J31
2
Title
THERMAL SENSOR SMSC EMC2103

A3
LA480 SD
5 4 3 2 1
5 4 3 2 1
5V_S0 1A
http://laptopblue.vn AUD_5V
5V_S0
R2902 1 2 0R5J-5-GP
1 2 AUD_PVDD 1 2
R2903 0R0805-PAD C2902 C2903 C2904 C2927 Close to Codec R2904 0R0805-PAD
1
1
1
SC10U6D3V3MX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V3MX-GP
C2905
<<Attention>> SC10U6D3V3MX-GP
2
DY Surges of PVDD >7V duration 0.1ms when
2
class D amplifier is working may damage AU_GND
the amplifier, 10uF tantalum capacitors AU_GND Tied at one point only under the
are required at PVDD1 and PVDD2 to ALC269 or near the ALC269
suppress the surge.
D D
Close to Codec
AUD_PORTA_R 1 2 AUD_HPOUT_R 82
R2905 75R2J-1-GP
AUD_PORTA_L 1 2 AUD_HPOUT_L 82
R2906 75R2J-1-GP
AUD_MIC1_VREFO_L EXT MIC
AUD_MIC2_VREFO 58
2 1 AUD_CPVEE
AU_GND
C2906 1 2 AU_GND
SC2D2U10V3KX-1GP AUD_LDO_CAP C2907
SC10U6D3V3MX-GP
close to pin27 AUD_MIC1_VREFO_L 1 2
R2922 2K2R2J-2-GP
1
C2909 AUD_MIC1_COMBO 1 2 AUD_MIC1_COMBO_R
AUD_MIC1_COMBO_R 82
C2908 SC1U6D3V2KX-GP C2910 R2923 1KR2J-1-GP R2924
SC2D2U10V3KX-1GP SCD1U10V2KX-5GP AUD_COMBOJACK 1 2
AUD_CBP 2
2
22KR2J-GP
AUD_CBN
AUD_5V AUD_5V
Close to Codec
AU_GND
2
close to pin27
1
R2925 C2928
1
1
C2911 C2912 C2913 C2901 22KR2J-GP SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SC4D7U6D3V3KX-GP Capacitor Working Voltage
36
35
34
33
32
31
30
29
28
27
26
25
2
AU_GND U2901 ALC269 having AVDD=5V ±5%, so the capacitors must have a 10V working voltage. A working
2
1
voltage of 16V is recommended to provide margin for variations in the application
CBP
CPVEE
HP-OUT-L
MIC1-VREFO-L
MIC2-VREFO
LDO-CAP
AVSS1
AVDD1
CBN
HP-OUT-R
MIC1-VREFO-R
VREF
AU_GND AU_GND
AU_GND AU_GND AU_GND
37 24
AVSS2 LINE1-R
38 23
AVDD2 LINE1-L
AUD_PVDD 39 22 AUD_PORTB_R C2914 1 2 SC4D7U6D3V3KX-GP AUD_MIC1_COMBO EXT MIC
PVDD1 MIC1-R
40 21 AUD_PORTB_L C2915 1 2 SC4D7U6D3V3KX-GP
58 AUD_SPK_L+ SPK-L+ MIC1-L
C
58 AUD_SPK_L- 41 20 C
SPK-L- MONO-OUT
42 19 AUD_JDREF 1 2
PVSS1 JDREF AU_GND
R2909
43 18 20KR2F-L-GP
PVSS2 SENSE_B
ALC269Q-VC-GR-GP AUD_PORTF_R C2916
58 AUD_SPK_R- 44 17 1 2 SC4D7U6D3V3KX-GP AUD_MIC2 58
SPK-R- MIC2-R
B Series-MIC ANALOG MIC
45 16 AUD_PORTF_L C2917 1 2 SC4D7U6D3V3KX-GP
58 AUD_SPK_R+ SPK-R+ MIC2-L
B Series-MIC
AUD_PVDD 46 15
PVDD2 LINE2-R
AUD_COMBOJACK 47 14
EAPD/COMBO_JACK LINE2-L
48 13 AUD_SENSE_A 1 2
SPDIFO GPIO0/DMIC-DATA SENSE_A HPOUT_JD 82
R2912
GPIO1/DMIC-CLK
49 39K2R2F-L-GP
GND
SDATA-OUT
ANALOG
SDATA-IN
DVDD-IO
PCBEEP
RESET#
BIT-CLK
DVDD1
DVSS2
SYNC
PD#
DIGITAL
1
10
11
12
3D3V_S0
1 2 AUD_DVDD
AUD_SDATA_OUT
R2913 0R0805-PAD C2919 C2920 AUD_PC_BEEP 2 1 KBC_BEEP_R 2 1 R2914 HDA_SPKR 21

C2918 10KR2J-3-GP
1
1
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
AUD_DVDD
SCD1U10V2KX-5GP
2 1 R2916 KBC_BEEP 27
R2915 C2921 10KR2J-3-GP
2
2
4K7R2J-2-GP SC100P50V2JN-3GP
2
HDA_CODEC_RST#
58 AUD_DMIC_DATA HDA_CODEC_RST# 21
1 2 AUD_DMIC_CLK_R
B 58 AUD_DMIC_CLK HDA_CODEC_SYNC 21 B
R2901 0R0402-PAD
AUD_SDATAIN 2 1
3D3V_S0 HDA_SDIN0 21
R2917 22R2J-2-GP
27 AMP_MUTE#
1 2 HDA_CODEC_BITCLK_R 2 1
21 HDA_CODEC_SDOUT HDA_CODEC_BITCLK 21
1
R2918 0R0402-PAD R2919 0R0402-PAD

R2921
10KR2J-3-GP
2
AMP_MUTE# AUD_DMIC_CLK AUD_DMIC_DATA AUD_SDATA_OUT HDA_CODEC_RST# HDA_CODEC_BITCLK_R

1
1
C2922 C2923 C2924 C2925 C2926
SC33P50V2JN-3GP DY SC33P50V2JN-3GP DY SC22P50V2JN-4GP DY SC6D8P50V2DN-GPDY SC6D8P50V2DN-GPDY
R2920 DY
2
2
4K7R2J-2-GP
2
For EMI issue.
20100705_AUD
A A
<Core Design>
Wistron Corporation
Title
AUDIO CODEC
A2
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Title
Reserved
A4 SD
LA480
5 4 3 2 1
5 4 3 2 1
main pwr if have no ASF
25MHz XTAL http://laptopblue.vn 3D3V_S0
1
LAN_XTAL0
R3136
X3101 1KR2J-1-GP
4 1 LAN_XTAL1 C3103 C3148
2
RTL_ISOLATE#
15pF
1
3 2
VB480 78.15034.1FL
12pF
R3119
12pF 15KR2F-GP
XTAL-25MHZ-155-GP VB580 12pF
2
82.30020.D41 78.12034.1FL
D D
2nd = 82.30020.G71
3rd = 82.30020.G61
1 2 1D05V_LAN_S5 1D05V_LAN_S5
R3130 1M1R2J-GP 3D3V_LAN_S5 3D3V_LAN_S5
1
C3103 C3148 High:Link up

SC12P50V2JN-3GP SC12P50V2JN-3GP
BOM CTRL Low:Link down 3D3V_LAN_S5
2
LAN_XTAL0
LAN_XTAL1
GPO R3120 1 2 1KR2J-1-GP
1 2 LAN_RSET
GPO LAN_ACT_LED# 59
R3123 2K49R2F-GP
LAN_EECS R3122 1 2 10KR2J-3-GP
SPEED_100# 59
71.08111.N03, IC PCIE CTRL RTL8111F-CGT QFN 48P LAN_EEDI R3126 1 2 10KR2J-3-GP
SMB_LAN_DATA R3128 2 10KR2J-3-GP
48
47
46
45
44
43
42
41
40
39
38
37
71.08111.J03, IC PCI-E RTL8111E-VL-CGT QFN 48P 1
U3101
8111F can use GPIO to inform system to do LAN PHY power down. The SM DATA with 10K ohm pull GND.
49
AVDD33
AVDD33
AVDD10
CKXTAL2
CKXTAL1
AVDD33
DVDD10
LED0
DVDD3
LED1/EESK
RSET
GPO/SMBALERT
GND
3D3V_LAN_VDDSREG
R3125 For Enable Switch Regulator.
R3124 For Disable Switch Regulator.
59 MDI0+ 1 36 1D05V_LAN_REGOUT
MDIP0 REGOUT 3D3V_LAN_S5
59 MDI0- 2 35
MDIN0 VDDREG
1D05V_LAN_S5 3 34
AVDD10 VDDREG LAN_ENSWREG
59 MDI1+ 4 33 1 2
MDIP1 ENSWREG LAN_EEDI R3125 0R0402-PAD
59 MDI1- 5 32
1
MDIN1 EEDI/SDA LAN_EEDO TP3102
1D05V_LAN_S5 6 31 1
AVDD10 LED3/EEDO LAN_EECS
59 MDI2+ 7 30
MDIP2 EECS/SCL R3124
59 MDI2- 8 29 1D05V_LAN_S5
MDIN2 DVDD10 0R2J-2-GP
1D05V_LAN_S5 9
AVDD10 LANWAKE#
28 PCIE_WAKE# 19,65,66 DY
59 MDI3+ 10 27 3D3V_LAN_S5
2
MDIP3 DVDD33 RTL_ISOLATE#
59 MDI3- 11 26
MDIN3 ISOLATE#
3D3V_LAN_S5 12 25 PLT_RST# 5,18,27,36,65,66,71,80,82,83,97
AVDD33 PERST#
REFCLK_N
REFCLK_P
SMBDATA
CLKREQ#
SMBCLK
DVDD10
EVDD10
HSON
HSOP
Make sure PCIE_Wake# & PCIE_CLK_LAN_RQ1#connected to 10K
HSIN
HSIP
GND
C resistor pull high close to PCH side C
RTL8111F-CGT-GP
13
14
15
16
17
18
19
20
21
22
23
24
1D05V_LAN_S5
SMB_LAN_DATA
2 1 LAN_CLKREQ#
20 PCIE_CLK_LAN_REQ#
0R0402-PAD R3121
20 PCIE_TXP4
20 PCIE_TXN4
20 CLK_PCIE_LAN
20 CLK_PCIE_LAN#
1D05V_LAN_EVDD10 3D3V_LAN_S5
DY
3D3V_S5 1 2
C3145 1 2 PCIE_RXP4_C R3135 0R5J-5-GP
20 PCIE_RXP4
SCD1U10V2KX-4GP
C3147 1 2 PCIE_RXN4_C
20 PCIE_RXN4
SCD1U10V2KX-4GP
C3152 S D
C3151
1
SCD1U10V2KX-4GP
Q3103
1
SCD1U10V2KX-4GP
R3133 AO3419L-GP C3150
G
100KR2J-1-GP 84.03419.031
SC1U10V2KX-1GP
2nd = 84.00048.031
2
3rd = 84.03334.031
2
LAN_PWR_ON_T
D
Q3104
2N7002K-2-GP
1D05V_LAN_S5 84.2N702.J31
2ND = 84.2N702.031
1D05V_LAN_REGOUT 1 2 1 2 1D05V_LAN_EVDD10
L3102 C3146 C3129 C3130 C3131 C3132 C3133 C3134 C3138 C3139 R3131 C3128
S
IND-4D7UH-192-GP 0R0603-PAD C3149
SC4D7U6D3V3KX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC1U10V2KX-1GP
B B
1
SCD1U10V2KX-4GP
1
27 LAN_PWR_ON
2
L3102 adopt spec. Layout Note: C3128&C3149

C3104 change to 4.7uF X5R Layout Note: Close to U3101 pin C3130 ~ C3134,C3138,C3139 Close to U3101 pin21
type capacitor For VDD10 pins - 3, 6, 9, 13, 29, 41, 45.
3D3V_LAN_S5 3D3V_LAN_VDDSREG
1 2
C3135 C3140 C3141 C3142 C3143 C3144 R3134 C3136 C3137
0R0603-PAD
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
1
1
2
Layout Note: C3135, C3140~C3144 Close to U3101 pin

For VDD33 pins - 12, 27, 39, 42, 47, 48.
A A
Wistron Corporation
Taipei<Core
HsienDesign>
221, Taiwan, R.O.C.
Title
LAN RTL8111F
A2
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
R5U220 (CARD READER)
A1
LA480 SD
5 4 3 2 1
A B C D E
4 4
BLANK
3 3
2 2
<Core Design>
1
Wistron Corporation 1
Title
Reserved
A4
LA480 SD
A B C D E
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Title
Reserved
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Title
USB 3.0 Controller

A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
5V_S0 5V_S5
Power Sequence Run Power 1

2
U3601
S
S
D 8
D 7
1 2 3 S D 6
2ND = 84.00610.C31 RUN_ENABLE C3607 SCD1U50V3KX-GP 4 G D 5
DCBATOUT 84.S0610.B31 DY
R3614 Q3604 AO4468-GP
R3614 CRB : 1K Z_12V
84.04468.037
1 2 S D 1 2 2nd = 84.08882.037
D 1 2 R3619 10KR2J-3-GP R3626 0R0402-PAD D
K
28,42 IMVP_PWRGD SYS_PWROK 19
1
NDS0610-NL-GP C3606 R3621
1
1KR2F-3-GP D3602
SCD22U25V3KX-GP
330KR2J-L1-GP
R3620 MMPZ5239BPT-GP 3D3V_S0 3D3V_S5
2
1
C3612 10KR2J-3-GP 83.9R103.D3F U3602
1 DY SCD01U50V2KX-1GP 1 2 Z_12V_G3 1 S D 8
A
R3618 330KR2J-L1-GP 2 S D 7
2
1
3 3 S D 6
19,27,37,47 PM_SLP_S3# G D 5
R3617 Z_12V_D4 4
2 3D3V_AUX_S5 100KR2J-1-GP
D3603
RUN_ENABLE_ALL_G
AO4468-GP
BAS16-6-GP 1 2 84.04468.037
2
83.00016.K11 R3612 10KR2J-3-GP 2nd = 84.08882.037
2ND = 83.00016.M11
3rd = 83.00016.N11 Q3603 Q3605
19,27,37,47 PM_SLP_S3# G 4 3
D PM_SLP_S3 5 2 PM_SLP_S3# 1D5V_S0 1D5V_S3

U3606
S 6 1 1 S D 8
2 S D 7
2N7002K-2-GP 2N7002KDW-GP 3 S D 6
84.2N702.J31 84.2N702.A3F 4 G D 5
2nd = 84.2N702.031 2nd = 84.DM601.03F
1
AO4468-GP
C3611 84.04468.037
SCD01U50V2KX-1GP 2nd = 84.08882.037
2
1D5V_S0
MAX Current 3000 mA
Design Current 2100 mA
Total= 11.39A
C C
1D05V_VTT 1
R3622
DY 2 H_THERMTRIP# 5,22
56R2J-4-GP 3D3V_S5
E
1 2 PS_S3CNTRL 37,97
5,18,27,31,65,66,71,80,82,83,97 PLT_RST# 1 2 B Q3601 R3608 100KR2J-1-GP
R3616 MMBT2222A-3-GP
1
4K7R2J-2-GP
SCD1U10V2KX-5GP
D
C
C3602
R3632
2K2R2J-2-GP Q3606
1
2N7002K-2-GP
84.2N702.J31
2
2ND = 84.2N702.031
S
2
19,27,37,47 PM_SLP_S3#
3 PURE_HW_SHUTDOWN# 27,28,86
D3601
41 3V_5V_EN 1 BAS16-6-GP
83.00016.K11
1
2ND = 83.00016.M11
R3602 3rd = 83.00016.N11
200KR2F-L-GP
DY 1 2 S5_ENABLE 27,97
R3603 2KR2F-3-GP
2
TP3601 1
B B
A A
<Core Design>
Wistron Corporation
Title
Power Plane Enable

A1 SD
LA480
5 4 3 2 1
5 4 3 2 1
Close to CPU
S3 Power Reduction Circuit Processor VREF_DQ Implementation
http://laptopblue.vn Close to DIMM
S3 Power Reduction Circuit SM_DRAMPWROK
DEL R3714 0D75V_S0 1D5V_S0
R3705 ->100K
1
R3703 R3704
R3707
1 DY20R2J-2-GP
DY C3701 22R2J-2-GP 220R2J-L2-GP DY
2
D Q3708 D
Q3701_D
Q3702_D
S +V_SM_VREF_CNT 9
1
12 +V_SM_VREF D
R3705 C3701
G 100KR2J-1-GP SCD1U10V2KX-4GP
2
DY
D
FROM M1/M3 2N7002K-2-GP Q3701 Q3702
2
84.2N702.J31 DY
2ND = 84.2N702.031
2N7002K-2-GP 2N7002K-2-GP
PM_SLP_S3# 19,27,36,47 84.2N702.J31 84.2N702.J31
2ND = 84.2N702.031 2ND = 84.2N702.031
G
S
S
PS_S3CNTRL
36,97 PS_S3CNTRL
SM_DRAMPWROK must have a maximum of 15ns rise or fall time Close to CPU
over VDDQ * 0.55± 200mV and the edge must be monotonic
S3 Power Reduction Circuit SM_DRAMPWROK Close to CPU
3D3V_S5 S3 Power Reduction Circuit SM_DRAMPWROK
add 0.1uF
1D5V_S3
1D5V_S0
1
1
C R3713 C
1
200R2F-L-GP R3706
R3708 1KR2F-3-GP
U3701 200R2F-L-GP
2
19 PM_DRAM_PW RGD 1 2 PM_DRAM_PW RGD_R 1 5 DY
2
R3715 0R0402-PAD IN B VCC
1 2
2
0D75V_EN 2 R3709 0R2J-2-GP S3 Power Reduction Circuit
IN A
1
3 4 VDDPW RGOOD_R 1 2 VDDPW RGOOD 5 Q3703 SM_DRAMRST#

C3704 GND OUT Y R3719
DY 5 SM_DRAMRST# 1 2SM_DRAMRST#_R S
1
SCD1U10V2KX-5GP 74VHC1G09DFT2G-GP 130R2F-1-GP R3711
2
OD AND gate required 0R0402-PAD D SM_DRAMRST#_D 1 2 DDR3_DRAMRST# 14,15
1
73.01G09.AAH R3722 R3712
1
2nd = 73.01G09.0AB DY 39R2J-L-GP G 1KR2F-3-GP
3rd = 73.01G09.BAH 2 R3720 R3701 DY C3702
0R2J-2-GP 4K99R2F-L-GP 2N7002K-2-GP SC100P50V2JN-3GP
VDDPWRGOOD_D
DY
2
DY 84.2N702.J31
2
Q3707 DY 2ND = 84.2N702.031
2
36,97 PS_S3CNTRL G
D DRAMRST_CNTRL_PCH 12,20
1
S C3703
SCD047U16V2KX-1-GP
2N7002K-2-GP
2
84.2N702.J31
2ND = 84.2N702.031
B B
5 S3 Power Reduction
Q3704
36,97 PS_S3CNTRL G
D 0D75V_EN
2N7002K-2-GP
84.2N702.J31 1.05VTT_PW RGD 45,48
2ND = 84.2N702.031
1
R3710
0R0402-PAD
2
19,27,36,47 PM_SLP_S3# 1
R3716
DY 22R2J-2-GP
2 0D75V_EN 46
A <Core Design> A
1
C3705
DY SCD1U10V2KX-5GP
Wistron Corporation
2

Title
ADAPTER
A3 SD
LA480
5 4 3 2 1
5 4 3 2 1
Adaptor in to generate DCBATOUT
D D
ADT_TYPE_R1 1 2 ADT_TYPE 27
PR3806
0R0402-PAD
1
R3801
274R2F-GP
2
PD3802
3
C ADT_TYPE_R 1 2 3D3V_AUX_KBC
C
BAV99-8-GP
DCIN14
1 6
AD_JK AD+
2 7
3 8 F3801 PU3801
4 9 AD_JK_F 1 2 1 S D 8
5 10 2 S D 7
K
1
FUSE-7A24V-5-GP PD3801 3 S D 6
1
MLX-CONN10-4-GP PC3806 PR3803 PC3801 P6SBMJ27APT-GP AD+_2 4 G D 5
21.D0241.205 SCD1U50V3KX-GP DY 200KR2F-L-GP SCD1U50V3KX-GP 83.P6SBM.DAG PR3801 PC3802
SC1KP50V2KX-1GP
1
C3801 C3802 PC3807 DY DY 2ND = 83.P6SMB.JAG AO4407AL-GP
1
200KR2F-L-GP
SC1U50V5ZY-1-GP
SCD1U50V3KX-GP 3TH = 83.P6SMB.CAG 84.04407.G37
SC100P50V2JN-3GP
A
2
AD_DETECT 27 Id= -10A
2
PQ3802 Qg= -22nC
2
Rdson=14~22mohm
R2
E
AD_OFF#_1 B
1
R1
PC3803 C
SCD1U50V3KX-GP DY PR3804
DY 34K8R2F-1-GP PDTA124EU-1-GP
1
PQ3801 84.00124.K1K
C 2ND = 84.00024.01K PR3802
2
R1
27 AD_OFF B DY PR3805
100KR2J-1-GP
100KR2J-1-GP
E
R2
2
B PDTC124EU-1-GP B
84.00124.H1K
2ND = 84.00124.X1K
AFTP3805 1
AFTP3804 1
AFTP3801 1 AD_JK_F
AFTP3802 1 ADT_TYPE_R
AFTP3803 1 GND
AFTP3806 1
DCIN14 for 14" VB480 & VB485

DCIN15 for 15" VB580 & VB585
A <Core Design> A
Wistron Corporation
Title
DCIN_JACK
A3 LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
BATTERY CONNECTOR
BT+
1
PC3901 PC3902
SCD1U50V3KX-GP SC2200P50V2KX-2GP
2
Swap for V480 BAT1
RN3901 BT+ 1 BAT_VCC

1 8 2 BAT_VCC
2 7 BATA_SCL_1 3
27,40 BAT_SCL I2C_CLK
C 3 6 BATA_SDA_1 4 C
27,40 BAT_SDA I2C_DAT
27 BAT_IN# 4 5 BAT_IN#_1 5
PL3901 PL3902 PL3903 PC3904 PC3903 TEMP
6 GND
SRN33J-7-GP 7 GND
MLVS0402M04-GP
MLVS0402M04-GP
MLVS0402M04-GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
8 GND
1
9 GND
1
PC3905
SC470P50V2KX-3GP
K
ALP-CON7-33-GP
2
83.5R603.D3F PD3901 DY DY DY 20.81720.007
2ND = 83.5R603.Q3F MMPZ5232BPT-GP-U
2
AFTP3908 1 ME change P/N at SIT
Old 20.81529.007
A
AFTP3909 1 Nwq 20.81720.007

Varistor AFTP3910 1
BAT_IN#
BAT_SDA
BAT_SCL
AFTP3902 1 BATA_SDA_1
AFTP3903 1 BATA_SCL_1
AFTP3904 1 BT+
AFTP3905 1
AFTP3906 1
AFTP3907 1 BAT_IN#_1
B DY D3902 DY D3903 DY D3901 B
3
3
1 2 1 2 1 2
BAV99-8-GP BAV99-8-GP BAV99-8-GP
3D3V_AUX_KBC
DY on LAB stage
A <Core Design> A
Wistron Corporation
Title
BATT_CONN
LA480 SD
5 4 3 2 1
5 4 3 2 1
SSID = Charger
AD+ 8 D
D
PU4001
S
S
1
http://laptopblue.vn AD+_TO_SYS DCBATOUT
1
2
PU4002
S
S
S
D
D
D
8
7
BT+
7 2 1 PR4004 2 3 6
1
6 D S 3 D01R3721F-GP-U AD+ 4 G D 5
5 D G 4 PR4002
100KR2J-1-GP AO4407AL-GP
AO4407AL-GP 84.04407.G37
A8( ANNIE/ASTRO)
1
84.04407.G37
1
PR4007,PR4008 PR4001
10KR2F-2-GP
AD+_G_2
PG4001 PG4002 PR4005
Id= -10A Id= -10A
1
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP 470KR2J-2-GP
Qg= -22nC PR4003 Qg= -22nC
2
AD+ total power R1 R2 Rdson=14~22mohm 49K9R2F-L-GP Rdson=14~22mohm
2
DC_IN_D
D 12.4K D
2
65w 64.12425.6DL 100K PQ4001 2 1
AD+_G_1
3 4 PC4003 68.00143.041
80w 41.2k 100K
AC_IN 2 5 L4001
60.4k 1 2
DCBATOUT
90w 64.60425.6DL 100K 1 6 BLM18PG330SN1D-GP
1
PC4002 L4002
AD_JK SCD1U50V3KX-GP PC4004 DCBATOUT_L 1 2
2N7002KDW-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
120w 118k 100K SCD1U50V3KX-GP BLM18PG330SN1D-GP
PC4024
PC4005
84.2N702.A3F
PWR_CHG_ACN
PWR_CHG_ACP
68.00143.041
1
2nd = 84.DM601.03F
SC1U25V5KX-1GP
1 2 BQ24737_VCC BQ24737_REGN PC4006
PC4001
PR4015 CHG_AGND 1st = 83.R2003.P8F SCD1U25V2KX-GP
2
CHG_AGND
1
20R5F-1GP 2nd = 83.1R003.N8F
5
6
7
8
PR4006 3rd = 83.R2003.B8M PC4009
D
D
D
D
3D3V_AUX_S5 316KR3F-2-GP PR4019 SC1U10V2KX-1GP PU4004
2
1 2 K A 1 2 SIS412DN-T1-GE3-GP
2 CHG_AGND
1
PU4003 0R2J-2-GP PD4003
BQ24737_REGN CH520S-30PT-GP
ACP
ACN
2
G
S
S
S
PWR_CHG_IOUT 20
1
PR4009 VCC PC4017
4
3
2
1
10KR2F-2-GP STOP_CHG# PR4007 PR4011 SCD1U50V3KX-GP
2
R1 12K4R2F-GP 100KR2J-1-GP BQ24737_ACDET 6 17 BQ24737_BTST
connects to KBC
1
ACDET BTST
BOM CTRL Charger Current=1.4~3.6A
1
PR4010 PC4007
1 2
49K9R2F-L-GP SCD01U50V2KX-1GP BQ24737_CMPOUT 16
27 STOP_CHG# REGN
2
1
PR4014 3
D
PR4008 120KR2F-L-GP CMPOUT BQ24737_HIDRV

18
PQ4005 100KR2F-L1-GP PR4016 HIDRV PL4001 PR4017 BT+
R2
2N7002A-7-GP CHG_AGND 3D3MR2J-GP 4 D01R3721F-GP-U
2
BQ24737_CMPOUT CMPIN BQ24737_PHASE BT+_R
G 19 1 2 1 2
2
2
PHASE
SCD1U50V3KX-GP
CHG_AGND BQ24737_CMPIN IND-5D6UH-48-GP-U1
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PC4022
9 15 BQ24737_LODRV
27,39 BAT_SCL
S
1
SCL LODRV
PG4003
CHG_AGND PC4020 PC4021
PG4004
5
6
7
8
PC4019
D
D
D
D
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
8 PC4025 PU4005
C C
2
27,39 BAT_SDA SDA
SIS412DN-T1-GE3-GP
3D3V_AUX_S5 PR4025 SC470P50V2KX-3GP
1
10R2F-L-GP
2
13 BQ24737_SRP 1 2
1
BQ24737_ILIM SRP
CHG_AGND 10
ILIM
G
S
S
S
PR4020 12 BQ24737_SRN 1 2
100KR2J-1-GP SRN PR4024
4
3
2
1
BQ24737_REGN_R 11 7D5R2F-GP
BM#
2
1
BQ24737RGRR-GP
PR4022
10KR2F-2-GP
DY 5 7 PWR_CHG_IOUT 1 2
ACOK# IOUT AD_IA 27
PR4013 BQ24737_CSOP_1
GND
GND
2
BQ24737_REGN 0R0402-PAD
3D3V_AUX_S5
1
21
14
PR4026
1
1
33KR2F-GP
DY PR4032 PC4016
100KR2J-1-GP 1 2 SCD1U50V3KX-GP
2
2
PR4018 PC4011
D
1
PQ4007 0R0402-PAD SC220P50V2KX-3GP BQ24737_CSON_1
2
2N7002A-7-GP
SCD1U25V2KX-GP
2
CHG_AGND G CHG_ON# 27
1
PC4023
3D3V_AUX_S5 CHG_AGND
S
2
1 DY 2 BAT_SCL 3D3V_AUX_S5
PR4033 3K3R2J-3-GP
1
CHG_AGND CHG_AGND
PR4029
1 DY 2 BAT_SDA 100KR2J-1-GP
PR4034 3K3R2J-3-GP
3D3V_AUX_S5
2
1
PR4030
100KR2J-1-GP AC_IN#
B 27 AC_IN#
B
2
AC_IN
D
84.2N702.E31
2ND = 84.2N702.D31 PQ4008
AC_IN# G
2N7002A-7-GP
S
A A
<Core Design>
Wistron Corporation
Title
<Title>

A2 LA480 SD
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_5v3p3v
D D
DCBATOUT DCBATOUT_PWR_3D3V DCBATOUT DCBATOUT_PWR_5V
PWR_5V_EN1 2 1
PG4102 PR4121 PG4133
1 2 0R0402-PAD 1 2
GAP-CLOSE-PWR GAP-CLOSE-PWR
PG4103 PG4131
1 2 1 2
PG4104 PWR_3D3V_EN2 2 1 PG4130
PR4127 3V_5V_EN 36
1 2 1 2
0R0402-PAD
PG4132
1 2
GAP-CLOSE-PWR
PG4128
1 2
GAP-CLOSE-PWR
PG4129
1 2
DCBATOUT GAP-CLOSE-PWR
DCBATOUT_PWR_3D3V
PC4112 PC4113 DCBATOUT_PWR_5V
SC10U25V5KX-GP
SCD01U50V2KX-1GP
PC4109 PC4110 PC4111
1
Id=12A, Qg=3.8nC, PC4114 PC4115 PC4116
DY
1
1
SC10U25V5KX-GP
SCD1U50V3KX-GP
SC10U25V5KX-GP
1
Rdson=24~30 mohm
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U50V3KX-GP
Id=12A, Qg=3.8nC,
2
D
2
8
7
6
5
5
6
7
8
Design Current=5.25A Rdson=24~30 mohm 5V_PWR 5V_S5
2
D
D
D
D
D
D
D
D
PU4101 D Design Current=5.25A PG4119

OCP>7.8A PU4104 SIS412DN-T1-GE3-GP
12
1 2
SIS412DN-T1-GE3-GP PU4103 OCP>7.8A GAP-CLOSE-PWR
VIN
PG4120
G
S
S
S
SCD1U50V3KX-GP
Cyntec. 2.2uH 7.3*6.6*3
S
S
S
G
C
PR4108 1 2 C
3D3V_S5 3D3V_PWR PC4117 PR4109 PC4118 G S Cyntec. 3.3uH 6.5*6.9*3
1
2
3
4
4
3
2
1
PG4108 DCR=18~20mohm S G 2 1PWR_3D3V_VBST2_1
1 2 PWR_3D3V_VBST29
VBST2 VBST1
17 PWR_5V_VBST1 1 2PWR_5V_VBST1_1 1 2 GAP-CLOSE-PWR
1 2 Idc=8A, Isat=14A SCD1U50V3KX-GP 1D5R2F-GP 1D5R2F-GP DCR=28~30mohm PG4121
3D3V_PWR PWR_3D3V_DRVH210 16 PWR_5V_DRVH1 5V_PWR 1 2
GAP-CLOSE-PWR PL4102 DRVH2 DRVH1 PL4101 Idc=6A, Isat=13.5A
PG4109 1 2 PWR_3D3V_LL2 8 18 PWR_5V_LL1 1 2 GAP-CLOSE-PWR
IND-2D2UH-46-GP-U SW2 SW1 IND-3D3UH-57GP PG4122
1 2
1
68.2R210.20B PWR_3D3V_DRVL2 PWR_5V_DRVL1

D 11 15 68.3R310.20A 1 2
1
DRVL2 DRVL1
GAP-CLOSE-PWR D
8
7
6
5
5
6
7
8
PG4110 PR4110 DY PR4111 PT4101 GAP-CLOSE-PWR
D
D
D
D
SCD1U10V2KX-4GP
D
D
D
D
1 2 PC4119 PT4102 PG4116 2D2R5F-2-GP 14 PWR_5V_VO1 PU4102 DY 2D2R5F-2-GP PG4117 PC4120 PG4114
1
1
VO1
SE330U6D3VM-15-GP
PU4105 SIS412DN-T1-GE3-GP 1 2
2
1
SE220U6D3VM-30-GP
GAP-CLOSE-PWR-3-GP
SIS412DN-T1-GE3-GP
GAP-CLOSE-PWR-3-GP
SCD1U10V2KX-4GP
GAP-CLOSE-PWR PWR_3D3V_FB2 4 2 PWR_5V_FB1
2
PG4111 VFB2 VFB1 GAP-CLOSE-PWR
1PWR_3D3V_SNUB
2
1 2 PG4115
2
2
G
S
S
S
S
S
S
G
Id=16A, Qg=7.3nC, 1 2
1PWR_5V_SNUB
GAP-CLOSE-PWR PWR_3D3V_EN2 PWR_5V_EN1
6 20 G S
1
2
3
4
4
3
2
1
PG4112 EN2 EN1 Rdson=13.5~16.5 mohm GAP-CLOSE-PWR
1 2
S G
1
PWR_3D3V_CS2 5 1 PWR_5V_CS1
GAP-CLOSE-PWR CS2 CS1 PC4129
1
1
PG4113 SC2200P50V2KX-2GP
2
1 2 PC4121 DY Id=12A, Qg=3.8nC, PR4101 19 PR4102
121KR2F-L-GP VCLK 121KR2F-L-GP PC4123
DY
2
GAP-CLOSE-PWR SC330P50V3KX-GP Rdson=24~30 mohm SC560P50V-GP
2
7 21
2
2
1
PGOOD GND
VREG3
VREG5
PC4128
SC2200P50V2KX-2GP
2
1
TPS51225CRUKR-GP
3
13
PR4113 5V_PWR_2 PR4114
1
PR4112 3D3V_PWR_2
DY0R2J-2-GP 0R2J-2-GP DY
PWR_5V3D3V_VREG3
6K65R2F-GP PG4101 PR4115

1 2 15KR2F-GP
2
1 2
1 2
PWR_3D3V_FB2_R PWR_5V_FB1_R
PC4124 GAP-CLOSE-PWR-3-GP
2
DYSC18P50V2JN-1-GP PC4125 DY
SC18P50V2JN-1-GP
2
2
B B
1
1
3D3V_S5
PR4117 PR4120
2
10KR2F-2-GP 10KR2F-2-GP
1
DY PC4127 PC4126 3D3V_PWR_2 3D3V_AUX_S5

PR4119 SC1U10V2KX-1GP SC1U10V2KX-1GP Close to VFB Pin (pin2)
2
2
100KR2J-1-GP
2 1
PR4116
2
19 3V_5V_POK 0R0603-PAD
Close to VFB Pin (pin5)
DCBATOUT 3D3V_PWR_2 DCBATOUT

1
PR4122
2
10KR2F-2-GP
PU4106 DY PD4105
1
Vz=5.1V DY27MMPZ5231BPT-GP
2
PR4125 4 3 ECRST#
40K2R2F-GP
DY
1
5 2 DCBATOUT_UVP_2
DY
2
DCBATOUT_UVP_1 6 1
PR4126
1
1KR2F-3-GP
PR4129 DY
750KR2F-GP 2N7002DW-7F-GP
DY
2
A A
2
<Core Design>
Wistron Corporation
Title
TPS51123_5V_3D3V
SD
5 4 3 2 1
5 4 3 2 1
Close to PWR IC
PC4202 PW R_CPU_CORE_CCSP2 43
Open DY
1 2 PW R_CPU_CORE_CCSN2 43
SCD22U10V2KX-1GP PW R_CPU_CORE_CCSN1 43
PW R_CPU_CORE_CCSP1 43
1 PR4202 2 H_CPU_SVIDDAT
D 130R2F-1-GP D
CPU_CURRENT 27
PC4201
1D05V_VTT 1 PR4203 2 H_CPU_SVIDCLK 1 2
SCD22U10V2KX-1GP
54D9R2F-L1-GP PR4204
1 2 1 2 VCORE_AGND
121KR2F-L-GP PR4201 75KR2F-GP
VCORE_AGND
PC4204
PC4203
PW R_CPU_CORE_VREF 1 2 1 DY 2
SC33P50V2JN-3GP SCD1U10V2KX-4GP
PR4205 PR4206
PWR_CPU_CORE_CTHERM
PWR_CPU_CORE_CCOMP
PWR_CPU_CORE_COCP-I
PWR_CPU_CORE_CIMON
1 2 1 2
10K7R2F-GP NTC-100K-1-GP
8 VCCSENSE
3D3V_S5
8 VSSSENSE
1 PR4207 2PW R_CPU_CORE_VREF
15K8R2F-GP
5V_S5
C C
12
11
10
9
8
7
6
5
4
3
2
1
1
PR4208 PR4209
3D3V_S0 1 2 1 2 PR4210
CCSN3
CCSP3
CCSP2
CCSN2
CCSN1
CCSP1
CTHERM
CIMON
CGFB
CVFB
CCOMP
COCP_I
VCORE_AGND
24KR2F-GP 90K9R2F-GP 10R2F-L-GP
VCORE_AGND
1
PC4205
SC1U6D3V2KX-GP 49
2
SCD33U6D3V2KX-1-GP PW R_CPU_CORE_CF-IMAX GND
13 48
2
CF_IMAX V5
1
PC4206 1 2 PW R_CPU_CORE_VREF 14 47 PW R_CPU_CORE_CDH1 43

PR4211 VREF CDH1
3D3V_S5 15 V3R3 CBST1 46 PW R_CPU_CORE_CBST1 43 5V_S5 SC2D2U10V3KX-1GP
1
10KR2J-3-GP 48 D85V_PW RGD 2 1 PW R_CPU_CORE_VRON 16 45 PW R_CPU_CORE_CSW 1 43
PR4234 0R0402-PAD VR_ON PU4201 CSW1 PC4207
28,36 IMVP_PW RGD 17 CPGOOD CDL1 44 PW R_CPU_CORE_CDL1 43
2 1 PW R_CPU_CORE_VCLK 18 43
2
2
8 H_CPU_SVIDCLK VCLK V5DRV
SC4D7U10V3KX-GP
PR4232 2 1 0R0402-PAD PW R_CPU_CORE_ALERT# 19 TPS51640ARSLR-GP 42
8 VR_SVID_ALERT# PR4213 2 ALERT# PGND
8 H_CPU_SVIDDAT 1 0R0402-PAD PW R_CPU_CORE_VDIO 20 VDIO CDL2 41 PW R_CPU_CORE_CDL2 43
1
PR4233 2 1 0R0402-PAD PW R_CPU_CORE_VR_HOT# 21 40 PW R_CPU_CORE_CSW 2 43 PC4208
5,27 H_PROCHOT# PR4231 0R0402-PAD PW R_CPU_CORE_SLEW A VR_HOT# CSW2
22 SLEWA CBST2 39 PW R_CPU_CORE_CBST2 43
PW R_GFX_PW RGD 23 38 PW R_CPU_CORE_CDH2 43
2
PW R_CPU_CORE_GF-IMAX GPGOOD CDH2 N221068268
24 GF_IMAX VBAT 37 1 2
GTHERM
GCOMP
GOCP_I
CPWM3
GSKIP#
PR4216 10KR2F-2-GP
CSKIP#
GIMON
GPWM
GCSN
GGFB
GCSP
GVFB
DCBATOUT_VCC_CORE
25
26
27
28
29
30
31
32
33
34
35
36
PWR_CPU_CORE_GCOMP
9 VSS_AXG_SENSE
PWR_CPU_CORE_GTHERM
B B
PWR_CPU_CORE_GOCP-I
PWR_CPU_CORE_GIMON
9 VCC_AXG_SENSE
1 2 PW R_CPU_CORE_VREF
PW R_CPU_CORE_VREF 1 2
DY
PR4217100KR2F-L1-GP
PR4218 5K76R2F-2-GP PW R_CPU_CORE_CSKIP# 1 2 VCORE_AGND
1
PR4219 56KR2F-GP
PR4220 PR4221 PW R_GFX_GPW M 44
200KR2F-L-GP 169KR2F-1-GP 1 2
PC4209 SC33P50V2JN-3GP 1 2 PW R_CPU_CORE_VREF
PR4222 DY
100KR2F-L1-GP
2
PW R_CPU_CORE_GF-IMAX PW R_CPU_CORE_SLEW A
1 DY 2 VCORE_AGND
1
PR4223 20KR2F-L-GP
PR4224 PR4225 PW R_GFX_GSKIP# 44
30KR2F-GP 150KR2F-L-GP
1 2 PW R_CPU_CORE_VREF
PR4226 15K8R2F-GP
2
1 2
VCORE_AGND VCORE_AGND PR4227 NTC-100K-1-GP
1 DY 2
PC4211 SCD1U10V2KX-4GP
44 PW R_GFX_CORE_GSCN
PR4228
44 PW R_GFX_CORE_GSCP
1 2 1 2 VCORE_AGND
PR4229 75KR2F-GP
309KR2F-GP
1 2
A PR4230 PC4210 <Core Design> A
0R0402-PAD 1 2
SCD22U10V2KX-1GP
VCORE_AGND Wistron Corporation
1 2 Taipei Hsien 221, Taiwan, R.O.C.
VGA_CURRENT 27
PR4239
0R0402-PAD Title
TPS51640_CPU_CORE(1/3)
<Doc> SD
5 4 3 2 1
5 4 3 2 1
http://laptopblue.vn DCBATOUT_VCC_CORE
DCBATOUT DCBATOUT_VCC_CORE
1
PC4312
SC10U25V5KX-GP
PC4302
SC10U25V5KX-GP
PC4303
SC10U25V5KX-GP
PC4304
SC10U25V5KX-GP
PG4304
DY PC4315 1 2
SCD1U50V3KX-GP
2
GAP-CLOSE-PW R
PG4305
D 1 2 D
PU4301
2 GAP-CLOSE-PW R
3 PG4306
42 PW R_CPU_CORE_CDH1 1 4 1 2
10 Design current: 42.4A
9 GAP-CLOSE-PW R
42 PW R_CPU_CORE_CSW 1 PG4307
7
8 6 1 2
PW R_CPU_CORE_CBST1_1 5
VCC_CORE GAP-CLOSE-PW R
PG4308
PC4301 FDMS3600-02-RJK0215-COLAY-GP PL4301 1 2
42 PW R_CPU_CORE_CBST1 1 2 1 2 DY 1 2
PR4301 L-D36UH-1-GP GAP-CLOSE-PW R
0R3J-0-U-GP SCD1U50V3KX-GP PU4302 PG4309
2 1 2
3
2
1 4 GAP-CLOSE-PW R
1
10 PR4236 PG4301 PT4302 PT4303 PT4305
9 18KR2F-GP GAP-CLOSE-PW R-3-GP PT4306
SE100U25VM-10GP
ST330U2VDM-4-GP
ST330U2VDM-4-GP
ST330U2VDM-4-GP
7
2
8 6 PR4238
2
42 PW R_CPU_CORE_CDL1
5
1 2
FDMS3600-02-RJK0215-COLAY-GP
121KR2F-L-GP
84.03606.037
PR4237 PR4235
C Main source 2nd source 1 2 1 2 C
NTC-100K-1-GP
28KR2F-GP 1st = 69.60011.071
84.03606.037
PU4301 FDMS3606S-GP-U 1 2 PW R_CPU_CORE_CCSN1 42
PC4216 SCD027U25V2KX-GP
84.03606.037 BOM control

PU4302 FDMS3606S-GP-U PW R_CPU_CORE_CCSP1 42
DCBATOUT_VCC_CORE
84.03606.037
PU4303 FDMS3606S-GP-U
1
PC4310
SC10U25V5KX-GP
PC4306
SC10U25V5KX-GP
PC4307
SC10U25V5KX-GP
PC4305
SC10U25V5KX-GP
DY PC4316
84.03606.037 SCD1U50V3KX-GP
2
PU4304 FDMS3606S-GP-U
PU4304
2
3
42 PW R_CPU_CORE_CDH2 1 4
10
42 PW R_CPU_CORE_CSW 2 9
B B
7
8 6
PW R_CPU_CORE_CBST2_1 5
VCC_CORE
PC4308 FDMS3600-02-RJK0215-COLAY-GP PL4302
42 PW R_CPU_CORE_CBST2 1 2 1 2 84.03606.037 1 2
PR4302 L-D36UH-1-GP
0R3J-0-U-GP SCD1U50V3KX-GP PU4303
2
3
2
1 4
1
10 PG4302
9 PR4308 GAP-CLOSE-PW R-3-GP
7 18KR2F-GP
1
8 6 PT4304 PT4301
42 PW R_CPU_CORE_CDL2
5
2
ST330U2VDM-4-GP
ST330U2VDM-4-GP
PR4309
2
FDMS3600-02-RJK0215-COLAY-GP 1 2
DY
121KR2F-L-GP
PR4310
1 2 1 2
NTC-100K-1-GP
28KR2F-GP PR4303
A 1st = 69.60011.071 <Core Design> A
1
PC4314
2
SCD027U25V2KX-GP PW R_CPU_CORE_CCSN2 42 Wistron Corporation
Title
PW R_CPU_CORE_CCSP2 42 TPS51640_CPU_CORE(2/3)
<Doc> SD
5 4 3 2 1
5 4 3 2 1
Main source 2nd source
84.07608.037
PU4402 FDMS7608S-GP
84.07608.037
D PU4403 FDMS7608S-GP D
DCBATOUT DCBATOUT_VCC_GFXCORE
PG4401
1 2
GAP-CLOSE-PW R
PG4402
1 2 BOM control
GAP-CLOSE-PW R DCBATOUT_VCC_GFXCORE
PG4403
1 2
GAP-CLOSE-PW R
PG4404
1
PC4409
SC10U25V5KX-GP
PC4402
SC10U25V5KX-GP
PC4403
SC10U25V5KX-GP
PC4404
SC10U25V5KX-GP
1 2
PC4410
GAP-CLOSE-PW R SCD1U50V3KX-GP
2
PU4402
2
3
PW R_GFX_CORE_DRVH 1 4
10 Design current: 22A
9
7
C 8 6 C
PW R_GFX_CORE_SW 5
PL4401 VCC_GFXCORE
PW R_GFX_CORE_BST 1 2PW R_GFX_CBST1_1 1 2 84.07608.037 1 2
PR4401 0R3J-0-U-GP L-D36UH-1-GP
PC4401 SC1U25V3KX-1-GP PU4403
1
2
2
3 PR4410
1 4 18KR2F-GP PG4303
1
10 PT4401
GAP-CLOSE-PW R-3-GP PT4402 PT4403
9
1
PR4407
ST330U2VDM-4-GP
ST330U2VDM-4-GP
ST330U2VDM-4-GP
7
2
PW R_GFX_CORE_DRVL 8 6 1 2
5 121KR2F-L-GP
84.07608.037
PR4405
1 2 1 2
NTC-100K-1-GP
28KR2F-GP PR4409
1st = 69.60011.071
1 2 PW R_GFX_CORE_GSCN 42
B PC4408 SCD022U25V2KX-GP B
PW R_GFX_CORE_GSCP 42
PU4401
PW R_GFX_CORE_BST 1 9 5V_S5
BST GND PW R_GFX_CORE_DRVH
42 PW R_GFX_GSKIP# 2 SKIP# DRVH 8
3 7 PW R_GFX_CORE_SW
42 PW R_GFX_GPW M PWM SW
4 GND VDD 6
5 PW R_GFX_CORE_DRVL
DRVL
1
TPS51601DRBR-GP
PC4407
SC2D2U10V3KX-1GP
2
A <Core Design> A
Wistron Corporation
Title
TPS51640_CPU_CORE(3/3)
<Doc> SD
5 4 3 2 1
5 4 3 2 1
TPS51219 for 1D05V

DCBATOUT PWR_DCBATOUT_VCCP 1D05V_PWR 1D05V_VTT
1 2 PWR_VCCP_EN PG4519
46,47 RUNPWROK PR4510 PG4520
1 2
0R0402-PAD 1 2
GAP-CLOSE-PWR
1
PG4516 GAP-CLOSE-PWR-3-GP
D PC4514 DY 1 2 PG4521 D
SC1U6D3V2KX-GP 1 2
2
PR4505 PWR_DCBATOUT_VCCP GAP-CLOSE-PWR
1 2 PG4517 GAP-CLOSE-PWR-3-GP
1KR2F-3-GP 1 2 PG4522
1 2
84.00172.037 GAP-CLOSE-PWR
1
D PC4516 PC4517 PC4520 PG4518 GAP-CLOSE-PWR-3-GP
PG4523
3D3V_S0 1 2 Id=20A, Qg=9.8~15nC, 1 2
SCD1U50V3KX-GP
PWR_VCCP_MODE
SC10U25V5KX-GP
SC10U25V5KX-GP
PR4509 10KR2J-3-GP 1 2
2
5
6
7
8
Rdson=10.3~12.4 mohm GAP-CLOSE-PWR
D
D
D
D
1 2 GAP-CLOSE-PWR-3-GP
37,48 1.05VTT_PWRGD PR4502 0R0402-PAD PU4502 PG4524
SIR172DP-T1-GE3-GP
PWR_VCCP_VREF 1 2
PC4513
EC_SC_1003 3D3V_S5 PWR_VCCP_VBST 1 2 PWR_VCCP_LL_1 GAP-CLOSE-PWR-3-GP
1 2 Design Current = 11.69A
G
S
S
S
PR4508 2D2R3J-2-GP PG4525
SCD1U50V3KX-GP OCP> 17.9A 1 2
4
3
2
1
1
G S
17
16
15
14
13
1
PR4518 PR4511 PU4501 GAP-CLOSE-PWR-3-GP

PC4515 DY 8K25R2F-1-GP 100KR2F-L1-GP PG4526
MODE
GND
PGOOD
EN
BST
SCD1U10V2KX-4GP 1D05V_PWR 1 2
2
PL4501
2
1 12 PWR_VCCP_SW 1 2 GAP-CLOSE-PWR-3-GP
H_SNB_IVB#_PWRCTRL 2 VREF SW PWR_VCCP_DRVH PG4527
11
REFIN DH PWR_VCCP_DRVL COIL-D68UH-5-GP
3 10 1 2
2
GSNS DL
4 9
PR4513 VSNS V5 5V_S5 PT4502 PT4501 GAP-CLOSE-PWR-3-GP
0.68uH 7.3*6.6*3
COMP
1
1
PGND
SE330U2D5VDM-1GP
SE330U2D5VDM-1GP
PC4510 DY 0R2J-2-GP PG4528
TRIP
GND
PR4521 DCR=5~5.5mohm 1 2
1
DY PR4514
10KR2F-2-GP
Idc=15.5A, Isat=25A
2
2
SC2200P50V2KX-2GP
TPS51219RTER-GP 3D3R2F-GP D GAP-CLOSE-PWR-3-GP

5
1PWR_VCCP_TRIP 6
7
8
PG4529
2
5
6
7
8
PC4512 PU4503 1 2
D
D
D
D
SCD01U50V2KX-1GP
SIR460DP-T1-GE3-GP
2
1 2PWR_VCCP_COMP PWR_VCCP_V5FILT
84.00460.037 GAP-CLOSE-PWR-3-GP
PG4530
1
PC4518
Id=40A, Qg=16.8~25.5nC, 1 2
SC2D2U6D3V2MX-GP 77.C3371.051
Rdson=4.9~6.1 mohm
S
S
S
G
GAP-CLOSE-PWR-3-GP
2
PC4519 330uF, 2.5V, PG4531
4
3
2
1
1
SC1KP50V2KX-1GP
C DY PR4520 G S 1 2 C
64K9R2F-1-GP ESR=9mΩ, Iripple=3.726A
1
GAP-CLOSE-PWR-3-GP
2
PR4515 PG4532
2
0R0402-PAD 1 2
REFIN Vout GAP-CLOSE-PWR-3-GP

2
PG4533
1 2
H 1.05V PWR_VCCP_VSNS 1 2 VCCIO_SENSE 8
TPS51219_GSNS_M PR4519 1 2 0R0402-PAD GAP-CLOSE-PWR-3-GP
PR4522 0R0402-PAD VSSIO_SENSE 8 PG4534
1 2
L 1V Parallel
Differential Sense feedback GAP-CLOSE-PWR-3-GP
Resistor need close to controller
3D3V_S5
PG4540
1 2
GAP-CLOSE-PWR PU4504
PG4541 1D05V_PWR_M
1 2 PWR_1D05V_PVDD 10 1 1D05V_M 1D05V_VTT
PVIN LX#1 PL4502
PG4543
GAP-CLOSE-PWR 1 2 PWR_1D05V_SVIN 9 2 PWR_1D05V_PHASE 1 2 1 2 1 2
PR4524 PVIN LX#2 R4501 0R5J-5-GP
1
2D2R2J-GP SBA 8 3 IND-2D2UH-161-GP-U GAP-CLOSE-PWR Non-SBA

SVIN LX#3
GAP-CLOSE-PWR-3-GP
SBA PC4523 SBA PG4544
2
SC1U6D3V2KX-GP 7 SBA 1 2
2
NC#7
PG4547
PWR_1D05V_EN 5
1
1
PC4521 PC4522 EN PC4526 PC4527 GAP-CLOSE-PWR
6
FB
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SBA 3D3V_S5 4 SBA
1
PGOOD
DY 11
2
2
GND
SC10U6D3V3MX-GP
1
PR4525 RT8068AZQWID-GP-U
SBA SBA 1D05V_FB_GAP
100KR2F-L1-GP
1
B B
PR4526 R1 SBA
2
1
15KR2F-GP
19 MPWROK SBA PC4525
SC100P50V2JN-L-GP
19,27 PM_SLP_A# 1 2
2
2
PR4523 0R0402-PAD
PWR_1D05V_FB
1
DY PC4524
1
SC22P50V2GN-GP
2
PR4527
20KR2F-L-GP R2
SBA
Vo=0.6*(1+(R1/R2))
2
A A
<Core Design>
Wistron Corporation
Title
TPS51211_1D05V
SD
5 4 3 2 1
A B C D E
SSID = PWR.Plane.Regulator_1p5v0p75v
http://laptopblue.vn DCBATOUT
PG4601
DCBATOUT_1D5V 1D5V_PWR 1D5V_S3
1 2
GAP-CLOSE-PWR-3-GP PG4605
1 2
PG4602 GAP-CLOSE-PWR-3-GP
1 2
GAP-CLOSE-PWR-3-GP PG4606
4 PR4601 1 2 4
PWR_1D5V_VCC5 2 1 5V_S5 PG4603 GAP-CLOSE-PWR-3-GP
5D1R2F-GP 1 2
GAP-CLOSE-PWR-3-GP
1
PC4602
SC1U10V2KX-1GP PG4604
1 2
2
PR4602 DCBATOUT_1D5V GAP-CLOSE-PWR-3-GP PG4608
2
PC4601
SC1KP50V2KX-1GP
1 2
9K76R2F-1-GP
GAP-CLOSE-PWR-3-GP
2
PG4609
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U50V3KX-GP
PWR_1D5V_PVCC5 1 2 5V_S5 1 2
PC4611
PC4612
PC4613
PR4603 GAP-CLOSE-PWR-3-GP
D
2
0R0603-PAD
PU4602
5
6
7
8
84.00172.037 PG4610
D
D
D
D
SIR172DP-T1-GE3-GP
PC4607 1 2
1
PWR_1D5V_CS SC1U10V2KX-1GP GAP-CLOSE-PWR-3-GP
Id=20A, Qg=9.8~15nC,
2
3D3V_S0
Rdson=10.3~12.4 mohm PG4611
1
1 2
G
S
S
S
PR4604 GAP-CLOSE-PWR-3-GP
13
11
12
10KR2F-2-GP PU4601
4
3
2
1
DY PG4612
CS
VDDP
VDD
DCBATOUT_1D5V PC4608 Design Current = 11.69A 1 2
2
BOOT
18 PWR_1D5V_VBST 1 2PWR_1D5V_VBST_1 1 2 G S OCP>19.92A
GAP-CLOSE-PWR-3-GP
10 PR4605 2D2R3J-2-GP
45,47 RUNPWROK PGOOD SCD1U50V3KX-GP
Cyntec. 1.0uH 7.3*6.6*3 PG4613
PR4606
1 2 PWR_1D5V_TON 9 TON UGATE 17 PWR_1D5V_UGATE DCR=9~10mohm 1 2
3 1D5V_PWR GAP-CLOSE-PWR-3-GP 3
620KR3J-GP
PWR_1D5V_EN 8
PL4601 Idc=11A, Isat=22A
S5 PG4614
7 16 PWR_1D5V_PHASE 1 2 1 2
37 0D75V_EN S3 PHASE GAP-CLOSE-PWR-3-GP
SCD1U50V3KX-GP
1D5V_PWR 19 VLDOIN COIL-1UH-34-GP-U
1
PG4615
1
EC4601
PC4610 PWR_1D5V_LGATE PC4620 PC4621 PT4602
LGATE 15 D 1 2
SE330U2D5VDM-1GP
SC10U6D3V3MX-GP PR4607 GAP-CLOSE-PWR-3-GP
2
DY DY
5
6
7
8
GAP-CLOSE-PWR-3-GP
PG4626
SC4D7U6D3V3KX-GP
SCD1U10V2KX-4GP
84.00460.037 PU4603 2D2R5F-2-GP
2
2
D
D
D
D
PG4616
SIR460DP-T1-GE3-GP
2
1 VTTGND PGND 14 Id=40A, Qg=16.8~25.5nC, 1 2
GAP-CLOSE-PWR-3-GP
1
PWR_1D5V_SW_1
Rdson=4.9~6.1 mohm
+0D75V_DDR_P 5 PWR_1D5V_VDDQ PG4617
VDDQ
1
S
S
S
G
20 6 PWR_1D5V_FB DY PC4615
1 2
GAP-CLOSE-PWR-3-GP
4
3
2
1
VTT FB
1
SC330P50V2KX-3GP
2
1
PR4608 PG4618
2
VTTSNS DY
VTTREF
30K9R2F-GP PC4616 1 2
DY SC18P50V2JN-1-GP GAP-CLOSE-PWR-3-GP
R1 G S
GND
GND
2
1
PC4623 PC4618 PC4617
2
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
PG4619
RT8207MZQW-GP-U 1 2
2
21
GAP-CLOSE-PWR-3-GP
R2 1 PR4609 PG4620
1PWR_1D5V_VTTREF
30KR2F-GP 1 2
GAP-CLOSE-PWR-3-GP
2 2
2
1 2 DDR_VREF_S3
PR4610
0R0402-PAD
1 2 PWR_1D5V_EN
19,27,97 PM_SLP_S4# PR4611
PC4619 Vout=0.75*(1+R1/R2) 0R0402-PAD
1
SCD033U16V2KX-GP PC4622
SCD1U10V2KX-5GP
DY
2
2
0D75V_S0 +0D75V_DDR_P
PG4624
1 2
GAP-CLOSE-PWR-3-GP
PG4625
1 2
GAP-CLOSE-PWR-3-GP
1 <Core Design> 1
Wistron Corporation
Title
RT8207M_1D5V_0D75V
<Doc> SD
A B C D E
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p8v
D D
3D3V_S5
PG4712
RT8068A for 1D8V_S0 Design Current=1.1A
1 2
GAP-CLOSE-PW R PU4701
PG4701 1D8V_PW R
1 2 PW R_1D8V_PVDD 10 1 1D8V_S0
PVIN LX#1 PL4702 PG4713
GAP-CLOSE-PW R 1 2 PW R_1D8V_SVIN 9 2 PW R_1D8V_PHASE 1 2 1 2
PG4703 PR4703 PVIN LX#2 IND-2D2UH-46-GP-U
1
1 2 2D2R2J-GP 8 3 GAP-CLOSE-PW R
SVIN LX#3
GAP-CLOSE-PWR-3-GP
PC4703 PG4704
2
GAP-CLOSE-PW R SC1U6D3V2KX-GP 7 1 2
2
NC#7
PG4714
PC4707 PC4702 PC4709 PW R_1D8V_EN 5 EN
1
1
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SCD1U50V3KX-GP
6 PC4706 PC4708 GAP-CLOSE-PW R
FB
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
3D3V_S0 4 PG4705
1
PGOOD
DY 11 1 2
2
2
GND
1
RT8068AZQW ID-GP-U GAP-CLOSE-PW R
PR4705 1D8V_FB_GAP PG4711
100KR2J-1-GP 1 2
1
PR4704 R1 GAP-CLOSE-PW R
1
20KR2F-L-GP
PC4705
45,46 RUNPW ROK
SC100P50V2JN-3GP
19,27,36,37 PM_SLP_S3# 1 2
2
C PR4702 0R0402-PAD C
PW R_1D8V_FB
1
DY PC4704
1
SC22P50V2GN-GP
2
PR4706
10KR2F-2-GP R2
Vo=0.6*(1+(R1/R2))
2
B B
A A
<Core Design>
Wistron Corporation
Title
PWM_1D8V_RT8015B
SD
5 4 3 2 1
5 4 3 2 1
TPS51461 for VCCSA

5V_S5 3D3V_S0
D D
1
PR4809
4K7R2J-2-GP
1
1
PC4814
2
5V_S5 PW R_VCCSA_VIN
SC1U10V2KX-1GP
PR4806 1 2 D85V_PW RGD 42
2
1R2F-GP PR4808
0R0402-PAD 1 2DY
PR4812 1KR2F-3-GP
2
PG4807
1 2 PW R_VCCSA_VID1 1 2 VCCSA_SELECT1 9
PWR_VCCSA_PGOOD
1 PC4816 PR4804 0R0402-PAD
SC2D2U10V3KX-1GP
GAP-CLOSE-PW R PW R_VCCSA_VID0 1 2 VCCSA_SELECT0 9
PG4808 PR4805 0R0402-PAD
1 2
2
GAP-CLOSE-PW R PW R_VCCSA_EN 1 2
PG4809 PR4801 1.05VTT_PW RGD 37,45
1 2 0R0402-PAD
20101130 X02:
1
GAP-CLOSE-PW R PWR_VCCSA_V5DRV Follow the standard schematics.
DY
2
PU4801 PC4804
18
17
16
15
14
13
TPS51461RGER-GP SC1U6D3V2KX-GP Design Current = 4.2A
VID1
VID0
PGOOD
EN
V5DRV
V5FILT
20101130 X02: PC4805 OCP> 8.4A
C Follow the standard schematics. SCD1U50V3KX-GP C
TDK. 0.35uH 5*5*3
19 PGND
PW R_VCCSA_VIN 20 PGND BST 12 PW R_VCCSA_BST1 PR4807 2 PW R_VCCSA_BST_R 1 2 DCR=3.9mohm
21 11 0R2J-2-GP 0D85V_S0 VCCSA
PW R_VCCSA_VIN 22
PGND SW#11
10
Idc=11A, Isat=14.9A
VIN SW#10
23 VIN SW#9 9
24 8 PL4801 PG4801
VIN SW#8
1
PC4803 PC4815 PC4813 25 7 PW R_VCCSA_SW 1 2 1 2

GND SW#7
PC4809
PC4807
PC4810
PC4811
PC4801
PC4812
IND-D35UH-GP
COMP
MODE
1
SLEW
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
VOUT
SCD1U50V3KX-GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SCD1U50V3KX-GP
VREF
68.R3510.101 GAP-CLOSE-PW R
GND
2
PR4803 PG4802
1
74.51461.043 DY 2D2R5F-2-GP 1 2
DY DY
1
2
3
4
5
6
GAP-CLOSE-PW R
1PWR_VCCSA_SNUB
2
2
PG4803
PW R_VCCSA_VOUT 1 PR4811 2
PWR_VCCSA_VREF
PWR_VCCSA_COMP
0D85V_S0 1 2
100R2F-L1-GP-U
PW R_VCCSA_SLEW 20101130 X02: GAP-CLOSE-PW R
Follow the standard schematics. PG4804
1 2 VCCSA_SENSE 9 1 2
PR4810
0R0402-PAD GAP-CLOSE-PW R
2
PC4818 PG4805
PC4806 DY SC560P50V-GP 1 2
1
SCD01U50V2KX-1GP
1
2
PR4802 GAP-CLOSE-PW R
4K99R2F-L-GP PG4806
1 2
2
B GAP-CLOSE-PW R B
PWR_VCCSA_COMP_1
VID0 VID1 VCCSA
L L 0.9V
L H 0.8V
H L 0.725V
1
PC4817
H H 0.675V SC3300P50V2KX-1GP
2
2
PC4802
SCD22U10V2KX-1GP
1
A <Core Design> A
Wistron Corporation
Title
VCCSA_TPS51461
<Doc> SD
5 4 3 2 1
SSID = VIDEO LVDS connector
LCD / Inverter Connector
DCBATOUT_LCD
3D3V_S0
1.2A
SC1U25V3KX-1-GP
2
1
SCD1U50V3KX-GP
RN4902
2
SRN2K2J-1-GP
C4902 C4906 C4916
SCD01U50V2KX-L-GP
1
3
4
LVDS_DDC_DATA_R
LVDS_DDC_CLK_R
LVDS1
41
1
2
3
CAMERA POWER L_BKLT_CTRL R4928
BLON_OUT_C
LCD_BRIGHTNESS
4
5
1 2 33R2J-2-GP 6
2 1 LCD_PRESENCE# 7
18 LCD_DET#
3D3V_S0_CAMERA 0R0402-PAD R4926 8
3D3V_S0 2 1 USB_CAMERA# 9
3D3V_S0_CAMERA 18 USB_PN12
0R0402-PAD 2 1 R4925 USB_CAMERA 10
18 USB_PP12
U4902 0R0402-PAD R4924 11
Pin11 is CAMERA GND 12
Layout 40 mil 3D3V_S0_CAMERA_IN
1 5 1 2 13
OUT IN R4922 0R0805-PAD
2 14
GND Pin15 is CAMERA shielding GND
3 4 CAMERA_EN 27 15
OC# EN/EN# LID_CLOSE#
27,70 LID_CLOSE# 16
1
C4912 C4911 3D3V_AUX_S5 17

SC4D7U6D3V3KX-GP SY6288CAAC-GP SC4D7U6D3V3KX-GP 18
74.06288.07F 19
2
Pin20 is Hall Sensor GND 20 AFTP4901 1 LID_CLOSE#

21
22
17 LVDSA_CLK 23
17 LVDSA_CLK# 24
25
17 LVDSA_DATA2 26
17 LVDSA_DATA2# 27
28
SILERGY 74.06288.07F SY6288CAAC High Active 17 LVDSA_DATA1 29
30
17 LVDSA_DATA1#
DIODES 74.02171.07F AP2171WG-7 High Active 31
32
17 LVDSA_DATA0
UPI 74.07534.A7F OBS High Active 17 LVDSA_DATA0# 33
34
3D3V_S0 17 LVDS_DDC_DATA_R
GMT 74.05240.A7F OBS High Active 35
LCD POWER LCDVDD 1
F4903
2
17 LVDS_DDC_CLK_R
FUSE-D5A32V-14-GP
3D3V_DDC_S0
36
37
38
1 2 LCDVDD_R 39
F4902 FUSE-3A32V-12-GP 40
42
1
DCBATOUT_LCD DCBATOUT
C4922 C4921 JAE-CON40-4-GP
SC1U6D3V2KX-GP SCD1U10V2KX-5GP 20.K0568.040
2
2 1
C4905 C4904
F4901
SCD1U50V3KX-GP
SC1KP50V2KX-1GP
POLYSW-1D1A24V-GP-U
1
2nd = 69.50007.A41
2
Main:69.50007.A41
LCDVDD 3D3V_S0 Second:69.50007.A31
Layout 40 mil U4901
1 5
C4908 OUT IN C4907
2
3
GND
OC# EN/EN#
4 LVDS_VDD_EN LCDVDD Discharge LCDVDD
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1
SY6288CAAC-GP C4909
1
R4903
2
SCD1U16V2KX-3GP
3D3V_AUX_S5 R4930 1 2 BLON_OUT_C

27 BLON_OUT
1
100R2J-2-GP
1KR2J-1-GP
DY R4911 C4910
1
1
74.05285.07F OBS Q4901
2
1
100KR2J-1-GP
SC100P50V2JN-3GP
check 2nd source=74.05285.07F R4929 4 3 LCDVDD_DISCHARGE
100KR2J-1-GP
5 2 LVDS_VDD_EN
2
2
2
LVDS_VDD_EN# 6 1
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
For EMI request

Close to LVDS connector
Panel BL brightness/Power En/BL En
LCD_BRIGHTNESS
LVDSA_CLK# 1 2
17 L_BKLT_EN PANEL_BLEN 27
LVDSA_CLK R4905 0R0402-PAD L_BKLT_CTRL
17 L_BKLT_CTRL LVDS_VDD_EN
EC4904 EC4905 EC4902 17 LVDS_VDD_EN
1
1
SC33P50V2JN-3GP
DY DY
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
DY C4901
SC100P50V2JN-3GP
2
<Core Design>
Wistron Corporation
Title
LCD Connector
A2
LA480 SD
5 4 3 2 1
CRT connector
5V_CRT_S0
9
CRT1
VCC_CRT NC#4
NC#11
4
11
http://laptopblue.vn CRT DDCDATA & DDCCLK level shift
C5013 CRT_DDCDATA_CON 12
Pull High 5V Design on CRT Board
1
SCD01U50V2KX-1GP CRT_DDCCLK_CON DDCDATA_ID1

15
DDCCLK_ID3 AFTP5009
5 1
CRT_R GND
1 6
2
CRT_G CRT_RED GND

2 7
CRT_B CRT_GREEN GND 5V_CRT_S0 5V_S0
3 8
CRT_BLUE GND 3D3V_S0
10
CRT_VSYNC_CON GND
14
VSYNC GND
16 500mA
CRT_HSYNC_CON 13 17 3D3V_S0_DDC 1 2
HSYNC GND R5003 10KR2J-3-GP
1
D D
D-SUB-15-136-GP F5001 D5001
20.20961.015 FUSE-1D1A6V-4GP-U CH551H-30PT-GP
69.50007.691 83.R5003.C8F
2nd = 69.50007.771 2ND = 83.5R003.08F
2
3D3V_S0 3rd = 83.R5003.G8F
5V_CRT_DDC
2
1
3
4
AFTP5001 1 5V_CRT_S0 RN5002
AFTP5002 1 CRT_DDCDATA_CON SRN2K2J-1-GP RN5003
AFTP5003 1 CRT_DDCCLK_CON 3D3V_S0_DDC SRN10KJ-5-GP
AFTP5004 1 CRT_R
AFTP5005 1 CRT_G
Q5001
3
4
AFTP5006 1 CRT_B
2
1
AFTP5007 1 CRT_VSYNC_CON 4 3 CRT_DDCDATA_CON
17 CRT_DDC_DATA
AFTP5008 1 CRT_HSYNC_CON
5 2
6 1
2N7002KDW-GP
17 CRT_DDC_CLK
84.DM601.03F
2nd = 84.2N702.A3F
CRT_DDCCLK_CON
CRT Hsync & Vsync level shift

5V_S0
1
C5007
C 2 SCD1U10V2KX-5GP C
U5001
1 2 CRT_VSYNC 17
G1# A1
7 5 CRT_HSYNC 17
G2# A2
6 CRT_VSYNC1_2 R5001 1 2 10R2J-2-GP CRT_VSYNC_CON 5V_CRT_S0
Y1 CRT_HSYNC1_2 R5002 CRT_HSYNC_CON
4 3 1 2 10R2J-2-GP
GND Y2 5V_CRT_S0
8
VCC
D5002
TC7WT125FU-GP 2 D5006
73.7W125.007 2
CRT RGB 2nd = 73.2G125.A0B DY 3 CRT_HSYNC_CON
DY 3 CRT_RED
1
1
CH221GP-GP-U
CH221GP-GP-U
L5001 D5003
1 2 CRT_R 2 D5007
17 CRT_RED FCM1608CF-220T05-GP 2
68.00245.011 DY 3 CRT_VSYNC_CON
2nd = 68.00230.021 DY 3 CRT_GREEN
1
1
L5002 CH221GP-GP-U
1 2 CRT_G CH221GP-GP-U
17 CRT_GREEN FCM1608CF-220T05-GP D5004
68.00245.011 2 D5008
2nd = 68.00230.021 2
DY 3 CRT_DDCDATA_CON
DY 3 CRT_BLUE
1
L5003 1
1 2 CRT_B CH221GP-GP-U
17 CRT_BLUE C5001 C5002 C5003 FCM1608CF-220T05-GP C5004 C5005 C5006 CH221GP-GP-U
68.00245.011 D5005
8
7
6
5
SC8P250V2CC-GP
SC8P250V2CC-GP
SC8P250V2CC-GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
B 2nd = 68.00230.021 2 B
1
RN5001 DY CRT_DDCCLK_CON
DY DY DY 3
2
SRN150F-1-GP 1
1
2
3
4
CH221GP-GP-U
CRT_DDCDATA_CON
CRT_HSYNC_CON
CRT_VSYNC_CON
CRT_DDCCLK_CON
C5008 C5009 C5010 C5011
SC100P50V2JN-3GP
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
SC100P50V2JN-3GP
1
DY DY DY DY
2
A A
<Core Design>
Wistron Corporation
Title
CRT Connector
A2
LA480 SD
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
HDMI Passive Level Shifter
Close to HDMI Connector HDMI CONNECTOR
HDMI1
D C5103 1 2 SCD1U10V2KX-5GP HDMI_CLK_R_C1# 20 D
17 HDMI_CLK_R# C5104 SCD1U10V2KX-5GP HDMI_CLK_R_C1 CHASSIS
1 2
17 HDMI_CLK_R HDMI_DATA2_R_C
1
C5105 1 2 SCD1U10V2KX-5GP HDMI_DATA0_R_C1#
17 HDMI_DATA0_R# C5106 SCD1U10V2KX-5GP HDMI_DATA0_R_C1
1 2 2
17 HDMI_DATA0_R HDMI_DATA2_R_C#
3
C5110 1 2 SCD1U10V2KX-5GP HDMI_DATA1_R_C1# 4 HDMI_DATA1_R_C
1 2 5
6
C5108 1 2 SCD1U10V2KX-5GP HDMI_DATA2_R_C1# 7 HDMI_DATA0_R_C
1 2 8
9
10 HDMI_CLK_R_C
11
12 HDMI_CLK_R_C# 83.R5003.C8F
Close to HDMI Connector 13 HDMI_PIN13
3rd = 83.R5003.G8F
8
7
6
5
5
6
7
8
14
RN5101 RN5102 15 DDC_CLK_HDMI 2ND = 83.5R003.08F
SRN680-U-GP SRN680-U-GP 16 DDC_DATA_HDMI CH551H-30PT-GP
17 F5101
18 5V_HDMI 2 1 5V_HDMI_S0 2 1 5V_S0
19 HPD_HDMI_CON C5102
1
2
3
4
4
3
2
1
FUSE-1D1A6V-4GP-U
69.50007.691 D5101
SCD1U10V2KX-5GP
CHASSIS 21 1 AFTP5121
2nd = 69.50007.771
1
HDMI_PLL_GND SKT-HDMI21-1-GP-U
22.10296.571 1 DY 0R2J-2-GP
2
2
R5113
D Q5103
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.J31
3D3V_S0
G
S
1
C R5104 C
100KR2J-1-GP
DY
2
ESD Request
EMI's request HDMI_PIN13
R5114 R5118 HPD_HDMI_CON

0R2J-2-GP 0R2J-2-GP
HDMI_CLK_R_C1# 1 2 HDMI_CLK_R_C# HDMI_DATA1_R_C1# 1 2 HDMI_DATA1_R_C# DDC_DATA_HDMI
DDC_CLK_HDMI
1
HDMI_DATA2_R_C 1 2 HDMI_DATA2_R_C#
R5107 DY 180R2F-1-GP D5105 D5106 D5107 D5108
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
PESD5V0U1BL-GP-U1
R5108 DY 180R2F-1-GP
2
R5109 DY 180R2F-1-GP
HDMI_CLK_R_C 1 2 HDMI_CLK_R_C#
R5110 DY 180R2F-1-GP
R5115 R5119
0R2J-2-GP 0R2J-2-GP
HDMI_CLK_R_C1 1 2 HDMI_CLK_R_C HDMI_DATA1_R_C1 1 2 HDMI_DATA1_R_C
R5116 R5120
0R2J-2-GP 0R2J-2-GP
B HDMI_DATA0_R_C1# 1 2 HDMI_DATA0_R_C# HDMI_DATA2_R_C1# 1 2 HDMI_DATA2_R_C# B
HDMI DDC Passive Level Shifter

D5102
BAW56-5-GP
83.00056.Q11
R5117 R5121 2nd = 83.00056.K11
0R2J-2-GP 0R2J-2-GP
HDMI_DATA0_R_C1 1 2 HDMI_DATA0_R_C HDMI_DATA2_R_C1 1 2 HDMI_DATA2_R_C 1
3 5V_S0
2
5V_HDMI_S0_1
5V_HDMI_S0_2
3D3V_S0
1
R5101
1MR2F-GP DG: 2.2K PU
Q5102
2
4
3
G 3D3V_S0
RN5103
D HPD_HDMI_CON SRN2K2J-1-GP
A A
17 HDMI_PCH_DET S
1
Q5104
1
2
2N7002K-2-GP R5106
84.2N702.J31 100KR2J-1-GP 1 6 DDC_DATA_HDMI
17 PCH_HDMI_DATA
2ND = 84.2N702.031
2 5
2
<Core Design>
3 4
DG: 20K PD
2N7002KDW-GP
Wistron Corporation
DDC_CLK_HDMI 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
84.2N702.A3F Taipei Hsien 221, Taiwan, R.O.C.
17 PCH_HDMI_CLK 2nd = 84.DM601.03F
Title
HDMI Level Shifter/Connector

A2
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Title
eDP
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Title
S-VIDEO
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Title
Reserved
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
SSID = User.Interface
D
ITP Connector D
H_CPURST# use pull-up Resistor close

ITP connector 500 mil ( max ),
others place near CPU side.
C C
CPU ITP Connector

TCK(PIN 5)
TCK(PIN AC5)
FBO(PIN 11)
B B
<Core Design>
A
Title
ITP
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
SATA HDD Connector
HDD1
24
NP2
22
D 21 SATA_TXP1 SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
2
2
1 C5614
1 C5613
SATA_TXP1_C
SATA_TXN1_C
21
20
D
21 SATA_TXN1
19
21 SATA_RXN1 SCD01U50V2KX-1GP 1 2 C5616 SATA_RXN1_C 18
21 SATA_RXP1 SCD01U50V2KX-1GP 1 2 C5615 SATA_RXP1_C 17
16
3D3V_S0 1 2 3D3V_S0_HDD 15
R5603 C5604 C5601 14
0R0805-PAD 13
SC10U6D3V5KX-1GP
SCD1U10V2KX-5GP
12
1
27 HDD_DET# 11
DY DY 5V_S0_HDD
10
5V_S0 1 2 9
2
R5606 C5605 C5606 8
0R0805-PAD 7
SC10U10V5KX-2GP
SCD1U10V2KX-5GP
6
1
FFS_INT2 5
4 TP5607 1 FFS_INT2
3
2
2
1
NP1
23
SKT-SATA22P-27-GP-U1
62.10065.471
C C
ODD Connector SATA_ODD_DA#_C

SATA_ODD_PRSNT# 22
2 DY 1
R5602
SATA_ODD_DA# 18,27
SATA_RX- and SATA_RX+ Trace 0R2J-2-GP

Length match within 20 mil SCD01U50V2KX-1GP 2 1 C5611 SATA_TXN4_C
21 SATA_TXN4
21 SATA_TXP4 SCD01U50V2KX-1GP 2 1 C5612 SATA_TXP4_C
1
Mars:
R5604
Exchange ODD and ESATA differential pair each other. SCD01U50V2KX-1GP
21 SATA_RXN4 2 1 C5607 SATA_RXN4_C 10KR2J-3-GP
21 SATA_RXP4 SCD01U50V2KX-1GP 2 1 C5608 SATA_RXP4_C DY
2
SATA Zero Power ODD
74.02069.079 TI TPS2069DGNR MSOP 8P Current limit
ODD_PW R_5V 74.07534.D79 UPI UP7534PRA8-15 MSOP 8P
ODD1 74.00547.C79 GMT G547F1P81U MSOP 8P (OBS)
Active High
B P2 P4 SATA_ODD_DA#_C
74.07534.A79 UPI UP7534ARA8-15 MSOP8P typ =>2A ODD_PW R_5V B
+5V MD SATA_ODD_PRSNT# U5601
P3 +5V DP P1 22 SATA_ODD_PW RGT
TPS2064DGNR-GP-U
GND S1
SATA_TXN4_C S3 S4 5
SATA_TXP4_C A- GND 5V_S0 OC2# ODD_PW R_5V
S2 A+ GND S7 4 EN2# OUT2 6
GND P5
When the drive is powered on, the FET to the MD/DA pin drive is OFF. 3 EN1# OUT1 7 100 mil
P6 1 2 ODD_PW R_5V_IN 2 8
SATA_RXN4_C GND R5607 IN OC1#
S5 B- GND 14 When the drive is powered off, the FET to the MD/DA pin is ON 1 GND GND 9
1
SATA_RXP4_C S6 15 C5609 0R0805-PAD C5610
B+ GND
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
NP1
2
NP1
NP2 NP2
5V_S0
SKT-SATA7P-6P-59-GP-U
22.10300.B91
1
R5605
100KR2J-1-GP
TI 74.02069.079 TPS2069DGNR High Active
2
SATA_ODD_DA#_C
DIODES AP2171WG-7 High Active
ODD_PWRGT#
UPI 74.07534.A7F OBS High Active

3D3V_S0
A SATA_ODD_PW RGT 1 2
<Core Design>
A
6
SATA_ODD_DA# R5608 1 2 10KR2J-3-GP

R5609 DY 10KR2J-3-GP Q5601
2N7002KDW -GP Wistron Corporation
84.2N702.A3F 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2nd = 84.DM601.03F Taipei Hsien 221, Taiwan, R.O.C.
1
SUPPORT ZERO SATA ODD Title
HDD/ODD
SATA_ODD_PW RGT SATA_ODD_DA# A3 SD
LA480
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Title
E-SATA+USB
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
Int. Digital MIC for V series http://laptopblue.vn 3D3V_S0
MIC1
6
4
AUD_DMIC_CLK_L 3
V Series-MIC AUD_DMIC_DATA_L 2
L5801 1
SBY100505T-601Y-N-GP V Series-MIC
1 2 AUD_DMIC_CLK_L 5
29 AUD_DMIC_CLK
1
1 2 AUD_DMIC_DATA_L
29 AUD_DMIC_DATA L5802 C5804 ACES-CON4-17-GP-U1
1
D SBY100505T-601Y-N-GP 20.F1621.004 D
2
SC1KP50V2KX-1GP
V Series-MIC
C5805 C5806
DY DY ME change P/N at SIT
Old 20.F1639.004
MLVG0402220NV09BP-GP
MLVG0402220NV09BP-GP
New 20.F1621.004
2
CHECK PIN DEFINE
AFTP5809 1 AUD_DMIC_CLK_L
AFTP5810 1 AUD_DMIC_DATA_L
AFTP5805 1 3D3V_S0
AFTP5806 1 GND
INTERNAL STEREO SPEAKERS

Int. Mono Analog MIC for B series 29 AUD_SPK_L+
29 AUD_MIC2_VREFO 1 2 29 AUD_SPK_L- SPK1

R5811 2K2R2J-2-GP 3
1
B Series-MIC EC5801 EC5802 1
SC47P50V2JN-3GP SC47P50V2JN-3GP
1 2 AUD_DMIC_CLK_L 2
2
29 AUD_MIC2 R5808 1KR2J-1-GP AFTP5807 1 4
1
B Series-MIC 1 2 AUD_DMIC_DATA_L
D5801 R5812 0R2J-2-GP ACES-CON2-17-GP
1
DY B Series-MIC 20.F1621.002
MLVG0402220NV05BP-GP-U
C5807
2
SC100P50V2JN-3GP Only needed if speaker
2
1 2 B Series-MIC connector is physically far from SPK2
R5813 0R2J-2-GP 3
DY audio codec. When in doubt, it's Place these EMI components 1
C always a good idea to have close to speaker connector. C
AU_GND AU_GND population option. 2
AFTP5808 1 4
AU_GND
29 AUD_SPK_R+
ACES-CON2-17-GP
29 AUD_SPK_R- 20.F1621.002
1
EC5803 EC5804
SC47P50V2JN-3GP SC47P50V2JN-3GP CHECK PIN DEFINE, RIGHT? LEFT?
2
AFTP5801 1 AUD_SPK_L+
AFTP5802 1 AUD_SPK_L- Table 58.1 - Bi-direction ESD multi-source
AFTP5803 1 AUD_SPK_R+
AFTP5804 1 AUD_SPK_R-
Supplier Description Lenovo P/N Wistron P/N
ROHM RSB5.6SMT2R N/A 83.RSB56.BAF
ON SEMI ESD5B5.0ST1G N/A 83.ESD5B.0AF
NXP PESD5V0S1BB N/A 83.0005V.0AF
B B
A A
<Core Design>
Wistron Corporation
Title
Audio Jack
A2
LA480 SD
5 4 3 2 1
5 4 3 2 1
FOR CO-LAY
TVS
GIGA Lan Transformer 83.00005.BAE
DIODE ARR SRV05-4.TCT SOT-23-6
XF5901
1CT:1CT RJ45_7
D 31 MDI3+ 2 23 D
XRF_TDC 1 24 MCT2
83.09904.AAE
1 C5903
31 MDI3- 3 22 RJ45_8
SCD01U50V2KX-1GP
DIODE ESD AZC099-04S SOT23-6L
2
1CT:1CT RJ45_4
31 MDI2+ 5 20
4 21 MCT1
C5901 value modify to 0.01uF ~
0.4uF capacitor 31 MDI2- 6 19 RJ45_5
Swap for V480
DY
1CT:1CT D5901
8 17 RJ45_3
31 MDI1+
RJ45_6 4 SRV05-4-2-GP 3 RJ45_2
7 18 MCT4
9 16 RJ45_6
31 MDI1-
1CT:1CT 5 2
11 14 RJ45_1
31 MDI0+
10 15 MCT3 1 RJ45_1
RJ45_3 6
12 13 RJ45_2
31 MDI0-
XFORM-24P-19-GP
C 68.IH601.301 DY C
2ND = 68.89240.30D D5902
RJ45_4 4 SRV05-4-2-GP 3 RJ45_7
1st
68.IH601.301(Taimag) for 1000
68.HH035.301(Taimag) for 10/100
2nd 5 2
68.2413S.30A(Lankom) for 1000
68.H6441.301(Lankom) for 10/100
1 RJ45_8
RJ45_5 6
MCT2
MCT1
LAN Connector MCT4
MCT3
8
7
6
5
RN5902
SRN75J-1-GP
3D3V_LAN_S5
1
2
3
4
RJ45
B CHASSIS CHASSIS
B
16 15
MCT_R
10 YELLOW
31 LAN_ACT_LED# 1 2 LAN_ACT_LED#_1 9
R5903 330R2J-3-GP RJ45_8 8
RJ45_7 7
RJ45_6 6
2
RJ45_5 5 C5904
RJ45_4 4 SC1KP2KV6KX-GP
RJ45_3 3
1
RJ45_2 2
RJ45_1 1
31 SPEED_100# 1 2 SPEED_100#_1 11 GREEN
R5904 330R2J-3-GP 12
1
14 13
EC5901 CHASSIS CHASSIS
SCD1U50V3KX-GP RJ45-8P-91-GP
2
22.10277.U11
close to RJ45
A <Core Design> A
Wistron Corporation
Title
RJ45 / Transformer
A3
LA480 SD
5 4 3 2 1
5 4 3 2 1
SSID = Flash.ROM http://laptopblue.vn

SPI FLASH ROM (8M byte) for PCH
D D
3D3V_SPI 3D3V_SPI
3D3V_SPI 3D3V_S5
1 2
2
1
C6001 C6002 R6010
1
RN6001 0R0402-PAD
SC10U6D3V5KX-1GP
SCD1U10V2KX-5GP
R6004 SRN4K7J-8-GP
1
4K7R2J-2-GP
DY the same page 23 VCCSPI power
2
3
4
2
3D3V_SPI
U6001
21,27 SPI_CS0#_R 1 S# GND 9

21,27 SPI_SO_R 1 2 SPI_SO 2 8
R6001 SPI_W P# DQ1 VCC SPI_HOLD_0#
3 W#/VPP HOLD# 7
33R2J-2-GP 4 6 SPI_CLK_R_1 1 2 SPI_CLK_R 21,27
VSS C SPI_SI_R_1 R6006 1
DQ0 5 233R2J-2-GP SPI_SI_R 21,27
1
R6007 33R2J-2-GP
EC6002 DY
1
SC4D7P50V2CN-1GP LILY-BIOS-COLAY-GP-U
2
C EC6003 DY DY EC6001 C
SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP
2
3D3V_SPI
4MB
Marcronix MX25L3206EM2I-12G 72.25320.C01
1
SO8 Winbond W25Q032BVSSIG 72.25Q32.A01

R6005
4K7R2J-2-GP SBA Numonyx N25Q032A13ESE40 72.25032.H01
8MB
2
U6002 3D3V_SPI
21 SPI_CS1#_R 1 S# GND 9 Marcronix MX25L6406EM2I-12G 72.25640.D01

21,27 SPI_SO_R 1 2 SPI_SO1 2 8 SBA
R6003 SPI_W P# DQ1 VCC SPI_HOLD_0#
3 W#/VPP HOLD# 7 SO8 Winbond W25Q064CVSSIG 72.25Q64.B01
33R2J-2-GP 4 6 SPI_CLK_R_2 1 2 SPI_CLK_R 21,27
VSS C SPI_SI_R_2 R6008 1
SBA DQ0 5 233R2J-2-GP SPI_SI_R 21,27 Numonyx N25Q064A13ESE40 72.25Q64.D01
1
R6009 33R2J-2-GP
EC6004 DY SBA
1
16MB
1
SC4D7P50V2CN-1GP LILY-BIOS-COLAY-GP-U
2
SBA EC6005 DY DY EC6006

SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP Marcronix MX25L12836EZNI-10G 72.25128.X01
2
2
B B
WSON MX25L12835EZNI-10G 72.25128.Y01
Winbond W25Q128BVEIG 72.25128.I01

Numonyx N25Q128A13EF840 72.25128.B03
SSID = RBATT
R6012
0R2J-2-GP
1 DY 2
RTC_AUX_S5 3D3V_AUX_S5 +RTC_VCC Q6002
Q6001 RTC_PW R G
2
D RTC_DET# 20
2
3 RTC14
3 R6011 S
1 RTC_PW R 1 2 +RTC_VCC 1 10MR2J-L-GP
2
R6002 1KR2J-1-GP 2N7002K-2-GP

C6003 CH715FPT-GP 2
1
SC1U6D3V2KX-GP 4
1
83.R0304.B81
A 2nd = 83.00040.E81 Width=20mils <Core Design> A
ACES-CON2-11-GP
20.F0772.002
Wistron Corporation
AFTP6002 1 +RTC_VCC Title

AFTP6001 GND
1
Flash/RTC
A3
LA480 SD
5 4 3 2 1
5 4 3 2 1
USB Board CONN.
D D
Support 2A
5V_S5 5V_USB4_S3
U6102
at least 80 mil at least 80 mil
5 IN OUT 1
GND 2
27,62,82 USB_PW R_EN_R 4 EN/EN# OC# 3 USB_OC#2_3 18
1
C6103
DY
SCD1U10V2KX-5GP
SY6288CAAC-GP
2
74.06288.07F
Place U6102 close to USBCN1
C C
B B
A <Core Design> A
Wistron Corporation
Title
USB Connector
A3 SD
LA480
5 4 3 2 1
5 4 3 2 1
USB3.0 Port1
2A http://laptopblue.vn
USB3.0 Port2 USB3.0 Port3
USB3.0 Port4
5V_S5 U6201
1 9
GND GND
2 8 USB_OC#0_1 18 at least 80 mil
C6205 IN OC1#
3 7 5V_USB1_S3
27,61,82 USB_PWR_EN_R EN1# OUT1
4 6 5V_USB2_S3
1
EN2# OUT2
SCD1U10V2KX-5GP
5 USB_OC#4_5 18
OC2#
2
TPS2064DGNR-GP-U
D D
5V_USB1_S3
5V_USB2_S3
USB1 USB2
1 5 USB3_RX1_N_R 1 5 USB3_RX3_N_R
VBUS STDA_SSRX- USB3_RX1_P_R VBUS STDA_SSRX- USB3_RX3_P_R
6 6
STDA_SSRX+ STDA_SSRX+
USB_PN1_R 2 8 USB3_TX1_N_R USB_PN3_R 2 8 USB3_TX3_N_R D6204
1
1
USB_PP1_R D- STDA_SSTX- USB3_TX1_P_R USB_PP3_R D- STDA_SSTX- USB3_TX3_P_R USB3_RX1_N_R USB3_RX1_N_R
3 9 3 9 1 8
TC6201 D+ STDA_SSTX+ TC6202 D+ STDA_SSTX+ USB3_RX1_P_R L1#1L1#8 USB3_RX1_P_R
2 7
L2#2L2#7
SE220U6D3VM-30-GP
SE220U6D3VM-30-GP
10 10 G1 G2
2
2
10 10 USB3_TX1_N_R GNDGND USB3_TX1_N_R
11 11 3 6
11 11 USB3_TX1_P_R L3#3L3#6 USB3_TX1_P_R
12 4 12 4 4 5
12 GND 12 GND L4#4L4#5
13 7 13 7
13 GND_DRAIN 13 GND_DRAIN
RCLAMP0524P-GP
SKT-USB13-77-GP TC6202 place near SKT-USB13-77-GP
22.10339.K61 the USB2 connector 22.10339.K61 1st = 83.3V3U4.0A0
TC6201 place near
the USB1 connector
R6201 R6207
D6201
18 USB3_TX1_P 1 2 USB3_TX1_P_C 1 2 USB3_TX1_P_R 18 USB3_TX3_P 1 2 USB3_TX3_P_C 1 2 USB3_TX3_P_R USB3_RX3_N_R 1 8 USB3_RX3_N_R
C6206 SCD1U16V2KX-3GP 0R0402-PAD C6209 SCD1U16V2KX-3GP 0R0402-PAD USB3_RX3_P_R L1#1L1#8 USB3_RX3_P_R
2 7
L2#2L2#7
G1 G2
USB3_TX3_N_R GNDGND USB3_TX3_N_R
3 6
USB3_TX3_P_R L3#3L3#6 USB3_TX3_P_R
4 5
L4#4L4#5
RCLAMP0524P-GP
1st = 83.3V3U4.0A0
C C
R6202 R6208
18 USB3_TX1_N 1 2 USB3_TX1_N_C 1 2 USB3_TX1_N_R

18 USB3_TX3_N 1 2 USB3_TX3_N_C 1 2 USB3_TX3_N_R
C6208 SCD1U16V2KX-3GP 0R0402-PAD C6210 SCD1U16V2KX-3GP 0R0402-PAD
R6203 R6210
USB3_RX1_P 1 2 USB3_RX1_P_R 1 2 USB3_RX3_P_R
18 USB3_RX1_P 18 USB3_RX3_P
0R0402-PAD 0R0402-PAD
R6204 R6209
USB3_RX1_N 1 2 USB3_RX1_N_R 1 2 USB3_RX3_N_R
18 USB3_RX1_N 18 USB3_RX3_N
0R0402-PAD 0R0402-PAD
5V_USB1_S3
5V_USB2_S3
B 1 4 B
1 4
D6202
PRTR5V0U2X-GP D6203
DY PRTR5V0U2X-GP
DY
USB_PP1_R 2 3 USB_PN1_R
USB_PP3_R 2 3 USB_PN3_R
R6205
1 2 USB_PN1_R
18 USB_PN1 R6211
0R0402-PAD
18 USB_PN3 1 2 USB_PN3_R
0R0402-PAD
R6206
1 2 USB_PP1_R
18 USB_PP1 R6212
0R0402-PAD
1 2 USB_PP3_R
18 USB_PP3
0R0402-PAD
A A
<Core Design>
Wistron Corporation
Title
USB 3.0 Port*2

A2
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
Bluetooth conn.
3D3V_BT_S0
3D3V_S0
U6301
1 5 3D3V_BT_IN 1 2
OUT IN R6301
2 GND
1
EC6302 3 4 0R0805-PAD
OC# EN/EN#
1
SCD1U16V2KX-3GP BLUETOOTH_EN 27,65 C6302
DY SC4D7U6D3V3KX-GP
2
SY6288CAAC-GP DY
2
74.06288.07F
C DY C
SILERGY 74.06288.07F SY6288CAAC High Active

DIODES 74.02171.07F AP2171WG-7 High Active
UPI 74.07534.A7F OBS High Active
BT Module pin definition is same as LA470
GMT 74.05240.A7F OBS High Active
BT1 AFTP6302 1 3D3V_BT_S0

B 7 AFTP6303 1 USB_PP4 B
AFTP6304 1 USB_PN4
1 3D3V_BT_S0 1 BT_LED
AFTP6305 1 GND
2 AFTP6306
3 USB_PN4 18
4 USB_PP4 18
5 BT_LED
6
ACES-CON6-42-GP
20.F1705.006
DY
<Core Design>
A
Title
Bluetooth
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
Finger Printer Connector
D D
3D3V_S0
1 2 3V_FP_S0
R6403
1
0R0805-PAD C6401 FPCN1
SCD1U10V2KX-4GP 7
2
C 1 C
2
3
18 USB_PP10 1 2 Biometric_USBPP 4
18 USB_PN10 R6401 1 2 0R0402-PAD Biometric_USBPN 5
R6402 0R0402-PAD 1 6
AFTP6401
8
ACES-CON6-13-GP
20.K0320.006
AFTP6402 1 3V_FP_S0
AFTP6403 1 Biometric_USBPN
AFTP6404 1 Biometric_USBPP
B B
<Core Design>
A
Title
Finger Printer Connector
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
SSID = Wireless http://laptopblue.vn

Mini Card Connector(802.11a/b/g/n)
D D
+1D5V_MINI_W LAN 1D5V_S0 +3V_MINI_W LAN 3D3V_S0
3D3V_S5 Place near MINI Card CONN
1
1
R6512
R6521 0R0805-PAD 0R5J-5-GP
R6516 +3V_MINI_W LAN
10KR2J-3-GP AOAC-DY
2
+1D5V_MINI_W LAN
1
W LAN1 C6502 C6503 C6504
53 SCD1U16V2KX-3GP SC10U6D3V5KX-1GP SCD1U16V2KX-3GP
27 PCIE_W LAN_W AKE# 1 2 NP1
2
19,31,66 PCIE_W AKE# R6520 1 2 0R2J-2-GP PCIE_W AKE#_1 1 2 +3V_MINI_W LAN
R6511 DY 0R2J-2-GP
3 4
27,63 BLUETOOTH_EN 1 2 BT_ENABLE 5 6
20 PCIE_CLK_W LAN_REQ# R6513 0R2J-2-GP 7 8 LPC_AD0_C
9 10 LPC_AD1_C
20 CLK_PCIE_W LAN# 11 12 LPC_AD2_C
20 CLK_PCIE_W LAN 13 14 LPC_AD3_C
15 16 LPC_FRAME#_C W IFI_RF_EN 27 +1D5V_MINI_W LAN
E51_RXD_R PLT_RST# 5,18,27,31,36,66,71,80,82,83,97

27 E51_RXD 1 2 17 18
R6501 1 2 0R0402-PAD E51_TXD_R 19 20 +3V_MINI_W LAN
27 E51_TXD
1
R6502 0R0402-PAD 21 22 PLT_RST#_W LAN 1 2 C6505 C6506 C6507
C
20 PCIE_RXN2 23 24 R6510 0R0402-PAD SC10U6D3V5KX-1GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP C
20 PCIE_RXP2 25 26
2
27 28
29 30 PCH_SMBCLK 14,15,20,66
20 PCIE_TXN2 31 32 PCH_SMBDATA 14,15,20,66
20 PCIE_TXP2 33 34
35 36 USB_PN11 18
37 38 USB_PP11 18
+3V_MINI_W LAN +3V_MINI_W LAN 39 40
41 42 5V_S5
43 44 W LAN_LED# 1 TP6501
45 46 CLK_PCI_LPC_C
1
5V_S5 47 48 C6501
DY 49 50 SCD1U16V2KX-3GP
1 2 +5V_MINI_DEBUG 51 52
2
R6503 0R3J-0-U-GP NP2
54
BLUETOOTH_EN 1 2
R6519 0R2J-2-GP TYCO-CONN52A-2-GP
20.F1743.052
B Reserve for AOAC B
LPC_AD0_C G6501 1 2
GAP-OPEN LPC_AD0 21,27,71
LPC_AD1_C G6502 1 2
3D3V_S5 +3V_MINI_W LAN GAP-OPEN LPC_AD1 21,27,71
LPC_AD2_C G6503 1 2
LPC_AD3_C G6504 1 2
LPC_FRAME#_C G6505 1 2
GAP-OPEN LPC_FRAME# 21,27,71
SCD1U10V2KX-5GP
AOAC
100KR2J-1-GP
AOAC AOAC U6501

1
TPCF8105-GP
C6508 R6515
G6506~G6511
2
placememt close close WLAN1

4
AOAC_EN_2 in bottom side

1
AOAC R6518
1
10KR2J-3-GP DY
A Q6502 AOAC <Core Design> A
2
C AOAC_EN_1 R6517
B R1 10KR2J-3-GP CLK_PCI_LPC_C G6511 1 2
27 AOAC_EN CLK_PCI_LPC 18,71
GAP-OPEN
E
Wistron Corporation
2
R2
PDTC115EE-1-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
84.00115.C1K Taipei Hsien 221, Taiwan, R.O.C.
2nd = 84.09115.011
3rd = 84.00015.01H Title
MINICARD(WLAN)/ITP CONN
A3
LA480 SD
5 4 3 2 1
5 4 3 2 1
SSID = Wireless http://laptopblue.vn
D
mSATA for V Series Only D
Place near MINI Card CONN Mini Card Connector(Full Card)

+3V_MINI_W W AN
+1D5V_MINI_W W AN 1D5V_S0 +3V_MINI_W W AN 3D3V_S0
C6618 C6619 C6601 C6602 C6603 C6604
1
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD047U16V2KX-1-GP
SCD047U16V2KX-1-GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
1
1
0R0805-PAD 0R0805-PAD
DY R6607 R6606
2
2
+1D5V_MINI_W W AN
W LAN2
53
NP1
19,31,65 PCIE_W AKE# 1 DY 2 1 2 +3V_MINI_W W AN
Place near Pin 24 R6604 0R2J-2-GP
3 4
C +1D5V_MINI_W W AN +3V_MINI_W W AN 5 6 C
7 8
9 10
C6606 C6607 C6608 11 12
13 14
SCD047U16V2KX-1-GP
SC33P50V2JN-3GP
SCD1U16V2KX-3GP
15 16
1
17 18
19 20
2
21 22 PLT_RST#_W AN 1 2
C6611 1 PLT_RST# 5,18,27,31,36,65,71,80,82,83,97
21 SATA_RXP0 2SCD01U50V2KX-1GP SATA_RXP0_C 23 24 +3V_MINI_W W AN R6605
21 SATA_RXN0 C6612 1 2SCD01U50V2KX-1GP SATA_RXN0_C 25 26 0R0402-PAD
27 28
29 30 PCH_SMBCLK
PCH_SMBCLK 14,15,20,65
21 SATA_TXN0 C6614 1 2SCD01U50V2KX-1GP SATA_TXN0_C 31 32 PCH_SMBDATA
PCH_SMBDATA 14,15,20,65
21 SATA_TXP0 C6620 1 2SCD01U50V2KX-1GP SATA_TXP0_C 33 34
+1D5V_MINI_W W AN 35 36 USB_P8- R6603 1 DY 2 0R3J-0-U-GP USB_PN8 18
37 38 USB_P8+ R6601 1 DY 2 0R3J-0-U-GP USB_PP8 18
+3V_MINI_W W AN +3V_MINI_W W AN 39 40
C6609 C6610 41 42 3G_LED# 1 TP6602
43 44
SCD047U16V2KX-1-GP
SC33P50V2JN-3GP
45 46
1
47 48
49 50
27 -MSATA_DET 1 2 51 52
2
R6608 NP2
0R0402-PAD 54
B TYCO-CONN52A-2-GP B
20.F1743.052
A <Core Design> A
Wistron Corporation
Title
WWAN Connector
A3
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Title
Reserved
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
R6824 DY
1 2
0R2J-2-GP
LEDCN1
10
Q6810
R2
E SATA_LED#_Q 3D3V_S0 8
21 SATA_LED# B R1 7
D C NUM_LED_Q 1 2 NUM_LED_R 6 D
1
CAP_LED_Q R6813 1 2 470R2J-2-GP CAP_LED_R 5
PDTA143ET-GP EC6808 SATA_LED#_Q R6812 1 2 470R2J-2-GP SATA_LED#_R 4
84.00143.M11 APS_LED#_Q R6810 1 2 100R2J-2-GP APS_LED#_R 3
2
2nd = 84.02143.011 R6818 470R2J-2-GP 2
V Series-APS
1
1
SC1KP50V2KX-1GP EC6806 EC6811 EC6807 EC6809 C6813 9
V Series-APS DY
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SCD1U16V2KX-3GP
Q6802 ACES-CON8-15-GP
2
4 3 NUM_LED_Q 20.K0315.008
27 NUM_LED 5 2 CAP_LED 27
1
6 1 AFTP6808
2N7002KDW -GP
CAP_LED_Q
1 3D3V_S0
AFTP6801
1 NUM_LED_R
AFTP6803 1 CAP_LED_R
AFTP6804 1 SATA_LED#_R
Q6801 AFTP6805 1 APS_LED#_R
3 APS_LED#_Q AFTP6806
C 1 R1 C
21 APS_LED
2
R2
LTC043ZUB-FS8-GP
84.00043.011
CHARGER LED
Q6804 LED2
4 3 DC_BATFULL#_Q GREEN
5 2 DC_BATFULL#_Q 2 3 CHARGE_LED#_R 1 2 3D3V_S5
27 DC_BATFULL CHARGE_LED 27 R6802 100R2J-2-GP
6 1 Yellow
CHARGE_LED#_Q 1
2N7002KDW -GP
CHARGE_LED#_Q LED-GY-8-GP-U
83.00326.070
B B
1
1
G6801 AFTP6814
GAP-OPEN 1 BTNCN1 1 3D3V_S5

AFTP6813 7 AFTP6809 1 PW RLED
2
1 AFTP6810 1 KBC_NOVO_BTN#_R
AFTP6811 1 KBC_PW RBTN#_R
27 KBC_PW RBTN# 1 2 KBC_PW RBTN#_R 2 AFTP6812
27 KBC_NOVO_BTN# R6809 1 2100R2J-2-GP KBC_NOVO_BTN#_R 3
R6807 100R2J-2-GP PW RLED 4
27 PW RLED
5
1
EC6801 EC6802 EC6804 3D3V_S5 6

8
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
2
EC6805 ACES-CON6-22-GP-U
20.K0487.006
SC1KP50V2KX-1GP
A <Core Design> A
2
Wistron Corporation
Title
LED Bard/Power Button
A3
LA480 SD
5 4 3 2 1
A B C D E
SSID = KBC http://laptopblue.vn

SSID = Touch.Pad
Normal Pad for B Series 5V
ClickPad for V Series 3.3V
Internal KeyBoard Connector
RN6903
5V_S0 TP_SW_R 4 1 TP_PIN5
TP_SW_L 3 2 TP_PIN4
KROW[0..7] 27
SRN100J-3-GP
KCOL[0..15] 27 B Series-TP
1
2
RN6904 1
RN6901 4 1 TP_PIN6 AFTP6942
TP_DATA 3 2 TP_PIN3
KCOL15 AFTP6904 SRN10KJ-5-GP
4 1 4
KCOL10 1 AFTP6905 SRN0J-6-GP TPAD1
KCOL11 1 AFTP6906 B Series-TP 7
4
3
KCOL14 1 AFTP6907 RN6905
KCOL13 1 AFTP6908 TP_CLK 4 1 TP_PIN2 TP_PIN1 1
KCOL12 1 AFTP6909 RN6902 3 2 TP_PIN1
5V_S0
KB14 KCOL3 1 AFTP6910 27 TPCLK TPCLK 1 4 TP_CLK TP_PIN2 2
25 KCOL6 1 AFTP6911 TPDATA 2 3 TP_DATA SRN0J-6-GP TP_PIN3 3
27 TPDATA
1
SCD1U10V2KX-4GP
KCOL8 1 AFTP6912 C6901 B Series-TP TP_PIN4 4
1 KCOL15 KCOL7 1 AFTP6913 SB 1015 Swap data and clk SRN33J-5-GP-U B Series-TP TP_PIN5 5
KCOL4 1 AFTP6914 TP_PIN6 6
2
2 KCOL10 KCOL2 1 AFTP6915
3 KCOL11 KROW0 1 AFTP6916 8
5 KCOL13 KCOL5 1 AFTP6918 ACES-CON6-13-GP
6 KCOL12 KROW3 1 AFTP6919 20.K0320.006
7 KCOL3 KROW2 1 AFTP6920
9 KCOL8 KROW5 1 AFTP6922 AFTP6901 1 TP_PIN6
11 KCOL4 KCOL9 1 AFTP6924 AFTP6929 1 TP_PIN4
13 KROW0 KROW7 1 AFTP6926 AFTP6932 1 TP_PIN2 TP_DATA RN6906
14 KCOL1 KROW1 1 AFTP6927 3D3V_S0 4 1 TP_PIN1
PCH_SMBCLK 14,15,20,66
15 KCOL5 GND 1 AFTP6928 TP_CLK TP_CLK 3 2 TP_PIN2
1
16 KROW3
1
SCD1U10V2KX-4GP
17 KROW2 AFTP6939 1 TP_PIN3 C6902 SRN0J-6-GP R6901
18 KCOL0 C6903
6903 C6904
6904 V Series-TP V Series-TP 0R2J-2-GP
2C
2C
19 KROW5 DY DY DY
2
SC100P50V2JN-3GP
SC100P50V2JN-3GP
20 KROW4
2
21 KCOL9 AFTP6902 1 TP_SW_L
1
KROW6 TP_SW_R PCH_SMBDATA 14,15,20,66
22 AFTP6903 1 RN6907
23 KROW7 TP_DATA 4 1 TP_PIN3
24 KROW1 3 2 TP_PIN4
26 SRN0J-6-GP
V Series-TP
ACES-CON24-7-GP
20.K0320.024
2nd = 20.K0391.024
3 3
TPSW1 TPSW2
SW-TACT4-14-GP SW-TACT4-14-GP
5
62.40009.D71 62.40009.D71
1 2 TP_SW_L 1 2 TP_SW_R
B Series-TP B Series-TP
3 4 3 4
6
KB14 for 14" VB480 & VB485 1 1
KB15 for 15" VB580 & VB585 AFTP6940 AFTP6941
2 2
1 1
<Core Design>
Wistron Corporation
Title
TOUCH PAD CONNECTOR

A2 SD
LA480
A B C D E
5 4 3 2 1
D D
C C
B B
<Core Design>
A
Title
Hall Sensor
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
3D3V_S0
DB1
1
21,27,65 LPC_AD0 2
21,27,65 LPC_AD1 3
21,27,65 LPC_AD2 4
21,27,65 LPC_AD3 5
21,27,65 LPC_FRAME# 6
5,18,27,31,36,65,66,80,82,83,97 PLT_RST# 7
8
18,65 CLK_PCI_LPC 9
10
C 11 C
12
MLX-CON10-7-GP
20.D0183.110
DY
B B
<Core Design>
A
Title
Dubug connector
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Title
Reserved
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Title
Reserved
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
CARD Reader CONN

A2
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Title
New Card
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Title
Reserved
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
<Core Design>
A
Title
Reserved
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
BLANK C
B B
<Core Design>
A
Title
Reserved
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
3D3V_S5
VCC3M_Q34 1 2 10R2J-2-GP VCC3_ACC

R7901 C7901 C7902
G-Sensor
C
E
SC10U6D3V5KX-1GP
SCD1U10V2KX-4GP
1
1
D Q7901 D
PDTA114EE-3-GP-U
V Series Only
R2
84.00114.H1K
2
2nd = 84.09114.A11
R1
3rd = 84.00014.01H
B
ANALOG_AGND
27 GSENSE_ON#
1
R7902
100KR2J-1-GP
DY
2
14
15
U7901 GSENSE_Z 1 TP7901
VDD
RES
TP7902 1 GSENSE_TST 2
C
ST
3 GND VOUTZ 8 C
5 10 GSENSE_Y_R 1 2
GND VOUTY GSENSE_Y 27
1
6 R7906 56KR2J-L1-GP
GND
1
R7903 R7904 7 12
100KR2J-1-GP GND VOUTX C7904 C7907
0R0402-PAD
1 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
2
NC#1
11
2
NC#11
4 NC#4
13 ANALOG_AGND
NC#13
ANALOG_AGND 9 16
NC#9 NC#16 GSENSE_X_R 1 2 GSENSE_X 27
R7907 56KR2J-L1-GP
1
LIS34ALTR-GP C7905 C7908
2nd = 74.KXTC8.0BZ SCD1U10V2KX-4GP SCD1U10V2KX-4GP
2
ROHM-KIONIX
74.KXTC8.0BZ
KXTC8-2850-GP ANALOG_AGND
B B
<Core Design>
A
Layout Comment : Wistron Corporation A
(1) Place C483, C484, Q46, R528, R530, Taipei Hsien 221, Taiwan, R.O.C.
C479, C476, R509, R508 close to U55. Title
(2) Avoid routing under DCDC switching area. G-Sensor
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
RFID
3D3V_S0 3D3V_S5
1
R8001 3D3V_S5
4K7R2J-2-GP
U8001
2
1 NC#1 VCC 8
Q8001 2 7
C PROT_EEPROM NC#2 WP
C 3 PROT# SCL 6 SMB_CLK 20
C
B R1 4 5
GND SDA SMB_DATA 20
E
1
PDTC115TE-GP BUL08-1FVJ-WGE2-GP C8001
84.00115.E1K 72.BUL08.A0Q SCD01U50V2KX-1GP
2
2nd = 84.09115.A11 2nd = 72.24S08.A0Q
3rd = 84.00015.B1H 3rd = 72.26C08.00R
PLT_RST# 5,18,27,31,36,65,66,71,82,83,97
Table 80.1- Transistor multi-source
NXP PDTC115TE N/A 84.00115.E1K

B B
ROHM LTC015TEB N/A 84.00015.B1H
Panasonic DRC9115T0L N/A 84.09115.A11
Table 80.2- EEPROM multi-source

<Core Design>
ROHM BUL08-1FVJ-WGE2 N/A 72.BUL08.A0Q

A
NXP PCA24S08ADP N/A 72.24S08.A0Q Taipei Hsien 221, Taiwan, R.O.C.
Title
SANYO LE26CAP08TT-TLM-H N/A 72.26C08.00R
RF ID
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C
BLANK C
B B
<Core Design>
A
Title
Reserved
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
5V_USB4_S3
R8201 and R8203 Dual layout with TR8201
1
EC8202
SCD1U16V2KX-3GP USBCN1
2
18 USB_PN2 USB_PN2_R 11
1
3
D 2 D
TR8202 3
FILTER-130-GP 3D3V_AUX_S5 4
1st = 68.11900.20A 5
27 ADP_LED 6
USB_PN2_R 7
USB_PP2_R 8
9
AFTP8206 1 10
4
12
18 USB_PP2 USB_PP2_R
ACES-CON10-19-GP
20.K0420.010
RN8202
18 USB_OC#8_9 1 4 USB_PW R_OC#
2 3 USB_PW R_EN
27,61,62 USB_PW R_EN_R
SRN0J-6-GP AFTP8201 1 5V_USB4_S3
B Series-USB PWR AFTP8202 1 3D3V_AUX_S5
AFTP8203 1 ADP_LED
AFTP8204 1 USB_PN2_R
AFTP8205 1 USB_PP2_R
C RN8201 C
1 4 USB_PW R_OC#
27 CHG_USB_OC# USB_PW R_EN AFTP8210 HPOUT_JD
27 USB_CHG_EN 2 3 1
AFTP8213 1 USB_PW R_OC#
SRN0J-6-GP AFTP8223 1 USB_PW R_EN
V Series-USB PWR AFTP8212 1 USB_AO_SEL0
AFTP8209 1 AUD_MIC1_COMBO_R
18 USB_PN9 USB_PN9_R AFTP8207 1 AUD_HPOUT_R

AFTP8208 1 AUD_HPOUT_L
2
CDRCN1
TR8201 32 AFTP8211 1 AU_GND
FILTER-130-GP 30
1st = 68.11900.20A 29 AUD_HPOUT_R 29
28 AFTP8214 1 USB_PP5_R
AUD_HPOUT_L 29
27 AFTP8215 1 USB_PN5_R
AUD_MIC1_COMBO_R 29
26 AFTP8216 1 USB_PP9_R
HPOUT_JD 29
25 AFTP8217 1 USB_PN9_R
24 AFTP8218 1 CLK_PCH_48M
1
23 AFTP8219 1 PLT_RST#
USB_PP9_R USB_PW R_OC# USB_AO_SEL0 27 AFTP8220 3D3V_S0_CARD
18 USB_PP9 22 1
21 AU_GND AFTP8221 1 5V_S5
20 USB_PP5_R AFTP8224 1
19 USB_PN5_R
18 Cardreader AFTP8222 1 GND
17 USB_PP9_R AFTP8225 1
B USB_PN9_R B
16
15 USB Port3
14 USB_PW R_EN
13 3D3V_S0 3D3V_S0_CARD
12
11 CLK_PCH_48M 20 1 2
10 R8202
PLT_RST# 5,18,27,31,36,65,66,71,80,83,97
9 0R0805-PAD
8
7 3D3V_S0_CARD
18 USB_PN5 0R0402-PAD 1 2 R8206 USB_PN5_R 6
5 CLK_PCH_48M
4
3
1
2
DY EC8203
1 SC22P50V2JN-4GP
5V_S5
2
31
1
ACES-CON30-9-GP-U EC8201
20.K0510.030
SCD1U16V2KX-3GP
2
18 USB_PP5 0R0402-PAD 1 2 R8207 USB_PP5_R
A <Core Design> A
Wistron Corporation
Title
IO Board Connector
A3
LA480 SD
5 4 3 2 1
5 4 3 2 1
http://laptopblue.vn PCI Express PEX_IOVVD/Q Combined (DG-05587-001_v03_p.72_Table 10)
Capacitor Type Footprint Population Location
1.0uF X6S 0402 4 Under GPU

SPEC. (DG-05587-001_v03_p.70) 4.7uF X6S 0603 2 Near GPU
PEX_CLK_REQ_N is an open-drain bi-directional signal; 10uF X5R 0805 4 Midway Between GPU and Power Supply
by default it should have a 10 kΩ pull-up to 3.3V. 22uF X5R 0805 4 Midway Between GPU and Power Supply
This signal is an active low signal.
4 PEG_TXP[0..15] PEG_RXP[0..15] 4 X6S (+/-22%、-55~105℃)
1D05V_VGA_S0
D 4 PEG_TXN[0..15] PEG_RXN[0..15] 4
3D3V_VGA_S0
X5R (+/-15%、-55~85℃) D
1.05V ±30mV 3300mA total
(DG-05587-001_v03_p.71_Table 9)
OPS
10KR2J-3-GP
10KR2J-3-GP
SC22U6D3V5MX-2GP
SC4D7U6D3V3KX-GP
1
1
3D3V_VGA_S0 DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
OPS OPS OPS OPS OPS
1
R8302 R8303 VGA1A 1 OF 17 C8336
OPS C8333 C8334 C8335 SC10U6D3V3MX-GP C8339
1/17 PCI_EXPRESS
2
Q8301
G AJ11
PEX_WAKE#
AG19
VGA_RST# AJ12 PEX_IOVDD_1
20 PEG_CLKREQ# D AG21
PEX_RST# PEX_IOVDD_2
AG22
VGA_PEG_CLKREQ# PEX_IOVDD_3
S AK12 AG24
PEX_CLKREQ# PEX_IOVDD_4
PEX_IOVDD_5
AH21 1uF(X5R) 4.7uF(X5R) 10uF(X5R) 22uF(X5R)
20 CLK_PCIE_VGA AL13 AH25
2N7002K-2-GP PEX_REFCLK PEX_IOVDD_6 K0402 ×4 K0603 ×2 M0805 ×4 M0805 ×4
20 CLK_PCIE_VGA# AK13
84.2N702.J31 PEX_REFCLK#
2ND = 84.2N702.031 PEG_RXP0 SCD22U10V2KX-1GP OPS 1 2 C8301 PEG_C_RXP0 AK14

PEG_RXN0 SCD22U10V2KX-1GP PEG_C_RXN0 PEX_TX0
OPS 1 2 C8302 AJ14
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC4D7U6D3V3KX-GP
PEX_TX0#
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PEG_TXP0 AN12 OPS OPS OPS OPS OPS OPS
1
PEG_TXN0 PEX_RX0 C8343
AM12 AG13
PEX_RX0# PEX_IOVDDQ_1 C8340 C8341 C8342 C8345 C8346
AG15 SC10U6D3V3MX-GP
PEG_RXP1 SCD22U10V2KX-1GP PEG_C_RXP1 PEX_IOVDDQ_2
OPS 1 2 C8304 AH14 AG16
2
PEG_RXN1 SCD22U10V2KX-1GP PEG_C_RXN1 PEX_TX1 PEX_IOVDDQ_3
OPS 1 2 C8303 AG14 AG18
PEX_TX1# PEX_IOVDDQ_4
AG25
PEG_TXP1 PEX_IOVDDQ_5
AN14 AH15
PEG_TXN1 PEX_RX1 PEX_IOVDDQ_6
AM14 AH18
PEX_RX1# PEX_IOVDDQ_7
AH26
PEG_RXP2 SCD22U10V2KX-1GP PEG_C_RXP2 PEX_IOVDDQ_8
OPS 1 2 C8306 AK15 AH27
PEG_RXN2 SCD22U10V2KX-1GP PEG_C_RXN2 PEX_TX2 PEX_IOVDDQ_9
OPS 1 2 C8305 AJ15 AJ27 Under GPU Near GPU Midway Between GPU and Power Supply
PEX_TX2# PEX_IOVDDQ_10
AK27
PEG_TXP2 PEX_IOVDDQ_11
AP14 AL27
PEG_TXN2 PEX_RX2 PEX_IOVDDQ_12
AP15 AM28
PEX_RX2# PEX_IOVDDQ_13
AN28
PEG_RXP3 PEG_C_RXP3 PEX_IOVDDQ_14
SCD22U10V2KX-1GP OPS 1 2 C8308 AL16
PEX_TX3
PCI Express PEX_SVDD/PLL_HVDD Connected to NV3V3 (DG-05587-001_v03_p.72_Table 12)
PEG_RXN3 SCD22U10V2KX-1GP OPS 1 2 C8307 PEG_C_RXN3 AK16
C PEG_TXP3 AN15
PEX_TX3#
PEX_RX3 Capacitor Type Footprint Population Location

C
SPEC. (DG-05587-001_v03_p.70) PEG_TXN3 AM15
PEX_RX3#
For PCI ECPRESS connection, PEG_RXP4 SCD22U10V2KX-1GP OPS 1 2 C8310 PEG_C_RXP4 AK17 0.1uF X5R 0402 1 Near GPU
please use 0.22uF,20%,0402,X5R PEG_RXN4 SCD22U10V2KX-1GP PEG_C_RXN4 PEX_TX4
OPS 1 2 C8309 AJ17 4.7uF X5R 0603 2 Near GPU
PEX_TX4#
or better AC couplimg capacitors.
PEG_TXP4 AN17
PEG_TXN4 PEX_RX4
AM17
PEX_RX4#
X5R (+/-15%、-55~85℃)
PEG_RXP5 SCD22U10V2KX-1GP OPS 1 2 C8312 PEG_C_RXP5 3D3V_VGA_S0
0.22uF(X5R) AH17
K0402
PEG_RXN5 SCD22U10V2KX-1GP OPS 1 2 C8311 PEG_C_RXN5 AG17
PEX_TX5
PEX_TX5#
AH12 3.3V ±10% 210mA total dGPU reset
PEG_TXP5 PEX_PLL_HVDD
AP17
PEX_RX5
(DG-05587-001_v03_p.71_Table 9) DY
PEG_TXN5 AP18 AG12 1 2 VGA_RST#
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
PEX_RX5# PEX_SVDD_3V3 5,18,27,31,36,65,66,71,80,82,97 PLT_RST#
R8310 0R2J-2-GP
PEG_RXP6 SCD22U10V2KX-1GP OPS 1 2 C8314 PEG_C_RXP6 AK18 OPS OPS OPS
1
OPS 1 2 C8313 AJ18 0.1uF(X5R) 4.7uF(X5R)
PEX_TX6# C8347 C8348 C8349
PEG_TXP6 AN18 K0402 ×1 K0603 ×2
2
PEG_TXN6 PEX_RX6 3D3V_S0
AM18 U8301
PEX_RX6#
18 DGPU_HOLD_RST# 1
PEG_RXP7 SCD22U10V2KX-1GP PEG_C_RXP7 B
OPS 1 2 C8316 AL19 5
PEG_RXN7 SCD22U10V2KX-1GP PEG_C_RXN7 PEX_TX7 PLT_RST# VCC
OPS 1 2 C8315 AK19 2
PEX_TX7# A VGA_RST#
4
PEG_TXP7 Y
AN20 VGA_CORE 3
2
PEG_TXN7 PEX_RX7 GND
AM20 Near GPU
PEX_RX7# 74LVC1G08GW-1-GP R8319
PEG_RXP8 PEG_C_RXP8
DY
SCD22U10V2KX-1GP OPS 1 2 C8318 AK20 1 2 73.01G08.L04 OPS 10KR2J-3-GP
OPS 1 2 C8317 AJ20 R8304 0R2J-2-GP OPS
PEX_TX8#
L4 1st = 73.01G08.DHG
1
VDD_SENSE NVVDD_SENSE 92
PEG_TXP8 AP20 2nd = 73.7SZ08.DAH
PEG_TXN8 PEX_RX8
AP21
PEX_RX8# 3rd = 73.01G08.FHG
L5 NVGND_SENSE 92
PEG_RXP9 SCD22U10V2KX-1GP PEG_C_RXP9 GND_SENSE
OPS 1 2 C8320 AH20
1
OPS 1 2 C8319 AG20
PEX_TX9# R8305
PEG_TXP9 AN21 0R2J-2-GP
PEG_TXN9 PEX_RX9
AM21
PEX_RX9# DY
PCI Express PEX_PLLVDD (DG-05587-001_v03_p.72_Table 11)
2
PEG_RXP10 SCD22U10V2KX-1GP OPS 1 2 C8322 PEG_C_RXP10 AK21
B PEG_RXN10 SCD22U10V2KX-1GP OPS 1 2 C8321 PEG_C_RXN10 AJ21
PEG_TXP10
PEX_TX10
PEX_TX10#
NC_3V3AUX
P8 Capacitor Type Footprint Population Location B
AN23
PEG_TXN10 PEX_RX10
AM23
PEX_RX10# SPEC. (DG-05587-001_v03_p.70)
PEX_TSTCLK_OUT should be 100nF X6S 0402 1 Under GPU
PEG_RXP11 SCD22U10V2KX-1GP OPS 1 2 C8324 PEG_C_RXP11 AL22
PEG_RXN11 SCD22U10V2KX-1GP 2 C8323 PEG_C_RXN11 AK22 PEX_TX11 terminated with a 200Ω resistor. 1.0uF X5R 0603 1 Near GPU
OPS 1
PEX_TX11# 4.7uF X5R 0805 1 Near GPU
PEG_TXP11 AP23
PEG_TXN11 PEX_RX11
AP24
PEX_RX11#
OPS X6S (+/-22%、-55~105℃)
AJ26 PEX_TSTCLK_OUT R8306 2 1 200R2F-L-GP
PEG_RXP12 SCD22U10V2KX-1GP OPS 1 2 C8326 PEG_C_RXP12 AK23 PEX_TSTCLK_OUT
AK26 PEX_TSTCLK_OUT# X5R (+/-15%、-55~85℃) 1D05V_VGA_S0
PEG_RXN12 SCD22U10V2KX-1GP PEG_C_RXN12 AJ23 PEX_TX12 PEX_TSTCLK_OUT#
OPS 1 2 C8325
PEX_TX12#
PEG_TXP12 AN24
PEG_TXN12 PEX_RX12
AM24
PEX_RX12# 100nF(X7R) 1.0nF(X5R) 4.7nF(X5R) OPS-BOM CTRL
PEG_RXP13 PEG_C_RXP13 AH23 K0402 ×1 K0402 ×1 K0603 ×1 R8311
SCD22U10V2KX-1GP OPS 1 2 C8328
PEG_RXN13 SCD22U10V2KX-1GP OPS 1 2 C8327 PEG_C_RXN13 AG23 PEX_TX13
AG26 VCC1R05VIDEO_PEX_PLLVDD 1.05V ±30mV 150mA total 2 1
PEX_TX13# PEX_PLLVDD 0R3J-0-U-GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
PEG_TXP13 AN26 (DG-05587-001_v03_p.71_Table 9)
PEG_TXN13 PEX_RX13
AM26
PEX_RX13# 3D3V_VGA_S0
1
PEG_RXP14 SCD22U10V2KX-1GP OPS 1 2 C8330 PEG_C_RXP14 AK24 OPS DY OPS OPS OPS
PEG_RXN14 PEG_C_RXN14 AJ24 PEX_TX14
SCD22U10V2KX-1GP OPS 1 2 C8329 AK11 TESTMODE 1 2 1 2 C8350 C8351 C8352 Stuff 0 ohm(63.00000.00L) for N13P-GS/N13M-GS,
PEX_TX14# TESTMODE R8307 10KR2J-3-GP R8308 10KR2J-3-GP
2
PEG_TXP14 AP26 Stuff bead(68.00082.001) for N13P-GL/N13M-GE
PEG_TXN14 PEX_RX14
AP27
PEX_RX14#
PEG_RXP15 SCD22U10V2KX-1GP OPS 1 2 C8332 PEG_C_RXP15 AL25
PEG_RXN15 SCD22U10V2KX-1GP PEG_C_RXN15 AK25 PEX_TX15
OPS 1 2 C8331
PEX_TX15#
OPS
PEG_TXP15 AN27 AP29 PEX_TERMP 1 2
PEG_TXN15 AM27
PEX_RX15 PEX_TERMP R8309 2K49R2F-GP
Under GPU Near GPU
PEX_RX15#
N13P-GS-A1-GP
OPS-BOM CTRL
SPEC. (DG-05587-001_v03_p.214)
By default, pull-down the TESTMODE pin to GND with a 10kΩ resistor.
For XOR tree testing, TESTMODE should be pulled up to 3v3 with a 10 kΩ resistor.
A A
SPEC. (DG-05587-001_v03_p.70)
PEX_TERMP is used for internal calibration; <Core Design>
pull-down this signal with 2.49 kΩ,1% resistor.
Wistron Corporation
Title
N13P_GPU (1/5): PEG

A2 SD
LA48
5 4 3 2 1
A B C D E
VGA1J 10 OF 17
LVDS Interface 5/17 IFPAB
ALL PINS NC FOR GF117
AN6
IFPA_TXC#
AM6
TP8401 IFPAB_RSET IFPA_TXC VGA1K 11 OF 17
1 AJ8
IFPAB_RSET
4 6/17 IFPC 4
AN3
IFPA_TXD0#
AP3
IFPA_TXD0 ALL PINS NC FOR GF117
IFPAB_PLLVDD AH8
IFPAB_PLLVDD TP8403 IFPC_RSET
AM5 1 AF8
1
R8401 IFPA_TXD1# IFPC_RSET
AN5 DVI/HDMI DP
10KR2J-3-GP IFPA_TXD1
OPS
AK6 IFPC_PLLVDD AF7 I2CW_SDA AG2
IFPA_TXD2# IFPC_PLLVDD IFPC_AUX_I2CW_SDA#
AL6 I2CW_SCL AG3
1
IFPA_TXD2 R8405 IFPC_AUX_I2CW_SCL
SPEC. (DG-05587-001_v03_p.160) 10KR2J-3-GP
Pull down IFPxy IOVDD with 10kΩ resistor. IFPA_TXD3#
AH6 OPS TXC IFPC_L3#
AG4
AJ6 TXC AG5
Pull down IFPxy PLLVDD with 10kΩ resistor. IFPA_TXD3 IFPC_L3
2
The other IO pins can be NC, this includes unused data lines. TXD0 IFPC_L2#
AH4
IFPB_TXC#
AH9 IFPC TXD0 IFPC_L2
AH3
AJ9
IFPB_TXC
TXD1 AJ2
IFPC_L1#
AG8 TXD1 AJ3
IFPA_IOVDD IFPC_L1
AP5
IFPAB_IOVDD IFPB_TXD4#
AG9 AP6 TXD2 AJ1
IFPB_IOVDD IFPB_TXD4 IFPC_L0#
TXD2 AK1
IFPC_L0
AL7
1
IFPB_TXD5#
AM7
R8402 IFPB_TXD5 IFPC_IOVDD AF6 P2
10KR2J-3-GP IFPC_IOVDD GPIO15
1
OPS IFPB_TXD6#
AM8 R8406
AN8 10KR2J-3-GP N13P-GS-A1-GP
2
IFPB_TXD6
OPS OPS-BOM CTRL
AL8
2
IFPB_TXD7#
AK8
IFPB_TXD7
N4
GPIO14
3
IFPAB 3
N13P-GS-A1-GP
OPS-BOM CTRL
VGA1M 13 OF 17
8/17 IFPEF
VGA1L 12 OF 17
ALL PINS NC FOR GF117 HDMI Interface 7/17 IFPD
ALL PINS NC FOR GF117

DVI-DL DVI-SL/HDMI DP
TP8404 1 IFPD_RSET AN2
IFPD_RSET
DVI/HDMI DP
I2CY_SDA I2CY_SDA AB4
IFPE_AUX_I2CY_SDA#
I2CY_SCL I2CY_SCL AB3
IFPEF_PLLVDD IFPE_AUX_I2CY_SCL IFPD_PLLVDD
AB8 AG7 I2CX_SDA AK2
IFPEF_PLLVDD IFPD_PLLVDD IFPD_AUX_I2CX_SDA#
I2CX_SCL AK3
IFPD_AUX_I2CX_SCL
TXC TXC AC5
1
TP8402 IFPF_REST IFPE_L3#
1 AD6 TXC TXC AC4
IFPEF_RSET IFPE_L3
TXC AK5
1
R8407 IFPD_L3#
AC3 TXC AK4
TXD0 TXD0 IFPE_L2# 10KR2J-3-GP IFPD_L3
AC2
TXD0 TXD0 IFPE_L2
R8403 OPS AL4
2
TXD0 IFPD_L2#
10KR2J-3-GP
TXD1 TXD1 IFPE_L1#
AC1 IFPD TXD0 IFPD_L2
AL3
OPS AD1
2
IFPE TXD1 TXD1 IFPE_L1

TXD1 IFPD_L1#
AM4
AD3 TXD1 AM3
TXD2 TXD2 IFPE_L0# IFPD_L1
AD2
2 TXD2 TXD2 IFPE_L0 2
TXD2 AM2
IFPD_L0#
TXD2 AM1
IFPD_L0
HPD_E HPD_E R1 IFPD_IOVDD AG6 M6

GPIO18 IFPD_IOVDD GPIO17
1
N13P-GS-A1-GP
OPS-BOM CTRL
R8408
10KR2J-3-GP
OPS
2
IFPEF_IOVDD AC7
IFPE_IOVDD
I2CZ_SDA AF2
IFPF_AUX_I2CZ_SDA#
I2CZ_SCL AF3
IFPF_AUX_I2CZ_SCL
AC8
IFPF_IOVDD
1
TXC AF1
IFPF_L3#
TXC AG1
R8404 IFPF_L3
10KR2J-3-GP TXD3 TXD0 AD5
IFPF_L2#
OPS TXD3 TXD0 AD4
2
IFPF_L2
TXD4 TXD1 AF5
IFPF TXD4 TXD1
IFPF_L1#
IFPF_L1
AF4
TXD5 TXD2 AE4

IFPF_L0#
TXD5 TXD2 AE3
IFPF_L0
HPD_F P3
GPIO19
N13P-GS-A1-GP
OPS-BOM CTRL
1 1
<Core Design>
Wistron Corporation
Title
N13P_GPU (2/5): DIGITALOUT
A2
LA48 SD
A B C D E
5 E1 (DA-05691-001_v03_p.4_Table 2) 4 3 2 GPU FBVDDQ Decoupling (DG-05587-001_v03_p.86_Table 22)
1
VGA1B 2 OF 17 N13P-GL NC VGA1C 3 OF 17
89 FBA_D[63..0]
FBA_D0 L28
2/17 FBA
FBA_D0 FB_CLAMP
E1
N13M_GE1
N13M-GS
N13P-GS
PS_FB_CLAMP 1
NC
Pull down FB_CLAMP with a 10kΩ
Pull down FB_CLAMP with a 10kΩ
2
http://laptopblue.vn 90,91 FBB_D[63..0]
FBB_D0 G9
3/17 FBB
FBB_D0
Capacitor Type
0.1uF
1uF
X7R
X7R
Footprint
0402
0603
8
2
Population Location
8
2
Under GPU
Under GPU
FBA_D1 M29 R8522 10KR2F-2-GP FBB_D1 E9
FBA_D2 FBA_D1 FBB_D2 FBB_D1 4.7uF X6S 0603 2 2 Under GPU
L29
FBA_D2
DY G8
FBB_D2
FBA_D3 M28 FBB_D3 F9 10uF X5R 0805 4 4 Near GPU
FBA_D4 FBA_D3 FBB_D4 FBB_D3
N31 F11
FBA_D5 FBA_D4 FB_PLLVDD FBB_D5 FBB_D4
P29 K27 G11
FBA_D6 FBA_D5 FB_DLL_AVDD FBB_D6 FBB_D5
R29 F12
P28
FBA_D7 35mA G12
FBB_D7
X7R (+/-15%、-55~125℃)
FBA_D8 J28 FBB_D8 G6
FBA_D9 FBA_D8 FBB_D9 FBB_D8 X6S (+/-22%、-55~105℃)
H29
FBA_D9 (DG-05587-001_v03_p.88_Table 25) F5
FBB_D9
FBA_D10 J29 FBB_D10 E6 X5R (+/-15%、-55~85℃) 1D5V_VGA_S0
H28
FBA_D11
F6
FBB_D11 0.1uF(X7R)
D FBA_D12
FBA_D13
FBA_D14
G29
E31
E32
FBA_D12
FBA_D13
Mode D Command Mapping
FBB_D12
FBB_D13
FBB_D14
F4
G4
E2
FBB_D12
FBB_D13
K0402 ×8 D
F30 (DG-05587-001_v03_p.78_Table 16) F3
FBA_D16 FBA_D15 FBB_D16 FBB_D15 VGA1D 4 OF 17
C34 C2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
D32 D4 14/17 FBVDDQ
B33 D3 OPS OPS OPS OPS OPS OPS OPS OPS
1
C33
FBA_D19
N13x DDR3 Data Bits Data Bits C1
FBB_D19
AA27
FBVDDQ_1
FBA_D20 F33 FBB_D20 B3 AA30 C8501 C8502 C8503 C8504 C8505 C8506 C8507 C8508
FBA_D21 F32
FBA_D20 mode D [31:0] [63:32] FBB_D21 C4
FBB_D20
AB27
FBVDDQ_2
2
FBA_D22 FBA_D21 FBB_D22 FBB_D21 FBVDDQ_3
H33 B5 AB33
H32
FBA_D23 FBx_CMD0 CS0# C5
FBB_D23
AC27
FBVDDQ_5
FBA_D24 P34 FBB_D24 A11 AD27
FBA_D25 P32
FBA_D24 FBx_CMD1 FBB_D25 C11
FBB_D24
AE27
FBVDDQ_6
FBA_D26 FBA_D25 FBx_CMD2 ODT FBB_D26 FBB_D25 FBVDDQ_7
P31 D11 AF27
P33
FBA_D27 FBx_CMD3 CKE B11
FBB_D27
AG27
FBVDDQ_9
FBA_D28 L31 FBB_D28 D8 B13
FBA_D29 L34
FBA_D28
FBA_D29
FB CMD mapping FBx_CMD4 A14 A14 FBB_D29 A8
FBB_D28
FBB_D29
FB CMD mapping B16
FBVDDQ_10
FBVDDQ_11 Under GPU
FBA_D30 L32 FBx_CMD5 RST RST FBB_D30 C8 B19
FBA_D31 L33
FBA_D30 Mode D-N13x FBx_CMD6 A9 A9 FBB_D31 B8
FBB_D30 Mode D-N13x E13
FBVDDQ_12
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
AG28 F24 E16
FBA_D33 AF29
FBA_D32
U30 FBx_CMD7 A7 A7 FBB_D33 G23
FBB_D32
D13 E19
FBVDDQ_14
OPS OPS OPS OPS
1
FBA_D33 FBA_CMD0 FBA_CS0# 88 FBB_D33 FBB_CMD0 FBB_CS0# 90 FBVDDQ_15
FBA_D34 AG29
FBA_D34 FBA_CMD1
T31 FBx_CMD8 A2 A2 FBB_D34 E24
FBB_D34 FBB_CMD1
E14 H10
FBVDDQ_16
FBA_D35 AF28 U29 FBB_D35 G24 F14 H11 C8509 C8510 C8511 C8512 1uF(X7R)
FBA_D36 FBA_D35 FBA_CMD2 FBA_ODT0 88 FBx_CMD9 A0 A0 FBB_D36 FBB_D35 FBB_CMD2 FBB_ODT0 90 FBVDDQ_17
AD30 R34 D21 A12 H12
2
FBA_D37 FBA_D36 FBA_CMD3 FBA_CKE0 88 FBx_CMD10 A4 A4 FBB_D37 FBB_D36 FBB_CMD3 FBB_CKE0 90 FBVDDQ_18 K0603 ×4
AD29 R33 E21 B12 H13
FBA_D38 FBA_D37 FBA_CMD4 FBB_D38 FBB_D37 FBB_CMD4 FBVDDQ_19
AC29
FBA_D38 FBA_CMD5
U32
FBA_RST 88,89
FBx_CMD11 A1 A1 G21
FBB_D38 FBB_CMD5
C14
FBB_RST 90,91
H14
FBVDDQ_20
FBA_D39 AD28 U33 FBB_D39 F21 B14 H15
FBA_D40 AJ29
FBA_D39 FBA_CMD6
U28
FBA_A9 88,89 FBx_CMD12 BA0 BA0 FBB_D40 G27
FBB_D39 FBB_CMD6
G15
FBB_A9 90,91
H16
FBVDDQ_21
FBA_D41 FBA_D40 FBA_CMD7 FBA_A7 88,89 FBx_CMD13 WE# WE# FBB_D41 FBB_D40 FBB_CMD7 FBB_A7 90,91 FBVDDQ_22
AK29 V28 D27 F15 H18
FBA_D42 FBA_D41 FBA_CMD8 FBA_A2 88,89 FBB_D42 FBB_D41 FBB_CMD8 FBB_A2 90,91 FBVDDQ_23
AJ30
FBA_D42 FBA_CMD9
V29
FBA_A0 88,89 FBx_CMD14 A15 A15 G26
FBB_D42 FBB_CMD9
E15
FBB_A0 90,91
H19
FBVDDQ_24
FBA_D43 AK28 V30 FBB_D43 E27 D15 H20
FBA_D44 AM29
FBA_D43 FBA_CMD10
U34
FBA_A4 88,89 FBx_CMD15 CAS# CAS# FBB_D44 E29
FBB_D43 FBB_CMD10
A14
FBB_A4 90,91
H21
FBVDDQ_25
FBA_D45 FBA_D44 FBA_CMD11 FBA_A1 88,89 FBx_CMD16 CS0# FBB_D45 FBB_D44 FBB_CMD11 FBB_A1 90,91 FBVDDQ_26
AM31 U31 F29 D14 H22
FBA_D45 FBA_CMD12 FBA_BA0 88,89 FBB_D45 FBB_CMD12 FBB_BA0 90,91 FBVDDQ_27
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
FBA_D46 AN29 V34 FBx_CMD17 FBB_D46 E30 A15 H23
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
FBA_D47 FBA_D46 FBA_CMD13 FBA_WE# 88,89 FBB_D47 FBB_D46 FBB_CMD13 FBB_WE# 90,91 FBVDDQ_28
AM30 V33 D30 B15 H24
FBA_D48 AN31
FBA_D47 FBA_CMD14
Y32
FBA_A15 88,89 FBx_CMD18 ODT FBB_D48 A32
FBB_D47 FBB_CMD14
C17
FBB_A15 90,91
H8
FBVDDQ_29
OPS OPS OPS OPS
1
FBA_D48 FBA_CMD15 FBA_CAS# 88,89 FBx_CMD19 FBB_D48 FBB_CMD15 FBB_CAS# 90,91 FBVDDQ_30
FBA_D49 AN32
FBA_D49 FBA_CMD16
AA31
FBA_CS1# 89
CKE FBB_D49 C31
FBB_D49 FBB_CMD16
D18
FBB_CS1# 91
H9
FBVDDQ_31
C8515 C8516
FBA_D50 AP30 AA29 FBx_CMD20 A13 FBB_D50 C32 E18 L27 C8513 C8514
FBA_D51 FBA_D50 FBA_CMD17 A13 FBB_D51 FBB_D50 FBB_CMD17 FBVDDQ_32
AP32 AA28 B32 F18 M27
2
FBA_D52 AM33
FBA_D51 FBA_CMD18
AC34
FBA_ODT1 89 FBx_CMD21 A8 A8 FBB_D52 D29
FBB_D51 FBB_CMD18
A20
FBB_ODT1 91
N27
FBVDDQ_33
FBA_D52 FBA_CMD19 FBA_CKE1 89 FBB_D52 FBB_CMD19 FBB_CKE1 91 FBVDDQ_34
FBA_D53 AL31 AC33 FBx_CMD22 A6 A6 FBB_D53 A29 B20 P27
C FBA_D54
FBA_D55
AK33
AK32
FBA_D53
FBA_D54
FBA_D55
FBA_CMD20
FBA_CMD21
FBA_CMD22
AA32
AA33
FBA_A13
FBA_A8
FBA_A6
88,89
88,89
88,89
FBx_CMD23 A11 A11 FBB_D54
FBB_D55
C29
B29
FBB_D53
FBB_D54
FBB_D55
FBB_CMD20
FBB_CMD21
FBB_CMD22
C18
B18
FBB_A13
FBB_A8
FBB_A6
90,91
90,91
90,91
R27
T27
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
C
FBA_D56 AD34 Y28 FBx_CMD24 A5 A5 FBB_D56 B21 G18 T30
FBA_D57 AD32
FBA_D56 FBA_CMD23
Y29
FBA_A11 88,89
FBx_CMD25 A3 A3 FBB_D57 C23
FBB_D56 FBB_CMD23
G17
FBB_A11 90,91
T33
FBVDDQ_38 Near GPU
FBA_D58 FBA_D57 FBA_CMD24 FBA_A5 88,89 FBB_D58 FBB_D57 FBB_CMD24 FBB_A5 90,91 FBVDDQ_39
AC30
FBA_D58 FBA_CMD25
W31
FBA_A3 88,89 FBx_CMD26 BA2 BA2 A21
FBB_D58 FBB_CMD25
F17
FBB_A3 90,91
V27
FBVDDQ_40 4.7uF(X5R) 10uF(X5R)
FBA_D59 AD33 Y30 FBB_D59 C21 D16 W27
FBA_D60 AF31
FBA_D59 FBA_CMD26
AA34
FBA_BA2 88,89 FBx_CMD27 BA1 BA1 FBB_D60 B24
FBB_D59 FBB_CMD26
A18
FBB_BA2 90,91
W30
FBVDDQ_41 K0603 ×2 M0805 ×2
FBA_D61 FBA_D60 FBA_CMD27 FBA_BA1 88,89 FBB_D61 FBB_D60 FBB_CMD27 FBB_BA1 90,91 FBVDDQ_42
AG34
FBA_D61 FBA_CMD28
Y31
FBA_A12 88,89 FBx_CMD28 A12 A12 C24
FBB_D61 FBB_CMD28
D17
FBB_A12 90,91
W33
FBVDDQ_43
FBA_D62 AG32 Y34 FBB_D62 B26 A17 Y27
FBA_D63 AG33
FBA_D62 FBA_CMD29
Y33
FBA_A10 88,89 FBx_CMD29 A10 A10 FBB_D63 C26
FBB_D62 FBB_CMD29
B17
FBB_A10 90,91 FBVDDQ_44
FBA_D63 FBA_CMD30 FBA_RAS# 88,89 FBx_CMD30 RAS# RAS# FBB_D63 FBB_CMD30 FBB_RAS# 90,91
V31 E17
FBA_CMD31 FBB_CMD31
FBx_CMD31 F1
FB_VDDQ_SENSE
88 FBA_DQM0 P30 R32 E11 C12
FBA_DQM0 FBA_CMD_RFU0 90 FBB_DQM0 FBB_DQM0 FBB_CMD_RFU0
88 FBA_DQM1 F31 AC32 E3 C20
FBA_DQM1 FBA_CMD_RFU1 90 FBB_DQM1 FBB_DQM1 FBB_CMD_RFU1
88 FBA_DQM2 F34 A3 F2 1D5V_VGA_S0
FBA_DQM2 90 FBB_DQM2 FBB_DQM2 FB_GND_SENSE
88 FBA_DQM3 M32 C9 1D5V_VGA_S0
FBA_DQM3 90 FBB_DQM3 FBB_DQM3
89 FBA_DQM4 AD31
FBA_DQM4 1D5V_VGA_S0 91 FBB_DQM4
F23
FBB_DQM4
OPS
AL29 F27 J27 FB_CAL_PD_VDDQ 1 2
89 FBA_DQM5 FBA_DQM5 91 FBB_DQM5 FBB_DQM5 FB_CAL_PD_VDDQ
AM32 C30 R8501 40D2R2F-GP
89 FBA_DQM6 FBA_DQM6 91 FBB_DQM6 FBB_DQM6
89 FBA_DQM7 AF34 R28 R8518 1 DY 260D4R2F-GP A24 G14 R8520 1 DY 2 60D4R2F-GP
FBA_DQM7 FBA_DEBUG0 91 FBB_DQM7 FBB_DQM7 FBB_DEBUG0
AC28 1 DY 2 G20 1 DY 2 H27 FB_CAL_PU_GND
FBA_DEBUG1 R8519 10KR2J-3-GP FBB_DEBUG1 R8521 10KR2J-3-GP FB_CAL_PU_GND
88 FBA_DQS_WP0 M31 90 FBB_DQS_WP0 D10

FBA_DQS_WP0 FBB_DQS_WP0
88 FBA_DQS_WP1 G31 90 FBB_DQS_WP1 D5 H25 FB_CAL_TERM_GND
FBA_DQS_WP1 FBB_DQS_WP1 FB_CAL_TERM_GND
88 FBA_DQS_WP2 E33 R30 90 FBB_DQS_WP2 C3 D12 OPS OPS
1
FBA_DQS_WP2 FBA_CLK0 FBA_CLK0 88 FBB_DQS_WP2 FBB_CLK0 FBB_CLK0 90
M33 R31 B9 E12
51D1R2F-GP
42D2R2F-GP
88 FBA_DQS_WP3 FBA_DQS_WP3 FBA_CLK0# FBA_CLK0# 88 90 FBB_DQS_WP3 FBB_DQS_WP3 FBB_CLK0# FBB_CLK0# 90
AE31 AB31 E23 E20 N13P-GS-A1-GP
89 FBA_DQS_WP4 FBA_DQS_WP4 FBA_CLK1 FBA_CLK1 89 91 FBB_DQS_WP4 FBB_DQS_WP4 FBB_CLK1 FBB_CLK1 91
AK30 AC31 E28 F20 OPS-BOM CTRL R8502 R8503
89 FBA_DQS_WP5 FBA_DQS_WP5 FBA_CLK1# FBA_CLK1# 89 91 FBB_DQS_WP5 FBB_DQS_WP5 FBB_CLK1# FBB_CLK1# 91
89 FBA_DQS_WP6 AN33 91 FBB_DQS_WP6 B30
FBA_DQS_WP6 FBB_DQS_WP6
AF33 A23
2
89 FBA_DQS_WP7 FBA_DQS_WP7 91 FBB_DQS_WP7 FBB_DQS_WP7
88 FBA_DQS_RN0 M30 K31 90 FBB_DQS_RN0 D9 F8

FBA_DQS_RN0 FBA_WCK1 FBB_DQS_RN0 FBB_WCK1
88 FBA_DQS_RN1 H30 L30 90 FBB_DQS_RN1 E4 E8
FBA_DQS_RN1 FBA_WCK1# FBB_DQS_RN1 FBB_WCK1#
88 FBA_DQS_RN2 E34
FBA_DQS_RN2 FBA_WCK23
H34 90 FBB_DQS_RN2 B2
FBB_DQS_RN2 FBB_WCK23
A5 Default GPU Drive Calibration for DDR3 (DG-05587-001_v03_p.82_Table 17)
88 FBA_DQS_RN3 M34 J34 90 FBB_DQS_RN3 A9 A6
89 FBA_DQS_RN4 AF30 AG30 91 FBB_DQS_RN4 D22 D24
89 FBA_DQS_RN5 AK31
FBA_DQS_RN5 FBA_WCK45#
AG31 91 FBB_DQS_RN5 D28
FBB_DQS_RN5 FBB_WCK45#
D25 Memory/PKG FBVDDQ FBCAL_PU_GND FBCAL_PU_VDDQ FBCAL_TERM_GND
89 FBA_DQS_RN6 AM34 AJ34 91 FBB_DQS_RN6 A30 B27
89 FBA_DQS_RN7 AF32 AK34 91 FBB_DQS_RN7 B23 C27
DDR3 1.5V 42.2Ω 40.2Ω 51.1Ω
B THE FBA_WCKBxx
FBA_WCKB1
FBA_WCKB1#
J30
J31 THE FBB_WCKBxx
FBB_WCKB1
FBB_WCKB1#
D6
D7 B
PINS ARE USED
FBA_WCKB23
J32 (DG-05587-001_v03_p.88_Table 25) PINS ARE USED
FBB_WCKB23
C6 *Use only 1% resistors for driver calibration.
ONLY ON GK107 J33 ONLY ON GK107 B6
FBA_WCKB23# 1D05V_VGA_S0 FBB_WCKB23#
AH31
THEY ARE NC
FOR GF108
FBA_WCKB45
AJ31
1.05V ±30mV 167mA total THEY ARE NC
FOR GF108
FBB_WCKB45
F26
E26 (DG-05587-001_v03_p.88_Table 25)
FBA_WCKB45# FBB_WCKB45#
AND FOR GF117
FBA_WCKB67
AJ32
66mA 100nF(X7R) OPS-BOM CTRL AND FOR GF117
FBB_WCKB67
A26
AJ33 R8523 A27
FBA_WCKB67# K0402 ×3 0R3J-0-U-GP FBB_WCKB67# 66mA
TP8507 1 FB_VREF H26 U27 FB_PLLVDD 1 2 H17 FB_PLLVDD
FB_VREF FBA_PLL_AVDD FBB_PLL_AVDD
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
N13P-GS-A1-GP N13P-GS-A1-GP
OPS-BOM CTRL OPS OPS OPS OPS-BOM CTRL
1
C8517 C8518 C8519

Stuff 0 ohm(63.00000.00L) for N13P-GS/N13M-GS,
2
Stuff bead(68.00084.H41) for N13P-GL/N13M-GE

FBCLK Termination placed at each VRAM (DG-05587-001_v03_p.83_Table 19)
FBx_PLL_AVDD, FB_DLL_AVDD and PLLVDD combined
(DG-05587-001_v03_p.88_Table 26) FBA_CLK1 FBA_CLK0 FBB_CLK1 FBB_CLK0
Under GPU
1
Capacitor Type Footprint Population Location R8504 R8505 R8506 R8507
160R2F-GP 160R2F-GP 160R2F-GP 160R2F-GP
OPS OPS OPS OPS
100nF X7R 0402 1 per pin Under GPU
22uF X5R 0805 1 Near GPU
2
FBA_CLK1# FBA_CLK0# FBB_CLK1# FBB_CLK0#
Bead Type
Memory ODTx, CKEx and RST Termination (DG-05587-001_v03_p.84_Table 20)
30Ω @100MHz
(ESR=0.01Ω) 0603 1 Near GPU
FBA_CKE0 FBB_CKE0
FBA_CKE1 FBB_CKE1
FBA_RST FBB_RST
X7R (+/-15%、-55~125℃) FBA_ODT0 FBB_ODT0
A X5R (+/-15%、-55~85℃) FBA_ODT1 FBB_ODT1

A
1
OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
R8508 R8509 R8510 R8511 R8512 R8513 R8514 R8515 R8516 R8517
<Core Design>
2
Wistron Corporation
Title
N13P_GPU (3/5): VRAM I/F

A2 SD
LA48
5 4 3 2 1
5 4 3 2 1
3D3V_VGA_S0 3D3V_VGA_S0
1D05V_VGA_S0
3
4
3
4
VGA1Q 17 OF 17 RN8606 RN8604 (DG-05587-001_v03_p.177_Table 95)
10/19 MISC1 SRN2K2J-1-GP SRN2K2J-1-GP
3D3V_VGA_S0
22uF(X5R) 100nF(X7R)
T4 SMBC_Therm_NV
I2CS_SCL SMBD_Therm_NV OPS OPS M0805 ×1 K0402 ×1
T3
I2CS_SDA 1.05V ±30mV 60mA 1 ( ( 2 PLLVDD
2
1
2
1
GPU_LVDS_CLK L8601
R2 I2CA=>CRT, I2CC=>LVDS.
SCD1U10V2KX-5GP
I2CC_SCL
SC4D7U6D3V3KX-GP
R3 GPU_LVDS_DATA BLM18KG300TN1D-GP
I2CC_SDA
3
4
OPS OPS
1
R7 I2CB_SCL_G3 RN8605 OPS
I2CB_SCL I2CB_SDA_G2 SRN4K7J-8-GP C8601 C8602
K4 R6
THERMDN I2CB_SDA
OPS
2
K3 RN8603 OPS
THERMDP Q8601
1 4 OPS
2
1
R8619 2 3 SMBC_Therm_NV 1 6 SMBC_Therm 27,28
1 DY 2 N13P_TCK AM10
TP8603 10KR2J-3-GP N13P_TMS JTAG_TCK SRN10KJ-5-GP
1 AP11 2 5
TP8604 N13P_TDI JTAG_TMS
TP8605
1
N13P_TDO
AM11
JTAG_TDI R8623
1 DY 2
10KR2J-3-GP
SMBD_Therm 27,28
1 AP12 3 4
N13P_TRST AN11 JTAG_TDO
1 OPS 2
JTAG_TRST# GPIO0
P6 NV_VID4 92
R8620 M3 NV_VID3 92 22uF(X5R) 4.7uF(X5R) 100nF(X7R)
GPIO1
D D
10KR2J-3-GP VGA_LBKLT_CTL SMBD_Therm_NV 2N7002KDW-GP
L6
GPIO2
P5 VGA_LCDVDD_EN 84.2N702.A3F 1 2 M0805 ×1 K0603 ×1 K0402 ×2 PLLVDD_PWR
GPIO3 VGA_BLEN L8602
P7 2nd = 84.DM601.03F 1.05V ±30mV 90mA total
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
GPIO4 BLM18PG181SN1D-GP VGA1O 15 OF 17
L7 NV_VID1 92
GPIO5 3D3V_VGA_S0
GPIO6
M7 NV_VID2 92 OPS (DG-05587-001_v03_p.177_Table 95) OPS OPS OPS OPS 11/17 XTAL_PLL
1
N8 RN8607
GPIO7 -VIDEO_THERM_OVERT C8604 C8605 C8606
M1 1 4
GPIO8 -VIDEO_THERM_ALERT
M2 2 3 AD8
2
GPIO9 PLLVDD
L1 AE8
GPIO10 SP_PLLVDD
GPIO11
M5 NV_VID0 92 SRN10KJ-5-GP
N3 N13P_GPIO12_H7 1 OPS 2 AD7 NC
GPIO12 R8611 10KR2J-3-GP VID_PLLVDD
M4 NV_VID5 92
GPIO13
R8 GF108/GKx GF117
GPIO16
P4 Near GPU Under GPU
GPIO20
GPIO21
P1 GPIO Description (DG-05587-001_v03_p.82_Tale 98)
3D3V_VGA_S0 VIDEO_CLK_XTAL_SS H1 J4 N12P_XTAL_OUTBUFF
XTAL_SSIN XTAL_OUTBUFF
Q8602 GPIO pin Normal Function PLL Power Rail Filter-PLL_VDD
1
Name Function I/O Description (DG-05587-001_v03_p.177_Table 96)
1 2 3V_VGA_S0_R G R8601 H3 H2 R8602
R2813 0R0402-PAD 10KR2J-3-GP XTAL_IN XTAL_OUT 10KR2J-3-GP
D PURE_HW_SHUTDOWN# 27,28,36GPIO0 GPU_VID4 O GPU Core VDD VID4 OPS N13P-GS-A1-GP OPS
N13P-GS-A1-GP Capacitor Type Footprint Population Location OPS-BOM CTRL
2
OPS-BOM CTRL -VIDEO_THERM_OVERT S GPIO1 GPU_VID3 O GPU Core VDD VID3 20PF 5% 50V +/-0.25PF 0402
GPIO2 LCD_BL_PWM O Panel Backlught PWM Brightness Control
2N7002K-2-GP GPIO3 LCD_VCC O Panel Power Enable 100nF X7R 0402 1 Under GPU 1 DY 2
R8603 1MR2F-GP
22uF X7R 0805 1 Near GPU
2
1st = 84.2N702.031 GPIO4 LCD_BLEN O panel Backlight Enale
2ND = 84.2N702.J31 R8604
GPIO5 GPU_VID1 O GPU Core VDD VID1
OPS GPIO6 GPU_VID2 O GPU Core VDD VID2 Bead Type 0R2J-2-GP
X8601
XTAL-27MHZ-46-GP OPS
GPIO7 3D Vision O 3D Vision Left/Right signal
1
30Ω(ESR=0.05) 0402 1 Near GPU X8601_GND 4 3 27MHZ_OUT_R
GPIO8 OVERT I/O Active Low Thermal Catastrophic Over Temperature
GPIO9 ALERT I/O Active Low Thermal Alert 27MHZ_IN 1 2 X8601_GND
2
GPIO10 MEM_VREF_CTL O Memory VREF Control X7R (+/-15%、-55~125℃)
1
82.30034.351 R8636 C8608
GPIO11 GPU_VID0 O GPU Core VDD VID0 OPS 0R2J-2-GP SC15P50V2JN-2-GP
1
C8607 OPS
GPIO12 PWR_LEVEL I AC Power Detect Input. High = AC, Low = Battery DY
2
SC12P50V2JN-3GP
1
GPIO13 GPU_VID5 O GPU Core VDD VID5 PLL Power Rail Filter-SP_PLLVDD and VIDPLLVDD Combined OPS
2
GPIO14 HPD_AB I Hot Plog Detect for IFPAB (DG-05587-001_v03_p.178_Table 97)
GPIO15 HPD_C I Hot Plog Detect for IFPC R8636 is reserved for Metal Xtal
GPIO16 MEM_VDD_CTL O Memory VDD VID
GPIO17 HPD_D I Hot Plog Detect for IFPD Capacitor Type Footprint Population Location SPEC. (DG-05587-001_v03_p.176)
GPIO18 HPD_E I Hot Plog Detect for IFPE XTALOUTBUFF signal should be pull down using a 10kΩ resistor.
GPIO19 HPD_F I Hot Plog Detect for IFPF 100nF X7R 0402 2 Under GPU XTALSSIN signal should be pull down using a 10kΩ resistor.
GPIO20 Reserved 4.7uF X7R 0402 1 Near GPU REmember to place components as close ti the GPU as possible.
GPIO21 Reserved 22uF X7R 0805 1 Near GPU
Bead Type
180Ω(ESR=0.2) 0603 1 Near GPU
C X7R (+/-15%、-55~125℃) C
SPEC. (DG-05587-001_v03_p.162)
Adding a pull down to the DACA_VDD with a 10kΩ resistor to GND.
3D3V_VGA_S0 3D3V_VGA_S0
All other DAC I/O pins (including DACA_VREF, DACA_REST)
can be left floating. The GB4-128 package is available in a 29 mm × 29mm footprint.
128-bit memory interfaces respectively.
3
4
1
VGA1P 16 OF 17
RN8601 12/17 MISC2 R8624 R8626
SRN2K2J-1-GP 2KR2F-3-GP 15KR2F-GP Recommended NVVDD Voltage Regulator Phase Coount
1
VGA1N 14 OF 17 DY OPS-BOM CTRL
4/17 DACA
OPS
2
R8625 GPU SKU Phase Count Target
2
1
GF108/GKx GF117 GF117 GF108/GKx 10KR2F-2-GP

H6
DACA_VDD VGA_CRT_DDCCLK ROM_CS#
AG10 NC NC R4 DY
2
DACA_VDD I2CA_SCL
2
R5 VGA_CRT_DDCDATA H5 ROM_SI_H5 N13M-GE1 Single phase

NC I2CA_SDA ROM_SI
R8629 TP8620 1DACA_VREF AP9 H7 ROM_SO_H7
DACA_VREF TSEN_VREF ROM_SO N13M-GS Two phase
10KR2J-3-GP STRAP0 J2 H4 ROM_SLK_H4
STRAP0 ROM_SCLK
1
OPS TP8621 1DACA_RSET AP8
DACA_RSET NC NC DACA_HSYNC
AM9 VGA_CRT_HSYNC 1 TP8611 STRAP1 J7
STRAP1
N13P-GL Two phase
AN9 VGA_CRT_VSYNC 1 TP8612 STRAP2 J6 R8618
NC N13P-GS Two phase
1
DACA_VSYNC STRAP2
1
STRAP3 J5 15KR2F-GP
STRAP4 STRAP3 R8617
J3
STRAP4 OPS-BOM CTRL
AK9 VGA_CRT_RED 1 TP8613 R8627 30KR2F-GP
NC
2
DACA_RED 15KR2F-GP OPS-BOM CTRL
VGA_CRT_GREEN TP8614 OPS-BOM CTRL
NC AL10 1 29 x 29 PACKAGE
2
DACA_GREEN
NC DACA_BLUE
AL9 VGA_CRT_BLUE
BUFRST#
L2 V: N13P-GS/GL (25~30W)
B: N13M-GS/GE (15~20W)
N13P-GS-A1-GP
MULTI_STRAP_REF2_GND J1 L3
MULTI_STRAP_REF0_GND CEC
1
RN8602 128Mx16:
OPS-BOM CTRL VGA_CRT_BLUE 1 8 OPS 3D3V_VGA_S0
VGA_CRT_GREEN 2 7 R8313
VGA_CRT_RED 3 6 40K2R2F-GP R8628 hynix - H5TQ2G63BFR-11C
4 5 CEC_L3 1 2
2
10KR2F-2-GP Samsung - K4W2G1646C-HC11

SRN75J-1-GP OPS-BOM CTRL
OPS N13P-GS-A1-GP L3 (DA-05691-001_v04_p.3_Table 2)
SPEC. (DG-05587-001_v03_p.191_Table 102) 64Mx16:
N13P-GL 10kΩ pull-up to 3.3V
Multi_Strap_Ref0_GND 40.2kΩ 1% toOPS-BOM
GND CTRL
N13M_GE1 NC Hynix - H5TQ1G63DFR-11C
N13M-GS NC Samsung - K4W1G1646G-BC11
B N13P-GS NC
B
TABLE VIDEO MEMORY
HYNIX SAMSUNG HYNIX Samsung

128Mx16 128Mx16 64Mx16 64Mx16
0110 0111 0010 0011
900MHz 72.52G63.A0U 72.42164.D0U 72.51G63.H0U 72.41164.Q0U

1-007155 1-007156 1-007157 1-007356
ROM_SI
PD 34.8Kohm 45.3Kohm 15Kohm 20Kohm
64.34825.6DL 64.45325.6DL 64.15025.6DL 64.20025.6DL
R8627
TABLE N12P-GE N12P-GV N12M-GE

NVIDIA DEV ID: DEV ID: DEV ID:
0xDF5 0x0DF7(ES) 0xA7A 3D3V_VGA_S0
0101 1010 20100702_NV 3D3V_VGA_S0
35Kohm
1
STRAP1 R8632 DY DY
1
64.34825.6DL R8630 R8632 R8634

45K3R2F-L-GP 34K8R2F-1-GP 45K3R2F-L-GP R8314 R8316
35Kohm 35Kohm OPS DY OPS-BOM CTRL 45K3R2F-L-GP 34K8R2F-1-GP
R8633 DY DY DY
2
64.34825.6DL 64.34825.6DL STRAP0

2
STRAP1 STRAP3
45Kohm 15Kohm STRAP2 STRAP4
STRAP2 R8634 DY
1
64.45325.6DL 64.15025.6DL R8631

2KR2F-3-GP R8633 R8635 R8315 R8317
30Kohm DY 34K8R2F-1-GP 30KR2F-GP 5K1R2F-2-GP 20KR2F-L-GP
R8635 DY DY OPS-BOM CTRL DY OPS-BOM CTRL OPS-BOM CTRL
64.30025.6DL
2
A A
<Core Design>
Wistron Corporation
Title
N13P_GPU (4/5): GPIO/STRAP

A1 SD
LA48
5 4 VGA_CORE
3 2 1
VGA1F 6 OF 17 VGA1I 9 OF 17 VGA1H 8 OF 17 VGA1E 5 OF 17
http://laptopblue.vn AA12
AA14
13/17 NVVDD
VDD_1
VDD_2
A2
AA17
AA18
GND_1
GND_5
GND_6
15/17 GND_1/2
GND_71
GND_72
GND_73
AM25
AN1
AN10
N19
N2
GND_141
GND_142
16/17 GND_2/2
GND_170
GND_171
T28
T32
9/17 XVDD
CONFIGURABLE
POWER
AA16 AA20 AN13 N21 T5 CHANNELS
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
VDD_3 GND_7 GND_74 GND_143 GND_172
AA19 VDD_4 AA22 GND_8 GND_75 AN16 N23 GND_144 GND_173 T7 XVDD_1 U1
OPS DY OPS DY OPS DY OPS OPS AA21 VDD_5 AB12 GND_9 GND_76 AN19 N28 GND_145 GND_174 U12 XVDD_2 U2
1
4.7uF(X5R) AA23 VDD_6 AB14 GND_10 GND_77 AN22 N30 GND_146 GND_175 U14 XVDD_3 U3
C8701 C8702 C8703 C8704 C8705 C8706 C8707 C8708 AB13 AB16 AN25 N32 U16 U4
K0603 ×15 AB15
VDD_7
AB19
GND_11 GND_78
AN30 N33
GND_147 GND_176
U19
XVDD_4
U5
2
VDD_8 GND_12 GND_79 GND_148 GND_177 XVDD_5
AB17 VDD_9 AB2 GND_13 GND_80 AN34 N5 GND_149 GND_178 U21 XVDD_6 U6
AB18 VDD_10 AB21 GND_14 GND_81 AN4 N7 GND_150 GND_179 U23 XVDD_7 U7
D AB20
AB22
VDD_11 A33
AB23
GND_2 GND_82 AN7
AP2
P13
P15
GND_151 GND_180 V12
V14
XVDD_8 U8 D
AC12 VDD_13 AB28 GND_16 GND_84 AP33 P17 GND_153 GND_182 V16
AC14 VDD_14 AB30 GND_17 GND_85 B1 P18 GND_154 GND_183 V19 XVDD_9 V1
AC21 VDD_17 AB7 GND_20 GND_88 B25 R12 GND_157 GND_186 W13 XVDD_12 V4
AC23 AC13 B28 R14 W15 V5
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
VDD_18 GND_21 GND_89 GND_158 GND_187 XVDD_13
M12 VDD_19 AC15 GND_22 GND_90 B31 R16 GND_159 GND_188 W17 XVDD_14 V6
OPS DY OPS DY OPS OPS OPS M14 VDD_20 AC17 GND_23 GND_91 B34 R19 GND_160 GND_189 W18 XVDD_15 V7
1
M16 VDD_21 AC18 GND_24 GND_92 B4 R21 GND_161 GND_190 W20 XVDD_16 V8
C8709 C8710 C8711 C8712 C8713 C8714 C8715 M19 AA13 B7 R23 W22
M21 AC20 C10 T13 W28
2
M23 VDD_24 AC22 GND_26 GND_95 C13 T15 GND_164 GND_193 Y12 XVDD_17 W2
N13 VDD_25 AE2 GND_27 GND_96 C19 T17 GND_165 GND_194 Y14 XVDD_18 W3
N22 VDD_30 AE5 GND_32 GND_101 D2
P12 VDD_31 AE7 GND_33 GND_102 D31
P14 VDD_32 AH10 GND_34 GND_103 D33
P16 AA15 E10
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VDD_33 GND_4 GND_104
P19 VDD_34 AH13 GND_35 GND_105 E22 XVDD_23 Y1
OPS DY OPS DY OPS DY OPS DY P21 VDD_35 AH16 GND_36 GND_106 E25 XVDD_24 Y2
1
1
0.1uF(X7R) P23 VDD_36 AH19 GND_37 GND_107 E5 AG11 GND_F GND_H AH11 XVDD_25 Y3
C8716 C8717 C8718 C8719 C8720 C8721 C8722 C8723 R13 AH2 E7 Y4
K0402 ×8 R15
VDD_37
AH22
GND_38 GND_108
F28
XVDD_26
Y5
2
2
VDD_38 GND_39 GND_109 XVDD_27
R17 VDD_39 AH24 GND_40 GND_110 F7 XVDD_28 Y6
C R18
R20
VDD_40 AH28
AH29
GND_41 GND_111 G10
G13
XVDD_29 Y7
Y8
C
VDD_41 GND_42 GND_112 XVDD_30
R22 VDD_42 AH30 GND_43 GND_113 G16
T12 VDD_43 AH32 GND_44 GND_114 G19
Under GPU T14 VDD_44 AH33 GND_45 GND_115 G2 GND_OPT_1 C16 XVDD_31 AA1
T16 VDD_45 AH5 GND_46 GND_116 G22 GND_OPT_2 W32 XVDD_32 AA2
T19 VDD_46 AH7 GND_47 GND_117 G25 XVDD_33 AA3
T21 VDD_47 AJ7 GND_48 GND_118 G28 Optional CMD GNDs (2)
XVDD_34 AA4
T23 VDD_48 AK10 GND_49 GND_119 G3 NC for 4-Lyr cards
XVDD_35 AA5
U13 AK7 G30 AA6
SC22U6D3V5MX-2GP
VDD_49 GND_50 GND_120 N13P-GS-A1-GP XVDD_36

U15 VDD_50 AL12 GND_51 GND_121 G32 XVDD_37 AA7
22uF(X5R) OPS 47uF(X5R) U17 VDD_51 AL14 GND_52 GND_122 G33 OPS-BOM CTRL XVDD_38 AA8
1
U18 AL15 G5
M0805 ×1 C8724 M0805 ×1 U20
VDD_52
AL17
GND_53 GND_123
G7 N13P-GS-A1-GP
U22 AL18 K2 OPS-BOM CTRL
2

V13 VDD_55 AL2 GND_56 GND_126 K28
V15 VDD_56 AL20 GND_57 GND_127 K30
V17 VDD_57 AL21 GND_58 GND_128 K32
V18 VDD_58 AL23 GND_59 GND_129 K33
V20 VDD_59 AL24 GND_60 GND_130 K5
V22 VDD_60 AL26 GND_61 GND_131 K7
W12 VDD_61 AL28 GND_62 GND_132 M13
W14 VDD_62 AL30 GND_63 GND_133 M15
W16 VDD_63 AL32 GND_64 GND_134 M17
W19 VDD_64 AL33 GND_65 GND_135 M18
W21 VDD_65 AL5 GND_66 GND_136 M20
4.7uF(X5R) W23 VDD_66 AM13 GND_67 GND_137 M22
Y13 AM16 N12
K0805 ×5 Y15
VDD_67
AM19
GND_68 GND_138
N14
Y17 AM22 N16
B Y18
VDD_69
VDD_70
GND_70 GND_140 B
Y20 VDD_71
Y22 VDD_72
NVVDD Decoupling Requirement N13P-GS-A1-GP
(DG-05587-001_v03_p.56_Table 7) OPS-BOM CTRL
N13P-GS-A1-GP
OPS-BOM CTRL VDD33 Decoupling (DG-05587-001_v03_p.57_Table 8)
4.7uF X6S 0603 15 10 Under GPU 0.1uF(X7R) 1uF(X5R) 4.uF(X5R) 3D3V_VGA_S0
0.1uF X7R 0402 8 4 Under GPU K0402 ×3 K0402 ×2 K0603 ×2 0.1uF X7R 0402 3 3 Under GPU
47uF X5R 0805 1 1 Near GPU VGA1G 7 OF 17 1uF X5R 0402 2 2 Near GPU
22uF X5R 0805 1 1 Near GPU 17/17 NC/VDD33 4.7uF X5R 0603 1 1 Near GPU
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
4.7uF X5R 0805 5 5 Near GPU AC6 J8
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
NC#AC6 VDD33_1
AJ28 NC#AJ28 VDD33_2 K8 OPS OPS OPS OPS OPS OPS X7R (+/-15%、-55~125℃)
1
1
AJ4 L8
X7R (+/-15%、-55~125℃) AJ5
NC#AJ4 VDD33_3
M8 C8731 C8732 C8733 C8734 C8735 C8736 X5R (+/-15%、-55~85℃)
NC#AJ5 VDD33_4
AL11
X6S (+/-22%、-55~105℃)
2
2
NC#AL11
C15 NC#C15
X5R (+/-15%、-55~85℃) D19 NC#D19
D20 NC#D20
D23 NC#D23
D26 NC#D26
H31 NC#H31 Under GPU Near GPU
T8
A V32
NC#T8
NC#V32
<Core Design>
A
Wistron Corporation
N13P-GS-A1-GP 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
OPS-BOM CTRL Title
N13P_GPU (5/5): PWR/GND

A3 SD
LA48
A B C D E
VIDEO FRAME BUFFER PORT A

1D5V_VGA_S0
VRAM1
http://laptopblue.vn FBA_D[63..0] 85,89
1D5V_VGA_S0
VRAM2
FBA_D[63..0] 85,89
K8 E3 FBA_D11 K8 E3 FBA_D23
VDD DQL0 FBA_D13 VDD DQL0 FBA_D22
K2 VDD DQL1 F7 K2 VDD DQL1 F7
N1 F2 FBA_D9 N1 F2 FBA_D21
R9 VDD DQL3 F8 R9 VDD DQL3 F8 128 X 16
B2 H3 FBA_D8 B2 H3 FBA_D16
D9
VDD DQL4
H8 FBA_D15 D9
VDD DQL4
H8 FBA_D17 72.52G63.A0U
VDD DQL5 VDD DQL5
G7 VDD DQL6 G2 FBA_D10 G7 VDD DQL6 G2 FBA_D18 72.42164.D0U IC VRAM K4W2G1646C-HC11 FBGA96
R1 H7 FBA_D14 R1 H7 FBA_D19
VDD DQL7 VDD DQL7
4 N9 VDD N9 VDD 4
D7 FBA_D3 D7 FBA_D26 64 X 16
DQU0 FBA_D5 DQU0 FBA_D25
A8 VDDQ DQU1 C3 A8 VDDQ DQU1 C3 72.51G63.H0U IC VRAM H5TQ1G63DFR-11C FBGA 96BALLS
A1 C8 FBA_D0 A1 C8 FBA_D31
VDDQ DQU2 FBA_D6 VDDQ DQU2 FBA_D28 72.41646.Q0U IC VRAM K4W1G1646G-BC11 FBGA 96BALLS
C1 VDDQ DQU3 C2 C1 VDDQ DQU3 C2
C9 A7 FBA_D2 C9 A7 FBA_D29
VDDQ DQU4 FBA_D7 VDDQ DQU4 FBA_D27
D2 VDDQ DQU5 A2 D2 VDDQ DQU5 A2
E9 B8 FBA_D1 E9 B8 FBA_D30
F1 VDDQ DQU7 A3 F1 VDDQ DQU7 A3
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 FBA_DQS_W P0 85 H2 VDDQ DQSU C7 FBA_DQS_W P3 85
DQSU# B7 FBA_DQS_RN0 85 DQSU# B7 FBA_DQS_RN3 85
FBA_VREF_0 H1 FBA_VREF_0 H1
VREFDQ VREFDQ
M8 VREFCA DQSL F3 FBA_DQS_W P1 85 M8 VREFCA DQSL F3 FBA_DQS_W P2 85
VRAM_CH_A_ZQ_1 L8 G3 VRAM_CH_A_ZQ_2 L8 G3
243R2F-2-GP
ZQ DQSL# FBA_DQS_RN1 85 ZQ DQSL# FBA_DQS_RN2 85
243R2F-2-GP
1
1
OPS ODT K1 FBA_ODT0 85 OPS ODT K1 FBA_ODT0 85
85,89 FBA_A0 N3 A0 85,89 FBA_A0 N3 A0
R8801 85,89 FBA_A1 P7 R8802 85,89 FBA_A1 P7
A1 A1
85,89 FBA_A2 P3 A2 CS# L2 FBA_CS0# 85 85,89 FBA_A2 P3 A2 CS# L2 FBA_CS0# 85
85,89 FBA_A3 N2 T2 FBA_RST 85,89 85,89 FBA_A3 N2 T2 FBA_RST 85,89
2
2
A3 RESET# A3 RESET#
85,89 FBA_A4 P8 A4 85,89 FBA_A4 P8 A4
85,89 FBA_A5 P2 A5 85,89 FBA_A5 P2 A5
85,89 FBA_A6 R8 A6 NC#T7 T7 85,89 FBA_A6 R8 A6 NC#T7 T7
85,89 FBA_A7 R2 A7 NC#L9 L9 85,89 FBA_A7 R2 A7 NC#L9 L9
85,89 FBA_A8 T8 A8 NC#L1 L1 85,89 FBA_A8 T8 A8 NC#L1 L1
85,89 FBA_A9 R3 A9 NC#J9 J9 85,89 FBA_A9 R3 A9 NC#J9 J9
85,89 FBA_A10 L7 A10/AP NC#J1 J1 85,89 FBA_A10 L7 A10/AP NC#J1 J1
85,89 FBA_A11 R7 A11 85,89 FBA_A11 R7 A11
3 N7 N7 128Mx16: 3
85,89 FBA_A12 A12/BC# 85,89 FBA_A12 A12/BC#
85,89 FBA_A13 T3 A13 VSS J8 85,89 FBA_A13 T3 A13 VSS J8
85,89 FBA_A15 M7 A15 VSS M1 85,89 FBA_A15 M7 A15 VSS M1
VSS M9 VSS M9 hynix - H5TQ2G63BFR-11C
J2 J2
FB CMD mapping85,89 FBA_BA0 M2 BA0
VSS
VSS P9 FB CMD mapping85,89 FBA_BA0 M2 BA0
VSS
VSS P9
Samsung - K4W2G1646C-HC11
85,89 FBA_BA1 N8 G8 85,89 FBA_BA1 N8 G8
Mode D-N13x 85,89 FBA_BA2 M3
BA1
BA2
VSS
VSS B3 Mode D-N13x 85,89 FBA_BA2 M3
BA1
BA2
VSS
VSS B3 64Mx16:
VSS T1 VSS T1
VSS A9 VSS A9
85 FBA_CLK0 J7 CK VSS T9 85 FBA_CLK0 J7 CK VSS T9 Hynix - H5TQ1G63DFR-11C
K7 E1 K7 E1
85 FBA_CLK0# CK# VSS
P1
85 FBA_CLK0# CK# VSS
P1
Samsung - K4W1G1646G-BC11
VSS VSS
85 FBA_CKE0 K9 CKE 85 FBA_CKE0 K9 CKE
VSSQ G1 VSSQ G1
VSSQ F9 VSSQ F9
85 FBA_DQM0 D3 DMU VSSQ E8 85 FBA_DQM3 D3 DMU VSSQ E8
85 FBA_DQM1 E7 DML VSSQ E2 85 FBA_DQM2 E7 DML VSSQ E2
VSSQ D8 VSSQ D8
VSSQ D1 VSSQ D1
85,89 FBA_W E# L3 WE# VSSQ B9 85,89 FBA_W E# L3 WE# VSSQ B9
85,89 FBA_CAS# K3 CAS# VSSQ B1 85,89 FBA_CAS# K3 CAS# VSSQ B1
85,89 FBA_RAS# J3 RAS# VSSQ G9 85,89 FBA_RAS# J3 RAS# VSSQ G9
H5TQ1G63BFR-12C-GP H5TQ1G63BFR-12C-GP
BOM CTRL BOM CTRL
2 2
Combined Memory FBVDD/Q Decoupling DDR3×16 with Clamshell Layout

0.1uF(X7R)
1D5V_VGA_S0 (DG-05587-001_v03_p.87_Table 23)
K0402 ×4
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
0.1uF X7R 0402 4 Close to VRAM

OPS OPS OPS OPS 1D5V_VGA_S0
1uF X7R 0603 8 Close to VRAM
1
C8801 C8802 C8803 C8804

X7R (+/-15%、-55~125℃)
1K33R2F-GP
2
1
*Per clamshell pair OPS
R8803
1.0uF(X7R)
2
K0603 ×8
FBA_VREF_0
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SCD01U50V2KX-1GP
1K33R2F-GP
1 <Core Design> 1
1
1
C8805 C8806 C8807 C8808 C8809 C8810 C8811 C8812 R8804 C8813
Wistron Corporation
2

2
Title
CHANNEL-A_VRAM1,2 (1/4)
Close to VRAM(For VRAM1 & VRAM2) A3 SD
LA48
A B C D E
A B C D E
VIDEO FRAME BUFFER PORT A

1D5V_VGA_S0
VRAM3
http://laptopblue.vn FBA_D[63..0] 85,88
1D5V_VGA_S0
VRAM4
FBA_D[63..0] 85,88
K8 E3 FBA_D35 K8 E3 FBA_D44
K2 VDD DQL1 F7 K2 VDD DQL1 F7
N1 F2 FBA_D33 N1 F2 FBA_D47
R9 VDD DQL3 F8 R9 VDD DQL3 F8
B2 H3 FBA_D32 B2 H3 FBA_D42
D9 VDD DQL5 H8 D9 VDD DQL5 H8
G7 G2 FBA_D36 G7 G2 FBA_D46
R1 VDD DQL7 H7 R1 VDD DQL7 H7
4 N9 VDD N9 VDD 4
D7 FBA_D49 D7 FBA_D56
DQU0 FBA_D54 DQU0 FBA_D62
A8 VDDQ DQU1 C3 A8 VDDQ DQU1 C3
A1 C8 FBA_D48 A1 C8 FBA_D61
C1 VDDQ DQU3 C2 C1 VDDQ DQU3 C2
C9 A7 FBA_D51 C9 A7 FBA_D57
D2 VDDQ DQU5 A2 D2 VDDQ DQU5 A2
E9 B8 FBA_D50 E9 B8 FBA_D58
F1 VDDQ DQU7 A3 F1 VDDQ DQU7 A3
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 FBA_DQS_W P6 85 H2 VDDQ DQSU C7 FBA_DQS_W P7 85
DQSU# B7 FBA_DQS_RN6 85 DQSU# B7 FBA_DQS_RN7 85
FBA_VREF_1 H1 FBA_VREF_1 H1
VREFDQ VREFDQ
M8 VREFCA DQSL F3 FBA_DQS_W P4 85 M8 VREFCA DQSL F3 FBA_DQS_W P5 85
VRAM_CH_A_ZQ_3 L8 G3 VRAM_CH_A_ZQ_4 L8 G3
ZQ DQSL# FBA_DQS_RN4 85 ZQ DQSL# FBA_DQS_RN5 85
243R2F-2-GP
243R2F-2-GP
OPS ODT K1 FBA_ODT1 85 OPS ODT K1 FBA_ODT1 85
1
1
85,88 FBA_A0 N3 A0 85,88 FBA_A0 N3 A0
85,88 FBA_A1 P7 A1 85,88 FBA_A1 P7 A1
R8901 85,88 FBA_A2 P3 L2 FBA_CS1# 85 R8902 85,88 FBA_A2 P3 L2 FBA_CS1# 85
A2 CS# A2 CS#
85,88 FBA_A3 N2 A3 RESET# T2 FBA_RST 85,88 85,88 FBA_A3 N2 A3 RESET# T2 FBA_RST 85,88
85,88 FBA_A4 P8 85,88 FBA_A4 P8
2
2
A4 A4
85,88 FBA_A5 P2 A5 85,88 FBA_A5 P2 A5
85,88 FBA_A6 R8 A6 NC#T7 T7 85,88 FBA_A6 R8 A6 NC#T7 T7
85,88 FBA_A7 R2 A7 NC#L9 L9 85,88 FBA_A7 R2 A7 NC#L9 L9
85,88 FBA_A8 T8 A8 NC#L1 L1 85,88 FBA_A8 T8 A8 NC#L1 L1
85,88 FBA_A9 R3 A9 NC#J9 J9 85,88 FBA_A9 R3 A9 NC#J9 J9
85,88 FBA_A10 L7 A10/AP NC#J1 J1 85,88 FBA_A10 L7 A10/AP NC#J1 J1
85,88 FBA_A11 R7 A11 85,88 FBA_A11 R7 A11
3 N7 N7 3
85,88 FBA_A12 A12/BC# 85,88 FBA_A12 A12/BC#
85,88 FBA_A13 T3 A13 VSS J8 85,88 FBA_A13 T3 A13 VSS J8
85,88 FBA_A15 M7 A15 VSS M1 85,88 FBA_A15 M7 A15 VSS M1
VSS M9 VSS M9
J2 J2
FB CMD mapping85,88 FBA_BA0 M2 BA0
VSS
VSS P9 FB CMD mapping85,88 FBA_BA0 M2 BA0
VSS
VSS P9
85,88 FBA_BA1 N8 G8 85,88 FBA_BA1 N8 G8
Mode D-N13x 85,88 FBA_BA2 M3
BA1
BA2
VSS
VSS B3 Mode D-N13x 85,88 FBA_BA2 M3
BA1
BA2
VSS
VSS B3
VSS T1 VSS T1
VSS A9 VSS A9
85 FBA_CLK1 J7 CK VSS T9 85 FBA_CLK1 J7 CK VSS T9
85 FBA_CLK1# K7 CK# VSS E1 85 FBA_CLK1# K7 CK# VSS E1
VSS P1 VSS P1
85 FBA_CKE1 K9 CKE 85 FBA_CKE1 K9 CKE
VSSQ G1 VSSQ G1
VSSQ F9 VSSQ F9
85 FBA_DQM6 D3 DMU VSSQ E8 85 FBA_DQM7 D3 DMU VSSQ E8
85 FBA_DQM4 E7 DML VSSQ E2 85 FBA_DQM5 E7 DML VSSQ E2
VSSQ D8 VSSQ D8
VSSQ D1 VSSQ D1
85,88 FBA_W E# L3 WE# VSSQ B9 85,88 FBA_W E# L3 WE# VSSQ B9
85,88 FBA_CAS# K3 CAS# VSSQ B1 85,88 FBA_CAS# K3 CAS# VSSQ B1
85,88 FBA_RAS# J3 RAS# VSSQ G9 85,88 FBA_RAS# J3 RAS# VSSQ G9
H5TQ1G63BFR-12C-GP H5TQ1G63BFR-12C-GP
BOM CTRL BOM CTRL
2 2

0.1uF(X7R)
K0402 ×4
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

1
C8901 C8902 C8903 C8904

X7R (+/-15%、-55~125℃)
1K33R2F-GP
2
1
R8903
1.0uF(X7R)
2
K0603 ×8
FBA_VREF_1
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SCD01U50V2KX-1GP
1K33R2F-GP
1 <Core Design> 1
1
1
C8905 C8906 C8907 C8908 C8909 C8910 C8911 C8912 R8904 C8913
Wistron Corporation
2

2
Title
CHANNEL-A_VRAM3,4 (2/4)
LA48
A B C D E
A B C D E
VIDEO FRAME BUFFER PORT C

1D5V_VGA_S0
K8
VRAM5
VDD DQL0 E3
FBB_D1
FBB_D[63..0] 85,91
1D5V_VGA_S0
K8
K2
VRAM6
VDD
VDD
DQL0
DQL1
E3
F7
FBB_D29
FBB_D31
FBB_D[63..0] 85,91
K2 F7 FBB_D3 N1 F2 FBB_D28
VDD DQL1 FBB_D0 VDD DQL2 FBB_D24
N1 VDD DQL2 F2 R9 VDD DQL3 F8
R9 F8 FBB_D2 B2 H3 FBB_D27
B2 VDD DQL4 H3 D9 VDD DQL5 H8
D9 H8 FBB_D4 G7 G2 FBB_D25
G7 VDD DQL6 G2 R1 VDD DQL7 H7
R1 H7 FBB_D6 N9
VDD DQL7 VDD FBB_D20
N9 VDD DQU0 D7
4 D7 FBB_D13 A8 C3 FBB_D17 4
DQU0 FBB_D11 VDDQ DQU1 FBB_D23
A8 VDDQ DQU1 C3 A1 VDDQ DQU2 C8
A1 C8 FBB_D14 C1 C2 FBB_D18
VDDQ DQU2 FBB_D10 VDDQ DQU3 FBB_D21
C1 VDDQ DQU3 C2 C9 VDDQ DQU4 A7
C9 A7 FBB_D12 D2 A2 FBB_D16
D2 VDDQ DQU5 A2 E9 VDDQ DQU6 B8
E9 B8 FBB_D15 F1 A3 FBB_D19
VDDQ DQU6 FBB_D9 VDDQ DQU7
F1 VDDQ DQU7 A3 H9 VDDQ
H9 VDDQ H2 VDDQ DQSU C7 FBB_DQS_W P2 85
H2 VDDQ DQSU C7 FBB_DQS_W P1 85 DQSU# B7 FBB_DQS_RN2 85
B7 FBB_VREF_0 H1
DQSU# FBB_DQS_RN1 85 VREFDQ
FBB_VREF_0 H1 M8 F3
VREFDQ VREFCA DQSL FBB_DQS_W P3 85
M8 F3 VRAM_CH_C_ZQ_2 L8 G3
VREFCA DQSL FBB_DQS_W P0 85 ZQ DQSL# FBB_DQS_RN3 85
VRAM_CH_C_ZQ_1 L8 G3
243R2F-2-GP
243R2F-2-GP
ZQ DQSL# FBB_DQS_RN0 85
OPS ODT K1 FBB_ODT0 85
1
1
OPS ODT K1 FBB_ODT0 85 85,91 FBB_A0 N3 A0
85,91 FBB_A0 N3 A0 85,91 FBB_A1 P7 A1
R9001 85,91 FBB_A1 P7 R9002 85,91 FBB_A2 P3 L2 FBB_CS0# 85
A1 A2 CS#
85,91 FBB_A2 P3 A2 CS# L2 FBB_CS0# 85 85,91 FBB_A3 N2 A3 RESET# T2 FBB_RST 85,91
85,91 FBB_A3 N2 T2 FBB_RST 85,91 85,91 FBB_A4 P8
2
2
A3 RESET# A4
85,91 FBB_A4 P8 A4 85,91 FBB_A5 P2 A5
85,91 FBB_A5 P2 A5 85,91 FBB_A6 R8 A6 NC#T7 T7
85,91 FBB_A6 R8 A6 NC#T7 T7 85,91 FBB_A7 R2 A7 NC#L9 L9
85,91 FBB_A7 R2 A7 NC#L9 L9 85,91 FBB_A8 T8 A8 NC#L1 L1
85,91 FBB_A8 T8 A8 NC#L1 L1 85,91 FBB_A9 R3 A9 NC#J9 J9
85,91 FBB_A9 R3 A9 NC#J9 J9 85,91 FBB_A10 L7 A10/AP NC#J1 J1
85,91 FBB_A10 L7 A10/AP NC#J1 J1 85,91 FBB_A11 R7 A11
85,91 FBB_A11 R7 A11 85,91 FBB_A12 N7 A12/BC#
85,91 FBB_A12 N7 A12/BC# 85,91 FBB_A13 T3 A13 VSS J8
3 T3 J8 M7 M1 3
85,91 FBB_A13 A13 VSS 85,91 FBB_A15 A15 VSS
85,91 FBB_A15 M7 A15 VSS M1 VSS M9
M9 J2
VSS
J2 FB CMD mapping85,91 M2
VSS
P9
FB CMD mapping85,91 FBB_BA0 M2
VSS
P9 85,91
FBB_BA0
FBB_BA1 N8
BA0 VSS
G8
85,91 FBB_BA1 N8
BA0 VSS
G8 Mode D-N13x 85,91 FBB_BA2 M3
BA1 VSS
B3
Mode D-N13x 85,91 FBB_BA2 M3
BA1
BA2
VSS
VSS B3
BA2 VSS
VSS T1
VSS T1 VSS A9
VSS A9 85 FBB_CLK0 J7 CK VSS T9
85 FBB_CLK0 J7 CK VSS T9 85 FBB_CLK0# K7 CK# VSS E1
85 FBB_CLK0# K7 CK# VSS E1 VSS P1
VSS P1 85 FBB_CKE0 K9 CKE
85 FBB_CKE0 K9 CKE VSSQ G1
VSSQ G1 VSSQ F9
VSSQ F9 85 FBB_DQM2 D3 DMU VSSQ E8
85 FBB_DQM1 D3 DMU VSSQ E8 85 FBB_DQM3 E7 DML VSSQ E2
85 FBB_DQM0 E7 DML VSSQ E2 VSSQ D8
VSSQ D8 VSSQ D1
VSSQ D1 85,91 FBB_W E# L3 WE# VSSQ B9
85,91 FBB_W E# L3 WE# VSSQ B9 85,91 FBB_CAS# K3 CAS# VSSQ B1
85,91 FBB_CAS# K3 CAS# VSSQ B1 85,91 FBB_RAS# J3 RAS# VSSQ G9
85,91 FBB_RAS# J3 RAS# VSSQ G9
H5TQ1G63BFR-12C-GP
H5TQ1G63BFR-12C-GP BOM CTRL
BOM CTRL
2 2

0.1uF(X7R)
K0402 ×4
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

1
C9001 C9002 C9003 C9004

X7R (+/-15%、-55~125℃)
1K33R2F-GP
2
1
R9003
1.0uF(X7R)
2
K0603 ×8
FBB_VREF_0
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SCD01U50V2KX-1GP
1K33R2F-GP
1 <Core Design> 1
1
1
C9005 C9006 C9007 C9008 C9009 C9010 C9011 C9012 R9004 C9013
Wistron Corporation
2

2
Title
CHANNEL-C_VRAM5,6 (3/4)
LA48
A B C D E
A B C D E
1D5V_VGA_S0
VRAM7
http://laptopblue.vn FBB_D[63..0] 85,90 1D5V_VGA_S0
VRAM8
FBB_D[63..0] 85,90
K8 E3 FBB_D35
VDD DQL0 FBB_D37 FBB_D60
K2 VDD DQL1 F7 K8 VDD DQL0 E3
N1 F2 FBB_D32 K2 F7 FBB_D58
R9 VDD DQL3 F8 N1 VDD DQL2 F2
B2 H3 FBB_D36 R9 F8 FBB_D57
D9 VDD DQL5 H8 B2 VDD DQL4 H3
G7 G2 FBB_D33 D9 H8 FBB_D59
R1 H7 G7 G2
4 N9
VDD
VDD
DQL7 VIDEO FRAME BUFFER PORT C R1
VDD
VDD
DQL6
DQL7 H7 FBB_D56 4
D7 FBB_D51 N9
DQU0 FBB_D53 VDD FBB_D40
A8 VDDQ DQU1 C3 DQU0 D7
A1 C8 FBB_D48 A8 C3 FBB_D47
C1 VDDQ DQU3 C2 A1 VDDQ DQU2 C8
C9 A7 FBB_D49 C1 C2 FBB_D44
D2 VDDQ DQU5 A2 C9 VDDQ DQU4 A7
E9 B8 FBB_D50 D2 A2 FBB_D46
F1 VDDQ DQU7 A3 E9 VDDQ DQU6 B8
H9 F1 A3 FBB_D45
VDDQ VDDQ DQU7
H2 VDDQ DQSU C7 FBB_DQS_W P6 85 H9 VDDQ
DQSU# B7 FBB_DQS_RN6 85 H2 VDDQ DQSU C7 FBB_DQS_W P5 85
FBB_VREF_1 H1 B7
VREFDQ DQSU# FBB_DQS_RN5 85
M8 F3 FBB_VREF_1 H1
VREFCA DQSL FBB_DQS_W P4 85 VREFDQ
VRAM_CH_C_ZQ_3 L8 G3 M8 F3
243R2F-2-GP
ZQ DQSL# FBB_DQS_RN4 85 VREFCA DQSL FBB_DQS_W P7 85

VRAM_CH_C_ZQ_4 L8 G3
ZQ DQSL# FBB_DQS_RN7 85
1
OPS K1
243R2F-2-GP
ODT FBB_ODT1 85
1
85,90 FBB_A0 N3 A0 OPS ODT K1 FBB_ODT1 85
R9101 85,90 FBB_A1 P7 85,90 FBB_A0 N3
A1 R9102 A0
85,90 FBB_A2 P3 A2 CS# L2 FBB_CS1# 85 85,90 FBB_A1 P7 A1
85,90 FBB_A3 N2 T2 FBB_RST 85,90 85,90 FBB_A2 P3 L2 FBB_CS1# 85
2
A3 RESET# A2 CS#
85,90 FBB_A4 P8 85,90 FBB_A3 N2 T2 FBB_RST 85,90
2
A4 A3 RESET#
85,90 FBB_A5 P2 A5 85,90 FBB_A4 P8 A4
85,90 FBB_A6 R8 A6 NC#T7 T7 85,90 FBB_A5 P2 A5
85,90 FBB_A7 R2 A7 NC#L9 L9 85,90 FBB_A6 R8 A6 NC#T7 T7
85,90 FBB_A8 T8 A8 NC#L1 L1 85,90 FBB_A7 R2 A7 NC#L9 L9
85,90 FBB_A9 R3 A9 NC#J9 J9 85,90 FBB_A8 T8 A8 NC#L1 L1
85,90 FBB_A10 L7 A10/AP NC#J1 J1 85,90 FBB_A9 R3 A9 NC#J9 J9
85,90 FBB_A11 R7 A11 85,90 FBB_A10 L7 A10/AP NC#J1 J1
3 N7 R7 3
85,90 FBB_A12 A12/BC# 85,90 FBB_A11 A11
85,90 FBB_A13 T3 A13 VSS J8 85,90 FBB_A12 N7 A12/BC#
85,90 FBB_A15 M7 A15 VSS M1 85,90 FBB_A13 T3 A13 VSS J8
VSS M9 85,90 FBB_A15 M7 A15 VSS M1
J2 M9
FB CMD mapping85,90 M2
VSS
P9
VSS
J2
85,90
FBB_BA0
FBB_BA1 N8
BA0 VSS
G8 FB CMD mapping85,90 FBB_BA0 M2
VSS
P9
Mode D-N13x 85,90 FBB_BA2 M3
BA1 VSS
B3 85,90 FBB_BA1 N8
BA0 VSS
G8
BA2 VSS
VSS T1 Mode D-N13x 85,90 FBB_BA2 M3
BA1
BA2
VSS
VSS B3
VSS A9 VSS T1
85 FBB_CLK1 J7 CK VSS T9 VSS A9
85 FBB_CLK1# K7 CK# VSS E1 85 FBB_CLK1 J7 CK VSS T9
VSS P1 85 FBB_CLK1# K7 CK# VSS E1
85 FBB_CKE1 K9 CKE VSS P1
VSSQ G1 85 FBB_CKE1 K9 CKE
VSSQ F9 VSSQ G1
85 FBB_DQM6 D3 DMU VSSQ E8 VSSQ F9
85 FBB_DQM4 E7 DML VSSQ E2 85 FBB_DQM5 D3 DMU VSSQ E8
VSSQ D8 85 FBB_DQM7 E7 DML VSSQ E2
VSSQ D1 VSSQ D8
85,90 FBB_W E# L3 WE# VSSQ B9 VSSQ D1
85,90 FBB_CAS# K3 CAS# VSSQ B1 85,90 FBB_W E# L3 WE# VSSQ B9
85,90 FBB_RAS# J3 RAS# VSSQ G9 85,90 FBB_CAS# K3 CAS# VSSQ B1
85,90 FBB_RAS# J3 RAS# VSSQ G9
H5TQ1G63BFR-12C-GP
BOM CTRL H5TQ1G63BFR-12C-GP
BOM CTRL
2 2

0.1uF(X7R)
K0402 ×4
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

1
C9101 C9102 C9103 C9104

X7R (+/-15%、-55~125℃)
1K33R2F-GP
2
1
R9103
1.0uF(X7R)
2
K0603 ×8
FBB_VREF_1
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SCD01U50V2KX-1GP
1K33R2F-GP
1 <Core Design> 1
1
1
C9105 C9106 C9107 C9108 C9109 C9110 C9111 C9112 R9104 C9113
Wistron Corporation
2

2
Title
CHANNEL-C_VRAM7,8 (4/4)
LA48
A B C D E
5 4 3 2 1
SSID = PWR.Plane.Regulator_GFX http://laptopblue.vn PWR_DCBATOUT_VGA_CORE
Main source 2nd source

OPS OPS OPS
DCBATOUT PWR_DCBATOUT_VGA_CORE 84.03606.037 PC9202 PC9203 PC9204
1
PG9201 PU9202 1 2 VGA_CSP1_R
SC10U25V5KX-GP
SC10U25V5KX-GP
FDMS3606S-GP-U
SCD01U50V2KX-1GP
1 2
1
GAP-CLOSE-PWR-3-GP PR9201 PC9201
2
OPS
30K9R2F-GP PR9202
SCD012U25V2KX-GP
D PG9202 84.03606.037 OPS
42K2R2F-L-GP D
2
1 2 PU9206 FDMS3606S-GP-U
GAP-CLOSE-PWR-3-GP PR9203
1
76K8R2F-GP PWR_VGA_CORE_PN1
PG9203 OPS OPS
1
1 2
2
GAP-CLOSE-PWR-3-GP PU9202 OPS
BOM control 2 PR9204
PG9204 3 NTC-150K-GP
1 2 1 4
GAP-CLOSE-PWR-3-GP 10
VGA_CSN1_R
2
9
PG9205 7
1 2 N13P-GS N13P-GL N13M-GS N13M-GE1 8 6
GAP-CLOSE-PWR-3-GP 5
71.0N13P.00U 71.0N13P.B0U 71.0N13M.E0U 71.0N13M.C0U
2
PG9206
1 2 NVVDD 0.9V 0.975V 0.9V 0.875V FDMS3600-02-RJK0215-COLAY-GP
GAP-CLOSE-PWR-3-GP 84.03606.037 PG9213
Boot Voltage VID[6:0]=0110000 VID[6:0]=0101010 VID[6:0]=0110000 VID[6:0]0110010 GAP-CLOSE-PWR-3-GP
1
PWR_VGA_CORE_V5FILT OPS
PR9215 DY 63.10334.1DL DY 63.10334.1DL PL9201 VGA_CORE
NV_VID1
PR9230 63.10334.1DL DY 63.10334.1DL DY PWR_VGA_CORE_UGATE1
2
1 2
0R2J-2-GP
PR9208
PR9217 DY 63.10334.1DL DY DY
NV_VID3 0R0402-PAD PT9201 PT9202
DY
2
PR9207 COIL-D36UH-5-GP
PR9232 63.10334.1DL DY 63.10334.1DL 63.10334.1DL OPS OPS
1
ST330U2VDM-4-GP
ST330U2VDM-4-GP
1 2 VGA_VBST1_R
1 2 PR9212
Panasonic. 0.36uH 10*11.5*4
PWR_VGA_CORE_VBST1
PR9218 63.10334.1DL DY 63.10334.1DL 63.10334.1DL 2D2R3J-2-GP
NV_VID4 PR9209 PC9206 DCR=1.1mohm
2
2
2
PR9233 DY 63.10334.1DL DY DY 2D2R2J-GP SCD1U50V3KX-GP DY
0R2J-2-GP
Idc=17A, Isat=24A
1
PWR_VGA_CORE_TER1
PR9210
DY OPS OPS
0R0402-PAD
1
PR9211
PC9207
1
SC470P50V2KX-3GP
2
3D3V_VGA_S0
3D3V_VGA_S0 DY
PWR_VGA_CORE_LGATE1
C OPS-BOM CTRL PWR_VGA_CORE_AGND C
PWR_DCBATOUT_VGA_CORE
1
PWR_VGA_CORE_TRIPSEL
5V_S0 PR9213
1
56R2J-4-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
PR9214
PR9215
PR9216
PR9217
PR9218
PR9219
PR9220
PU9201 OPS
DY DY OPS DY OPS Q1: Id=11A, Qg=10~14nC, OPS OPS OPS
2
PC9208 1 2 SC2D2U10V3KX-1GP 26 31 PC9210 PC9211 PC9212
1
PC9209 1 PWR_VGA_CORE_V5FILT 38 V5IN TRIPSEL PWR_VGA_CORE_VREF Rdson=7.5~9.8 mohm
2 SC2D2U10V3KX-1GP 36
2
V5FILT TONSEL
SCD01U50V2KX-1GP
SC10U25V5KX-GP
SC10U25V5KX-GP
OPS-BOM CTRL OPS PWR_VGA_CORE_VBST1 22
Q2: Id=23A, Qg=27~38nC,
2
VBST1
OPS PWR_VGA_CORE_VBST2 29
VBST2 DRVH1
21 Rdson=1.7~2.1 mohm
24
PC9214 1 PWR_VGA_CORE_VREF DRVL1
2 SCD22U10V2KX-1GP 40 PU9206
VREF
30 2
DRVH2
OPS DRVL2
27 3
PR9221 1 2 0R0402-PAD PWR_VGA_CORE_AGND PWR_VGA_CORE_VID0 20 1 4
86 NV_VID0 PR9222 0R0402-PAD PWR_VGA_CORE_VID1 VID0 PWR_VGA_CORE_THAL#
86 NV_VID1 1 2 19 10 10
PR9223 0R0402-PAD PWR_VGA_CORE_VID2 VID1 THAL# PWR_VGA_CORE_IMON
86 NV_VID2 1 2 18 11 9
PR9224 0R0402-PAD PWR_VGA_CORE_VID3 VID2 IMON PWR_VGA_CORE_OSRSEL
86 NV_VID3 1 2 17 32 7
PR9257 0R0402-PAD PWR_VGA_CORE_VID4 VID3 OSRSEL
86 NV_VID4 1 2 16 33 DGPU_PWROK 22,93 8 6
PR9258 0R0402-PAD PWR_VGA_CORE_VID5 VID4 PGD
86 NV_VID5 1 2 15 34 5
PWR_VGA_CORE_VID6 VID5 PG# PWR_VGA_CORE_DROOP
14
VID6 DROOP
39 OPS
PWR_VGA_CORE_UGATE2 VGA_CORE
PR9226 1 PL9202
VGA_CSP1_R 2 0R0402-PAD PWR_VGA_CORE_CSP1 6 FDMS3600-02-RJK0215-COLAY-GP
1
PR9227 1 CSP1
VGA_CSN1_R 2 0R0402-PAD PWR_VGA_CORE_CSN1 5 23 PWR_VGA_CORE_LL1 84.03606.037
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
CSN1 LL1 PWR_VGA_CORE_LL2

PR9229
PR9230
PR9231
PR9232
PR9233
PR9234
PR9235
28 1 2
PR9236 1 LL2
OPS DY OPS OPS VGA_CSP2_R 2 0R0402-PAD PWR_VGA_CORE_CSP2 3 COIL-D36UH-5-GP
DY VGA_CSN2_R PR9237 1 2 0R0402-PAD PWR_VGA_CORE_CSN2 4
CSP2
9 PWR_VGA_CORE_THRM PR9225
2
CSN2 THRM
1 2VGA_VBST2_R 1 2
2
PR9239 1 2 0R0402-PAD PWR_VGA_CORE_GFB 7 1 PWR_VGA_CORE_V5FILT OPS PR9242 PT9203

83 NVGND_SENSE PR9241 1 GFB PU
83 NVVDD_SENSE 2 0R0402-PAD PWR_VGA_CORE_VFB 8 2D2R2J-GP PC9215 2D2R3J-2-GP OPS
1
VFB
ST330U2VDM-4-GP
PWR_VGA_CORE_IMON PC9217 1 OPS2 SC3300P50V2KX-1GP SCD1U50V3KX-GP
2
OPS-BOM CTRL 3D3V_VGA_S0 PR9243 1 OPS 2 11K8R2F-GP 12 25 PWR_VGA_CORE_VBST2 OPS DY
NTC-150K-GP
1
SLP PGND
PG9211
GAP-CLOSE-PWR-3-GP
PR9238
13
2
PWR_VGA_CORE_PCNT
PR9256 1 PWR_VGA_CORE_VR_ON PCNT PWR_VGA_CORE_TER2
OPS-BOM CTRL 2 10KR2J-3-GP 35 2 OPS
1
EN GND
PWR_VGA_CORE_AGND 37 41
1
SLEW GND PC9216
OPS
1
PC9225 OPS SC470P50V2KX-3GP
2
SCD1U50V3KX-GP TPS51728RHAR-GP 1 PR9244 2 PWR_VGA_CORE_THRM_R
B OPS OPS DY B
2
3D3V_VGA_S0 2KR2F-3-GP
PWR_VGA_CORE_AGND
1 2 PWR_VGA_CORE_LGATE2 VGA_CSN2_R
PR9249
1
0R0402-PAD PWR_VGA_CORE_SLEW
NTC-150K-GP
PWR_VGA_CORE_CSN1
PWR_VGA_CORE_CSN2
PWR_VGA_CORE_CSP1
PWR_VGA_CORE_CSP2
PC9218
PR9240
1
OPS
SCD012U25V2KX-GP
2
DYPR9252 PR9253
1
0R2J-2-GP 124KR2F-GP PR9251
1
OPS 0R2J-2-GP PR9248
76K8R2F-GP
DY
2 2
1
1
PWR_VGA_CORE_SLP 9K09R2F-GP PWR_VGA_CORE_PN2
PR9246
2
PC9219 OPS OPS OPS

1
1
OPS
42K2R2F-L-GP
PR9247
2
2
2
SC220P50V2KX-3GP
PWR_VGA_CORE_VREF
2
PR9254 VGA_VREF_L
SC330P50V2KX-3GP
SC330P50V2KX-3GP
SC330P50V2KX-3GP
SC330P50V2KX-3GP
2
0R0402-PAD
1
1
DY DY DY DY PWR_VGA_CORE_AGND OPS
1
VGA_CSP2_R
PC9221
PC9222
PC9223
PC9224
PC9220 1 2
1
SC3300P50V2KX-1GP
2
PR9250
2
PWR_VGA_CORE_AGND PWR_VGA_CORE_VREF 30K9R2F-GP OPS

OPS
PWR_VGA_CORE_AGND
2 1
PR9255
0R0402-PAD
3D3V_VGA_S0
PWR_VGA_CORE_AGND
A A
1
PR9228
10KR2J-3-GP
2
<Core Design>
DGPU_PWROK
Wistron Corporation
Title
TPS51728_VGA_CORE
<Doc> SD
5 4 3 2 1
5 4 3 2 1
+3VS to 3.3V_DELAY Transfer http://laptopblue.vn

1D5V_VGA_S0
1.05V to 1.05V_VGA_S0 Transfer
DY
1D5V_S3 1D5V_VGA_S0 1D05V_VTT check layout 1D05V_VGA_S0
1 2 AO4468, SO-8
R9301 0R5J-5-GP
Id=11.6A, Qg=9~12nC U9301 U9302 3.6A
3D3V_VGA_S0 Rdson=17.4~22m ohm 8 D S 1 8 D S 1
OPS 7 D S 2 7 D S 2
S D 6 D S 3 TC9301 6 D S 3
3D3V_S0
1
C9301 5 D G 4 SE330U2D5VDM-1GP C9302 5 D G 4
D Q9302 SC10U6D3V3MX-GP OPS SCD1U16V2KX-3GP D
1
AO3419L-GP OPS AO4494L-GP OPS AO4468-GP
2
G
DY
1
R9302 84.03419.031 84.04494.037 84.04468.037

C9309 100KR2J-1-GP 2nd = 84.00048.031 2nd = 84.04168.037 2nd = 84.08882.037
SCD1U16V2KX-3GP OPS 3rd = 84.03334.031 OPS OPS
2
3.3V_ALW _1
DCBATOUT 1 2 DCBATOUT_RUN RUNON_R_1
R9315
1
0R2J-2-GP
4
R9304 OPS R9317
Q9301 100R2J-2-GP
2N7002KDW -GP RUN_ENABLE 1 2 1 2 RUN_ENABLE_1 S D RUNON_R 1 2 RUNON_R 1 2 RUNON_R_2
OPS R9316 Q9303 R9303 R9314
84.2N702.A3F
2
2nd = 84.2N702.A3F 0R2J-2-GP 10KR2J-3-GP NDS0610-NL-GP 5K1R2F-2-GP C9303 30KR2F-GP C9310
1
1
OPS DY OPS 84.S0610.B31 OPS SCD1U50V3KX-GP OPS SCD1U50V3KX-GP
G
2ND = 84.00610.C31 OPS OPS
K
OPS
2
3.3V_RUN_VGA_1 1 2DIS_EN_1D5_RUN_R D9301
R9305 MMPZ5239BPT-GP
1
330KR2J-L1-GP 83.9R103.D3F
OPS R9306 R9307 OPS
A
3D3V_S0 1 2 100KR2J-1-GP 5K1R2F-2-GP
R9308 C9308 OPS OPS
1
30KR2F-GP SCD1U16V2KX-3GP
DGPU_PWR_EN
2
OPS OPS
2
Q9305 DIS_EN_1D5_RUN 1 DY 2
G 3D3V_VGA_S0 1 2 R9313
C 18 DGPU_PW R_EN# PR9315 0R2J-2-GP C
OPS
D Q9304
D
10KR2J-3-GP 2N7002K-2-GP
S DY 84.2N702.J31
2ND = 84.2N702.J31
2N7002K-2-GP
84.2N702.J31 1 2 DGPU_PW ROK_R
22,92 DGPU_PW ROK
2ND = 84.2N702.J31 R9310
OPS 0R2J-2-GP
OPS
S
1
C9304 1D5V_VGA_S0
SCD1U10V2KX-4GP
2
DY
1
R9311
75R2F-2-GP 1D05V_VGA_S0
OPS
1
3D3V_S0
R9312
75R2F-2-GP
DGPU_PWROK#
OPS
DIS_FBVDD_L
R9318
Q9309
2
10KR2J-3-GP
OPS 4 3
2
B DGPU_PW ROK# DGPU_PW ROK_R B
5 2
DIS_1D05V_NV_L
6 1
4
2N7002KDW -GP Q9308
OPS 2N7002KDW -GP
OPS
3
DGPU_PWROK#
A <Core Design> A
Wistron Corporation
Title
DISCRETE VGA POWER
A3 LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C
BLANK C
B B
<Core Design>
Wistron Corporation
Title
<Title>

A4 LA480 SD

5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Title
Reserved
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK
B B
<Core Design>
A
Title
TOUCH PANEL
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
CPU Plate http://laptopblue.vn

VGA Std-Off MINI PCIE DCBATOUT VCCSA
XDP_DBRESET# 5,19
H_CPUPW RGD 5,22
PLT_RST# 5,18,27,31,36,65,66,71,80,82,83
H1 H2 H21 H18
H14 H15 H16 H17 STF237R128H42-1-GPSTF237R128H42-1-GP STF237R128H42-1-GP STF256R89H178-GP DY DY DY
1
HOLET157B276R134-GP HOLET157B276R134-GP HOLET157B276R134-GP HOLET157B276R134-GP 34.4B417.001 EC9729 EC9727 EC9728 EC9730 EC9731 EC9732 EC9733
ZZ.SCREW.091 ZZ.SCREW.091 ZZ.SCREW.091 ZZ.SCREW.091
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SC1KP50V2KX-1GP
2
2
1
1
1
D D
1
1
34.4GD01.001 34.4GD01.001 34.4GD01.001
14" Structure boss

H4 H5 H7 H8 H10 H11 H12 H13 H19
H3 HOLE256R115-GP HOLE315X315R91-S1-GP HOLE355X355R111-S1-GPHOLE335R115-GP HOLE237R95-GP HOLE237R95-GP HOLE335R115-GP HOLE237R95-GP HOLE315R95-GP
HOLE256R115-GP ZZ.00PAD.D11 ZZ.00PAD.581 ZZ.00PAD.571 ZZ.00PAD.D01 ZZ.00PAD.921 ZZ.00PAD.921 ZZ.00PAD.D01 ZZ.00PAD.921 ZZ.00PAD.911
ZZ.00PAD.D11
1
1
3D3V_S0 5V_S0
1
1
1
1
R9704 R9705
100R2J-2-GP 100R2J-2-GP
DY DY
2
C C
3D3V_RUNPWR
5V_RUNPWR
DCBATOUT 3D3V_S0_CAMERA 3D3V_AUX_S5 3D3V_AUX_KBC 3D3V_VGA_S0 ODD_PW R_5V VCC_CORE 5V_S5
Q9704 Q9705
D
2N7002A-7-GP 2N7002A-7-GP
DY DY
1
1
EC9705 EC9706 EC9707 EC9708 EC9709 EC9710 EC9711 EC9712 EC9713 EC9714 EC9715 EC9716 EC9717 EC9718 EC9719 EC9720 EC9721 EC9722 EC9723 EC9724
DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY PS_S3CNTRL G PS_S3CNTRL G
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
2
S
1D05V_VTT
5V_USB2_S3 5V_USB1_S3
1
B B
1
EC9725 EC9726 R9701
100R2J-2-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY
2
For Discharge
VTT_RUNPWR
AD+
1D8V_S0
VCC_CORE VCC_GFXCORE VCCSA 3D3V_S5 1D5V_S3
1
1
EC9702 EC9703 EC9704
1
1
R9702
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
R9706 R9707 R9709 100R2J-2-GP R9710 R9711
2
2
100R2J-2-GP 100R2J-2-GP 100R2J-2-GP 100KR2J-1-GP 100R2J-2-GP Q9701
DY DY
D
DY DY DY DY DY 2N7002A-7-GP
2
DY
2
1D05V_RUNPWR 2
2
1D8V_RUNPWR
PS_S3CNTRL
CORE_RUNPWR
GFX_RUNPWR
1D5V_RUNPWR
36,37 PS_S3CNTRL
PM_SLP_S4
S
Q9702
D
Q9706 Q9707 Q9709 2N7002A-7-GP Q9710 Q9711

D
D
2N7002A-7-GP 2N7002A-7-GP 2N7002A-7-GP DY 2N7002A-7-GP 2N7002A-7-GP
A DY DY DY PS_S3CNTRL
DY DY <Core Design> A
G
PS_S3CNTRL G PS_S3CNTRL G PS_S3CNTRL G G G
19,27,46 PM_SLP_S4#
Wistron Corporation
S

S
S
Title
UNUSED PARTS/EMI Capacitors

A3
LA480 SD
5 4 3 2 1
5 4 3 2 1
D D
C
(Blanking) C
B B
<Core Design>
A
Title
Change History
A4
LA480 SD
5 4 3 2 1
5 4 3 2 1
Intel-Power Sequence (S3-to-S0-to-S3)
(S5-to-S0-to-S5)
Intel PCH Main board PCH S3 S0 S3
Pin Name Pin Name
S5 S0 S5
VccSUS 3D3V_AUX_S5 Wake Event
(5V/3V ) 3D3V_AUX_S5
Wake Event
D 3D3V_AUX_S5
PM_PWRBTN#
PWRBTN#
SLP_A#
PM_PWRBTN#
SLP_A#
PM_PWRBTN#
D
SLP_LAN# SLP_LAN#
Minimum duration of PWRBTN# assertion = 16mS SLP_A# Te >0s ( SLP_A# to APWROK )
SLP_S5# PM_SLP_S5#
SLP_A# Te >0s ( SLP_A# to APWROK ) SLP_LAN#
SLP_S4# PM_SLP_S4#
SLP_LAN#
SLP_S3# PM_SLP_S3# SLP_S5#
VccASW/ VccASW/ (TEST POINT)
SLP_S5# VccSPI VccSPI SLP_S4#
(TEST POINT) T09 >30us ( SLP_S5# t0 SLP_S4# )
Vcc_WLAN +3V_MINI_WLAN
SLP_S4# T10 >30us ( SLP_S4# t0 SLP_S3# ) Ta >30us ( SLP_S4# t0 SLP_S5# ) SLP_S3#
SLP_S3# Tb >30us ( SLP_S3# t0 SLP_S4# ) PWROK/APWROK S0_PWR_GOOD VccASW/
VccASW/ CL_ RST# CL_ RST# VccSPI
VccSPI T29 >0s ( VccSUS to VccASW ) VCCPLL 1D8V_S0 +3V_MINI_WLAN
+3V_MINI_WLAN VDDQ 1D5V_S0 S0_PWR_GOOD T11 >1ms ( VccASW to APWROK )
Tc >40ns
S0_PWR_GOOD T11 >1ms ( VccASW to APWROK ) Tc >40ns VR_VDDQPWRGOOD VDDPWRGOOD CL_ RST#(TEST POINT) T12 >500Us ( APWROK to CL_RST# ) (APWROK# to VCCASW/VCCSPI)
CL_ RST#(TEST POINT) T12 >500Us ( APWROK to CL_RST# ) (APWROK# to VCCASW/VCCSPI) VCCSA VCCSA 1D8V_S0 T13 >5ms<650ms ( VCCPLL to UNCOREPWRGOOD )
1D8V_S0 T13 >5ms<650ms ( VCCPLL to UNCOREPWRGOOD ) IMVP7_VR_EN D85V_PWRGD 1D5V_S0
T17 >2ms<650ms ( VCCPLL to DRAMPWROK ) VccCore VCC_CORE VDDPWRGOOD
1D5V_S0 T17 >2ms<650ms ( VDDQ to DRAMPWROK ) VccAXG VCC_GFXCORE
VCCSA
VDDPWRGOOD IMVP7_PWRGD IMVP_PWRGD
D85V_PWRGD
SYS_PWROK SYS_PWROK
VCCSA T17 >2ms<650ms ( VCCSA to DRAMPWROK )
PWROK S0_PWR_GOOD VCC_CORE
D85V_PWRGD
C VCC_CORE
DRAMPWROK PM_DRAM_PWRGD
VCC_GFXCORE
C
Tf <500ms UNCOREPWRGOOD H_CPUPWRGD Tf <500ms
VCC_GFXCORE (SLP_3# to VCCCORE/VCCAWG) PLTRST# (SLP_3# to VCCCORE/VCCAWG)
PLT_RST# IMVP_PWRGD
IMVP_PWRGD
SYS_PWROK
SYS_PWROK
S0_PWR_GOOD T12 >100ms ( APWROK to PLTRST# )
T20 >100ms ( PWROK to UNCOREPWRGOOD)
PM_DRAM_PWRGD
S0_PWR_GOOD T12 >100ms ( APWROK to PLTRST# )
T20 >100ms ( PWROK to UNCOREPWRGOOD) H_CPUPWRGD T25 >1ms<100ms
PM_DRAM_PWRGD PLT_RST# ( UNCOREPOWERGOOD to PLTRST# )
Tn >30us
H_CPUPWRGD T25 >1ms<100ms Tk >100ns (DRAMPWROK to SLP_S4# ) (PLTRST# to UNCOREPOWERGOOD )
( UNCOREPOWERGOOD to PLTRST# ) Tn >30us
PLT_RST# (PLTRST# to UNCOREPOWERGOOD )
B B
A A
<Core Design>
Wistron Corporation
Title
Change History
A2
LA480 SD
5 4 3 2 1
A B C D E
Adapter
-4
DCBATOUT
D85V_PWRGD
RUNPWROK 3D3V_VGA_S0 1.05VTT_PWRGD PM_SLP_S4# 0D75V_EN
38
-3 PU4201 PU4501 PU9201 PU4801 PU4601
TPS51640RSLR TPS51219 TPS51728RHAR TPS51461RGER RT8207MZQW
AO4407A 42,43,44 45 92 48 46
4
Charger 6 4 2 2 3 4
BQ24707ARGRR VCC_CORE VCC_GFXCORE 1D05V_VTT VGA_CORE 0D85V_S0 DDR_VREF_S3 1D5V_S3 0D75V_S0
Battery +PBATT 1.05VTT_PWRGD DGPU_PWROK

IMVP_PWRGD PWR_GFX_PWRGD
39 40 VCCSA
U9302
AO4494L(MOS) D85V_PWRGD
U9301
0 5 AO4494L(MOS)
93
1D05V_VGA_S0
1D5V_VGA_S0
R6516
RUNPWROK
TPS51225RUKR
41 LAN_PWR_ON
3
-2 -1 -1 Q3103 3
3D3V_LAN_S5 LAN
3D3V_AUX_S5 5V_AUX_S5 5V_S5 3D3V_S5 AO3419L
PM_SLP_S3#
R6512 WLAN
-1
U6102 U3601 U3602 PU4701 R8202 Cardreader
R2707 R6010
UP7534BRA8 AO4468-GP AO4468-GP RT8068AZQW
41 61 36 36 47 60 R6403 Fingerprint
-2 1 R6301 Bluetooth
3D3V_AUX_KBC 5V_USB4_S3 5V_S0 3D3V_S0 1D8V_VGA_S0 3D3V_SPI
R4922 Camera
RUNPWROK
Q9302
G5285T11U
DMP2130L
49 93
2 2
LCDVDD 3D3V_VGA_S0
F4902 F4901
LCD
U4901
F4903
SY6288CAAC
ODD R5607
CRT withuot
HDMI F5101
56
FAN R2802 R5606 HDD R5603
TouchPad R6903 R2903 Audio_Codec R2913
R2904 <Core Design>
1 1
Wistron Corporation
Title
Power Block Diagram

A3
LA480 SD
A B C D E
5 4 3 2 1
PCH SMBus Block Diagram KBC SMBus Block Diagram
3D3V_S5 3D3V_S0
5V_S0
‧ ‧
3D3V_S0 ‧
SRN2K2J-1-GP SRN2K2J-1-GP
‧
D DIMM 1 SRN10KJ-5-GP
D
SMBCLK SMB_CLK
‧ ‧PCH_SMBCLK
SMBDATA SMB_DATA
‧ ‧ PCH_SMBDATA
SCL
SDA
SRN33J-5-GP TouchPad Conn.
GPIO35/PSDAT1 TPDATA
‧ TPDATA TPDATA
3D3V_S5
SMBus Address:A0 GPIO37/PSCLK1 TPCLK
‧TPCLK TPCLK
2N7002KDW
‧ 3D3V_AUX_KBC
DIMM 2
SRN2K2J-1-GP ‧PCH_SMBCLK SCL ‧
‧ PCH_SMBDATA SDA
SRN4K7J-8-GP
SMBus Address:A4
SML0CLK SML0_CLK
SML0DATA SML0_DATA Minicard GPIO17/SCL1/N2TCK BAT_SCL

SRN33J-3-GP
BATA_SCL_1
Battery Conn.
I2C_CLK
3D3V_S5
‧PCH_SMBCLK
WLAN
SMB_CLK
GPIO22/SDA1/N2TMS BAT_SDA BATA_SDA_1 I2C_DAT
‧ PCH_SMBDATA SMB_DATA
‧
SRN2K2J-8-GP
Minicard BQ24707
W-WAN
KBC SCL
SDA
SML1CLK
SML1DATA
SML1_CLK
SML1_DATA
‧
‧
PCH_SMBCLK
PCH_SMBDATA
SMB_CLK
SMB_DATA
NPCE855
3D3V_S5
C 3D3V_S0
‧ GPIO73/SCL2
C
‧ GPIO74/SDA2 ‧
‧
PCH SRN2K2J-1-GP
SRN10K2J-1-GP
2N7002KDW
Thermal IC
L_DDC_CLK LVDS_DDC_CLK_R ‧ CLK ‧ ‧ SMBC_THERM SMCLK
L_DDC_DATA LVDS_DDC_DATA_R ‧ DATA LCD CONN ‧ ‧ SMBD_THERM SMDATA
3D3V_S0 5V_S0 ‧
3D3V_S0
3D3V_VGA_S0
‧ ‧ ‧ ‧
3D3V_S0 SRN4K7J-8-GP
SRN2K2J-1-GP SRN10KJ-6-GP
‧ I2CS_SCL SMBC_Therm_NV ‧
CRT_DDC_CLK CRT_DDC_CLK ‧ CRT_DDCCLK_CON I2CS_SDA SMBD_Therm_NV
CRT_DDC_DATA CRT_DDC_DATA ‧ CRT_DDCDATA_CON

CRT CONN 2N7002DW-1-GP
2N7002DW-1-GP
GPU ‧
PEG_RX#0~15
B 3D3V_S0 5V_S0
PEG_RX0~15
PEG_RT#0~15
PEG_TX0~15
B
‧ ‧
3D3V_S0
PEG_RX0~15 PEG_RXP0~15
SRN2K2J-1-GP SRN10KJ-6-GP PEG_RX#0~15 PEG_RXN0~15
‧ PEG_TX0~15
PEG_RT#0~15
PEG_TXP0~15
PEG_TXN0~15
SDVO_CTRLCLK
SDVO_CTRLDATA
PCH_HDMI_CLK
PCH_HDMI_DATA ‧
‧ CRT_DDCCLK_CON
CRT_DDCDATA_CON
HDMI CONN
CPU
2N7002DW-1-GP
A A
<Core Design>
Wistron Corporation
Title
SMBUS Block Diagram

A2
LA480 SD
5 4 3 2 1
A B C D E
Thermal Block Diagram Audio Block Diagram
1 1
SPKR_PORT_D_L-
PAGE28 DXP P2800_DXP SPKR_PORT_D_R+ SPEAKER

MMBT3904-3-GP
SC2200P50V2KX-2GP
DXN P2800_DXN
UMA Place near CPU
Codec
Thermal PWM CORE
92HD79B1
P2800 HP1_PORT_B_L HP
MMBT3904-3-GP HP1_PORT_B_R
PAGE27 GPIO5 SYS_THRM TDR T8

OUT
2
KBC GPIO92 CPU_THRM TDL
OTZ THERM_SYS_SHDN#
2N7002
D
PURE_HW_SHUTDOWN#
EN 3V/5V 2
NPCE795P S
G
IMVP_PWRGD PGOD
VR
Put under CPU(T8 HW shutdown)
GPIO94 GPIO56
GPIO4 VGA_THRM TDR
PAGE28
HP0_PORT_A_L MIC
P2800_VGA_DXP HP0_PORT_A_R
DXP THRMDA
VREFOUT_A_OR_F IN
FAN_TACH1
SC2200P50V2KX-2GP SC2200P50V2KX-2GP
VGA DXN
P2800_VGA_DXN
THRMDC
VGA
Thermal
FAN1_DAC
TACH Place near GPU(DISCRETE only).

P2800
FAN
VIN
MMBT3904-3-GP DMIC_CLK/GPIO1 Digital
5V
DMIC0/GPIO2
3 MIC 3
PH
OTZ
VSET VOUT
VIN
FAN CONTROL
P2793 PORTC_L
PAGE28 PORTC_R
Analog
VREFOUT_C MIC
4 <Core Design> 4
Wistron Corporation
Title
Thermal/Audio Block Diagram

Custom
LA480 SD
A B C D E
5 4 3 2 1
D D
C C
(Blanking)
B B
<Core Design>
A
Title
Change History
A4
LA480 SD
5 4 3 2 1

Schematics Laptop Lenovo b490 La4801126410106

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Schematics Laptop Lenovo b490 La4801126410106

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5 4 3 2 1

Revision SC SC INPUTS OUTPUTS

DDRIII 1066/1333/1600 Channel A DDRIII Slot 0

FDI x 4 x 2 SYSTEM DC/DC

Bluetooth USB2.0 x 3 Panther Point WLAN 65

Internal DMIC 56 L1:Top L5:VCC

G-Sensor Touch Int. Thermal Fan Title

Default = Do not connect (floating)

SSID = CPU http://laptopblue.vn

PCI EXPRESS* - GRAPHICS

K27 PEG_C_TXP9 C423 1 2 OPS SCD22U10V2KX-1GP PEG_TXP9

Signal Routing Guideline:

Need Add Test Point

JTAG & BPM

DEL U501 19 XDP_DBRESET#

SSID = CPU http://laptopblue.vn

DDR SYSTEM MEMORY B

SSID = CPU http://laptopblue.vn CPU1E 5 OF 9

0:Lane Reversed CFG7 CFG6 RSVD#AM33

Display Port Presence Strap TP704 1 CFG16 AK31 G16

0: Enabled; An external Display Port device is AR35

DY DY CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

PEG DEFER TRAINING

Taipei Hsien 221, Taiwan, R.O.C.

0511-CHECK CAP. VCC CORE:53A http://laptopblue.vn

0511-CHECK CAP. VCCIO:8.5A

PEG AND DDR

DDR3 -1.5V RAILS

[0.9, 0.8] V for SNB

C926 C923 C922 C924 A6 VCCPLL

FC_C22 C22 VCCSA_SELECT0 48

SSID = CPU http://laptopblue.vn

AT35 VSS VSS AJ22

Size Document Number Rev

Date: Friday, January 06, 2012 Sheet 11 of 103

20,37 DRAMRST_CNTRL_PCH 20,37 DRAMRST_CNTRL_PCH

1 2 M_VREF_DQ_DIMM0 M_VREF_CA_DIMM0 1 2 +V_SM_VREF 37

CLOSE PIN R1218

Size Document Number Rev

Date: Friday, January 06, 2012 Sheet 13 of 103

SSID = MEMORY DIMM2

M_B_DQS#1 DQS0# VSS

Digital Display Interface

AH45 LVDSB_DATA#0 DDPC_HPD AT38

LVDSB_DATA0 DDPC_1P DDPB_[2]P TMDSB_DATA0

R1815 DGPU_HOLD_RST# USBP9N

Reserve Buffer or not? RN1802

SUS_ACK#: For non-DWS platforms, this signal can be left unconnected.

System Power Management

SYS_PWROK: the system is ready to start the exit from P12 N3

Active Sleep Well 1 2 MEPWROK L10 N14 SUS_CLK 1 R1913 2

H20 G16 PM_SLP_SUS# 1 TP1904

V45 K45 CLK_BUF_REF14

CLKOUT_PEG_B_P XTAL25_OUT CLK_BUF_EXP_P SRN10KJ-6-GP

SRN10KJ-5-GP – Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3

1 2 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 R2114 1 2 750R2F-GP

PLL ODVR VOLTAGE

PCH_TEMP_ALERT# 1 SLOAD/GPIO38 NC_1

EC_SMI# 1 8 PCH_GPIO48 V13 BG2

SRN10KJ-6-GP GPIO57 VSS_NCTF_17#BH3

RN2204 SRN10KJ-5-GP A5 BJ5 PCH_NCTF_5 1 TP2210

NCTF TEST PIN: