CMOS 8-Bit Binary Multiplier

Schematic & Layout & Simulations

Mert Doğar, 10256

Sabancı University
2009-2010
Introduction

This project contains 8 bit multiplier which implemented in AMS 0.35u CMOS technology. The main
purpose of the project is to create a fast and compact binary multiplier. To achieve the purpose of the
project, the multiplier topology has been chosen as Wallace Tree Multiplier. Wallace Tree Multiplier
has complexity proportional to the logarithm of the bit count. Therefore, Wallace Tree Multiplier is
suitable when the bit count increases. The topology can be seen below.

As can be seen, the Wallace Tree Multiplier topology ends in log(N) stages. The final adder stage
should be a fast adder to achieve a faster multiplier.

The Design

The first step of the design was the adder stage. First of all, a good and compact full adder should have
been design. Therefore, I have design a mirror adder with complementary CMOS technique. The full
adder was small and fast enough. The schematic and the layout can be found below.
The adder is symmetric therefore it is easy to draw the layout. The layout is below.

The layout is compact and contains small amount of metal-1 lines. The size of the layout is 22.50um-
11.8um.
The post layout simulations was good enough for the multiplier. Worst case delay of the full adder is
about 760p seconds.

Later on, I designed the and2 gate. Since the multiplier has 64 and2 gates, the and2 gates also should be
small and fast. The schematic and the layout of the and2 gate is below.

The sizes of the transistors are relatively bigger than the full adder. That is just because of not to lose
time in the “creation of product stage”. The layout is below.
The size of the and2 gate is 15.4um – 6.8um.
Later on, I design the multiplier with those elements. I used about 40 full adders and 64 and2 gates. The
schematic is below.

The left part was the product creator part and the right part is the adder part. I used a ripple carry adder
for the final adder section. The delay of the schematic is 1n sec but that would change after the layout
parasitics. The layout is below.
As can be understood, in this case the left part contains the adders and the right part contains the and2
gates. The whole layout has a size of 140um – 400um. The size is relatively small for such a multiplier.
Some other screen shots are below.
Those wide lines are power lines. They carry Vdd and Gnd voltages.

This screen shot shows the and2 table.

The overall delay of the multiplier is 15n seconds. That is caused by the parasitic effects that comes
with layout design. The sample run plot is below. The delay can be observed on the plot.
Conclusion

To conclude, for high speed applications, one of the most suitable topologies is Wallace Tree Multiplier.
The complexity depends on the logarithm of the input bit count.