ISSN 2322-0929

Vol.04, Issue.13,
December-2016,
Pages:1505-1508

www.ijvdcs.org
Design and Implementation of Modified Wallace MAC Based ALU using
Multi-Operand Adders
TADALA SRISATYA1, YANAMADALA APPARAO2
1
PG Scholar, V.S.M College of Engineering, Ramachandrapuram, AP, India, E-mail: srisatya.tadala@gmail.com.
2
Assistant Professor, V.S.M College of Engineering, Ramachandrapuram, AP, India, E-mail: danaappu08@gmail.com.

Abstract: Arithmetic Logic Units are one of the crucial component in embedded systems, it’s a key element of digital processors
like microprocessors microcontrollers, C.P.U. In this digital world technology depends on the operations of A.L.U. Multiplier and
accumulator unit (MAC) which forms an important part of an A.L.U is the vital component in many DSP applications involving
multiplications & accumulations, convolutions, filtering & inner products. In this paper, we have demonstrated an optimized high
performance A.L.U through the use of an efficient M.A.C unit whose operations whose operations are critical in A.LU. The main
concern of this paper is to reduce the overall power consumption without compromising the speed of the processor. The design
consists of 64- bit ALU Modified Wallace multiplier, 128 bit carry save adder in which is realized in Verilog HDL and
synthesized on Virtex FPGA through Xilinx 12.3.

Keywords: MAC, Wallace, A.L.U, Carry Save Adder.

I. INTRODUCTION Performance of an A.L.U is increased by implementing

In portable devices like PDA’S(personal digital assistants),
most of these devices runs on battery which puts a constraint
on standby time, to increase standby time more and more
battery life is needed, one way of solving this issue is to
reduce power consumption of device or equipment.
Arithmetic and Logic Unit (ALU) is one of the most power
consuming components in a microprocessor. So, to reduce
the power consumption of the entire ALU each of its
components should consume less power.ALU contains
Multiplier and accumulation (MAC) unit for the purpose of
multiplication and accumulation of data and is used for high
speed and low power by adopting the new technical
approach. Therefore the functionality of the MAC unit
enables high-speed filtering and other processing typical for
DSP applications. MAC is an integrating circuit that reduces
the power consumption, delay and area.
Fig.1. Symbol of ALU.
The main contribution of the paper is that we have
designed a 64-bit Arithmetic and Logic Unit for the
computation of ten functions. This paper makes use of the
carry save adder popularly called as carry save compressor.
Modified Wallace multiplier and addition by using Multi-
Operand input addition. The rest of the paper is organized as
follows. In Section II the literature survey in the field of
arithmetic logic unit and MAC are discussed. In Section III,
we have discussed design of our 64-bit ALU which is my
proposed work. In section IV, we have presented various
results along with simulation window. Section V concludes
the paper.
II. LITERATURE SURVEY
A. Multiplier & Accumulator Unit
The Multiplier-Accumulator (MAC) operation is the
crucial operation not only in DSP applications but also in
rapid information processing, DSP applications, optical
communication etc. MAC unit consist of multiplier, adder
and register/accumulator. In this paper, we used 64-bit
modified Wallace multiplier. The MAC inputs are obtained
from the memory location and given to the multiplier block.
The input which is being fed from the memory location is 64
bit and when given to the multiplier it starts computing value
for the given 64 bit input and the output will be 128 bits. The
multiplier output is given as input to carry save adder which
performs addition. The output of the carry save adder is the
129 bit(128 bit + 1 carry). The accumulator register used in
this design is Parallel In Parallel Out (PIPO) as the bits are
huge and also carry save adder produces all the output values
in parallel. PIPO register is used where the input bits are
taken in parallel & output is taken in parallel. The output of
the accumulator register is fed back as one of the input to the
carry save adder. Previously there exists conventional MAC
Unit based on conventional wallace multiplier [3] and carry
propagate adders [1] ,But due to the presence of large no of

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 TADALA SRISATYA, YANAMADALA APPARAO
half adders power consumption is increased. So,in order to If the calculated from the above equation for number of rows
reduce power we switch onto modified wallace multiplier in each stage in the second phase and the number of rows that
where there is drastic decrease in the number of half adders. are formed in each stage of the second phase does not match,
In this MAC operation is performed in two parts Partial only then the half adder is used.The final product of the
Product Generation (PPG) circuit using modified Wallace second stage will be in the height of two bits and passed onto
and accumulation using Multi-Operand Addition (MOA) the third stage.
circuit [1]. In the proposed scheme, we are using Modified
Wallace tree multiplier [2] which reduces the hardware 3. Third Stage: During the third stage the output of the
complexity. second stage is given to the carry propagation adder to
generate the final output.

Fig.2. MAC Architecture

As the proposed system requires less number of resources,

we optimize the power consumption. In this project, a new
ALU is designed based on modified Wallace tree multiplier
along with Multi operand adder.

B. Modified Wallace Multiplier

A modified Wallace multiplier is an efficient hardware
implementation of digital circuit multiplying two integers and
addition using carry save compressors. Basically in
conventional Wallace multipliers many full adders and half
adders are used in their reduction phase, but problem with the
half adders is they do not reduce the number of partial
product bits. So, by minimizing the number of half adders
used in a multiplier reduction will reduce the complexity.
The modified reduction method drastically reduces the
number of half adders with a very slight increase in the
number of full adders. Reduced complexity Wallace
multiplier reduction consists of three stages.
1. First Stage: The N x N product matrix is formed and
before the passing on to the second phase the product matrix
is rearranged to take the shape of inverted pyramid.
Fig.3. Modified Wallace 10X10 Bit Reduction
C. Carry Save Adder
A carry save adder contains full adders which computes a
single sum and carries bit based mainly on the respective bits
of the three input numbers. Carry save adder is popularly
known as Carry Save compressor or 3:2 counter as it counts
the number of bits and sets the output result. The number of
half adders are reduced in the partial product addition stage
of the multiplier and they are replaced by the various
compressors like 3:2, 4:2,5:2 in the reduction phase. The
reason behind using compressors especially 3:2, 4:2 are due
to less critical path. The concept of Multi-Operand Addition
using redundant adders is implemented by the use of higher
order compressors.

2. Second Stage : During the second phase the rearranged

partial product matrix is grouped into non-overlapping group
of three as shown in the figure 2, but the single bit and two
bits in the group will be passed on to the next stage and three
bits are given to a full adder. The number of rows in the in
each stage of the reduction phase is calculated by the
formula:- :-
ri+1= 2(ri/3) +ri mod3 (1)

if rimod3=0 ,then ri+1= 2(ri/3)

Fig.4. Compressor Block Diagram
International Journal of VLSI System Design and Communication Systems
Volume.04, IssueNo.13, December-2016, Pages: 1505-1508
 Design and Implementation of Modified Wallace MAC based ALU using Multi-Operand Adders
III. ARITHMETIC AND LOGIC UNIT IV. RESULTS
Arithmetic and Logic Unit is of fundamental importance The simulation waveform for the modified A.L.U is as
among all core units of any processor. Thus, optimization of shown:-
ALU has been pursued for a long time. Arithmetic section of
an ALU contains different blocks which perform different
arithmetic functions like addition, subtraction, multiplication,
incrementing, decrementing, etc... Hence, efficient design of
these units is of prime importance to realize an efficient
ALU. In this paper the proposed Arithmetic and Logic Unit
performs Ten operations that are addition, subtraction,
multiplication, multiplication and accumulation bitwise
AND,bitwise OR ,Logical AND, Logical OR, Concatenation,
depending upon the select line.

Fig.6.

Fig.5. Proposed Modified A.L.U Block Diagram

The Modified A.L.U architecture consists of modified

Wallace multiplier which takes two operands each of 64-bit
for multiplication. The control logic provides the selection
bits as opcode for selection of various operations in A.L.U
and the result is stored in the accumulator register, the output
of which it is given back to the A.L.U .The various
operations are shown in below table 1.

TABLE I. ALU Operations

A B C D OPERATION Fig.7. RTL Schematic of Top Module
0 0 0 0 ADDITION V. DEVICE UTILIZATION SUMMARY
0 0 0 1 SUBTRACTION TABLE II
Comparison using XC6VSX475TL-FF1156
0 0 1 0 LOGICAL AND
PARAMETERS CONVENTIONAL MODIFIED
0 0 1 1 LOGICAL OR A.L.U A.L.U
NO OF LUTs 7992 7057
0 1 0 0 BITWISE AND
NO OF IOBs 456 456
0 1 0 1 BITWISE OR
NO OF SLICES 2938 2671
0 1 1 0 CONCATENATION
DELAY 0.682ns 0.682ns
0 1 1 1 CONDITIONAL
1 0 0 0 MULTIPLICATION MEMORY 420700kb 307804kb
USAGE
1 0 0 1 ACCCUMULATION SPEED GRADE -1L -1L

International Journal of VLSI System Design and Communication Systems

Volume.04, IssueNo.13, December-2016, Pages: 1505-1508
 TADALA SRISATYA, YANAMADALA APPARAO
VI. CONCLUSION
ALU is the core of the processor and optimizing ALU can
significantly improve the performance of a processor. An
efficient 64-bit Arithmetic and Logic unit is successfully
designed, simulated and optimized in terms of area and
power using modified Wallace multiplier and carry save
compressors. The A.L.U is synthesized using VERILOG
HDL and successfully verified using XILINX 12.3I.

VII. REFERENCES
[1]Javier Hormigo, Julio Villalba, Member, IEEE, and
Emilio L. Zapata "Multi-operand Redundant Adders on
FPGAs"IEEE TRANSACTIONS ON COMPUTERS, VOL.
62, NO. 10, OCTOBER 2013
[2]Ron S. Waters and Earl E. Swartzlander, Jr., "A Reduced
Complexity Wall ace Multiplier Reduction, " IEEE
Transactions On Computers, vol. 59, no. 8, Aug 20 10.
[3]C.S.Wallace, "A suggestion for a fast multiplier," IEEE
Trans. Electron Comput., vol. EC-13, no. I, pp.14-17, Feb.
1964
[4]Sureka, N., Porselvi, R., and Kumuthapriya, K., “An
Efficient High Speed Wallace Tree Multiplier”, IEEE
International Conference on Information Communication
and Embedded system, Chennai, pp. 1023-1026, 2013.
[5] Gandhi, D. R., and Shah, N. N., “Comparative Analysis
For Hardware Circuit Architecture Of Wallace Tree
Multiplier”, IEEE International Conference on Intelligent
Systems and Signal Processing, Gujarat, pp. 1-6, 2013.
[6]Simran Kaur and Mr. Mansul bansar “
Implementation Of Efficient Modified Booth Wallace
Multiplier ”Thaipur University,Pune,June-2011.
[7]P.jagadesh and Mr.Ravi.“DESIGN OF HIGH
PERFORMANCE 64-BIT MAC UNIT ”,ICCPCT-2013.
[8]Shruti murugai and ashutosh mukerjee “ENERGY
EFFICIENT AND HIGH PERFORMANCE 64 BIT ALU
USING 28nm TECHNOLOGY”,IEEE,2015

International Journal of VLSI System Design and Communication Systems

Volume.04, IssueNo.13, December-2016, Pages: 1505-1508