© Adeel Pasha, LUMS, Spring 2018

EE-522: Lecture-6

Event-Driven Schedulers-II
Quick Review of GPIOs and Interrupts
 © Adeel Pasha, LUMS, Spring 2018

Rate Monotonic Analysis (RMA)

 Lehoczky’s Test
 pi  i −1
 Task Ti would meet its first deadline if ei +    × ek ≤ pi
k =1  pk 

where tasks are arranged in descending order of priorities

 Example:
 T1 = (20, 100), T2 = (30, 150), T3 = (90, 200)
 Necessary condition = 20/100+30/150+90/200=0.85 ≤ 1(pass)
 Liu and Layland test = 0.85 ≤ 0.78 (fail)
 Lehoczky’s test:
 e1+0 = 20 ≤ 100
 e2 + p2/p1 x e1 = 30 + 150/100 x 20 = 70 ≤ 150
 e3 + p3/p1 x e1 + p3/p2 x e2 = 90 + 200/100 x 20 + 200/150 x 30 = 190 ≤ 200
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 © Adeel Pasha, LUMS, Spring 2018

Rate Monotonic Analysis (RMA)

T1(2)=100
T2(2)=150
T3(2)=200

T1 T3
T1 T2 T3 (100 T3 T2 (180
(0-20) (20-50) (50-100) - (120-150) (150-180) -
120) 190)

20 50

 di 
i −1
What if di < pi ? ei +    × ek ≤ di
k =1  pk 

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 © Adeel Pasha, LUMS, Spring 2018

Can U in RMA be better than predicted?

 Liu & Layland criterion is pessimistic
 Max. achievable U could be ~ 0.69 for large no. of tasks
 But Necessary Condition Task-sets lying here can be scheduled
1 Sufficient Condition as well (conditionally)
0.69
Liu & Layland Criterion
1
0.95
0.9

Utilization
0.85
0.8
0.75

0.69 0.7
1
0.65
1 2 4 8 16 32 64 128 256 102420484096
Number of Tasks

 Practically, we can achieve around U=88% using Lehoczky’s

Test (or RTA)
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 © Adeel Pasha, LUMS, Spring 2018

RMA: Special Case

 Harmonically related tasks can achieve U =100%
 T1(p1=20) T2(p2=40) T3(p3=120)

Theorem 2.4: For harmonically related tasks,

N N
ei
U= =  ui ≤ 1
i =1 pi i =1
is both necessary and sufficient condition for RMA

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 © Adeel Pasha, LUMS, Spring 2018

Deadline Monotonic Analysis (DMA)

 RMA is no longer optimal if di ≠ pi, then use DMA
 In DMA priority is inversely proportional to deadline
k
prio(Ti ) =
di
 How to solve a scheduling problem under DMA
 Arrange tasks in ascending order of deadlines
N
 Use modified necessary condition:  ei ≤ 1
i =1 min( pi , di )
 Use modified Liu & Layland test:  ei
N 1
≤ N (2 N − 1)
i =1 min( pi , di )
 Use modified Lehoczky’s formula: i −1
 di 
ei +    × ek ≤ di
k =1  pk 

 Example 2.12 in the book (RTS by Rajib Mall) … DIY

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 © Adeel Pasha, LUMS, Spring 2018

RMA Practicalities
 Transient Overload:
 Since RMA is priority-driven preemptive scheduler
 Better than non-preemptive EDF in transient overload
 Static: low run-time overhead
 What happens if multiple tasks have same rate?
 Worst-case context switching overhead = 2c
 Where c = context switching time
 Same as FG-BG scheduling
 ek becomes ek+2c
 where ek is WCET of higher priority task Tk
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 © Adeel Pasha, LUMS, Spring 2018

RMA Practicalities
 Critical Tasks with longer periods?
 Period transformation
 Split a longer task Ti into m sub-tasks: {Ti1, Ti2, …Tim}
 Tim = (ei/m, pi/m, di/m)
 Fake higher value of U
 Total ui due to split-task Ti = m × (ei/m)/(pi/m) = m × ei/pi
 Static: Cannot handle sporadic/aperiodic tasks
 Solution: Server-based techniques
 Will be discussed later…

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 © Adeel Pasha, LUMS, Spring 2018

RMA Practicalities
 Limited Priority Levels?
 More no. of tasks (N) … Less no. of priority levels (n)
 Windows-NT-based OS
 Normal Thread Count: few100s at least
 Max no. of priority levels: 32
 Make tasks share priority levels
 Uniform
 Arithmetic
 Geometric
 Logarithmic
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 © Adeel Pasha, LUMS, Spring 2017

Quick Review of I/O Devices

From Second Textbook (CaC): Chapter-3

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 © Adeel Pasha, LUMS, Spring 2018

I/O Device Structure

Status
Register

Device
CPU Mechanism

Data
Register

 I/O devices may have some analog or even non-electronic components

◦ E.g. Magnetic tapes, HDDs have rotating disks with analog signals
 How to couple them with digital system?
11 ◦ Each I/O device has digital logic components (ADC and DAC)
EE-522: Embedded Systems 2/8/2018
 © Adeel Pasha, LUMS, Spring 2018

I/O Primitives
 Two ways interact with an I/O device
 I/O instructions (Programmed I/O)
 Special insts are used (like input or output)
 Memory-mapped I/Os
 I/O devices are mapped in the same address space as
code/data memory
 LD/SD can be used to access I/O’s registers
DEV1 EQU 0x5500
LDR R1, DEV1 ; DEV1 address is loaded into R1
LDR R0, [R1] ; Register indirect mode, read DEV1 into R0
LDR R2, #8 ; Setup a value to write
STR R2, [R1] ; 8 is stored into the device register
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 © Adeel Pasha, LUMS, Spring 2018

Motivation for Memory-Mapped I/Os?

0xFFFF 8KB
 Max. memory size in a system is limited by 0xE000 ROM
address-bus size 0xDFFF

 2addressbussize = total memory locations Free

 In embedded μ-controllers, lesser memory than Address
the address space e.g. Space
 16-bit address bus = 216 = 64K locations
 Available memory = 16KB RAM, 8KB ROM 0x4000
0x3FFF
 Easier to write programs with mem-mapped I/Os 16KB
RAM
 Needs extra protection though 0x0000
 Normally memory-mapped I/Os can be accessed
from kernel-level address space
 We will discuss this in future when we discuss Linux
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 © Adeel Pasha, LUMS, Spring 2018

Interacting with I/Os in C

 Use pointers to manipulate the addresses
 Traditional functions peek() and poke()
int peek (char *address){
return *address; // returns the value stored at a location pointed by address
}
void poke(char *address, char newVal){
(*address) = newVal; // stores newVal at a location pointed by address
}
#define DEV1_DATA 0x5500
#define DEV1_STATUS 0x5501
int dev_status = peek(DEV1_STATUS); //dev1_status points to device status register
poke(DEV1_DATA, 255); // device data register carries a new value = 255

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 © Adeel Pasha, LUMS, Spring 2018
Issue read
cmd to the
Busy-Wait I/Os I/O
CPU  I/O

Read status
of the I/O I/O CPU

Not
Ready
Check Error
Status
Ready
Read data
from the I/O I/O CPU
and store

No
Done

Yes
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 © Adeel Pasha, LUMS, Spring 2018

Busy-Wait I/Os: Example

#define IN_DEV_DATA 0x5500

#define IN_DEV_STATUS 0x5501
#define OUT_DEV_DATA 0x5600
#define OUT_DEV_STATUS 0x5601
char temp;
while (TRUE){
// read a char into temp
while(peek(IN_DEV_STATUS) == 0); //wait until device is ready
temp= (char) peek(IN_DEV_DATA); // read the character

//write this char into output device

poke(OUT_DEV_DATA, temp);
poke(OUT_DEV_STATUS, 1); // tell output device that data is ready
while (peek(OUT_DEV_STATUS) != 0); // wait until output device is done
}

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 © Adeel Pasha, LUMS, Spring 2017

Interrupts

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 © Adeel Pasha, LUMS, Spring 2018

Why Interrupts?
 Busy-Wait I/Os are extremely inefficient

 Processor remains idle waiting for I/O to finish

 Just peeking/polling the I/O device status register
 Something else useful could be done in the meanwhile

 Interrupts provide us with better efficiency

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 © Adeel Pasha, LUMS, Spring 2018

How do Interrupts Work?

CPU running in
normal mode

Restores the
PC back I/O device needs
CPU and signals it

ISR (also called

device driver) CPU stops current
serves the device execution, saves PC

Makes PC point to
the start of interrupt
service routine (ISR)

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 © Adeel Pasha, LUMS, Spring 2018

Example: Basic Interrupt Handler

void input_handler (){
// can also be called input_ISR
char temp= peek(IN_DEV_DATA);
char gotChar = TRUE;
poke(IN_DEV_STATUS,0);
}

void output_handler(){
}

main(){
while(TRUE){
if(gotChar){
poke(OUT_DEV_DATA, temp);
poke(OUT_DEV_STATUS, 1);
while (peek(OUT_DEV_STATUS) != 0);
gotChar = FALSE;
}
… … … … // something else
}
}
20 // Still inefficient implementation! (Why?)
EE-522: Embedded Systems 2/8/2018
 © Adeel Pasha, LUMS, Spring 2018

Example: I/O Devices with Buffers

 We know I/O devices are slower than CPU
 For better efficiency, we make them asynchronous
 Attach input/output buffers
 Can be implemented as global variables
 io_buf is a string that holds a queue of incoming chars
 buf_start and buf_end are integers pointing to first and last
start startchars in queue

a b c d e f g h

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Example: I/O Devices with Buffers

#define BUF_SIZE 8 void add_char(char achar){
char io_buf[BUF_SIZE]; io_buf[buf_end++] = achar;
int buf_start = 0, buf_end = 0; if (buf_end == BUF_SIZE)
buf_end = 0;
void empty_buffer(){ }
buf_end == buf_start;
} char remove_char(){
char achar;
void full_buffer(){ achar = io_buf[buf_start++];
(buf_end+1)%BUF_SIZE == buf_start; if (buf_start == BUF_SIZE)
} buf_start = 0;
return achar;
int nchars(){ }
if(buf_end>=buf_start)
return buf_end – buf_start;
else
return BUF_SIZE + buf_end – buf_start;
}

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 © Adeel Pasha, LUMS, Spring 2018

Writing Interrupt Handler

#define IN_DEV_DATA 0x5500
#define IN_DEV_STATUS 0x5501
#define OUT_DEV_DATA 0x5600
#define OUT_DEV_STATUS 0x5601
int error = 0;
void input_handler(){
char temp;
if(full_buffer())
error = 1;
else{
temp= peek(IN_DEV_DATA);
add_char(temp);
}
poke(IN_DEV_STATUS,0);
}
void ouput_handler(){
if(!empty_buffer() || nchars() >=1){
poke(OUT_DEV_DATA, remove_char());
poke(OUT_DEV_STATUS, 1);
}
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 © Adeel Pasha, LUMS, Spring 2018

Interrupts
 Pros
 Efficient in terms of performance

 Cons
 Debugging an interrupt handler (driver) is a nightmare
 It’s not free, there is an overhead
 Interrupt is like calling a sub-routine, there is context-switch

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 © Adeel Pasha, LUMS, Spring 2017

Quiz-2: Thursday Feb. 15 2018

Contents covered in lecture 4, 5 and 6

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 © Adeel Pasha, LUMS, Spring 2017

Next week will be lab week

Venue will be EE-LAB 2 and 7

Timings will be from 5:00pm – 7:00pm

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 © Adeel Pasha, LUMS, Spring 2018

Updated EE-522 Term Schedule

W2:30/1 W2:01/2 W3:06/2
W1:23/1 W1:25/1
Static Schedulers Static Schedulers II Dynamic + Priority-
Intro RT-Scheduling
(Table-Driven) (Cyclic) Driven Schedulers
W3:08/2 W4:13/2 W4:15/2 W5:22/2
W5:20/2
Mem-mapped I/Os, Lab1 Lab2 Linux Device
RTOS Basics
GPIO etc. (EasyPICV6/7) (EasyPICV6/7) Drivers
W6:27/2 W7: 06/3
W6:01/3 W7:08/3 W8:13/3
Lab3 Lab4
Commercial RTOS Aperiodic Servers Mid term
(VM-Linux Kernel) (Mini6410)
W9:27/3 W10:03/4 W10:05/4
W8:15/3 W9:29/3
Lab5 Task Scheduling in Lab6
Resource Sharing Resource Sharing II
(Mini6410) MP (Mini6410)
W11:10/4 W12:19/4 W13:24/4
W11:12/4 W12:17/4
Lab7 RT Comm. II Lab8
Clock Sync.in MP RT Comm.
(Mini6410) RT Databases (Mini6410)
W13:26/4 W14:03/5 W14:05/4 08/5
Lab9 Lab10 Lab11 Lab12
(Mini6410) (Lab Project) (Lab Project) (Lab Project Demo)

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