LOW POWER IIR FILTER USING PIPELINING AND PARALLEL PROCESSING

LOW POWER IIR FILTER USING PIPELINING AND PARALLEL

PROCESSING

By pipeling and parrallel processing can be used to reduce the power consumption of the
system by reducing the supply voltage.

Example 1

Consider a low power implementation of the following 4th order chebyshev low pass
filter.

0.001836(1+ z −1)4
H ( z) =
(1−1.5548 z−1 +0.6493 z −2)(1−1.4996 z−1 +0.8482 z−2)

Assume – capacitance due to multipliers is dominant .

capacitance due to adders is neglected.

Supply voltage of the original system – 5v.

Cmos threshold voltage - 1v.

Power consumption can be reduced by using pipelining without altering the sample speed.
since the pipelined system has a shorter critical path than the original system, this smaller
amount of charging capacitance can be charged or discharged during the same clock
period as the original system. Therefore the supply voltage of the pipelined system can be
reduced to βv0, where β < 1 and v0 is the supply voltage of the original system.

The propagation delay for the nonpipelined system is

Cc h arge∗5
T pd=
k (5−1)2

For the 4-level pipelined system, the propagation delay Tpd is

C ch arge∗5 β
T pd=
4∗k (5−1)2

SBMJCE Page 1
LOW POWER IIR FILTER USING PIPELINING AND PARALLEL PROCESSING

By equating the equations we obtain β=0.476.Therefore the supply voltage for the
pipelined system can be reduced to 2.38 v.

The power for the original system is

2
C (seq)
total ∗5
Pseq = = m seq C M (5)2 f s
T pd

Where

mseq = 5 represents the multiplication operation in the original system.

Cm represents the capacitance of a single multiplier.

The power consumption for the pipelined system is

2
C (pip)
total ∗2.38
P pip = = m seq C M (2.38)2 f s
T pd

Where

mseq = 13 represents the multiplication operation in the 4 level pipelined system.

Then

P pip 13 2.38 2
ratio=
P seq
=
5 ( )( ) 5
=0.5891

Therefore, the power consumption of the 4 level pipelined system is 58.91% of the
nonpipelined system.

SBMJCE Page 2
LOW POWER IIR FILTER USING PIPELINING AND PARALLEL PROCESSING

Example 2

Consider the 2nd order IIR filter . the input-output relation is described by

5 3
y ( n )= y ( n−1 )− y ( n−2 )+u ( n )+ 2u ( n−1 )+ u(n−2)
4 8

Assume capacitance and computations times are dominated by multiplier

capacitance and computations times are neglected for adders.

Supply voltage of the original system – 5v.

Cmos threshold voltage - 0.6v.

The propagation delay for the sequential filter is

C M∗v 0
T seq=
k ( v 0−v t )2

The propagation delay of the parallel filter is

C M β v0
T par =
k ( β v 0−v t )2

By solving equations

Tpar = 3 Tseq

We get β=0.4673. Therefore the supply voltage for 3 parallel filter can be reduced to
βv0=2.3365 v.

The power for the original system is

Pseq =¿ 3 C M v 20 f s

The total power consumption of the 3-parallel system is

Ppar= 4β 2 C M v 20 f s

SBMJCE Page 3
LOW POWER IIR FILTER USING PIPELINING AND PARALLEL PROCESSING

Then we have

P par 4 β 2
Ratio = = =¿ 29.116%
P seq 3

Therefore the 3 parallel IIR filter consumes 29.116% power of the original sequential
filter.

PIPELINED ADAPTIVE DIGITAL FILTERS

Adaptive digital filters are difficult to pipeline due to presence of long feedback loops.
Techniques such as look ahead computation can be used to pipeline these filters but the
resulting systems are not practical for integrated circuit implementations due to large
increase in hardware. The look ahead computation maintain exact input-output mapping
in frequency shaping filters, but such exact input- output mapping is not necessary in an
adaptive filter, since the coefficients continue to adapt until they converge. However,
analysis of the adaptation behaviour in adaptive filters as measured by the misadjustment
error and adaptation time constant is important.

In this section, relaxed look ahead transformation technique is to pipeline the adaptive
filters with little or no increase in hardware at expense of marginal degradation in
adaptive behaviour. The relaxed look-ahead transformation is based on certain relaxations
or approximations of look- ahead representation.

SBMJCE Page 4
LOW POWER IIR FILTER USING PIPELINING AND PARALLEL PROCESSING

RELAXED LOOK AHEAD

In adaptive filter we are more con

cerned with stochastic behaviour. As a result the relaxed look ahead technique can be
applied to pipeline the adaptive filter with marginal hardware.

Three forms of relaxations are used to pipeline the adaptive filters, including product,
sum, and delay relaxations. Different relaxations results in different topologies.

Product relaxation:

If the magnitude of a(n) is close to unity, then a(n) can be replaced by (1-ε (n)) , where ε
(n) is close to zero.

M −1
M
1) ∏ a ( n+i )=a ¿ ¿1) = (1-ε(n+M-1))M
i=0

M−1
2) y ( n+ M )=a ¿1)y(n)+ ∑ u (n+ M −1−i)
i=0

Sum relaxation:

M−1
If the input u(n) varies slowly over M cycles, then ∑ u (n+ M −1−i) Can be
i=0

approximated as Mu(n). This leads to

M −1
1)Y(n+M)= ∏ a ( n+ M −1−i ) y ( n ) + Mu ( n ) .
i=0

If u(n) is close to zero ,then Mu(n) can be approximated as u(n) to obtain

M −1
Y(n+M)= ∏ a ( n+ M −1−i ) y ( n ) +u ( n ) .
i=0

Delay relaxation:

Consider the recursion

SBMJCE Page 5
LOW POWER IIR FILTER USING PIPELINING AND PARALLEL PROCESSING

y(n)= y(n-1)+a(n)u(n)

And its M level look ahead pipelined version

M−1
y(n)=y(n-M)+ ∑ a ( n−i ) u(n−i)
i=0

The delay relaxation involves the use of delayed inputs u(n-M’) and delayed
coefficient a(n-M’)

we get

M−1
' '
y(n)= y(n-M)+ ∑ a ( n−M −i ) u ( n−M −i ) .
i=0

SBMJCE Page 6