Trung Tâm Máy Tính AV - AV Computer Center: Bearlake-B ATX

Trung Tâm Máy Tính AV - AV Computer Center
CR-1 :
8@FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE1
7 6 5 4 3 2 1
PAGE # COMPONENT/FUNCTION PAGE # COMPONENT/FUNCTION REVISIONS

[1. INDEX] REV DESCRIPTION DFT DATE CHK DATE APVD DATE
[50. PCI TERMINATION] PAGE # COMPONENT/FUNCTION 2.02 DESIGN 2006
[2. BLOCK DIAGRAM] [51. STD FRONT PANEL HDR]
[3. RESET MAP] [97. PRIMARY XDP-LITE]
[52. USB_FP_HEADER_POWER]
[4. CLOCK DISTRIBUTION] [98. PATA]
D [53. 1394 CONTROLLER]
[5. GPIO, IRQ, IDSEL MAP] [99. PATA] D
[54. 1394 BP REV1]
[6. CPU-SOCKET 1 OF 2] [100. TEST SITE CAPS]
[55. 1394 PWR/DCPL]
[7. CPU SOCKET 2 OF 2] [101. PCI EXPRESS X1 #2]
[56. LAN NINEVEH]
[8. CPU TERMINATION & MISC P/U P/D] [102. PCI EXPRESS X1 #3]
[57. LAN NINEVEH]
[9. CPU PLL FILTERED SUPPLY] [103. PCI CONN 3]
[58. LAN NINEVEH]
[10. MCH SECTIONS PAGE 1 OF 6] [104. AUX FAN CONFIGURATION]
[59. AUDIO CODEC]
[11. MCH SECTIONS PAGE 2 OF 6] [105. HARDWARE MANAGEMENT: HECETA]
[60. AUDIO DECOUPLING & JACK SENSE]
[12. MCH SECTIONS PAGE 3 OF 6] [106. ITE IT8211F 1 OF 2]
[61. AUDIO SPDIF]
[13. MCH SECTIONS PAGE 4 OF 6] [107. PATA 2ND CONNECTOR]
[62. AUDIO JACK (BLUE GREEEN PINK]
[14. MCH SECTIONS PAGE 5 OF 6] [63. AUDIO JACK (BLACK ORANGE]
C
[15.
[16.
MCH SECTIONS
PLL & CRT FILTERS]
PAGE 6 OF 6] [64.
[65.
AUDIO
AUDIO
FP HEADERS & HDA HEADER]
MIC BIAS]
BEARLAKE-B ATX C
[17. MCH DECOUPLING AND COMP] [66. AUDIO VREG]
CLASSIC SKU
[18. MCH DCPL & VGA TERMINATION] [67. SPDIF HEADER]
[19. MCH VREFS & TERMINATION] [68. TPM 1.2] FROSTBURG
[20. VGA CONNECTOR] [69. PORT ANGELES 1 OF 2] DRAGONTAIL PEAK
[21. PCI EXPRESS X16] [70. PORT ANGELES 2 OF 2]
[22. PCI EXPRESS X16] [71. FDD CONN]
FAB C
[23. PCI EXPRESS X16 COUPLING] [72. PS/2 CONNECTOR]
[24. 240P CONN DDR2, CH A] [72. LPT SIGNALS] TAPE-OUT: WWXX-2006
[25. 240P CONN DDR2, CH B] [73. LPT SIGNALS] FAB A
REV 3.03
[26. DDR VTT TERMINATION] [74. SERIAL PORT A] CONROE, BEARLAKE, DDR?, ICH9,
B [27. DDR VTT DECOUPLING] [75. STUDIES PURPOSE] 2-CHANNEL DDR2, PCIEXPRESS GFX, ATX B
[28. CK505 PAGE 1 OF 2] [76. SST SENSOR] CUSTOMER REFERENCE BOARD
[29. CK505 PAGE 2 OF 2] [77. FAN CONFIGURATION] POWER SYMBOLS USED:

[30. ICH9 1 0F 6 CONTROL] [78. MTG HOLES/LABELS] VCC3
VCC
[31. ICH9 2 OF 6 CONTROL] [79. CORE VREG] +12V
-12V
[32. ICH9 3 OF 6 CONTROL] [80. CORE VREG]
[33. ICH9 4 OF 6 - CONTROL] [81. VREG_SM_VTT]
[34. ICH 5 OF 6 - CONTROL] [82. VREG_1P25_CORE MCH]
[35. ICH 6 OF 6 - GROUND BODY] [83. MCH DCPL]
[36. GPIO TERMINATION & RST STRAPS] [84. CORE VREG] NOTES:
[37. ICH PIN STRAPS] [85. VREG_FSB VTT & SFR] 1. THIS SCHEMATIC DOCUMENTS THE GENERIC PRODUCT WITH
ALL POSSIBLE CONFIGURATIONS.
PLEASE REFER TO SPECIFIC PRODUCT PBA EPL S FOR
[38. ICH DECOUPLING] [86. VREG 1.25 MCH CL] ITEMS SHOWN AS OPTIONAL IN THE SCHEMATIC.
A [39. ME & CONTROL BUFFERS/ICH CIRCUITS] [87. CORE VREG] 2. RESISTORS ARE IN OHMS UNLESS OTHERWISE SPECIFIED. A
[40. SERIAL FLASH PRIMARY] [88. CORE VREG] 3. VCC = +5V UNLESS OTHERWISE SPECIFIED.
4. * SUFFIX INDICATES ACTIVE LOW SIGNAL.
[41. SATA CONNECTORS] [89. CORE VREG] 5. \I SUFFIX INDICATES SIGNAL EXITS HIERARCHICAL BLOCK.
[42. USB FP HDR 1] [90. NO PAGE TITLE FOUND!!!] 6. THIS DOCUMENT ALSO EXISTS ON ELECTRONIC MEDIA.
[43. USB FP HDR 2] [91. WAKE CONTROL SWITCH PS2/USB (BP RIGHT)] BOM_RELEASE_DATE ? PB_NUMBER ?
SIGNATURE DATE 3065 BOWERS AVE
[44.
[45.
USB FP HDR 2]
BACK PANEL USB]
[92.
[93.
VREG:
VCCP VREG]
DECOUPLING AND STITCHING]
DRN_BY ? ? inte SANTA CLARA, CA
95051
CHK_BY ? ? TITLE
[46. BACK PANEL USB WITH ESATA] [94. VCCP VREG] [PAGE_TITLE=INDEX] ENGR_APVD ? ? ?
[47. PCI EXPRESS X1 #1] [95. VCCP VREG] BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
[48. PCI CONN 1] [96. VREG: VCCP DECOUPLING / 2X2 CONN] frostburg_fabc.sch_1.1
INTEL
xxxxxx 1/107 3.01
[49. PCI CONN 2] Sun Mar 18 18:42:55 2007 CUSTOM TEXT B-PAGE CONFIDENTIAL
8 7 6 5 4 3 2 1
www.advancerepairlaptop.blogspot.com
CR-2 :
7 6 5 4 3 2 1
MODULE REV DETAILS

POWER
SUPPLY CONN VREG LAND GRID ARRAY (LGA) CONNECTOR
CORE SM BUS S0
MODULE NAME REV DATE
LGA775 CK_505 CLOCK

D XDP SSA PROCESSOR SOCKET
(BACKSIDE) D
FSB SM BUS S3
PCI E 1X16 GMCH: DUAL DATA RATE SDRAM

SM BUS S3
PECI GRAPHICS MEMORY CHANNEL A DDR2 667/800 (2-DDR SDRAM DIMMS) DIMM 0:1
GRFX CONN
CONTROLLER HUB
DUAL DATA RATE SDRAM
CHANNEL B DDR2 667/800 (2-DDR SDRAM DIMMS) DIMM 0:1
VGA CONN
SM BUS S0
FRONT PANEL
USB PORT 1
C USB PORT 2 RJ45 C
SPI FLASH SPI LAN
DMI
NINEVEH
FRONT PANEL OR EKRON
USB PORT 3 GLCI
USB PORT 4
SATA CONN LCI
(LAN CONNECT INTERFACE)
1 & 2 PCI SLOT 1
PCI (33MHZ) PCI SLOT 2
BACK PANEL 3 & 4 SM BUS S3
USB PORT 1 5 & 6 ICH9: I/O

USB PORT 2 PCI (33MHZ) FP HDR
PCIE X1 CONTROLLER HUB 2 PER
USB PORT 3 PCIE SLOT 1 1394
USB PORT 4
SST_CTL THERMAL SENSOR
B USB PORT 5 BACK PANEL B
USB PORT 6 SM BUS S3

THERMAL SENSOR
LPC BUS
BROADWATER HIGH DEF AUDIO LINK HD AUDIO

2X8 HDR
CHIPSET
PORT TPM: SECURITY HD 10 CH PC_SPKR

SM BUS S3
ANGELES AUDIO CODEC
SM BUS S0
SIO
A A
FRONT PANEL
LINE OUT
MIC IN SP/DIF OUT
LINE IN LINE OUT (SURR)
PS2 MOUSE & PARALLEL (1) FLOPPY DISK CD IN (ATAPI, BLACK) LINE OUT (SURR)
KEYBOARD SERIAL HEADER (2) DRIVE CONN SP/DIF IN LINE OUT (LFE/CENTER)
[PAGE_TITLE=BLOCK DIAGRAM]
BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
frostburg_fabc.sch_1.2
INTEL
SM BUS S3 = RESUME WELL xxxxxx 2 3.01
BLOCK DIAGRM UPDATED: 09/06/2005 SM BUS S0 = MAIN POWER WELL
Sun Mar 18 18:42:55 2007 CONFIDENTIAL
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
CR-3 :
7 6 5 4 3 2 1
MODULE REV DETAILS

AFTER P_PCIRST*, HANDSHAKE (ON HL BUS) BETWEEN ICH/MCH MUST
HAPPEN BEFORE H_CPURST* WILL BE ASSERTED/DE-ASSERTED
MCH: MEMORY
D CONTROLLER HUB XDP T_RST TRST* CPU\DBR*
FP_RST*
D
H_CPURST*
H_CPURST*
P_PCIRST* XDP-SSA 30-PIN
PWRGD_3V
ICH
RES:H_CPURST
LGA775 SOCKET
DB_RESET*
FP_RST* H_PWRGD
SIO
PORT ANGELES TPM (SECURITY)

LRESET*
PCIRST_OUT* RES:PLTRST - PCIE
RES: PA_PLTRST*
PCI_RST*
SLP_S4/S5* PCI E GRAPHICS
PWRGD_3V
SLP_S3* PWRGD 1X16 CONN
RSMRST*
C FP_RST* X1-PORT (2) C
PCI E CONN
X1-PORT (1)
PWRGD
POWER (2X12)
RES:5V_STBY - PS ON
SUPPLY CONN KBRST*
RES: PS_ON_HEADER* PS_ON* PWRGD_PS PS_ON*
PWRGD_PS
PCI SLOT 2
PCI SLOT 1
P_PCIRST*
B B
RESET* H_CPURST* RES: 1394_PCI_RST* P_PCIRST*

XDP-SSA 31-PIN
DBR* CKT: G_RST*
1394 CKT: G_RST* G_RST*
1394
LAN
RESET SWITCH RES:JRSTSYNC JRSTSYNC
PLTRST*
FP_RST* PWRGD_3V
P_PCIRST*
RSMRST* JRSTSYNC
FRONT PANEL CONN H_PWRGD

RCIN*
2X8 HEADER FP_RST* ICH9: I/O AC04 AUDIO CODEC
SYS_RESET* RESET*
SW_ON* CONTROLLER HUB
JUMPER-STRAP-GND RES: CDC_DOWN_RST*
RTC_RST* ACZ_RST*
PULL-UP TERMINATION 2X8 HDR
PWR ON SWITCH RES: AUD_LINK_RST_HDR* AUD_LINK_RST_HDR*
S4_STATE
SW_ON*
SW_ON* SLP_S4*
A SLP_S3* A
RES: SLP_S3*
[PAGE_TITLE=RESET MAP]
RESET MAP UPDATED: 09/06/2005 frostburg_fabc.sch_1.3
INTEL
xxxxxx 3 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
CR-4 :
7 6 5 4 3 2 1
MODULE REV DETAILS

JORDAN
LAN LANCLK 32.7KHZ
14.318MHZ RES: 14MHZ SUSCLK
CLK14
33MHZ PCICLK ICH

33MHZ CLK14
D RES: 33MHZ
1394 32.7KHZ SUSCLK
3.3 VOLT 33MHZ LPC BUS 2X10 (TPM)
RTCCLK SMBUS CLK SCLK D
33MHZ PCI SLOT 1
USBCLK
DMICLK
33MHZ RES: 33MHZ
SATACLK PORT
TPM AUD_BCLK ANGELES
SCLK KBCLK
MCLK
MS/KB
AUDIO
CODEC 12.288 MHZ
AUD_BCLK
33M
3.3 VOLT
C 25MHZ
LAN C
CRYSTAL JORDAN ICH
CK505
48MHZ
100MHZ
X16 PCI-EXPRESS
100MHZ
SRC CLOCK PAIRS
100MHZ
100MHZ X1 PCI-EXPRESS #1
100MHZ
X1 PCI-EXPRESS #2
100MHZ
B 100MHZ SPARE
B
14.318MHZ CHAN A
100MHZ
100MHZ
SPARE
MCH
SPARE
SCLK GCLKIN
DUAL CHANNEL
REFCLKIN DDR
HOST 2X200/266/333 MHZ DIMM0
SRC CLOCK PAIR
96MHZ
PCI E - GRAPHICS
DIMM1
XDP PORT
100/133/167/200 MHZ CPU_CK CHAN B
HOST CLOCK PAIRS 100/133/167/200 MHZ CPU_CK

CPU
CORE
A 100/133/167/200 MHZ CPU_CK A
XDP
CLK-OUT XDP CLK-OUT OPTION
DIMM0
DIMM1
[PAGE_TITLE=CLOCK DISTRIBUTION]
INTEL
CLOCK DISTRIBUTION UPDATED: 09/07/2005 xxxxxx 4 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
CR-5 :
7 6 5 4 3 2 1
ICH GPIO SIGNALS NOT USED: GP40-47

POWER AFTER MODULE REV DETAILS
PIN NAME WELL USAGE PLTRST S3/S5 NOTES MODULE NAME REV DATE
GP[0] MAIN (CORE) FP AUD DETECT IN 10K P/U TO VCC3
GP[1] MAIN (CORE) FRONT FAN TACH IN 3.3K P/U TO +12V (THRU 15K)
GP[2] MAIN (CORE) P_INTE IN 8.2K P/U TO VCC
GP[3] MAIN (CORE) P_INTF IN 8.2K P/U TO VCC
GP[4] MAIN (CORE) P_INTG IN 8.2K P/U TO VCC
IRQ ROUTING TABLE (EXCERPT FROM ICH BIOS BKM REV 0.72)
D PCI X1 PCI X16
USB1 USB2
GP[5] MAIN (CORE) P_INTH IN 8.2K P/U TO VCC
SLOT1 SLOT2 SLOT3 SLOT4 SLOT5 SLOT6 AUDIO LAN 2.0 2.0 #1 #2 #3 #1 #2 SMBUS D
GP[6] MAIN (CORE) REAR FAN TACH IN 3.3K P/U TO +12V (THRU 15K)
P_INTA* IRQD IRQC B A
GP[7] MAIN (CORE) EV FAN TACH IN 3.3K P/U TO +12V (THRU 15K),10K VCC3
P_INTB* IRQC IRQA A
GP[8] RESUME (STBY) SATA/HOT-SWAP IN 10K P/U TO V_3P3_STBY
P_INTC* IRQA IRQB IRQA C C
GP[9] RESUME (STBY) WOL OUT 100K P/D TO GND
P_INTD* IRQB IRQA C
GP[10] RESUME (STBY) NOT USED (RVP) OUT 10K P/U TO V_3P3_STBY
P_INTE* IRQD IRQC IRQD IRQB A
GP[11] RESUME (STBY) PORT 80 LED OUT(ALERT) 10K P/U TO V_3P3_STBY
P_INTF* IRQA IRQB IRQC IRQD
GP[12] RESUME (STBY) BOARD ID 3 IN 10K P/U TO V_3P3_STBY, 10K P/D
P_INTG* IRQB IRQA IRQD IRQC A
GP[13] RESUME (STBY) LPC_SIO_PME IN 10K P/U TO V_3P3_STBY
P_INTH* IRQC IRQD IRQB A
GP[14] RESUME (STBY) NOT USED (RVP) IN REQ/GNT 0 1 2 3
GP[15] RESUME (STBY) LAN DISABLE OUT IDSEL 16 17 18 19 20 21 24
GP[16] MAIN (CORE) BOARD ID 1 IN 10K P/U TO VCC3, 10K P/D
GP[17] MAIN (CORE) CPU FAN TACH IN 3.3K P/U TO +12V (THRU 15K)
GP[19] MAIN (CORE) SATA1GP IN 10K P/U TO VCC3
C GP[20] MAIN (CORE) NOT USED (TP): SATA HOTSWAP CTL OUT C
GP[21] MAIN (CORE) SATA0GP IN 10K P/U TO VCC3 SMBUS ADDRESS LINES SA [2-0] SMBUS ADDRESS
GP[22] MAIN (CORE) NOT USED IN 10K P/U TO VCC3
MEMORY SLOT-0 (CHANNEL-A: SLOT-0) 0 0 0 0A1H 0A0H
GP[23] MAIN (CORE) LDRQ1 OUT 10K P/U TO VCC3
GP[24] RESUME (STBY) V_SM LED CONTROL OUT 1K P/U TO V_SM (THRU EMPTY 0 OHM RES)
MEMORY SLOT-1 (CHANNEL-A: SLOT-1) 0 0 1 0A3H 0A2H
GP[25] RESUME (STBY) BOARD ID 4 IN 10K P/U TO V_3P3_STBY, 10K P/D MEMORY SLOT-2 (CHANNEL-B: SLOT-0) 0 1 0 0A5H 0A4H
GP[26] RESUME (STBY) S4_STATE OUT 10K P/U TO V_3P3_STBY (EV DESIGN ONLY)
MEMORY SLOT-3 (CHANNEL-B: SLOT-1) 0 1 1 0A7H0 A6H
GP[27] RESUME (STBY) NOT USED (TP) LOW ENERGY LAKE STATUS LED: GREEN
GP[28] RESUME (STBY) NOT USED (TP) LOW ENERGY LAKE STATUS LED: YELLOW
CK410 - - - 0D3H 0D2H
GP[29] RESUME (STBY) OC5 IN NOA SHARED WITH OVER-CURRENT
DB800/DB400 - - - 0DDH 0DCH
SMBUS DATA (EXCERPT FROM ICH BIOS BKM REV 0.72)
GP[33] MAIN (CORE) MFG_MODE (RVP) IN 4.7K P/U TO VCC3
GP[34] MAIN (CORE) ICH CFG JUMPER IN 1K P/U TO VCC3 (SUITCASE JMPR); 4.7K P/D TO GND: BIOS NORMAL, RECOVER, CONFIGURE
B GP[35] MAIN (CORE) NOT USED (TP) IN B
GP[39] MAIN (CORE) NOT USED IN 10K P/D TO GND
GP[49] CPU CPUPWRGD IN EMPTY 100 OHM P/U (VTT)
PORT ANGELES (BASED ON NATIONAL PA3.0, MAY 2004, REV 1.1; MULTI-PLEXED/PROGRAMMABLE GPIO PINS)
GPXX (PIN 103/118) STBY/VCC3 NOT USED (TP) I/O
GPXX (PIN 104/119) STBY/VCC3 1394 ENABLE I/O 1K P/D TO GND
GPXX (PIN 105/120) STBY/VCC3 NOT USED (TP) I/O
GPXX (PIN 106/121) STBY/VCC3 1 WATT VREG CONTROL I/O
GPXX (PIN 108/124) STBY/VCC3 1 WATT VREG CONTROL+ I/O
GPXX (PIN 109/126) STBY/VCC3 MEM. OVERVOLTAGE CONTROL1 I/O 10K EMPTY P/U TO V_3P3_STBY (1.8/1.9 VREG CTL)
GPXX (PIN 111/127) STBY/VCC3 MEM. OVERVOLTAGE CONTROL2 (TP) I/O
GPXX (PIN 112/128) STBY/VCC3 BOARD ID 5 I/O
A GPXX (PIN 116) STBY 5V_DDCSDA I/O 2.2K P/U TO VCC A
GPXX (PIN 114) STBY 5V_DDCSCL I/O 2.2K P/U TO VCC
GPXX (PIN 74/115/122) STBY/STBY/VCC3 3V_DDCSDA I/O 2.2K P/U TO VCC3
GPXX (PIN 75/113/125) STBY/STBY/VCC3 3V_DDCSCL I/O 2.2K P/U TO VCC3
GPXX (PIN 101) STBY 2X12 HDR DETECT I/O
GPXX (PIN 100) STBY NOT USED (TP) I/O
GPXX (PIN 102) N/C (PA30) NOT USED (PA30) N/C (PA30)
MULTI-PLEXED GPIO PINS ON PORT ANGELES WHICH ARE USED FOR SPECIFIC FUNCTIONS (NOT AS GPIO) ARE NOT IDENTIFIED HERE [PAGE_TITLE=GPIO, IRQ, IDSEL MAP]
UN-USED GPIO PINS ON PORT ANGELES ARE NOT IDENTIFIED HERE BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
TOTAL OF (33) POSSIBLE GPIO PINS ON PORT ANGELES (POWER WELL: STBY OR V_3P3_STBY = RESUME, VCC3 = MAIN). frostburg_fabc.sch_1.5
INTEL
xxxxxx 5 3.01
NOTE: (0-4) GP'S FROM THE FWH WERE NOT USED (POWER WELL = CORE, INPUT ONLY) Sun Mar 18 18:42:57 2007 CONFIDENTIAL
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
CR-6 :
7 6 5 4 3 2 1
MODULE REV DETAILS

J1PR J1PR MODULE NAME REV DATE
LGA775_C LGA775_C
10 BI H_A_N<16..3> REV=1.8
REV=1.8 32 ICH_H_SMI_N P2 SMI* TESTHI_0 F26 H_TESTHI_0 8
3 L5 A<3>* ADS* D2 H_ADS_N BI 10 IN H_A20M_N H_TESTHI_1
IN
32 IN K3 A20M* TESTHI_1 W3 IN 8
4 P6 A<4>* BNR* C2 H_BNR_N BI 10 H_FERR_N H_TESTHI_2_7
H_HIT_N 32 8 OUT R3 FERR*/PBE* TESTHI_2 F25 IN 8
5 M5 A<5>* HIT* D4 BI 10 H_INTR K1 G25
6 L4 A<6>* RSP* H4 TP_RSP_N 32 IN LINT0 TESTHI_3
H_BPRI_N 32 IN H_NMI L1 LINT1 TESTHI_4 G27
D 7 M4 A<7>* BPRI* G8 IN 10 H_IGNNE_N N2 G26
8 R4 A<8>* DBSY* B2 H_DBSY_N 32 IN IGNNE* TESTHI_5 D
BI 10 H_STPCLK_N M3 G24
9 T5 A<9>* DRDY* C1 H_DRDY_N 33 IN STPCLK* TESTHI_6
BI 10 F24
10 U6 A<10>* HITM* E4 H_HITM_N TESTHI_7
BI 10 H_VCCA A23 P1 H_TESTHI_11
11 T4 A<11>* IERR* AB2 H_IERR_N 9 IN VCCA TESTHI_11 IN 8
OUT 8 H_VSSA B23 W2 H_TESTHI_M
12 U5 A<12>* INIT* P3 H_INIT_N 9 IN VSSA TESTHI_12 IN 6 8
IN 32 H_VCCIOPLL C23 L2 H_TESTHI_13
13 U4 A<13>* LOCK* C3 H_LOCK_N 9 IN VCCIOPLL TESTHI_13 IN 8
BI 10 H_VCCPLL D23 AK6 H_FORCEPH_N
14 V5 A<14>* TRDY* E3 H_TRDY_N 16 9 6 IN VCC_PLL FORCEPR* IN 6 95
IN 10
15 V4 A<15>* BINIT* AD3 TP_BINIT_N H_VID<7..0>
16 W5 A<16>* DEFER* G7 H_DEFER_N
93 OUT 0 AM2 VID<0> PWRGOOD N1 H_PWRGD IN 8 33
N4
IN 10 1 AL5 VID<1> PROCHOT* AL2 H_PROCHOT_N IN 8 37 95
H_REQ_N<4..0> TP_RSVD_N4 RSVD 2 AM3 VID<2> THERMTRIP* M2 H_THERMTRIP_N
10 BI P5 AB3 OUT 8 32
TP_RSVD_P5 RSVD MCERR* TP_MCERR_N
3 AL6 VID<3>
0 K4 REQ<0>*
1 J5 REQ<1>* AP<0>* U2 TP_AP<0>
4 AK4 VID<4> COMP<0> A13 H_COMP0 IN 6
2 M6 REQ<2>* AP<1>* U3 TP_AP<1>
5 AL4 VID<5> COMP<1> T1 H_COMP1 IN 6
6 AM5 VID<6> COMP<2> G2 H_COMP2 IN 6
3 K6 REQ<3>* H_COMP3
7 AM7 VID<7> COMP<3> R1 IN 6
4 J6 REQ<4>* BR<0>* F3 H_BR_N<0> BI 8 10 VRD_VIDSEL H_COMP4
H_ADSTB0_N H_BPM3_2 93 8 OUT AN7 VID_SELECT COMP<4> J2 IN 6
10 BI R6 ADSTB<0>* TESTHI_8 G3 BI 97 H_COMP5
H_BPM2_2 COMP<5> T2 IN 6
TESTHI_9 G4 BI 97 CK_H_CPU_DP H_COMP6
H_TESTHI_10 29 IN F28 BCLK<0> COMP<6> Y3 IN 6
H_A_N<35..17> TESTHI_10 H5 BI 8 CK_H_CPU_DN H_COMP7
10 BI 29 IN G28 BCLK<1> COMP<7> AE3 IN 6
17 AB6 A<17>* B13 H_COMP8
18 W6 A<18>* DP<0>* J16 TP_CPU_J16
COMP<8> IN 6
70 33 OUT H_SKTOCC_N AE8 SKTOCC*
19 Y6 A<19>* DP<1>* H15 TP_CPU_H15
20 Y4 A<20>* DP<2>* H16 TP_CPU_H16
C 76 IN H_TEMP_SRC_DP AL1 THERMDA RSVD G1 H_BPM0_2 BI 97 C
21 AA4 A<21>* DP<3>* J17 TP_CPU_J17
76 OUT H_TEMP_RET_DN AK1 THERMDC RSVD U1 H_TESTHI_M OUT 6 R112PR
22 AD6 A<22>*
CPU_GTLREF0 AJ7 RSVD RSVD A24 H_DCKLPH2 8 1 2
23 AA5 A<23>* GTLREF0 H1 IN 8 AH7 E29 TP_SFRANAD2
24 AB5 A<24>* GTLREF1 H2 CPU_GTLREF1 RSVD RSVD 1K 5%
IN 8 EMPTY
25 AC5 E24 402
A<25>* GTLREF2 CPU_MCH_GTLREF
OUT 17 VCC_SENSE AN3 VCC_SENSE FC5 F2 CPU_GTLREF2
26 AB4 H29 TP_GTL_DET 93 OUT IN 8
A<26>* GTLREF_SEL VSS_SENSE AN4 VSS_SENSE RSVD G10 CPU_GTLREF3
27 AF5 93 OUT IN 8
A<27>* VCC_PKGSENSE AN5 VCC_MB_REGULATION
28 AF4 G23 H_CPURST_N 93 OUT
A<28>* RESET* IN 8 10 97 VSS_PKGSENSE AN6 VSS_MB_REGULATION RSVD AH2 TP_CPU_AH2
29 AG6 93 OUT
A<29>* VCCP AL8 VCC
30 AG4 B3 0 105 96 95 94 76 IN
A<30>* RS<0>* AL7 VSS MSID<1> V1 H_MSID1
AG5 F5 1 OUT 6
31 A<31>* RS<1>* TP_VTT_PKGSENSE F29 RSVD MSID<0> W1 H_MSID0
AH4 A3 2 OUT 6
32 A<32>* RS<2>*
33 AH5 A<33>* H_CPU_PD_F6 F6 IMPSEL
34 AJ5 A<34>* H_RS_N<2..0> CPU_BOOT
IN 10 TP_SLEW_CTRL G6 RSVD BOOTSELECT Y1 IN 6
35 AJ6 A<35>* TP_V2
105 BI H_PECI G5 PECI LL_ID<0> V2
TP_CPU_AC4 AC4 RSVD TP_LL_ID1
LL_ID<1> AA2
TP_CPU_AE4 AE4 RSVD
H_ADSTB1_N TP_MPG_NOBOOT AL3 NC
10 BI AD5 ADSTB<1>* 3 of 4
IC
1 of 4 R19PR 1 DESIGN NOTE:
51
5% 50OHM ON 1080 105 97 93 8 7 6 VTT_OUT_RIGHT
IC IN
B CH 2 TP ON 2116 B
402
DESIGN NOTE:
1 R131PR
7 6 IN VTT_OUT_RIGHT DESIGN NOTE:
STUFF R15PR FOR 95W YORKFIELD 1 R130PR 680
5%
105 97 93 8 1K
INTERNAL PU AVAILABLE 5% 2 CH
1 R1BU ATX DESIGN ONLY 2 EMPTY 402 VRD_ENABLE
OUT 93
1K R15PR 402
5% 6 IN H_MSID0 1 2
3
2 EMPTY R13PR 0 5%
402 CPU_BOOT 6 6 H_MSID1 1 2 402 EMPTY H_MSID_XSTR_BASE_1 1 Q1PR
OUT IN MMBT3904
R128PR 1 0 5% EMPTY
51 DESIGN NOTE: 402 EMPTY DESIGN NOTE: 2
5%
CH 2 STUFF R128PR TO PREVENT EMPTY Q1PR FOR VTT TOOL TEST
402 PSC,SMF,CDM & PSL CPU
FROM BOOTING DESIGN NOTE:
STUFF R13PR FOR 65W CPU:CNR/WOLFDALE
PRECISION FSB COMPENSATION RESISTORS
97 8 7 IN VTT_OUT_LEFT
105 97 93 8 7 6 IN VTT_OUT_RIGHT 1 1 1 1
1 1 1 1 R21PR
C2PR R14PR R18PR R17PR R20PR
A 1 .1UF R12PR R22PR 24.9 A
1 20% 49.9 49.9 49.9 49.9 1%
C1PR 25V 1% 1% 1% 1% 49.9 49.9
.1UF 1 R7PR 1 R16PR R8PR 2 EMPTY 1% 1% 2 CH
20% 130 603 CH CH CH CH 402
49.9 49.9 1% 402 402 402 402 CH CH
25V 402 402
2 EMPTY 1% 1%
EMPTY
2 2 2 2 2 2 H_COMP8
603 OUT 6
2 CH 2 CH 402
402 402 2 H_COMP0 OUT 6
H_VCCPLL H_COMP1 OUT 6

H_FORCEPH_N OUT 6 95
16 9 6 IN H_COMP2 OUT 6
H_COMP6 OUT 6 1 1 H_COMP3 OUT 6
H_COMP7 C18PR C3PR H_COMP4
OUT 6 10UF .01UF OUT 6
20% 20%
6.3V 50V H_COMP5 OUT 6
2 EMPTY 2 X7R
805 603 [PAGE_TITLE=CPU-SOCKET 1 OF 2]
INTEL
xxxxxx 6 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
CR-7 :
7 6 5 4 3 2 1
MODULE REV DETAILS

J1PR MODULE NAME REV DATE
LGA775_C
R124PR
39 8 VR_READY 1 2 H_VR_READY 7 97 H_TCK AE1 TCK REV=1.8 VTT A29 V_FSB_VTT 8 9 14 17 34 38 85
IN OUT IN H_TDI
IN
93 0 5% 97 IN AD1 TDI VTT B25
402 CH 97 OUT H_TDO AF1 TDO VTT B29
97 IN H_TMS AC1 TMS VTT B30
97 IN H_TRST_N AG1 TRST* VTT C29
D VTT A26
97 BI H_BPM_N<5..0> D
0 AJ2 BPM<0>* VTT B27
CAD NOTE: 1 AJ1 C28
BPM<1>* VTT
2 AD2 BPM<2>* VTT A25
PLACE CLOSE TO VR CONTROLLER 3 AG2 BPM<3>* VTT A28
4 AF2 BPM<4>* VTT A27
5 AG3 BPM<5>* VTT C30
VTT A30
97 70 51 36 33 OUT FP_RST_N AC2 DBR* VTT C25
VTT C26
97 OUT XDP_CLKOUT_DP AK3 ITPCLK<0> VTT C27
97 OUT XDP_CLKOUT_DN AJ3 ITPCLK<1> VTT B26
VTT D27
28 13 8 OUT H_FSBSEL0 G29 BSEL<0> VTT D28
28 13 8 OUT H_FSBSEL1 H30 BSEL<1> VTT D25
28 13 8 OUT H_FSBSEL2 G30 BSEL<2> VTT D26
VTT B28
VTT D29
CPU_N5 N5 RSVD VTT D30
97 BI H_BPM1_2 C9 RSVD VTT_PWRGD AM6 H_VR_READY IN 7
TP_CPU_E7 E7 RSVD
TP_CPU_AE6 AE6 RSVD VTT_OUT_RIGHT AA1 VTT_OUT_RIGHT OUT 6 8 93 97 105
VTT_OUT_LEFT J1 VTT_OUT_LEFT OUT 6 8 97 1 1
C TP_CPU_D16 D16 RSVD VTT_SEL F27 VTT_SEL OUT 85 C4PR C5PR C
TP_ACLKPH2 A20 RSVD .1UF .1UF
10% 10%
R33PR 1 16V 16V
TP_SFRANAC2 E23 RSVD 2 X7R 2 X7R
1K 603 603
5%
EMPTY 2 RSVD F23 TP_EXTBGREF
402 RSVD D14 TP_SFRANAD
DESIGN NOTE: E6
RSVD TP_SFRANAC R32PR
FOR DEBUG ONLY RSVD E5 H_DCLKPH 2 1
RSVD J3 H_ACLKPH 5% 1K
RSVD D1 TP_HFPLL EMPTY 402 DESIGN NOTE:
4 of 4 R31PR ENG FEATURE: 1K RES (EMPTY)
CAD NOTE: 2 1
IC PLACE A GND VIA 5% 1K
NEAR TP ON EMPTY 402
J1PR PIN D1
LGA775_C
H_D_N<15..0> H_D_N<47..32> BI 10 VCCP=AG22,K29,AM26,AE12,AE11
10 BI REV=1.8 VCCP=W23,W24,W25,T25,Y28,AL18,AC25,W30,Y30,AN14,AD28,Y26,AC29,M29,U24,J23,AC27,AM18,AM19,AB8
0 B4 D<0>* D<32>* G16 32
1 C5 D<1>* D<33>* E15 33 VCCP=AC26,J8,J28,T30,AM9,AF15,AC8,AE14,N23,W29,U29,AC24,AC23,Y23,AN26,AN25,AN11,AN18,Y27,Y25
2 A4 D<2>* D<34>* E16 34 VCCP=U27,AD24,AE23,AE22,AN19,V8,K8,AE21,AM30,AE19,AC30,AE15,M30,K27,M24,AN21,T8,AC28,N25,AE18,W26
3 C6 D<3>* D<35>* G18 35 VCCP=AD25,M8,N30,AD26,AJ26,AM29,M25,M26,L8,U25,Y8,AJ12,AD27,U23,M23,AG29,N27,AM22,U28,K28
B 4 A5 D<4>* D<36>* G17 36 VCCP=U8,AK18,AD8,K24,AH28,AH21,AK12,AH22,T29,AM14,AM25,AE9,Y29,AK25,AK19,AG15,J22,T24,AG21,AM21 B
5 B6 D<5>* D<37>* F17 37 VCCP=J25,U30,AL21,AG25,AJ18,J19,AH30,J15,AG12,AJ22,J20,AH18,AH26,W27,AL25,AN8,AH14,T23,R8
6 B7 D<6>* D<38>* F18 38 VCCP=AK22,AN29,AG11,AK26,J10,AJ15,AG26,AN9,AH15,AF18,AL15,J26,J18,J21,AG27,AK15,AF11,AD23,AM15,AF8
7 A7 D<7>* D<39>* E18 39 VCCP=AK21,AG30,AJ21,AM11,AL11,AJ11,K30,AL14,AN30,AH25,AL12,AJ9,AK11,AG14,N29,AL30,AJ25,AH9,J29,J11
8 A10 D<8>* D<40>* E19 40 VCCP=K25,P8,K23,AL19,AM8,T26,N28,AH12,AL22,AN15,AJ8,U26,AJ19,T27,AK8,AN12,AG9,N26,AF9,AF22
9 A11 D<9>* D<41>* F20 41 VCCP=AH11,AJ14,AH19,AH29,AH27,AG28,AL26,AM12,J24,J13,T28,W28,J12,J27,AG19,AL9,AD30,AF21,Y24,AK14
10 B10 D<10>* D<42>* E21 42 VCCP=J9,M27,AF14,J30,AG18,AA8,AG8,AL29,AD29,W8,AH8,N24,AN22,J14,K26,AF19,N8,AF12,M28,AK9
11 C11 D<11>* D<43>* F21 43 GND=C10,D12,C24,K2,C22,AN1,B14,K7,AE16,B11,AL10,AK23,H12,AF7,AK7
12 D8 D<12>* D<44>* G21 44 GND=H7,E14,L28,Y5,E11,AL16,AL24,AK13,D21,AL20,D18,AN2,AK16,AK20,AM27,AM1,AL13,AL17,C19
13 B12 D<13>* D<45>* E22 45 GND=E28,AK30,D24,AL23,A12,L25,J7,AE28,AE29,K5,J4,AE30,AN20,AF10,AE24,AM24,AN23,H9,H8
14 C12 D<14>* D<46>* D22 46 GND=H13,AC6,AC7,AH6,C16,AM16,AE25,AE27,AJ28,F19,AH13,AD7,AH16,AK17,E17,AH17,AH20,AE5,AH23
15 D11 D<15>* D<47>* G22 47 GND=AE7,AM13,AH24,AJ30,AJ10,AF3,AK5,AJ16,AF6,AK29,AJ17,F22,AH3,AK10,AM10,F16,AJ23,F13,AG7,F10
H_DBI_N<0> A8 DBI<0>* DBI<2>* D19 H_DBI_N<2> GND=L26,AD4,H11,L24,L23,AM23,A15,AH10,B24,L3,H27,A21,AE2,AJ29,AK27,AK28,B20,AM20
10 BI BI 10
H_STBN_N<0> C8 DSTBN<0>* DSTBN<2>* G20 H_STBN_N<2> GND=H26,B17,H25,H24,AA3,AA7,H23,AA6,H10,H22,H21,H20,H19,H18,AB7,H17,AJ24,AM17,AC3,H14
10 BI BI 10
H_STBP_N<0> B9 DSTBP<0>* DSTBP<2>* G19 H_STBP_N<2> GND=P28,V6,AK2,P27,P26,AM28,AJ13,W4,P25,AJ20,W7,P23,C7,L30,L29,D15,AL27,Y7,L27
10 BI BI 10
H_D_N<31..16> H_D_N<63..48> GND=AA29,N6,N7,AA28,AN13,AA27,AA26,P4,AA25,AA24,P7,E26,V30,R2,V29,V28,R5,V27,R7,E20
10 BI BI 10
16 G9 D<16>* D<48>* D20 48 GND=AN10,V25,T3,V24,V23,T6,E25,R29,R28,R27,R26,R25,U7,R24,R23,P30,V3,P29
17 F8 D<17>* D<49>* D17 49 GND=AF16,AE10,AF13,H6,A18,A2,E2,D9,C4,A6,D6,D5,A9,D3,B1,B5,B8,AJ4,AE26,AH1
18 F9 D<18>* D<50>* A14 50 GND=V7,C13,AK24,AB30,L6,L7,AB29,M1,AB28,AN17,AB27,AB26,AN16,M7,AB25,AB24,AB23,N3,AA30
19 E9 D<19>* D<51>* C15 51 GND=F4,AG10,AE13,AF30,H28,F7,AF29,AF28,AF27,AF26,AF25,AN28,AN27,AF24,AF23,AG24,AF17,AN24,H3
20 D7 D<20>* D<52>* C14 52 GND=Y2,P24,AE20,AE17,E27,T7,R30,AJ27,AB1,AM4,V26,AA23,AL28,AF20,AG23,AG20,E8,AG17,AG16,AG13
21 E10 D<21>* D<53>* B15 53
22 D10 D<22>* D<54>* C18 54
23 F11 D<23>* D<55>* B16 55
A 24 F12 D<24>* D<56>* A17 56 A
25 D13 D<25>* D<57>* B18 57
26 E13 D<26>* D<58>* C21 58
27 G13 D<27>* D<59>* B21 59
28 F14 D<28>* D<60>* B19 60
29 G14 D<29>* D<61>* A19 61
30 F15 D<30>* D<62>* A22 62
31 G15 D<31>* D<63>* B22 63
10 BI H_DBI_N<1> G11 DBI<1>* DBI<3>* C20 H_DBI_N<3> BI 10
10 BI H_STBN_N<1> G12 DSTBN<1>* DSTBN<3>* A16 H_STBN_N<3> BI 10
10 BI H_STBP_N<1> E12 DSTBP<1>* DSTBP<3>* C17 H_STBP_N<3> BI 10
2 of 4
[PAGE_TITLE=CPU SOCKET 2 OF 2]
IC BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
INTEL
xxxxxx 7 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
CR-8 :
7 6 5 4 3 2 1
105
MODULE REV DETAILS
97
8 7
93
6 IN VTT_OUT_RIGHT
DESIGN NOTE:
CPU GTLREF V_FSB_VTT
1 34 17 14
85
9 8 7
38
IN
GTLREF VOLTAGE SHOULD BE 0.67*VTT
R59PR (67% OF 1.2V) = 0.80V
115 2 R67PR 1 H_FSBSEL0
1% <FOR THIS DESIGN> OUT 7 13 28
100OHM OVER 200 OHM RESISTORS 470 5%
CH 402 CH
D 402 2 R68PR 1 H_FSBSEL1
9 IN
2 CPU_GTLREF0_DIVIDER 1 R63PR 2 CPU_GTLREF0 OUT 7 13 28
D
OUT 6 8 470 5%
1 10 5% 402 CH
402 CH 2 R69PR 1 H_FSBSEL2
1 OUT 7 13 28
R65PR C9PR 470 5%
200
1%
1.0UF
20% 1 402 CH FSB SELECTS
10V C8PR
CH 2 Y5V 220PF
402 603 10%
2 2
50V
EMPTY
402
97
8
6 IN VTT_OUT_RIGHT
7 DESIGN NOTE: CAD NOTE:
93 1 CAD NOTE:
105 GTLREF VOLTAGE SHOULD BE 0.67*VTT 105 PLACE AT CPU END OF
R60PR 8 7 6 IN VTT_OUT_RIGHT
85 38 34 PLACE AT ICH END OF
115 (67% OF 1.2V) = 0.80V 97 93 ROUTE V_FSB_VTT
1% VTT_OUT_LEFT 9 8 7 IN ROUTE
<FOR THIS DESIGN> 8 7 6 IN 17 14
CH 100OHM OVER 200 OHM RESISTORS 97
402
2
9 IN 1 1 1 1 1 1 1 1
1
R57PR 2 CPU_GTLREF1
CPU_GTLREF1_DIVIDER
OUT 6 8 R55PR R52PR R51PR R75PR R76PR R66PR R71PR R72PR
C 62 100 62 680 330 130 62 62 C
DESIGN NOTE: 10 5% 5% 5% 5% 5% 5% 1% 5% 5%
1 402 CH
CH EMPTY CH CH CH EMPTY CH CH
PRODUCT MAY 1 402 402 402 402 402 402 402 402
TIE GTLREFS R56PR 1
C10PR
C7PR 2 2 2 2 2 2 2 2
TOGETHER 200 1.0UF
220PF
1% 10%
20% 50V
CH 10V 2 H_THERMTRIP_N 6 32
2 Y5V
EMPTY OUT
402 402 H_FERR_N
2 603 OUT 6 32
H_PROCHOT_N 6 37 95
OUT
VR_READY 7 39 93
IN
VRD_VIDSEL 6 93
OUT
H_CPURST_N 6 10 97
R62PR OUT
1 2 H_PWRGD
6 IN CPU_GTLREF1 CPU_GTLREF0 OUT 6 8 OUT 6 33
8 0 5% H_BR_N<0> 6 10
OUT
402 EMPTY
CPU SIGNAL TERMINATION
B 97 8 7 6 VTT_OUT_LEFT B
IN
DESIGN NOTE:
1 85 38 34 17 14 9 8 7 IN V_FSB_VTT TESTHI PIN NAME MAPPING
GTLREF VOLTAGE SHOULD BE 0.67*VTT
R114PR (67% OF 1.2V) = 0.80V
115 VTT_OUT_RIGHT TESTHI[0] BYPASSEN
1% <FOR THIS DESIGN> 105 97 93 8 7 6 IN
100OHM OVER 200 OHM RESISTORS TESTHI[1] ODT
CH
402 TESTHI[5:2] MCLK[3:0]
2 1
R116PR 2 CPU_GTLREF2 VTT_OUT_LEFT
CPU_GTLREF2_DIVIDER 7 6 IN
OUT 6 97 8 TESTHI[7:6] MCLKIO[1:0]
1 10 5% 1 TESTHI[10:8] BR#[3:1]
1 402 CH 1 1 1 1 1 1 1
R115PR C14PR R35PR TESTHI[11] DPSLP#
200 1.0UF R54PR R49PR R53PR R64PR R50PR R48PR R70PR 51
1% 20% 1 51 51 51 51 51 62 51 5% TESTHI[12] DT_SVR#
10V C15PR 5% 5% 5% 5% 5% 5% 5%
CH 2 Y5V 220PF CH CH
402 603 10% CH CH CH CH CH CH 402 TESTHI[13] SLP#
2 50V 402 402 402 402 402 402 402 2
2 EMPTY 2 2 2 2 2 2 2
402
DESIGN NOTE:
H_TESTHI_0 6 CHANGE TO H_TESTHI_2-7
VTT_OUT_LEFT
OUT
97 8 7 6 IN H_TESTHI_2_7 FOR CRB
OUT 6
1 DESIGN NOTE:
H_IERR_N 6
R117PR GTLREF VOLTAGE SHOULD BE 0.67*VTT OUT
A 115 (67% OF 1.2V) = 0.80V H_TESTHI_1 6 A
OUT
1% <FOR THIS DESIGN>
CH 100OHM OVER 200 OHM RESISTORS
402 H_TESTHI_10
OUT 6
2 H_TESTHI_11
OUT 6
H_TESTHI_M 6
R119PR OUT
CPU_GTLREF3_DIVIDER 1 2 CPU_GTLREF3 H_TESTHI_13
OUT 6 OUT 6
DESIGN NOTE: 10 5% TESTHI PULLUPS
1 402 CH
PRODUCT MAY 1
TIE GTLREFS R118PR 1 C17PR
200 C16PR 220PF
TOGETHER 1% 1.0UF 10%
20% 50V
CH 2 10V 2 EMPTY
402 Y5V 402
2 603 [PAGE_TITLE=CPU TERMINATION & MISC P/U P/D]
DESIGN NOTE:
KF CPU GTLREF: DEFAULT EMPTY frostburg_fabc.sch_1.8
INTEL
xxxxxx 8 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
CR-9 :
7 6 5 4 3 2 1
MODULE REV DETAILS

PLL SUPPLY FILTER MODULE NAME REV DATE
85 38 34 17 14 9 8 7 IN V_FSB_VTT
1
693286-014 1 10UH
D FB1PR
VCCPLL SUPPLY EMPTY L1PR
EMPTY
721891-026
D
2
2
DESIGN NOTE:
V_SFR_OUT 1 R90PR 2 H_VCCPLL OUT INDUCTOR: 125 MA
87 IN 6 16
0805 PACKAGE
0 1A
603 CH
H_VCCIOPLL OUT 6
DESIGN NOTE:
DESIGN NOTE:
DO NOT STUFF 1
R86PR 1
BOTH R90PR, R87PR COST REDUX EXPERIMENT C11PR
EMPTY ONE INDUCTOR
0 1.0UF
DESIGN NOTE: 5% 20%
TO EVALUATE 10V
COST REDUCTION EXP
EMPTY 2 EMPTY
402 603
V_FSB_VTT 2
85 38 34 17 14 9 8 7 IN
V_1P5_ICH 1 R87PR 2
98 92 82 38 34 IN
0 1A 1
603 EMPTY 1 10UH 693286-014 1 10UH
FB2PR
L3PR L2PR
C EMPTY
EMPTY
EMPTY C
721891-026 2 721891-026
2 2
DESIGN NOTE:
VCC3 INDUCTOR: 125 MA H_VCCA 6
105 0805 PACKAGE OUT
101 92 90 105
86 85 84 86 87 88 90
69 64 59 V_3P3_STBY\G 48 49 53 59 DESIGN NOTE:
48 47 39 IN 9 21 22 28 32 33
36 34 33 34 36 37 38 39 47 L3PR: DUAL CORE SUPPORT 1 C13PR 1
22 21 9 IN V_3P3_STBY\G 64 69 70 82 84 85 33UF C12PR
32 28 1 R139PR 92 101 102 103 20% 1.0UF
38 37 1K 25V 20%
53 49 1 R140PR 1 R145PR EMPTY 10V
82 70
5% 2 RDL 2 EMPTY
2 EMPTY 1K 10K 603
88 87 5% 5%
103 102 1 R146PR 402
10K 2 EMPTY 2 EMPTY
5% 402 402
GTLREF_FET0 OUT 9 H_VSSA OUT 6
2 EMPTY
402
GTLREF_FET1 OUT 9
Q4PR CAD NOTE:
MBT3904DUAL 3 6
R137PR R138PR PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
B
SIO_PIN_108
1 2 SIO_PIN_108_R 5 2 SIO_PIN_106_R
1 2 B
69 IN SIO_PIN_106
IN 69 TRACE WIDTH TO CAPS MUST BE NO SMALLER THAN 12 MIL
1K 5% 1K 5%
402 EMPTY 402 EMPTY
4 1 EMPTY
DESIGN NOTE:
PULL UP FOR PIN 106 IS AVAILABLE ON SIO PAGE
R142PR R141PR
3
CPU_GTLREF0_DIVIDER_R 1 2 CPU_GTLREF0_DIVIDER
OUT 8 3 CPU_GTLREF1_DIVIDER_R 1 2 CPU_GTLREF1_DIVIDER
OUT 8
0 5% 0 5%
D Q3PR 402 EMPTY D Q2PR 402 EMPTY
BSS138N BSS138N
9 GTLREF_FET0 1 EMPTY 9 GTLREF_FET1 1 EMPTY

A IN G S IN G S A
2 GTLREF_FET0_Q 2
GTLREF_FET1_Q
1 R143PR
1.3K CAD NOTE:
1% 1 R144PR CAD NOTE:
2 EMPTY 576
402 PLACE CLOSE TO THE GTLREF DIVIDER 1%
2 EMPTY PLACE CLOSE TO THE GTLREF DIVIDER
402
[PAGE_TITLE=CPU PLL FILTERED SUPPLY]

INTEL
xxxxxx 9 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
CR-10 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE10
8 7 6 5 4 3 2 1
MODULE REV DETAILS

U1UB MODULE NAME REV DATE
BRLK_B U1UB
REV=1 BRLK_B
22 21 IN EXP_A_RX_0_DP F13 PEG_RXP_0 PEG_TXP_0 D11 EXP_A_TX_0_DP OUT 23 REV=1
EXP_A_RX_0_DN E13 D12 EXP_A_TX_0_DN R40 0 H_D_N<63..0> BI 7
22 21 IN PEG_RXN_0 PEG_TXN_0 OUT 23 6 BI H_A_N<35..3> 3 J42 FSB_DB_0
EXP_A_RX_1_DP K15 PEG_RXP_1 PEG_TXP_1 B11 EXP_A_TX_1_DP FSB_AB_3 FSB_DB_1 P41 1
22 21 IN OUT 23 4 L39
D EXP_A_RX_1_DN J15 PEG_RXN_1 PEG_TXN_1 A10 EXP_A_TX_1_DN FSB_AB_4 FSB_DB_2 R41 2
FSB
22 21 IN OUT 23 5 J40
EXP_A_RX_2_DP F12 PEG_RXP_2 PEG_TXP_2 C10 EXP_A_TX_2_DP FSB_AB_5 FSB_DB_3 N40 3 D
22 21 IN OUT 23 6 L37
EXP_A_RX_2_DN E12 PEG_RXN_2 PEG_TXN_2 D9 EXP_A_TX_2_DN FSB_AB_6 FSB_DB_4 R42 4
22 21 IN OUT 23 7 L36
EXP_A_RX_3_DP J12 PEG_RXP_3 PEG_TXP_3 B9 EXP_A_TX_3_DP FSB_AB_7 FSB_DB_5 M39 5
22 21 IN OUT 23 8 K42
EXP_A_RX_3_DN H12 PEG_RXN_3 PEG_TXN_3 B7 EXP_A_TX_3_DN FSB_AB_8 FSB_DB_6 N41 6
22 21 IN OUT 23 9 N32
EXP_A_RX_4_DP J11 PEG_RXP_4 PEG_TXP_4 D7 EXP_A_TX_4_DP FSB_AB_9 FSB_DB_7 N42 7
22 21 IN OUT 23 10 N34 FSB_AB_10 8
PCIE
22 21 IN EXP_A_RX_4_DN H11 PEG_RXN_4 PEG_TXN_4 D6 EXP_A_TX_4_DN OUT 23 FSB_DB_8 L41
EXP_A_RX_5_DP F7 B5 EXP_A_TX_5_DP
11 M38 FSB_AB_11 J39 9
22 21 IN PEG_RXP_5 PEG_TXP_5 OUT 23 12 N37 FSB_AB_12 FSB_DB_9
22 21 IN EXP_A_RX_5_DN E7 PEG_RXN_5 PEG_TXN_5 B6 EXP_A_TX_5_DN OUT 23 13 M36 FSB_DB_10 L42 10
EXP_A_RX_6_DP E5 PEG_RXP_6 PEG_TXP_6 B3 EXP_A_TX_6_DP FSB_AB_13 FSB_DB_11 J41 11
22 21 IN OUT 23 14 R34
EXP_A_RX_6_DN F6 PEG_RXN_6 PEG_TXN_6 B4 EXP_A_TX_6_DN FSB_AB_14 FSB_DB_12 K41 12
22 21 IN OUT 23 15 N35
EXP_A_RX_7_DP C2 PEG_RXP_7 PEG_TXP_7 F2 EXP_A_TX_7_DP FSB_AB_15 FSB_DB_13 G40 13
22 21 IN OUT 23 16 N38
EXP_A_RX_7_DN D2 PEG_RXN_7 PEG_TXN_7 E2 EXP_A_TX_7_DN FSB_AB_16 FSB_DB_14 F41 14
22 21 IN OUT 23 17 U37
EXP_A_RX_8_DP G6 PEG_RXP_8 PEG_TXP_8 F4 EXP_A_TX_8_DP FSB_AB_17 FSB_DB_15 F42 15
22 21 IN OUT 23 18 N39
EXP_A_RX_8_DN G5 PEG_RXN_8 PEG_TXN_8 G4 EXP_A_TX_8_DN FSB_AB_18 FSB_DB_16 C42 16
22 21 IN OUT 23 19 R37
EXP_A_RX_9_DP L9 PEG_RXP_9 PEG_TXP_9 J4 EXP_A_TX_9_DP FSB_AB_19 FSB_DB_17 D41 17
22 21 IN OUT 23 20 P42
EXP_A_RX_9_DN L8 PEG_RXN_9 PEG_TXN_9 K3 EXP_A_TX_9_DN FSB_AB_20 FSB_DB_18 F38 18
22 21 IN OUT 23 21 R39
EXP_A_RX_10_DP M8 PEG_RXP_10 PEG_TXP_10 L2 EXP_A_TX_10_DP FSB_AB_21 FSB_DB_19 G37 19
22 21 IN OUT 23 22 V36
EXP_A_RX_10_DN M9 PEG_RXN_10 PEG_TXN_10 K1 EXP_A_TX_10_DN FSB_AB_22 FSB_DB_20 E42 20
22 21 IN OUT 23 23 R38
EXP_A_RX_11_DP M4 PEG_RXP_11 PEG_TXP_11 N2 EXP_A_TX_11_DP FSB_AB_23 FSB_DB_21 E39 21
22 21 IN OUT 23 24 U36
EXP_A_RX_11_DN L4 PEG_RXN_11 PEG_TXN_11 M2 EXP_A_TX_11_DN FSB_AB_24 FSB_DB_22 E37 22
22 21 IN OUT 23 25 U33
EXP_A_RX_12_DP M5 PEG_RXP_12 PEG_TXP_12 P3 EXP_A_TX_12_DP FSB_AB_25 FSB_DB_23 C39 23
22 21 IN OUT 23 26 R35
EXP_A_RX_12_DN M6 PEG_RXN_12 PEG_TXN_12 N4 EXP_A_TX_12_DN FSB_AB_26 FSB_DB_24 B39 24
22 21 IN OUT 23 27 V33
C EXP_A_RX_13_DP R9 PEG_RXP_13 PEG_TXP_13 R2 EXP_A_TX_13_DP FSB_AB_27 FSB_DB_25 G33 25 C
22 21 IN OUT 23 28 V35
EXP_A_RX_13_DN R10 PEG_RXN_13 PEG_TXN_13 P1 EXP_A_TX_13_DN FSB_AB_28 FSB_DB_26 A37 26
22 21 IN OUT 23 29 Y34
EXP_A_RX_14_DP T4 PEG_RXP_14 PEG_TXP_14 U2 EXP_A_TX_14_DP FSB_AB_29 FSB_DB_27 F33 27
22 21 IN OUT 23 30 V42
EXP_A_RX_14_DN R4 PEG_RXN_14 PEG_TXN_14 T2 EXP_A_TX_14_DN FSB_AB_30 FSB_DB_28 E35 28
22 21 IN OUT 23 31 V38
EXP_A_RX_15_DP R6 PEG_RXP_15 PEG_TXP_15 V3 EXP_A_TX_15_DP FSB_AB_31 FSB_DB_29 K32 29
22 21 IN OUT 23 32 Y36
EXP_A_RX_15_DN R7 PEG_RXN_15 PEG_TXN_15 U4 EXP_A_TX_15_DN FSB_AB_32 FSB_DB_30 H32 30
22 21 IN OUT 23 33 Y38 FSB_AB_33 FSB_DB_31 B34 31
DMI_IT_MR_0_DP W2 V7 DMI_MT_IR_0_DP
34 Y39 FSB_AB_34 J31 32
31 BI DMI_RXP_0 DMI_TXP_0 BI 31 35 AA37 FSB_AB_35 FSB_DB_32
31 BI DMI_IT_MR_0_DN V1 DMI_RXN_0 DMI_TXN_0 V6 DMI_MT_IR_0_DN BI 31 FSB_DB_33 F32 33
DMI_IT_MR_1_DP Y8 DMI_RXP_1 DMI_TXP_1 W4 DMI_MT_IR_1_DP FSB_DB_34 M31 34
DMI
31 BI BI 31
31 BI DMI_IT_MR_1_DN Y9 DMI_RXN_1 DMI_TXN_1 Y4 DMI_MT_IR_1_DN BI 31 FSB_DB_35 E31 35
31 BI DMI_IT_MR_2_DP AA7 DMI_RXP_2 DMI_TXP_2 AC8 DMI_MT_IR_2_DP BI 31 FSB_DB_36 K31 36
31 BI DMI_IT_MR_2_DN AA6 DMI_RXN_2 DMI_TXN_2 AC9 DMI_MT_IR_2_DN BI 31 6 BI H_REQ_N<4..0> 0 F40 FSB_DB_37 G31 37
DMI_IT_MR_3_DP AB3 DMI_RXP_3 DMI_TXP_3 Y2 DMI_MT_IR_3_DP FSB_REQB_0 FSB_DB_38 K29 38
31 BI BI 31 1 L35
DMI_IT_MR_3_DN AA4 DMI_RXN_3 DMI_TXN_3 AA2 DMI_MT_IR_3_DN FSB_REQB_1 FSB_DB_39 F31 39
31 BI BI 31 2 L38 FSB_REQB_2 FSB_DB_40 J29 40
CK_PE_100M_MCH_DP B12 AC11 GRCOMP
3 G43 FSB_REQB_3 F29 41
29 IN EXP_CLKINP EXP_COMPO IN 17 4 J37 FSB_REQB_4 FSB_DB_41
29 IN CK_PE_100M_MCH_DN B13 EXP_CLKINN EXP_COMPI AC12 FSB_DB_42 L27 42
H_ADSTB0_N M34 FSB_DB_43 K27 43
SDVO_CTRL_DATA G17 SDVO_CTRLDATA CAD NOTE:
6 BI FSB_ADSTBB_0 FSB_DB_44 H26 44
22 21 BI H_ADSTB1_N U34
SDVO_CTRL_CLK E17 SDVO_CTRLCLK 6 BI FSB_ADSTBB_1 FSB_DB_45 L26 45
22 21 BI
2 OF 8 MCH COMP0/1 SIGNALS: H_STBP_N<0> M42 FSB_DB_46 J26 46
7 BI FSB_DSTBPB_0 M26 47
B TIE TOGETHER AT PINS. 7 H_STBN_N<0> M43 FSB_DSTBNB_0 FSB_DB_47 B
IC BI FSB_DB_48 C33 48
7 BI H_DBI_N<0> M40 FSB_DINVB_0
H_STBP_N<1> G35 FSB_DB_49 D35 49
7 BI FSB_DSTBPB_1 FSB_DB_50 E41 50
7 BI H_STBN_N<1> H33 FSB_DSTBNB_1
H_DBI_N<1> J33 FSB_DB_51 B41 51
FSB_DINVB_1
SIGNAL NAMING CONVENTION 7
7
BI
BI H_STBP_N<2> G27 FSB_DSTBPB_2 FSB_DB_52 D42
C40
52
53
H_STBN_N<2> H27 FSB_DSTBNB_2 FSB_DB_53
7 BI C35 54
EXP: PCI EXPRESS H_DBI_N<2> G29 FSB_DINVB_2 FSB_DB_54
7 BI B40 55
H_STBP_N<3> B38 FSB_DSTBPB_3 FSB_DB_55
7 BI D38 56
DMI: DIRECT MEDIA INTERFACE H_STBN_N<3> C38 FSB_DSTBNB_3 FSB_DB_56
7 BI D37 57
H_DBI_N<3> E33 FSB_DINVB_3 FSB_DB_57
7 BI B33 58
ITP: ICH TRANSMIT POSITIVE FSB_DB_58
FSB_DB_59 D33 59
ITN: ICH TRANSMIT NEGATIVE FSB_DB_60 C34 60
SDVO CTRL DATA 6 BI H_ADS_N W40 FSB_ADSB FSB_DB_61 B35 61
6 OUT H_TRDY_N Y40 FSB_TRDYB
IRP: ICH RECEIVE POSITIVE H_DRDY_N W41 FSB_DB_62 A32 62
6 OUT FSB_DRDYB FSB_DB_63 D32 63
1 SDVO CARD PRESENT, PEG DISABLED 6 OUT H_DEFER_N T43 FSB_DEFERB
IRN: ICH RECEIVE NEGATIVE H_HITM_N Y43 FSB_HITMB
6 OUT
0 SDVO DISABLED (DEFAULT) 6 OUT H_HIT_N U42 FSB_HITB
MTP: MCH TRANSMIT POSITIVE H_LOCK_N V41 FSB_LOCKB
6 IN B25 HXSWING
H_BR_N<0> AA42 FSB_BREQ0B FSB_SWING IN 17
8 6 OUT D23 HXRCOMP
MTN: MCH TRANSMIT NEGATIVE H_BNR_N W42 FSB_BNRB FSB_RCOMP IN 17
6 BI C25 HXSCOMP
H_BPRI_N G39 FSB_BPRIB FSB_SCOMP IN 17
6 OUT D25 HXSCOMPB
MRP: MCH RECEIVE POSITIVE H_DBSY_N U40 FSB_DBSYB FSB_SCOMPB IN 17
6 BI
A 0 U41 FSB_RSB_0 D24 MCH_GTLREF A
MRN: MCH RECEIVE NEGATIVE 1 AA41 FSB_RSB_1 FSB_DVREF IN 17
6 BI H_RS_N<2..0> FSB_ACCVREF B24
2 U39 FSB_RSB_2
97 8 6 OUT H_CPURST_N C31 FSB_CPURSTB
HPL_CLKINP R32 CK_H_MCH_DP IN 29
1 OF 8 HPL_CLKINN U32 CK_H_MCH_DN IN 29
HS1UB
BRDWTR_ATX_HS
IC
1 NC_1 NC_3 3
2 4 DESIGN NOTE:
J3UB J2UB J9UB J7UB NC_2 NC_4
MCH GTLREF0/1: SEPARATE SIGNALS ON EV ONLY;
1 1 1 8 NC_8 NC_5 5 TIE TOGETHER AT PINS ON CRB.
1 7 NC_7 NC_6 6
NC NC NC
NC HEATSINK [PAGE_TITLE=MCH SECTIONS PAGE 1 OF 6]
HDR HDR HDR HDR BPAGE DRAWING
C85376-001 INTEL DOCUMENT_NUMBER PAGE REV
xxxxxx 10 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
A
C
D
B
CR-11
:
8
8
U1UB
7
7
BRLK_B
REV=1
0 BB30 DDR_A_MA_0 DDR_A_DQS_0 AP2 0
1 AY25 AP3 0
@FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE11
DDR_A_MA_1 DDR_A_DQSB_0
2 BA23 DDR_A_MA_2 DDR_A_DM_0 AN2 0
3 BB23 DDR_A_MA_3
4 AY23 DDR_A_MA_4 DDR_A_DQ_0 AM1 0
5 BB22 DDR_A_MA_5 DDR_A_DQ_1 AN3 1
6 BA22 DDR_A_MA_6 DDR_A_DQ_2 AR2 2
7 BB21 DDR_A_MA_7 DDR_A_DQ_3 AR3 3
8 AW21 DDR_A_MA_8 DDR_A_DQ_4 AL3 4
9 BA21 DDR_A_MA_9 DDR_A_DQ_5 AM2 5
10 BB31 DDR_A_MA_10 DDR_A_DQ_6 AR5 6
11 AY21 DDR_A_MA_11 DDR_A_DQ_7 AR4 7
12 BC20 DDR_A_MA_12
13 AY38 DDR_A_MA_13 DDR_A_DQS_1 AW2 1
14 BA19 DDR_A_MA_14 DDR_A_DQSB_1 AW1 1
DDR_A_DM_1 AW3 1
6
6
BA33 DDR_A_WEB DDR_A_DQ_8 AV4 8

AW35 DDR_A_CASB DDR_A_DQ_9 AV3 9
AY33 DDR_A_RASB DDR_A_DQ_10 BA4 10
DDR_A_DQ_11 BB3 11
0 BA31 DDR_A_BS_0 DDR_A_DQ_12 AU2 12
1 AY31 DDR_A_BS_1 DDR_A_DQ_13 AU1 13
2 AY20 DDR_A_BS_2 DDR_A_DQ_14 AY2 14
DDR_A_DQ_15 AY3 15
0 BA34 DDR_A_CSB_0 DDR_A_DQS_2 AY7 2
1 AY35 DDR_A_CSB_1 DDR_A_DQSB_2 BA6 2
2 BB33 DDR_A_CSB_2 DDR_A_DM_2 BB6 2
3 BB38 DDR_A_CSB_3
DDR_A_DQ_16 BB5 16
0 AY19 DDR_A_CKE_0 DDR_A_DQ_17 AY6 17
1 AW18 DDR_A_CKE_1 DDR_A_DQ_18 BA9 18
2 BB19 DDR_A_CKE_2 DDR_A_DQ_19 BB9 19
3 BA18 DDR_A_CKE_3 DDR_A_DQ_20 BA5 20
DDR_A_DQ_21 BB4 21
5
5
0 BB35 DDR_A_ODT_0 DDR_A_DQ_22 BC7 22

1 BA38 DDR_A_ODT_1 DDR_A_DQ_23 AY9 23
2 BA35 DDR_A_ODT_2
3 BA39 DDR_A_ODT_3 DDR_A_DQS_3 AT20 3
DDR_A_DQSB_3 AU18 3
DDR_A_DM_3 AN18 3
DDR_A_DQ_24 AT18 24
M_MAA_A<14..0>
M_SCS_A_N<3..0>
AR31 AR18
M_SBS_A<2..0>
25
M_ODT_A<3..0>
DDR_A_CK_0 DDR_A_DQ_25
M_SCKE_A<3..0>
M_CAS_A_N
M_RAS_A_N
M_WE_A_N
AU31 DDR_A_CKB_0 DDR_A_DQ_26 AU21 26
AP27 DDR_A_CK_1 DDR_A_DQ_27 AT21 27
AN27 DDR_A_CKB_1 DDR_A_DQ_28 AP17 28
AV33 DDR_A_CK_2 DDR_A_DQ_29 AN17 29
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
AW33 DDR_A_CKB_2 DDR_A_DQ_30 AP20 30
AP29 DDR_A_CK_3 DDR_A_DQ_31 AV20 31
24
24
24
24
24
24
24
AP31 DDR_A_CKB_3
AM26 DDR_A_CK_4 DDR_A_DQS_4 AR41 4
26
26
26
26
26
26
26
AM27 DDR_A_CKB_4 DDR_A_DQSB_4 AR40 4
AT33 DDR_A_CK_5 DDR_A_DM_4 AU43 4
AU33 DDR_A_CKB_5
4
4
DDR_A_DQ_32 AV42 32
DDR_A_DQ_33 AU40 33
DDR_A_DQ_34 AP42 34
DDR_A_DQ_35 AN39 35
DDR_A_DQ_36 AV40 36
DDR_A_DQ_37 AV41 37
DDR_A_DQ_38 AR42 38
DDR_A_DQ_39 AP41 39
CK_M_DDR5_A_DP
CK_M_DDR4_A_DP
CK_M_DDR3_A_DP
CK_M_DDR2_A_DP
CK_M_DDR1_A_DP
CK_M_DDR0_A_DP
CK_M_DDR5_A_DN
CK_M_DDR4_A_DN
CK_M_DDR3_A_DN
CK_M_DDR2_A_DN
CK_M_DDR1_A_DN
CK_M_DDR0_A_DN
DDR_A_DQS_5 AL41 5
DDR_A_DQSB_5 AL40 5
DDR_A_DM_5 AM43 5
DDR_A_DQ_40 AN41 40
DDR_A_DQ_41 AM39 41
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
DDR_A_DQ_42 AK42 42
DDR_A_DQ_43 AK41 43
DDR_A_DQ_44 AN40 44
24
24
24
24
24
24
24
24
24
24
24
24
DDR_A_DQ_45 AN42 45
DDR_A_DQ_46 AL42 46
3
3
DDR_A_DQ_47 AL39 47
Sun Mar 18 18:43:04
DDR_A_DQS_6 AG42 6
DDR_A_DQSB_6 AG41 6
DDR_A_DM_6 AG40 6
2007
BPAGE DRAWING
DDR_A_DQ_48 AJ40 48
DDR_A_DQ_49 AH43 49
DDR_A DDR_A_DQ_50 AF39 50
AE40 51
DDR_A_DQ_51
DDR_A_DQ_52 AJ42 52
DDR_A_DQ_53 AJ41 53
DDR_A_DQ_54 AF41 54
DDR_A_DQ_55 AF42 55
TP_A_RCVEN_N AN21 RSVD DDR_A_DQS_7 AC42 7
DDR_A_DQSB_7 AC41 7
DDR_A_DM_7 AC40 7
AD40
CUSTOM TEXT
DDR_A_DQ_56 56
2
DDR_A_DQ_57 AD43 57
DDR_A_DQ_58 AB41 58
[PAGE_TITLE=MCH
DDR_A_DQ_59 AA40 59
INTEL
BPAGE
DDR_A_DQ_60 AE42 60
DDR_A_DQ_61 AE41 61
AC39 62
CONFIDENTIAL
DDR_A_DQ_62
DDR_A_DQ_63 AB42 63
3 OF 8
M_DQS_A_DP<7..0>
M_DQS_A_DN<7..0>
M_DATA_A<63..0>
IC
M_DQM_A<7..0>
MODULE
SECTIONS
NAME
BI
OUT
OUT
OUT
xxxxxx
24
24
24
24
REV
DOCUMENT_NUMBER
1
1
11
PAGE
PAGE 2 OF 6]
MODULE REV DETAILS
DATE
3.01
REV
A
C
D
B
A
C
D
B
CR-12
:
8
8
U1UB
BRLK_B
REV=1
0 AW15 DDR_B_MA_0 DDR_B_DQS_0 AV6 0
1 BB15 DDR_B_MA_1 DDR_B_DQSB_0 AU5 0
7
7
2 BA15 DDR_B_MA_2 DDR_B_DM_0 AR7 0

3 AY15 DDR_B_MA_3
4 BA14 DDR_B_MA_4 DDR_B_DQ_0 AN7 0
5 BB14 DDR_B_MA_5 DDR_B_DQ_1 AN8 1
6 AW12 DDR_B_MA_6 DDR_B_DQ_2 AW5 2
7 BA13 AW7 3
DDR_B_MA_7 DDR_B_DQ_3
8 BB13 DDR_B_MA_8 DDR_B_DQ_4 AN5 4
9 AY13 DDR_B_MA_9 DDR_B_DQ_5 AN6 5
10 BA17 DDR_B_MA_10 DDR_B_DQ_6 AN9 6
11 AY12 DDR_B_MA_11 DDR_B_DQ_7 AU7 7
12 BA11 DDR_B_MA_12
13 AY27 DDR_B_MA_13 DDR_B_DQS_1 AR12 1
14 BB11 DDR_B_MA_14 DDR_B_DQSB_1 AP12 1
DDR_B_DM_1 AW9 1
BB25 DDR_B_WEB DDR_B_DQ_8 AT11 8
AW26 DDR_B_CASB DDR_B_DQ_9 AU11 9
AY24 DDR_B_RASB DDR_B_DQ_10 AP13 10
DDR_B_DQ_11 AR13 11
0 BB17 DDR_B_BS_0 DDR_B_DQ_12 AR11 12
6
6
1 AY17 DDR_B_BS_1 DDR_B_DQ_13 AU9 13

2 AY11 DDR_B_BS_2 DDR_B_DQ_14 AV12 14
DDR_B_DQ_15 AU12 15
0 BA25 DDR_B_CSB_0 DDR_B_DQS_2 AP15 2
1 BA29 DDR_B_CSB_1 DDR_B_DQSB_2 AR15 2
2 BA26 DDR_B_CSB_2 DDR_B_DM_2 AW13 2
3 BA30 DDR_B_CSB_3
DDR_B_DQ_16 AU15 16
0 AW11 DDR_B_CKE_0 DDR_B_DQ_17 AV13 17
1 BC12 DDR_B_CKE_1 DDR_B_DQ_18 AU17 18
2 BA10 DDR_B_CKE_2 DDR_B_DQ_19 AT17 19
3 BB10 DDR_B_CKE_3 DDR_B_DQ_20 AU13 20
DDR_B_DQ_21 AM13 21
0 BB27 DDR_B_ODT_0 DDR_B_DQ_22 AV15 22
1 AW29 DDR_B_ODT_1 DDR_B_DQ_23 AW17 23
2 BA27 DDR_B_ODT_2
3 AY29 DDR_B_ODT_3 DDR_B_DQS_3 AT24 3
DDR_B_DQSB_3 AU26 3
DDR_B_DM_3 AP23 3
5
5
DDR_B_DQ_24 AV24 24
M_MAA_B<14..0>
M_SCS_B_N<3..0>
AW31 AT23
M_SBS_B<2..0>
25
M_ODT_B<3..0>
DDR_B_CK_0 DDR_B_DQ_25
M_SCKE_B<3..0>
M_CAS_B_N
M_RAS_B_N
M_WE_B_N
AV31 DDR_B_CKB_0 DDR_B_DQ_26 AT26 26
AU27 DDR_B_CK_1 DDR_B_DQ_27 AP26 27
AT27 DDR_B_CKB_1 DDR_B_DQ_28 AU23 28
AV32 DDR_B_CK_2 DDR_B_DQ_29 AW23 29
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
AT32 DDR_B_CKB_2 DDR_B_DQ_30 AR24 30
AR29 DDR_B_CK_3 DDR_B_DQ_31 AN26 31
25
25
25
25
25
25
25
AU29 DDR_B_CKB_3
AV29 DDR_B_CK_4 DDR_B_DQS_4 AW39 4
26
26
26
26
26
26
26
AW27 DDR_B_CKB_4 DDR_B_DQSB_4 AU39 4
AN33 DDR_B_CK_5 DDR_B_DM_4 AU37 4
AP32 DDR_B_CKB_5
DDR_B_DQ_32 AW37 32
DDR_B_DQ_33 AV38 33
DDR_B_DQ_34 AN36 34
DDR_B_DQ_35 AN37 35
DDR_B_DQ_36 AU35 36
DDR_B_DQ_37 AR35 37
4
4
DDR_B_DQ_38 AN35 38
DDR_B_DQ_39 AR37 39
CK_M_DDR5_B_DP
CK_M_DDR4_B_DP
CK_M_DDR3_B_DP
CK_M_DDR2_B_DP
CK_M_DDR1_B_DP
CK_M_DDR0_B_DP
CK_M_DDR5_B_DN
CK_M_DDR4_B_DN
CK_M_DDR3_B_DN
CK_M_DDR2_B_DN
CK_M_DDR1_B_DN
CK_M_DDR0_B_DN
DDR_B_DQS_5 AL35 5
DDR_B_DQSB_5 AL34 5
DDR_B_DM_5 AM37 5
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DDR_B_DQ_40 AM35 40
25
25
25
25
25
25
25
25
25
25
25
25
DDR_B_DQ_41 AM38 41
TP_DDR_RCOMPXPAD BA2 RSVD DDR_B_DQ_42 AJ34 42
TP_DDR_RCOMPYPAD AW42 RSVD DDR_B_DQ_43 AL38 43
TP_DDR_ANALOG_0 AN32 RSVD DDR_B_DQ_44 AR39 44
TP_DDR_ANALOG_1 AM31 RSVD DDR_B_DQ_45 AM34 45
TP_DDR_OBSERV_0 AG32 RSVD DDR_B_DQ_46 AL37 46
TP_DDR_OBSERV_1 AF32 RSVD DDR_B_DQ_47 AL32 47
TP_DDR_SLEWXDB AP21 RSVD
TP_DDR_SLEWYDB AA39 AG35 6
19
19
19
19
19
19
19
RSVD DDR_B_DQS_6
DDR_B_DQSB_6 AG36 6
DDR_B_DM_6 AG39 6
IN
IN
IN
IN
IN
IN
IN
3
3
DDR_B_DQ_48 AG38 48
DDR_B_DQ_49 AJ38 49
Sun Mar 18 18:43:05
DDR_B DDR_B_DQ_50 AF35 50

DDR_B_DQ_51 AF33 51
DDR_B_DQ_52 AJ37 52
CAD NOTE:
DDR_B_DQ_53 AJ35 53
2007
BPAGE DRAWING
DDR_B_DQ_54 AG33 54
AF34 55
MCH_VREF
DDR_B_DQ_55
BTX SPECIFIC:
ATX SPECIFIC:
TP_B_RCVEN_N AM21 AC36 7
RSVD DDR_B_DQS_7
DDR_B_DQSB_7 AC37 7
AM6 DDR_VREF DDR_B_DM_7 AD38 7
AD36
MCH_DDR_RCOMPVOL
56
MCH_DDR_RCOMPYPU
MCH_DDR_RCOMPYPD
MCH_DDR_RCOMPXPU
MCH_DDR_RCOMPXPD
DDR_B_DQ_56
MCH_DDR_RCOMPVOH
AL4 DDR_RCOMPXPD DDR_B_DQ_57 AC33 57

AL2 DDR_RCOMPXPU DDR_B_DQ_58 AA34 58
BB40 DDR_RCOMPYPD DDR_B_DQ_59 AA36 59
BA40 DDR_RCOMPYPU DDR_B_DQ_60 AD34 60

AM8 DDR_RCOMPVOL DDR_B_DQ_61 AF38 61
[PAGE_TITLE=MCH
AM10 AC34
CUSTOM TEXT
DDR_RCOMPVOH DDR_B_DQ_62 62
2
DDR_B_DQ_63 AA33 63
4 OF 8
INTEL
BPAGE
M_DATA_B<63..0>
IC
M_DQS_B_DP<7..0>
M_DQS_B_DN<7..0>
M_DQM_B<7..0>
CONFIDENTIAL
BI
OUT
OUT
OUT
MODULE
25
25
25
25
SECTIONS
NAME
DO NOT TESTPOINT (U1UB_PIN
xxxxxx
REV
DOCUMENT_NUMBER
1
AW42)
1
TESTPOINT ON DDR_RCOMPY_PAD (U1UB)
12
PAGE
PAGE 3 OF 6]
MODULE REV DETAILS
DATE
3.01
REV
A
C
D
B
8 7 6 5 4 3 2 1
U1UB MODULE REV DETAILS

BRLK_B
2
R10UB 1
70 53 33 13 IN PWRGD_3V PWRGD_3V_R OUT 13 REV=1
5% 0
CH 402 1 13 IN MCH_BSEL0 G20 BSEL0 CRT_HSYNC C15 VGA_HSYNC OUT 17
C147UB 13 IN MCH_BSEL1 J20 BSEL1 CRT_VSYNC E15 VGA_VSYNC OUT 17
220PF MCH_BSEL2 J18 BSEL2
VGA
10% 13 IN
D 50V TP_MCH_K20 K20 ALLZTEST
2 X7R TP_MCH_F20 F20 XORTEST CRT_RED B18 VGA_RED D
402 OUT 17 19 20
13 IN MCH_PIN_G18 G18 MTYPE CRT_GREEN C19 VGA_GREEN OUT 17 19 20
13 MCH_EXP_SLR E18 EXP_SLR CRT_BLUE B20 VGA_BLUE 17 19 20
IN OUT
TP_MCH_K17 K17 RSVD CRT_REDB C18
13 IN MCH_EXP_EN J17 EXP_EN CRT_GREENB D19
13 OUT MCH_RFU_G15 G15 RFU_G15 CRT_BLUEB D20
TP_MCH_L17 L17 RSVD CRT_DDC_DATA L13 VGA_MCH_DDCSDA BI 17 20

13 BI MCH_RFU_E20 E20 RFU_E20 CRT_DDC_CLK M13 VGA_MCH_DDCSCL BI 17 20
DESIGN NOTE: TP_MCH_N18 N18
DEFAULT STUFF (R10UB): DEFENSIVE DESIGN (ENG. EXP) RSVD
0 OHM ISOLATION RESISTOR (R10UB) ON PWRGD_3V TO PWRGD_3V_R TP_MCH_N15 N15 RSVD CRT_IREF A20 VGA_DACREFSET IN 17
TP_MCH_N17 N17 RSVD
TP_MCH_L15 L15 RSVD DPL_REFCLKINP C14 CK_96M_DREF_DP IN 17 29
TP_MCH_L18 L18 RSVD DPL_REFCLKINN D13 CK_96M_DREF_DN IN 17 29 105
TP_MCH_M18 M18 RSVD VCC L12 V_1P25_CORE IN 14 16 17 18 21 34
VSS M11 38 76 82 83 86 98
BOM NOTE: CL_N_DATA AD12 H18 TPEV_PM_EXTTS_N

32 BI CL_DATA RSVD
CL_N_CLK AD13 CL_CLK RSVD F17 TP_PM_BMBUSY_N
MISC
DESIGN NOTE: STUFF R12UB FOR AMT 32 BI
19 IN CL_N_VREF_MCH AM5 CL_VREF RSVD A14 TPEV_XDP_TESTIN_N
FAB A/B ONLY: DEFAULT STUFF (R12UB) FOR BOTH AMT AND NON-AMT CL_RST AA12 CL_RSTB RSTINB AM18 PLTRST_N
32 BI IN 33 68 69 98
AND FOR NON-AMT ADD 0 OHM SOLDER BLOB ACROSS R11UB MCH_CLPWROK_R AM15 CL_PWROK PWROK AM17 PWRGD_3V_R
32 13 IN IN 13
C 1 R12UB 2 ICH_SYNCB J13 ICH_SYNC_N C
MCH_CLPWROK MCH_CLPWROK_R OUT 33
86 39 IN OUT 13 TP_MCH_JTAG_TDI AA10
32 RSVD
0 5% TP_MCH_JTAG_TDO AA9 RSVD NC A42 TPEV_MCH_DET_N
402 EMPTY
TP_MCH_JTAG_TCK AA11 RSVD RSVD R20 TP_FSB_OBS
TP_MCH_JTAG_TMS Y12 RSVD
PWRGD_3V 1 R11UB 2
70 53 33 13 IN
0 5% TP_HPLLMON1_DP U30 RSVD
402 CH TP_HPLLMON1_DN U31 RSVD
TP_HPLLMON2_DP R29 RSVD
BOM NOTE: TP_HPLLMON2_DN R30 RSVD
1 R23BC 2
CAD NOTE: STUFF R11UB FOR NON AMT TP_DPLLMON1_DN U12 RSVD
TP_DPLLMON1_DP U11 RSVD 0 5%
TP_DPLLMON2_DN R12 402 EMPTY
OVERLAP PADS ON R11UB, R12UB RSVD DESIGN NOTE:
TP_DPLLMON2_DP R13 RSVD
DEBUG PURPOSE, ALWAYS EMPTY
5 OF 8
IC
DESIGN NOTE:
ENG FEATURE: NOA STRAPS AND FSBSEL ISOLATION
R13UB
B H_FSBSEL0 1 2 MCH_BSEL0 B
28 8 7 IN OUT 13
10K 5%
402 CH
R15UB
28 8 7 IN
H_FSBSEL1 1 2 MCH_BSEL1 OUT 13
10K 5%
402 CH
R14UB
H_FSBSEL2 1 2
NOA H L DESCRIPTION 28 8 7 IN
10K 5%
MCH_BSEL2 OUT 13
402 CH
0 SEE BSEL TABLE BSEL0 R101UB
1 SEE BSEL TABLE BSEL1 1 2 MCH_RFU_G15 OUT 13
1K 5%
2 SEE BSEL TABLE BSEL2 402 EMPTY
R102UB
4:3 SEE DFT MODE TABLE DFT MODE
1 2 MCH_RFU_E20 OUT 13
5 DDR2 DDR3 MEMORY TYPE BSEL TABLE 1K 5%
402 EMPTY
6 NORM REVERSE PCI-EXPRESS LANE REVERSAL R17UB
A 2 1 0 PSB FREQUENCY 1 2 MCH_PIN_G18 OUT 13
A
7 DISABLE ENABLE FSB HARDWARE STRAPS 1K 5%
0 0 0 267 MHZ (1067) 402 EMPTY
8 CONCURRENT NON-CONCURRENT PCI-E / SDVO CO-EXISTENCE
0 0 1 133 MHZ (533) R18UB
9 DISABLE ENABLE ITPM HOST INTERFACE 1 2 MCH_EXP_SLR
0 1 0 200 MHZ (800) 1K 5%
OUT 13
11 ENABLE DISABLE ME CRYPTO 402 EMPTY
0 1 1 167 MHZ (133)
R16UB
3,4,5,6,7,8,9 ALL HAVE INTERNAL PULL-UPS 1 0 0 333 MHZ (1333) 22 21 IN
EXP_PRSNT_N 1 2 MCH_EXP_EN OUT 13
1 0 1 100 MHZ (133) 0 5%
402 CH
1 1 0 400 MHZ (RSVD) [PAGE_TITLE=MCH SECTIONS PAGE 4 OF 6]
1 1 1 533 MHZ (133) BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
INTEL
xxxxxx 13 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
U1UB
BRLK_B MODULE REV DETAILS
105
82
98
76
BRLK_B MODULE NAME REV DATE
21 18 V_1P25_CORE
REV=1 V_1P25_CORE V_1P25_CL_MCH 19
14 13 IN AJ12 VCC VCC AG24 IN 13 14 16 17 18 21 34 P29 VTT_FSB VCC_CL AL26 IN 14
17 16 AJ11 VCC VCC AG23 38 76 82 83 86 98 105 P27 VTT_FSB VCC_CL AL24 16
38 34 AJ10 AG22 P26 AL23 86
86 83 VCC VCC VTT_FSB VCC_CL
AJ9 VCC VCC AG21 P24 VTT_FSB VCC_CL AL21
AJ8 VCC VCC AG20 P23 VTT_FSB VCC_CL AL20
AJ7 VCC VCC AG19 N29 VTT_FSB VCC_CL AL18
D AJ6 VCC VCC AG18 N26 VTT_FSB VCC_CL AL17
AJ5 VCC VCC AG17 N24 VTT_FSB VCC_CL AL15 D
AH4 VCC VCC AG15 N23 VTT_FSB VCC_CL AK30
AH2 VCC VCC AF26 M29 VTT_FSB VCC_CL AK29
AH1 VCC VCC AF25 M24 VTT_FSB VCC_CL AK27
AG14 VCC VCC AF24 M23 VTT_FSB VCC_CL AJ31
AG13 VCC VCC AF22 L24 VTT_FSB VCC_CL AJ30
AG12 VCC VCC AF20 L23 VTT_FSB VCC_CL AG31
AG11 VCC VCC AF18 K24 VTT_FSB VCC_CL AG30
AG10 VCC VCC AF17 K23 VTT_FSB VCC_CL AF31
AG9 VCC VCC AF15 J24 VTT_FSB VCC_CL AF30
AG8 VCC VCC AE27 J23 VTT_FSB VCC_CL AD32
AG7 VCC VCC AE26 H24 VTT_FSB VCC_CL AD30
AG6 VCC VCC AE17 H23 VTT_FSB VCC_CL AC32
AG5 VCC VCC AD27 G26 VTT_FSB VCC_CL AA32
AG4 VCC VCC AD26 G24 VTT_FSB VCC_CL AJ29
AG3 VCC VCC AD18 G23 VTT_FSB VCC_CL AJ27
AG2 VCC VCC AD15 F26 VTT_FSB VCC_CL AG29
AF14 VCC VCC AC26 F24 VTT_FSB VCC_CL AG27
AF13 VCC VCC AC15 F23 VTT_FSB VCC_CL AG26
AF12 VCC VCC AB26 E29 VTT_FSB VCC_CL AF29
AF11 VCC VCC AB17 E27 VTT_FSB VCC_CL AF27
AF3 VCC VCC AA26 E26 VTT_FSB VCC_CL AD29
AF2 VCC VCC AA15 E23 VTT_FSB VCC_CL AC30
C AF1 VCC VCC Y26 D29 VTT_FSB VCC_CL AC29 C
AE25 VCC VCC Y17 D28 VTT_FSB
POWER
AE23 VCC VCC W 27 D27 VTT_FSB VCC_CL AL12

AE21 VCC VCC W18 C30 VTT_FSB VCC_CL AL11
AE19 V27 C29 AL10 CAD NOTE:
VCC VCC VTT_FSB VCC_CL
AD24 VCC VCC V25 C27 VTT_FSB VCC_CL AL9 PLACE BACKSIDE RESISTOR R19BC CLOSE TO MCH BALL/PIN
AD22 VCC VCC V23 B30 VTT_FSB VCC_CL AL8
AD20 VCC VCC V21 B29 VTT_FSB VCC_CL AL7 1 R19BC
AD14 VCC VCC V19 B28 VTT_FSB VCC_CL AL6 0
AC25 V17 B27 AL5 DESIGN NOTE:
VCC VCC VTT_FSB VCC_CL 1A
AC23 VCC VCC U26 A30 VTT_FSB VCC_CL AK26 2 EMPTY
AC21 U24 A28 AK24 603 ENG FEATURE: 0 OHM RES R19BC (EMPTY)
VCC VCC VTT_FSB VCC_CL
AC19 VCC VCC U22 R27 VTT_FSB VCC_CL AK23
AC6 VCC VCC U15 85 38 34 17 9 8 7 V_FSB_VTT R23 VTT_FSB VCC_CL AK18 1
IN C7BC
AB24 R17
POWER
VCC VCC VCC_CL AK17 .1UF
AB22 VCC VCC AD17 27 25 24 19 18 14 V_SM BC39 VCC_DDR VCC_CL AK15 10%
IN 16V
AB20 VCC VCC AC27 86 82 81 80
V_1P25_PCIEXPRESS BC34 VCC_DDR VCC_CL AK3 2 EMPTY
AA25 AC17 18 17 IN BC30 AK2
VCC VCC VCC_DDR VCC_CL 603
AA23 VCC VCC AB27 BC26 VCC_DDR VCC_CL AK1
AA21 VCC VCC AB18 BC22 VCC_DDR VCC_CL AJ14
B AA19 VCC VCC AA27 BC18 VCC_DDR VCC_CL AJ13 B
AA14 VCC VCC AA17 BC14 VCC_DDR VCC_CL AJ4 CAD NOTE:
81 80 27 25 24 19 18 14 IN V_SM
AA13 VCC VCC Y27 BB39 VCC_DDR VCC_CL AJ3 86 82
AA3 Y18 BB37 AJ2 PLACE CAPS AND MULTI-SITE
VCC VCC VCC_DDR VCC_CL M1UB
Y24 Y15 BB32 AD31 CLOSE TO MCH BALLS FOR V_CKDDR
VCC VCC BOM NOTE: VCC_DDR VCC_CL 1 2
Y22 VCC VCC W26 BB28 VCC_DDR VCC_CL AC31 V_CKDDR
Y20 VCC VCC W 17 DEFAULT (M22UB): 1 OHM 0402 5% BB26 VCC_DDR VCC_CL AA31 MCH_V_CKDDR_R
MULTI
Y14 V26 OPTION (M22UB): 600 OHM FB (A51464-006) BB24 AA30
VCC VCC VCC_DDR VCC_CL 1 1 R94UB IND SM
Y13 VCC VCC V24 DESIGN NOTE: BB20 VCC_DDR VCC_CL Y31 C3UB C2UB 1 2
Y6 VCC VCC V22 BB18 VCC_DDR VCC_CL Y30 .1UF 22UF
EMPTY M22UB FOR NON-GRAPHIC SKU'S 20% 20% 1 5%
W25 VCC VCC V20 BB16 VCC_DDR VCC_CL AJ26 25V 6.3V 402 CH
W23 VCC VCC V18 M22UB BB12 VCC_DDR VCC_CL AJ24 2 Y5V 2 X5R R95UB
W21 V15 AY32 AJ23 603 805 1 2
VCC VCC V_3P3_DAC_FB 1 2 VCC_DDR VCC_CL
W19 U25 14 IN AW24 AJ21
VCC VCC 16 MULTI VCC_DDR VCC_CL 1 5%
V14 VCC VCC U23 AW20 VCC_DDR VCC_CL AJ20 402 CH
V13 U21 CH 1 402 AV26 AJ18
VCC VCC VCC_DDR VCC_CL BOM NOTE:
V12 VCC VCC U19 AV18 VCC_DDR VCC_CL AJ17
V10 VCC VCC U17 DESIGN NOTE: VCC_CL AJ15 DEFAULT: MULTI SITE M1UB TO USE 721891-022 (1UH INDUCTOR)
V9 VCC VCC R18 AC3 VCC_EXP VCC_CL AG25
U14 R15 STUFF R92UB FOR NON-GRAPHIC SKU'S AC4 AA29
VCC VCC R92UB VCC_EXP VCC_CL
U13 VCC 1 2 AD4 VCC_EXP VCC_CL Y29
16 14 IN V_1P25_CL_MCH U10 VCC AD5 VCC_EXP
86 19 U9 VCC VCC R14 0 5% AD6 VCC_EXP
402 EMPTY
ETCH U6 VCC VCC P15 AD7 VCC_EXP VSS V30
DESIGN NOTE: R22BC U3 P14 AD8
A 1 VCC VCC VCC_EXP A
ENG FEATURE: R22BC
0OHM P20 VCC VCC N12 AD9 VCC_EXP VCC_CL AL13 DESIGN NOTE:
N11 BOM NOTE: AD10 AK14
SM VCC VCC_EXP VCC_CL
2 N9 AD11 FOR CRB, TIE THIS PIN TO VSS
VCC DEFAULT (M24UB): 1 OHM 0402 5% VCC_EXP
Y11 N8 AL29 EV: CONNECT TO EVMC OR VREG ( TBD )
VCC VCC OPTION (M24UB): 600 OHM FB (A51464-006) VCC_CL
V_1P25_HPL Y32 VCC_CL_PLL VCC N6 VCC_CL AL27
VCCA_GPLL B15 VCCAPLL_EXP VCC N3 M24UB
16 IN VCCA_HPLL C23 VCCA_HPL VCC L6 V_3P3_DAC_FB
1 2 AC2 VCC_EXP VCC_CKDDR BB41
16 IN 14 IN
TP_MCH_VCCA_HPLL V31 RSVD VCC J6 16 MULTI AD1 VCC_EXP VCC_CKDDR BA42
16 VCCA_MPLL A24 VCCA_MPL VCC J3 CH 1 402 AD2 VCC_EXP VCC_CKDDR AY42
IN VCCA_DPLLA
16 IN A22 VCCA_DPL_A VCC J2 VCC_CKDDR BB42
16 VCCA_DPLLB C22 VCCA_DPL_B VCC G2 C17 VCCA_DAC VCC_CKDDR BA43
IN V_3P3_DAC_FILTERED
VCC F11 B16 VCCA_DAC

VCC F9 V_3P3_VCCABG_EXP A16 VCCA_EXP
VCC3 B17 VCC3_3 VCC D4 16 VCCD_CRT C21 VCCD_CRT
IN
VCC C13 16 IN VCCDQ_CRT B21 VCCDQ_CRT [PAGE_TITLE=MCH SECTIONS PAGE 5 OF 6]
6 OF 8 VCC C9 D16 VSS BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
INTEL
IC xxxxxx 14 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
U1UB MODULE REV DETAILS

U1UB MODULE NAME REV DATE
BRLK_B BRLK_B BRLK_B
BC37 VSS REV=1 VSS AE24 N5 VSS VSS B10 REV=1
BC32 VSS VSS AE22 M37 VSS VSS A39 TP_DDR_DRAMRST
BC28 VSS VSS AE20 M35 VSS VSS A34 DDR3_DRAMRSTB BC16
BC24 VSS VSS AE4 M33 VSS VSS A26 DDR3_DRAM_PWROK AN15 DRAM_PWROK_DDR3
DDR3
BC10 VSS VSS AE3 M27 VSS VSS A18
D BC5 VSS VSS AE2 M21 VSS VSS A12
DDR3_A_CSB1 AY37 DDR3_SCS_A_N1 D
BB7 VSS VSS AD42 M20 VSS VSS A7
DDR3_A_MA0 BB29 DDR3_MAA_A0
AY41 VSS VSS AD39 M17 VSS VSS BC41 1 R109UB
DDR3_A_WEB BB34 DDR3_WE_A_N
AY4 VSS VSS AD37 M15 VSS VSS BC3 0
DDR3_B_ODT3 AW32 DDR3_B_ODT_B3
AW43 VSS VSS AD35 M10 VSS VSS BA1 5%
AW 41 VSS VSS AD33 M7 VSS VSS AY40 2 CH
AV37 AD25 M1 AF23 DESIGN NOTE: 402
VSS VSS VSS VSS
AV35 VSS VSS AD23 L40 VSS VSS AF21 NO TESTPOINT NEEDED ON DDR2 SKEW
AV27 VSS VSS AD21 L33 VSS VSS AF19
AV23 VSS VSS AD19 L32 VSS VSS AE18 DESIGN NOTE:
TEST0 BC43 TP_CGC_NCTF_BC43
AV21 VSS VSS AC38 L31 VSS VSS AC18
TEST1 BC1 TP_CGC_NCTF_BC1 DDR2 BOARDS,STUFF R109UB= 0OHM
AV17 VSS VSS AC35 L29 VSS VSS AA18
TEST2 A43 TP_CGC_NCTF_A43
AV11 AC24 L21 V29
NC
VSS VSS VSS VSS
AV9 VSS VSS AC22 L20 VSS VSS U29
NC N20
AV7 VSS VSS AC20 L11 VSS VSS U27
NC BC42
AV2 VSS VSS AC10 L7 VSS VSS R21
NC BC2
AU42 VSS VSS AC7 L5 VSS VSS E1
NC BB43
AU38 VSS VSS AC5 L3 VSS VSS C43
NC BB2
AU32 VSS VSS AB43 K43 VSS VSS C1
NC BB1
AU24 VSS VSS AB25 K26 VSS VSS A41
NC B43
NC B42
NC B2
AU4 VSS VSS AB19 K13 VSS 8 OF 8
C AT31 VSS VSS AB2 K12 VSS C
AT29 VSS VSS AB1 K2 VSS IC
AT15 VSS VSS AA38 J38 VSS
AR38 VSS VSS AA22 J27 VSS
AR26 VSS VSS Y42 J5 VSS
AR23 Y37 H31
GND
VSS VSS VSS
GND
AR21 VSS VSS Y35 H29 VSS

AP43 VSS VSS Y19 H13 VSS
AP24 VSS VSS Y10 G42 VSS
AN38 VSS VSS Y1 G21 VSS
AN31 VSS VSS W24 G13 VSS
B AN24 VSS VSS W20 G11 VSS B
AN20 VSS VSS V43 G7 VSS
AN13 VSS VSS V39 G1 VSS
AN12 VSS VSS V37 F37 VSS
AM42 VSS VSS V11 F21 VSS
AM29 VSS VSS U38 E43 VSS
AM9 VSS VSS T42 E9 VSS
AM7 VSS VSS T1 E3 VSS
AM4 VSS VSS R36 D40 VSS
AL36 VSS VSS R33 D31 VSS
AK43 VSS VSS R8 D15 VSS
AJ39 VSS VSS R5 D3 VSS
A AJ36 VSS VSS R3 C26 VSS A
AJ33 VSS VSS P43 C11 VSS
AJ32 VSS VSS P30 C6 VSS
AH42 VSS VSS P21 C5 VSS
AG37 VSS VSS P18 C4 VSS
AG34 VSS VSS P17 B37 VSS
AF43 VSS VSS P2 B32 VSS
AF37 VSS VSS N36 B31 VSS
AF6 VSS VSS N10
AF5 VSS VSS N7 [PAGE_TITLE=MCH SECTIONS PAGE 6 OF 6]
7 OF 8 BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
IC frostburg_fabc.sch_1.15
INTEL
xxxxxx 15 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BOM NOTE:
VCC3 DEFAULT (M19UB)STUFF FB 0603 (693286-015)
M2UB
D V_1P25_CL_MCH 1 2 D
16 14 IN
M19UB 86 19 MULTI
1 2 EMPTY SM
MULTI PLACE MULTI-SITES M2UB AND
FB
CAD NOTE:
M10UB IN OVERLAP PATTERN
M10UB
1 2 VCCA_HPLL OUT 14
MULTI C16UB
IND SM 1 2
X5R 603
VCC BOM NOTE: 2.2UF 10%
6.3V
STUFF FOR FAB A VALIDATION
DESIGN NOTE:
M4UB
1 R29UB V_1P25_CL_MCH 1 2
16 14 IN
24 OHM 805 1/8W
24
5% 86 19 MULTI
USE A93555-010 2 EMPTY M18UB EMPTY SM
805
IV_3P3_DAC 1 2 V_3P3_DAC_FB 14
MULTI OUT
M11UB
1 R31UB 1 EMPTY 1 C25UB 1 2
32.4K C12UB 220UF 1 VCCA_MPLL OUT 14
2
1% 4.7UF 20.0% C22UB MULTI
1 Q1UB 20% 25V 1.0UF
CAD NOTE:
PLACE MULTI-SITES M4UB AND VCCA_MPLL_R_PAIR R96UB
MMBT3904 2 EMPTY 10V BOM NOTE: ELEC 20% M11UB IN OVERLAP PATTERN IND SM 1 2
C EMPTY 402
2 EMPTY 2 RDL 2 10V 1 C
3 805 DEFAULT (M18UB): FB 0603 (693286-015) Y5V C10UB 1 5%
V_3P3_DAC_FILTERED_FB 603 10UF
R30UB OPTION: STUFF FB 0603 (693286-015) 402 CH
1 20%
102K
2 6.3V R97UB
1% X5R 1 2
805
2 EMPTY 1 5%
402 402 CH
M6UB
1 2 1 R37UB 2 VCCA_GPLL
VCCA_GPLL_PN1 14
MULTI OUT
BOM NOTE: 1 5%
IND SM 402 CH 1 1
C20UB C17UB
DEFAULT (VCCA_GPLL, M6UB): USE 1 UH 721891-022 10UF .1UF
OPTION: MULTI SITE TO USE 0 OHM A93552-002 20% 10%
CHANGE TO OPTIONAL PART IF RT9199 IS ENABLED AND
1 R28UB 2 2 6.3V
2 16V
X5R X7R
SOURCING PWR. 1 5% 805 603
402 CH
M8UB
105 98 86 83 82 76 38 34 21 18 17 14 13 IN V_1P25_CORE 1 2 VCCA_DPLLA
OUT 14
MULTI
BOM NOTE: IND SM 1 C21UB 1
220UF C23UB
DEFAULT (VCCA_DPLLA, M8UB): USE 10 UH 721891-026
20% .1UF
6.3V 10%
B OPTION: MULTI SITE TO USE 0 OHM A93552-002
2 ALUM 2 16V B
CHANGE TO OPTIONAL PART IF RT9199 IS ENABLED AND SOURCING PWR RDL X7R
603
CHANGE TO 0 OHM RESISTOR FOR NON-GRAPHICS SKU.
BOM NOTE:
C21UB, C19UB: 220 UF CAN BE EMPTY
M9UB IF USING RT9199 OR FOR NON-GRPHICS
SKUS W/SERIES RES
1 2 VCCA_DPLLB
OUT 14
MULTI
BOM NOTE: IND SM 1 C19UB 1
220UF C18UB
BOM NOTE: DEFAULT (VCCA_DPLLB, M9UB): USE 10 UH 721891-026 20% .1UF
DEFAULT (M23UB): 1 OHM 0402 5% OPTION: MULTI SITE TO USE 0 OHM A93552-002 6.3V 10%
DEFAULT (H_VCCPLL, M3UB): FB 0603 (693286-015) BOM NOTE: ALUM 16V
OPTION (M3UB) TBD
OPTION (M23UB): 600 OHM FB (A51464-006) CHANGE TO OPTIONAL PART IF RT9199 IS ENABLED AND SOURCING PWR 2 RDL 2 X7R
CHANGE TO 0 OHM RESISTOR FOR NON-GRAPHICS SKU. 603
M3UB M23UB
H_VCCPLL 2 R127PR 1 1 2 VCCDQ_CRT_PN1 1 2 VCCDQ_CRT
9 6 IN OUT 14
1A 0
MULTI MULTI
BOM NOTE: CH 603 FB CH 1 402
DEFAULT (H_VCCPLL, R127PR): USE 0 OHM,
NON-GRAHPHIC SKU:EMPTY
BOM NOTE:
DEFAULT (VCCDQ, M16UB) GRAPHIC SKU: MULTI SITE TO USE 1 UF (602433-052)
OPTION (VCCDQ, M16UB) NON-GRAPHIC SKU: MULTI SITE TO USE 0 OHM
M16UB DEFENSIVE OPTION (VCCDQ, M16UB): USE 600 OHM FB (A51464-006)
A 1 2 A
MULTI
603 X5R
VCCD_CRT OUT 14
1
C4UB M17UB
4.7UF
10% 1 2 BOM NOTE:
2 6.3V MULTI DEFAULT (VCCD, M17UB) GRAPHIC SKU: MULTI SITE TO USE 0.1UF (602433-056)
X5R
603 603 X7R OPTION (VCCD, M17UB) NON-GRAPHIC SKU: MULTI SITE TO USE 0 OHM
[PAGE_TITLE=PLL & CRT FILTERS]

INTEL
xxxxxx 16 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
R38UB MODULE REV DETAILS

1 2 CPU_MCH_GTLREF IN 6 MODULE NAME REV DATE
17 14 9 8 7 V_FSB_VTT 0 5%
IN 1 DACREFSET & RGB MCH-SIDE TERMINATION
85 38 34
1 402 EMPTY C146UB
1UF
R45UB 20% DESIGN NOTE: VGA_DACREFSET
6.3V CAD NOTE:
100 EMPTY 2 13 OUT
STUFF FOR CPU LEGACY
1% 402 PLACE DACREFSET RES (R44UB) CLOSE
CH 20 19 13
VGA_RED TO MCH: <500 MILS TO MCH BALL
IN
D 402
2 R41UB 20 19 13
VGA_GREEN D
IN
MCH_GTLREF0_DIVIDER 1 2 MCH_GTLREF OUT 10
51 5% 20 19 13
VGA_BLUE
1 IN
1 402 CH 1
R47UB C32UB C30UB 1 R56UB 1 R55UB 1 R54UB 1 R44UB
1.0UF 220PF CAD NOTE:
200 20% 10% 150 150 150 1.3K
1% 10V 50V 1% 1% 1% 1%
CH Y5V 2 EMPTY 2 PLACE VGA RGB RESISTORS CLOSE
2 CH CH CH CH
2 2 2
402 603 402 TO MCH: <250 MILS TO MCH BALLS 402 402 402 402
2 DESIGN NOTE: BOM NOTE:
BOM NOTE:
MCH_GTLREF VOLTAGE SHOULD BE 0.67 * VTT = 0.8V VGA RGB RESISTORS (R54UB-R56UB): REPLACE 150 OHM WITH
CAD NOTE: 100 OHMS OVER 200 OHMS (072905) 0 OHM (A93549-001) FOR NON-GRAPHICS SKUS DACREFSET RESISTOR (R44UB): REPLACE 1.3K
WITH 0 OHM FOR NON-GRAPHICS SKUS
CAP (C30UB) ON GTLREF SHOULD BE CLOSE TO MCH PIN
USE 10MIL TRACE, ISOLATE W/7MIL SPACE AFTER 250 MIL BREAKOUT BOM NOTE:
98 86 83 82 76 38 34 21 18 16 14 13
V_1P25_CORE
105
IN
STUFF R93UB FOR NON-GRAPHICS SKUS 1 R93UB
10K
38 34 V_FSB_VTT CAD NOTE: 5%
9 8 7 IN 2 EMPTY
17 14 29 13
CK_96M_DREF_DP 402
85 HX_SWING VOLTAGE 10MIL TRACE, 10 MIL SPACE AFTER 250 MIL BREAKOUT. IN
C 1 C
PLACE DIVIDER RESISTORS NEAR VTT.
R49UB CK_96M_DREF_DN
301 29 13 IN
1% 1 R98UB
CH BOM NOTE: 0
402 5%
2 2 R88UB 1 2 EMPTY
HXSWING_DIVIDER HXSWING 10 STUFF R98UB FOR NON-GRAPHICS SKUS
OUT 402
1 49.9
402
1%
CH
R48UB 1 C31UB
100 DESIGN NOTE:
1% 0.1UF
CH
20%
16V HX_SWING S/B 1/4*VTT +/- 2% CAD NOTE: HSYNC/VSYNC SLEW RATE & EMI CONTROL
402 2 Y5V
2 402 HSYNC/VSYNC; LOCATE SERIES RESISTOR STRAPS (R52UB, R51UB) WITHIN 750 MILS OF MCH
BOM NOTE:
UN-STUFF 39 OHM SERIES RES (R52UB, R51UB) FOR NON-GRAPHICS SKUS

R52UB
13
VGA_VSYNC 1 2 VGA_VSYNC_3V 20
CAD NOTE: IN OUT
B 39 5% B
402 CH
USE 4MIL TRACE, ISOLATE W/14MIL SPACE AFTER 300 MIL BREAKOUT
R39UB R51UB
17 14 9 8 7 IN V_FSB_VTT 1 2 HXSCOMPB OUT 10
13
VGA_HSYNC 1 2 VGA_HSYNC_3V 20
85 38 34 49.9 1% IN OUT
402 CH 39 5% M25UB M26UB
402 CH 1 2 1 2
R46UB
1 2 HXSCOMP 10
MULTI MULTI
OUT
49.9 1% 402 EMPTY 402 EMPTY
402 CH 2 1 BOM NOTE:
C29UB C26UB
2.7PF 2.7PF
9.25%
FSB COMP SIGNAL 1
9.25%
25V
EMPTY 2 25V
EMPTY
STUFF 0 OHM RES (M25UB, M26UB) FOR NON-GRAPHICS SKUS
TERMINATION 402 402 DESIGN NOTE:

R50UB
1 2 HXRCOMP
MULTI-SITES TO BE USED FOR SLEW RATE/EMI CAPS ON GRAPHIC SKUS
OUT 10
CAD NOTE: 16.5 1%
402 CH
USE 5MIL TRACE, ISOLATE W/5MIL SPACE; IF >250MILS INCREASE TO 10/7 DDC MCH SIDE VCC3 VCC3
CAD NOTE:
TERMINATION
DDC_DATA/DDC_CLK; LOCATE PULL-UPS 1 1
A ANYWHERE ON ROUTE OF TRACE R42UB R43UB A
PCIE COMP SIGNAL TERMINATION 2.2K
5% 2.2K
5%
BOM NOTE:
CH
402 CH
R53UB 402
STUFF R42UB, R43UB FOR GRAPHICS/NON-GRAPHICS SKUS 2 2
18 14 IN V_1P25_PCIEXPRESS 1 2 GRCOMP
OUT 10
24.9 1% 20 13 IN VGA_MCH_DDCSDA
402 CH
20 13 IN VGA_MCH_DDCSCL
[PAGE_TITLE=MCH DECOUPLING AND COMP]

INTEL
xxxxxx 17 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

PCI EXPRESS DECOUPLING MODULE NAME REV DATE
27 25 24 19 14
V_SM
86 82 81 80
IN V_1P25_CORE
IN
2 2 2 2 2
C68UB C61UB C67UB C66UB C65UB
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
10% 10% 10% 10% 10%
D 1 6.3V
1 6.3V
1 6.3V
1 6.3V
1 6.3V I163 V_1P25_PCIEXPRESS
X5R X5R X5R X5R X5R 14 17 D
603 603 603 603 603 OUT
MCH MEMORY DECOUPLING

1 1
C70UB C72UB
2 10UF 10UF
CAD NOTE: C64UB 20% 20%
2.2UF 6.3V 6.3V
10% 2 X5R 2 X5R
6.3V 805 805
SERIES RESISTOR ON SIGNAL MCH_DDR_RCOMPYPU 1 X5R
603
PLACE 2.2UF CAP (C64UB) ON V_SM CLOSE TO 20 OHM
PCI-E SIGNAL TRANSITION STICHING CAPS
VCC_HVGIO DECOUPLING
C 105 98 C
76 38 34 V_1P25_CORE
16 14 13 IN
21 18 17 VCC3 VCC3
86 83 82
1 1 1 1
C36UB C37UB C135UB C136UB
0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20%
16V 16V 16V 16V
2 Y5V 2 Y5V 2 Y5V 2 Y5V 1 1
402 402 402 402 C62UB C35UB
.1UF 4.7UF
20% 20%
25V 10V
2 Y5V 2 Y5V
603 805
B B
A A
[PAGE_TITLE=MCH DCPL & VGA TERMINATION]

INTEL
xxxxxx 18 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
27 25
V_SM 1 R72UB 2
CAD NOTE: MODULE REV DETAILS
18 14 IN MODULE NAME REV DATE
24
81
19
80 1K 1% PLACE 0.1UF CAP CLOSE TO MCH
1 402 CH
86 82 C141UB MCH_VREF OUT 12
.1UF
10%
10V
2 EMPTY 1
402
1 R71UB 2 C76UB
0.1UF
1K 1% 20%
D 402 CH 2 16V
CAD NOTE: Y5V
402
D
PLACE RESISTORS CLOSE TO MCH
ON MCH_VREF
R75UB
1 2 MCH_DDR_RCOMPYPD OUT 12
19.1 1%
402 CH
27 25 CAD NOTE:
18 14 IN V_SM 1 R69MY 2
24 19
81 80 1K 1% PLACE 0.1UF CAP ON DIMM_VREF_B R70UB
86 82
1 402 CH
C60MY 1 2
.1UF CLOSE TO DIMM PIN 86 82 81 80 27 25 24 19 18 14 IN V_SM MCH_DDR_RCOMPYPU OUT 12
10% 19.1 1% CH
2 10V
EMPTY
DIMM_VREF_B OUT 25 1 402
402 R70MY
C145UB
1 2 .1UF
1 20%
CAD NOTE: 1K 1% C58MY 25V
402 CH .1UF
2 Y5V
20% 603
C PLACE RESISTORS CLOSE TO CH_B DIMMS 2 25V C
ON DIMM_VREF_B Y5V
603
R73UB
1 2 MCH_DDR_RCOMPXPD
OUT 12
19.1 1%
402 CH
CAD NOTE:
86 82
27
18
25
14 V_SM 1 R67MY 2 PLACE 0.1UF CAP ON DIMM_VREF_A
IN
24
81
19
80 1K 1% CLOSE TO DIMM PIN R74UB
1 402 CH
C59MY DIMM_VREF_A OUT 24 86 82 81 80 27 25 24 19 18 14 IN V_SM 1 2 MCH_DDR_RCOMPXPU OUT 12
.1UF
10% 19.1 1% CH
1 1
C77UB 1
10V
2 EMPTY C52MY C132UB 402
402
1 R68MY 2 .1UF .1UF .01UF
20% 20% 10% CAD NOTE:
25V
1K 1% 2 25V
Y5V
2 Y5V 2 25V
EMPTY
CAD NOTE: 402 CH 603 402
603 PLACE CAPS CLOSE
B B
TO RCOMPXPU
PLACE RESISTORS CLOSE TO CH_A DIMMS
ON DIMM_VREF_A AND VOH/VOL RESISTORS
86 82 81 80 27 25 24 19 18 14 IN V_SM
1
R60UB
1K DESIGN NOTE:
1%
CH
RGB ESD PROTECTION 402 DDR_RCOMPVOH: 0.8 * VSM
2
17 13 IN VGA_RED MCH_DDR_RCOMPVOH 12
20 OUT
17 13 IN VGA_GREEN
20 1
V_1P25_CL_MCH 1 C133UB
86 16 14 IN 17 13 IN VGA_BLUE .01UF
20 10%
R57UB 1 DESIGN NOTE: VCC3 R61UB 25V
1K 3.01K 2 X7R
1% 1% 402
CL VREF TARGET: 0.349V DESIGN NOTE:
CH 2 CR3UB CR4UB CR5UB DESIGN NOTE: CH
A
402
CL_N_VREF_MCH 3 GP 3 GP 3 GP 2
402
A
OUT 13 SOT23S SOT23S SOT23S DDR_RCOMPVOL: 0.2 * VSM
EMPTY EMPTY EMPTY MAX 0.5 PF
1 MCH_DDR_RCOMPVOL OUT 12
1
1
R58UB C73UB 1
392 0.1UF C80UB 1
1% 20% .1UF 1 2 1 2 1 2 BOM NOTE: R62UB C134UB
16V 20% 1K .01UF
CH 2 Y5V 25V
402 402 Y5V STUFF FOR CRB 1% 10%
25V
2 603 CH 2 X7R
2
402 402
2
[PAGE_TITLE=MCH VREFS & TERMINATION]

INTEL
xxxxxx 19 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
BW_ATX_CORE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BOM NOTE:
BOM NOTE: BW_ATX_CORE 1.06.00 5-5-06
DEFAULT: STUFF FERRITE BEAD <693286-006> FOR <200MHZ BANDWIDTH CUTOFF VCC
CHANGE FOR BANDWIDTH OPTIMIZE FOR CRB REPLACE WITH 0OHM 603 FOR >200MHZ BANDWIDTH CUTOFF
C92281-003
19 17 13 IN VGA_RED M15UB
1 2 RT1UB M12UB
19 17 13 IN VGA_GREEN M14UB MULTI 1 2 VGA_THERM_PN1 1 2
VGA_BLUE 1 2 MULTI 1
D 19 17 13 IN FB C94UB
M13UB MULTI THRMSTR CH 805 .1UF D
1 2 20%
MULTI FB 1.10 2 25V
Y5V
603
FB
693286-006
FB5UB
J4UB
1 2 16
693286-006 VGA_RED_FB1
FB4UB FB VGA_RED_CONN 1
693286-006 1 2 VGA_GREEN_FB1
VGA_THERM_9 9
FB3UB FB VGA_GREEN_CONN 2
1 2 VGA_BLUE_FB1
10
FB VGA_BLUE_CONN 3
TP_VGACONN_11_CORE_R 11
TP_VGACONN_4_CORE 4
12
17 IN VGA_HSYNC_3V 5
17 IN VGA_VSYNC_3V 13
6
1 1 1 14
C89UB BOM NOTE: C93UB C85UB 7
10PF 10PF 10PF 15
5% DEFAULT: STUFF 10PF <A36094-025> FOR BANDWIDTH <200MHZ 5% 5%
8 RCPT
50V REPLACE WITH 3.3PF FOR BANDWITH >200MHZ 50V 50V
2 COG 2 COG 2 COG
C 402 402 402
17 C
1
C87UB
100PF
1 1 1 5% 1
C90UB BOM NOTE: C81UB C84UB 50V C88UB
22PF 22PF 22PF
2 EMPTY 100PF
DEFAULT: STUFF 22PF <A36095-030> FOR BANDWIDTH <200MHZ 402 5%
5% 5% 5% 50V
2 50V REPLACE WITH 3.3PF FOR BANDWITH >200MHZ
2 50V
2 50V 2 EMPTY
COG COG COG 402
402 402 402
1 1 1
C92UB BOM NOTE: C82UB C83UB
10PF 10PF 10PF
5% DEFAULT: STUFF 10PF <A36094-025> FOR BANDWIDTH <200MHZ 5% 5%
50V 50V 50V
2 COG EMPTY FOR BANDWITH >200MHZ 2 COG 2 COG
402 402 402
"COG" "COG" "COG"
A36094-025
B VCC B
1 1 1
CR1UB CR2UB
R84UB R85UB R86UB VCC3 GP GP
150 150 150 3 SOT23S 3 SOT23S
1% CAD NOTE: 1% 1%
CH PLACE RESISTORS CLOSE TO FILTERS CH CH CR7UB
402 (CAPS / FERRITE-BEADS) 402 402 1
2 2 2 R13BU 1 2
1 2 1 2
0 EMPTY EMPTY
1A
2 EMPTY BAT54C DIO
603 3
SOT23C
VGA_DDC_5V_R 1
VGA_DDCSDA_5V_R
C144UB
1
VCC3 1 .1UF
10%
Q2UB R80UB R82UB 2 10V

EMPTY
BOM NOTE: 2.2K 2.2K 402
EMPTY 5% 5%
REPLACE 603400-001 WITH
CH CH
C79254-001 (PB FREE #) 402 402
2 R83UB
R110UB VGA_DDCSDA_5V VGA_DDCSDA_CONN
2
R112UB 1 2 2 1
VGA_MCH_DDCSDA_R
17 13 BI VGA_MCH_DDCSDA 1 2 0 5%
0 5% 402 CH
A 0 5% 402 EMPTY A
402 EMPTY
VCC3 R111UB R81UB
VGA_DDCSCL_5V_R 1 2 VGA_DDCSCL_5V 2 1
VGA_DDCSCL_CONN
R114UB
70 BI VGA_MCHSIO_DDCSDA 1 2 0
402
5%
EMPTY
0
402
5%
CH 1 1
TP_TVS6_2V_PIN4
TP_TVS6_2V_PIN6
0 5% Q3UB C86UB C91UB
402 CH EMPTY BOM NOTE: R116UB 100PF 100PF
1 2 VGA_SIO_DDCSDA_5V BI 70 5% 5%
50V 50V
REPLACE 603400-001 WITH 100 5% 6.2V 1 3 4 6 CR6UB 2 EMPTY 2 EMPTY
C79254-001 (PB FREE #) 402 CH TVS6_2V 402 402
VGA_MCH_DDCSCL R113UB EMPTY
17 13 BI 1 2 VGA_MCH_DDCSCL_R
0 5% R117UB
402 EMPTY 1 2 VGA_SIO_DDCSCL_5V 70
2 5
BI
R115UB 100 5%
70 BI VGA_MCHSIO_DDCSCL 1 2 402 CH [PAGE_TITLE=VGA CONNECTOR]
BOM NOTE:
0 5% BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
402 CH
UN-STUFF ALL COMPONENTS ON PAGE FOR NON-GRAPHICS SKUS frostburg_fabc.sch_1.20
INTEL
xxxxxx 20 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
BW_ATX_CORE
8 7 6 5 4 3 2 1
VCC3 +12V +12V VCC3 MODULE REV DETAILS

J6UB MODULE NAME REV DATE
SLOT 1 3GIO_X16
REV=2.0 BW_ATX_CORE 1.06.00 5-5-06
B1 12V PRSNT1* A1
PCI EXPRESS B2 A2
12V 12V
16-PORT 70 49 48 47 33 28 27 22 SMB_CLK_RESUME
B3 12V 12V A3
BI B4 GND GND A4
D RIGHT LATCH 105 103 102 101
B5 A5 TP_3G16_JTAG2 VCC3
(DEFAULT) SMCLK JTAG2 22
101 70 49 48 47 33 28 27 22 BI SMB_DATA_RESUME B6 SMDAT JTAG3 A6 TP_3G16_JTAG3 22 D
105 103 102 B7 GND JTAG4 A7 TP_3G16_JTAG4 22 C98UB
BOM NOTE: B8 A8 TP_3G16_JTAG5 1 2
105 103
3.3V JTAG5 22
STUFF J6UB 88 87 86 85 84 82 70 69 64 59 53 22 TP_3G16_JTAG1 B9 JTAG1 3.3V A9
V_3P3_STBY\G B10 A10 .1UF 20%
EMPTY J10UB 39 38 37 36 34 33 32 28 22 21 9 IN 3.3VAUX 3.3V 25V
49 48 47 102 101 98 47 36 33 22 OUT WAKE_N B11 WAKE* PWRGD A11 PLTRST_PCIE_SLOTS_N
IN 22 47 70 101 102 EMPTY
102 101 92 90 603
KEY +12V
22 TP_3G16_RSVD_B12 B12 RSVD GND A12
B13 A13 CK_PE_100M_16PORT_DP C97UB
GND REFCLK+ IN 22 29 1 2
23 22 IN EXP_A_TX_0_C_DP B14 HSOP0 REFCLK- A14 CK_PE_100M_16PORT_DN IN 22 29
23 22 IN EXP_A_TX_0_C_DN B15 HSON0 GND A15 .1UF 20%
B16 GND HSIP0 A16 EXP_A_RX_0_DP OUT 10 22 25V
SDVO_CTRL_CLK EXP_A_RX_0_DN Y5V
22 10 IN B17 PRSNT2* HSIN0 A17 OUT 10 22 603
B18 GND GND A18 105 103 102 101 92
49 48 47 39 38 37 36 34 33 32 28 22 21 9 IN V_3P3_STBY\G
90 88 87 86 85 84 82 70 69 64 59 53
23 22 IN EXP_A_TX_1_C_DP B19 HSOP1 RSVD A19 TP_3G16RSVD_A19 22
23 22 IN EXP_A_TX_1_C_DN B20 HSON1 GND A20
B21 A21 EXP_A_RX_1_DP C96UB
GND HSIP1 OUT 10 22 1 2
B22 GND HSIN1 A22 EXP_A_RX_1_DN OUT 10 22
23 22 IN EXP_A_TX_2_C_DP B23 HSOP2 GND A23 .1UF 20%
23 22 IN EXP_A_TX_2_C_DN B24 HSON2 GND A24 25V
C B25 A25 EXP_A_RX_2_DP Y5V C
GND HSIP2 OUT 10 22 603
23 22 IN EXP_A_TX_3_C_DP B27 HSOP3 GND A27
B29 A29 EXP_A_RX_3_DP DESIGN NOTE:
GND HSIP3 OUT 10 22
B30 RSVD HSIN3 A30 EXP_A_RX_3_DN OUT 10 22 ALWAYS STUFF C99UB & C95UB
22 10 IN SDVO_CTRL_DATA B31 PRSNT2* GND A31
B32 A32 TP_3G16_RSVD_A32 EVEN IF J6UB IS EMPTY
GND RSVD 22
FOR X1 DECOUPLING
EXP_A_TX_4_C_DP B33 A33 TP_3G16_RSVD_A33 +12V VCC3
23 22 IN EXP_A_TX_4_C_DN HSOP4 RSVD 22
23 22 IN B34 HSON4 GND A34 C99UB C95UB
B35 A35 EXP_A_RX_4_DP 470.0UF 100UF
GND HSIP4 OUT 10 22 1 2 1 2
23 22 IN EXP_A_TX_5_C_DP B37 HSOP5 GND A37 20% 16V 20.0% 25V
23 22 IN EXP_A_TX_5_C_DN B38 HSON5 GND A38 ALUM ELEC
B39 GND HSIP5 A39 EXP_A_RX_5_DP OUT 10 22 RDL RDL
B43 GND HSIP6 A43 EXP_A_RX_6_DP OUT 10 22
B 23 22 EXP_A_TX_7_C_DP B45 HSOP7 GND A45 B
IN
B47 A47 EXP_A_RX_7_DP DESIGN NOTE:
GND HSIP7 OUT 10 22
22 13 OUT EXP_PRSNT_N B48 PRSNT2* HSIN7 A48 EXP_A_RX_7_DN OUT 10 22 CAD NOTE: ATX FF ONLY
B49 GND GND A49
PLACE NEAR EDGE OF PEG SLOT
EXP_A_TX_8_C_DP B50 A50 TP_3G16_RSVD_A50 FOR SIGNAL TRANSITION REF
23 22 IN HSOP8 RSVD 22
23 22 IN EXP_A_TX_8_C_DN B51 HSON8 GND A51 V_1P25_CORE
B52 A52 EXP_A_RX_8_DP IN 13 14 16 17 18 34 38 76 82
GND HSIP8 OUT 10 22 83 86 98 105
23 22 EXP_A_TX_9_C_DN B55 HSON9 GND A55
IN EXP_A_RX_9_DP
B56 GND HSIP9 A56 OUT 10 22
23 22 IN EXP_A_TX_10_C_DP B58 HSOP10 GND A58 2 2 2 2 2
EXP_A_TX_10_C_DN B59 A59 C44BU C45BU C46BU C47BU C48BU
23 22 IN HSON10 GND 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
B60 GND HSIP10 A60 EXP_A_RX_10_DP OUT 10 22 20% 20% 20% 20% 20%
B61 A61 EXP_A_RX_10_DN 16V 16V 16V 16V 16V
GND HSIN10 OUT 10 22 1 Y5V 1 EMPTY 1 Y5V 1 Y5V 1 EMPTY
23 22 IN EXP_A_TX_11_C_DP B62 HSOP11 GND A62 402 402 402 402 402
C73571-001 B65 A65 EXP_A_RX_11_DN
GND HSIN11 OUT 10 22
J5UB 23 22 IN EXP_A_TX_12_C_DP B66 HSOP12 GND A66
A PCIE_RM
23 22 IN EXP_A_TX_12_C_DN B67 HSON12 GND A67 A
B68 GND HSIP12 A68 EXP_A_RX_12_DP OUT 10 22 2 2 2
B69 A69 EXP_A_RX_12_DN C49BU C50BU C51BU
GND HSIN12 OUT 10 22 0.1UF 0.1UF 0.1UF
1 23 22 EXP_A_TX_13_C_DP B70 HSOP13 GND A70 20% 20% 20%
2
GND
IN EXP_A_TX_13_C_DN 16V 16V 16V
GND 23 22 IN B71 HSON13 GND A71 1 Y5V 1 EMPTY 1 Y5V
B72 GND HSIP13 A72 EXP_A_RX_13_DP OUT 10 22 402 402 402
1.0 B73 A73 EXP_A_RX_13_DN
EMPTY
GND HSIN13 OUT 10 22
PCI E RETENTION MODEL B77 GND HSIN14 A77 EXP_A_RX_14_DN OUT 10 22
22 TP_3G16_RSVD_B80 B81 PRSNT2* HSIN15 A81 EXP_A_RX_15_DN OUT 10 22
22 TP_16PRSNT_B82 B82 RSVD 1 OF 1 GND
A82 [PAGE_TITLE=PCI EXPRESS X16]
CONN
INTEL
xxxxxx 21 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
BW_ATX_CORE
8 7 6 5 4 3 2 1
VCC3 +12V +12V VCC3 MODULE REV DETAILS

J10UB MODULE NAME REV DATE
SLOT 1 3GIO_X16
REV=2.0 BW_ATX_CORE 1.06.00 5-5-06
B1 12V PRSNT1* A1
PCI EXPRESS B2 A2
12V 12V
16-PORT 101 70 49 48 47 33 28 27 21 SMB_CLK_RESUME
B3 12V 12V A3
BI B4 GND GND A4
D LEFT LATCH 105 103 102
B5 A5 TP_3G16_JTAG2
SMCLK JTAG2 21
103 102 101 70 49 48 47 33 28 27 21 BI SMB_DATA_RESUME B6 SMDAT JTAG3 A6 TP_3G16_JTAG3 21 D
BOM NOTE: 105 B7 GND JTAG4 A7 TP_3G16_JTAG4 21
B8 3.3V JTAG5 A8 TP_3G16_JTAG5 21
STUFF J6UB TP_3G16_JTAG1 B9 A9
EMPTY J10UB 101 92 90 88 87 86 85 84 82 70 69 21 JTAG1 3.3V
47 39 38 37 36 34 33 32 28 21 9 IN V_3P3_STBY\G B10 3.3VAUX 3.3V A10
64 59 53 49 48 102 101 98 47 36 33 21 OUT WAKE_N B11 WAKE* PWRGD A11 PLTRST_PCIE_SLOTS_N
IN 21 47 70 101 102
105 103 102
KEY
21 TP_3G16_RSVD_B12 B12 RSVD GND A12
B13 GND REFCLK+ A13 CK_PE_100M_16PORT_DP IN 21 29
23 21 IN EXP_A_TX_0_C_DP B14 HSOP0 REFCLK- A14 CK_PE_100M_16PORT_DN IN 21 29
21 10 IN SDVO_CTRL_CLK B17 PRSNT2* HSIN0 A17 EXP_A_RX_0_DN OUT 10 21
B18 GND GND A18
DESIGN NOTE:
23 21 IN EXP_A_TX_1_C_DP B19 HSOP1 RSVD A19 TP_3G16RSVD_A19 21
B21 A21 EXP_A_RX_1_DP PCIE X16 GRAPHIC CONNECTOR WITH LEFT LATCH
GND HSIP1 OUT 10 21
C B25 A25 EXP_A_RX_2_DP C
GND HSIP2 OUT 10 21
B30 RSVD HSIN3 A30 EXP_A_RX_3_DN OUT 10 21
21 10 IN SDVO_CTRL_DATA B31 PRSNT2* GND A31
B32 GND RSVD A32 TP_3G16_RSVD_A32 21
23 21 EXP_A_TX_4_C_DP B33 HSOP4 RSVD A33 TP_3G16_RSVD_A33 21

IN EXP_A_TX_4_C_DN
23 21 IN B34 HSON4 GND A34
B 23 21 EXP_A_TX_7_C_DP B45 HSOP7 GND A45 B
IN
21 13 OUT EXP_PRSNT_N B48 PRSNT2* HSIN7 A48 EXP_A_RX_7_DN OUT 10 21
B49 GND GND A49
23 21 IN EXP_A_TX_8_C_DP B50 HSOP8 RSVD A50 TP_3G16_RSVD_A50 21

23 21 EXP_A_TX_9_C_DN B55 HSON9 GND A55
IN EXP_A_RX_9_DP
B56 GND HSIP9 A56 OUT 10 21
A 23 21 IN EXP_A_TX_12_C_DN B67 HSON12 GND A67 A
23 21 EXP_A_TX_13_C_DP B70 HSOP13 GND A70
IN EXP_A_TX_13_C_DN
23 21 IN B71 HSON13 GND A71
21 TP_3G16_RSVD_B80 B81 PRSNT2* HSIN15 A81 EXP_A_RX_15_DN OUT 10 21
21 TP_16PRSNT_B82 B82 RSVD 1 OF 1 GND
A82 [PAGE_TITLE=PCI EXPRESS X16]
EMPTY
INTEL
xxxxxx 22 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
BW_ATX_CORE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BW_ATX_CORE 1.06.00 5-5-06
D
EXP_A_TX_0_C_DN D
C103UB C102UB OUT 21 22
10 IN EXP_A_TX_0_DN 1 2 1 2 EXP_A_TX_0_C_DP OUT 21 22
10 IN EXP_A_TX_0_DP
.1UF 10% .1UF 10%
10V 10V BOM NOTE:
X5R X5R
402 402
STUFF ALL THE CAPS

EVEN UNSTUFF THE PCIEX16
C101UB
10 IN EXP_A_TX_1_DN 1 2
C100UB EXP_A_TX_1_C_DN OUT 21 22
10 IN EXP_A_TX_1_DP 1 2 EXP_A_TX_1_C_DP OUT 21 22
.1UF 10%
10V .1UF 10%
X5R 10V C109UB
10 IN EXP_A_TX_2_DN 402 X5R 1 2
10 IN EXP_A_TX_2_DP 402 1 2 EXP_A_TX_2_C_DP OUT 21 22
.1UF 10%
10V .1UF 10%
C107UB X5R 10V
10 EXP_A_TX_3_DN 1 2
C106UB
402 X5R EXP_A_TX_3_C_DN 21 22
IN OUT
C .1UF 10% C
10V .1UF 10%
X5R 10V
402 X5R
402
C105UB
.1UF 10%
10V .1UF 10%
C116UB X5R 10V
C115UB
402 X5R EXP_A_TX_5_C_DN OUT 21 22
.1UF 10%
10V .1UF 10%
X5R 10V C114UB
10 IN EXP_A_TX_6_DN 402 X5R 1 2
.1UF 10%
10V .1UF 10%
C112UB X5R 10V
C111UB
.1UF 10%
10V .1UF 10%
X5R 10V
402 X5R
B 402 B
EXP_A_TX_8_DN
C104UB
1 2 EXP_A_TX_8_C_DN OUT 21 22
10 IN C110UB
.1UF 10%
10V .1UF 10%
C122UB X5R 10V
C121UB
.1UF 10%
10V .1UF 10%
X5R C120UB
EXP_A_TX_10_DN 402 10V
X5R 1 2 EXP_A_TX_10_C_DN OUT 21 22
10 IN C119UB
.1UF 10%
10V .1UF 10%
C118UB X5R 10V
C131UB
.1UF 10%
10V .1UF 10%
X5R 10V C130UB EXP_A_TX_12_C_DN
10 IN EXP_A_TX_12_DN 402 X5R 1 2
C129UB OUT 21 22
.1UF 10%
10V .1UF 10%
C128UB X5R 10V
C127UB
10 IN EXP_A_TX_13_DP 1 2 402
EXP_A_TX_13_C_DP
.1UF 10% OUT 21 22
A 10V .1UF 10%
A
X5R
EXP_A_TX_14_DN 402 10V
X5R
C126UB
1 2 EXP_A_TX_14_C_DN OUT 21 22
10 IN C125UB
.1UF 10%
10V .1UF 10%
C124UB X5R
EXP_A_TX_15_DN 1 2 402 10V
X5R
EXP_A_TX_15_C_DN OUT 21 22
10 IN C123UB
.1UF 10%
10V .1UF 10%
X5R 10V
402 X5R
402
[PAGE_TITLE=PCI EXPRESS X16 COUPLING]

INTEL
xxxxxx 23 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
A
C
D
B
24
26
11 11
24
26
24
24
24
24
24
11
11
11
11
11
BI
BI
BI
CR-24
BI
BI
BI
IO
IO :
8
2 VSS NC 68 8
2 VSS NC 68 5 VSS NC/TEST 102
5 VSS NC/TEST 102 8 VSS NC 19
8 VSS NC 19 11 VSS
11 VSS 14 VSS ODT1 77 1
14 VSS ODT1 77 3 17 VSS ODT0 195 0
17 VSS ODT0 195 2 20 VSS
TP_SA_CB0_0
23 42
CHANNEL A
20 VSS VSS CB<0>
TP_SA_CB_0 TP_SA_CB0_1
23 VSS CB<0> 42 26 VSS CB<1> 43
26 VSS CB<1> 43 29 VSS CB<2> 48
29 VSS CB<2> 48 TP_SA_CB_3
32 VSS CB<3> 49
TP_SA_CB0_4
M_ODT_A<3..0>
M_ODT_A<3..0>
32 VSS CB<3> 49 35 VSS CB<4> 161
35 VSS CB<4> 161 38 VSS CB<5> 162
M_DQS_A_DP<7..0>
M_DQS_A_DN<7..0>
38 VSS CB<5> 162 41 VSS CB<6> 167
M_DQS_A_DP<7..0>
M_DQS_A_DN<7..0>
41 VSS CB<6> 167 44 VSS CB<7> 168
TP_SA_CB_7
44 VSS CB<7> 168 47 VSS
47 VSS 50 VSS DQS<0> 7 0
50 VSS DQS<0> 7 0 65 VSS DQS*<0> 6 0
65 VSS DQS*<0> 6 0 66 VSS
66 VSS 79 VSS DQS<1> 16 1
7
7
79 VSS DQS<1> 16 1 82 VSS DQS*<1> 15 1

82 VSS DQS*<1> 15 1 85 VSS
85 VSS 88 VSS DQS<2> 28 2
88 VSS DQS<2> 28 2 91 VSS DQS*<2> 27 2
24
91 VSS DQS*<2> 27 2 94 VSS

94 VSS 97 VSS DQS<3> 37 3
24
11
97 VSS DQS<3> 37 3 100 VSS DQS*<3> 36 3

103
11
100 VSS DQS*<3> 36 3 VSS
103 VSS 106 VSS DQS<4> 84 4
BI
106 VSS DQS<4> 84 4 109 VSS DQS*<4> 83 4
BI
109 VSS DQS*<4> 83 4 112 VSS
112 VSS 115 VSS DQS<5> 93 5
115 VSS DQS<5> 93 5 118 VSS DQS*<5> 92 5
118 VSS DQS*<5> 92 5 121 VSS
121 VSS 124 VSS DQS<6> 105 6
124 VSS DQS<6> 105 6 127 VSS DQS*<6> 104 6
127 VSS DQS*<6> 104 6 130 VSS
130 VSS 133 VSS DQS<7> 114 7
86
133 VSS DQS<7> 114 7 136 VSS DQS*<7> 113 7
86
136 VSS DQS*<7> 113 7 139 VSS
6
82
6
139 VSS 142 VSS DQS<8> 46 TP_SA_DQS0_8
82
81
142 VSS DQS<8> 46 TP_SA_DQS_8 145 VSS DQS*<8> 45 TP_SA_DQSB0_8

M_DQM_A<7..0>
145 VSS DQS*<8> 45 TP_SA_DQSB_8 148 VSS
81
M_DQM_A<7..0>
80
148 VSS 151 VSS DM0/DQS9 125 0

151 VSS DM0/DQS9 125 0 154 VSS NC/DQS9* 126
80
27
154 VSS NC/DQS9* 126 157 VSS

157 VSS 160 VSS DM1/DQS10 134
27
1
25
25
163 VSS NC/DQS10* 135 166 VSS
24
27
27
166 VSS 169 VSS DM2/DQS11 146 2
24
169 VSS DM2/DQS11 146 198 VSS NC/DQS11* 147
19
2
25
25
198 VSS NC/DQS11* 147 201 VSS
19
27
27
18
201 VSS 204 VSS DM3/DQS12 155 3

24
24
18
24
25
25
24 19
14
207 VSS NC/DQS12* 156 210 VSS

210 VSS 213 VSS DM4/DQS13 202 4
19
14
24
24
BI
BI
IN
IN

216 VSS NC/DQS13* 203 219 VSS
BI
BI
IN
IN
219 VSS 222 VSS DM5/DQS14 211 5
5
5
225 VSS NC/DQS14* 212 228 VSS

228 VSS 231 VSS DM6/DQS15 223 6
V_SM
231 VSS DM6/DQS15 223 234 VSS NC/DQS15* 224

27
6
234 VSS NC/DQS15* 224 237 VSS
27
V_SM
25
237 VSS 51 VDDQ DM7/DQS16 232 7

DIMM_VREF_A
51 VDDQ DM7/DQS16 232 7 56 VDDQ NC/DQS16* 233
25
24
56 VDDQ NC/DQS16* 233 62 VDDQ
DIMM_VREF_A
[PAGE_TITLE=240P
62 VDDQ 72 VDDQ DM8/DQS17 164
24
IN
72 VDDQ DM8/DQS17 164 75 VDDQ NC/DQS17* 165
SMB_CLK_MEM
SMB_DATA_MEM
SMB_CLK_MEM
75 VDDQ NC/DQS17* 165 78 VDDQ
IN
SMB_DATA_MEM
78 VDDQ 191 VDDQ DQ<0> 3 0

191 VDDQ DQ<0> 3 0 194 VDDQ DQ<1> 4 1
194 VDDQ DQ<1> 4 1 181 VDDQ DQ<2> 9 2
181 VDDQ DQ<2> 9 2 175 VDDQ DQ<3> 10 3
175 VDDQ DQ<3> 10 3 170 VDDQ DQ<4> 122 4
170 VDDQ DQ<4> 122 4 53 VDD DQ<5> 123 5
53 VDD DQ<5> 123 5 59 VDD DQ<6> 128 6
59 VDD DQ<6> 128 6 64 VDD DQ<7> 129 7
64 VDD DQ<7> 129 7 197 VDD DQ<8> 12 8
197 VDD DQ<8> 12 8 69 VDD DQ<9> 13 9
4
V_3P3_MEM
4
69 VDD DQ<9> 13 9 172 VDD DQ<10> 21 10
172 VDD DQ<10> 21 10 187 VDD DQ<11> 22 11
CONN DDR2,
V_3P3_MEM
187 VDD DQ<11> 22 11 184 VDD DQ<12> 131 12
M_DATA_A<63..0>
184 VDD DQ<12> 131 12 178 VDD DQ<13> 132 13

M_DATA_A<63..0>
178 VDD DQ<13> 132 13 189 VDD DQ<14> 140 14

189 VDD DQ<14> 140 14 67 VDD DQ<15> 141 15
TP_CH_A1_RC0_RFU
TP_CH_A1_RC1_RCU
67 VDD DQ<15> 141 15 DQ<16> 24 16

TP_CH_A2_RC0_RFU
TP_CH_A2_RC1_RCU
BI
DQ<16> 24 16 18 RC1 DQ<17> 25 17

BI
18 RC1 DQ<17> 25 17 55 RC0 DQ<18> 30 18
CH A]
55 RC0 DQ<18> 30 18 238 VDDSPD DQ<19> 31 19
11
238 VDDSPD DQ<19> 31 19 1 VREF DQ<20> 143 20

11
1 VREF DQ<20> 143 20 120 SCL DQ<21> 144 21

24
120 SCL DQ<21> 144 21 119 SDA DQ<22> 149 22

24
119 SDA DQ<22> 149 22 101 SA2 DQ<23> 150 23

101 SA2 DQ<23> 150 23 240 SA1 DQ<24> 33 24
240 SA1 DQ<24> 33 24 239 SA0 DQ<25> 34 25
239 SA0 DQ<25> 34 25 DQ<26> 39 26
DQ<26> 39 26 1 190 BA1 DQ<27> 40 27
1 190 BA1 DQ<27> 40 27 0 71 BA0 DQ<28> 152 28
0 71 BA0 DQ<28> 152 28 DQ<29> 153 29
3
3
DQ<29> 153 29 1 171 CKE1 DQ<30> 158 30
3 171 CKE1 DQ<30> 158 30 0 52 CKE0 DQ<31> 159 31
Sun Mar 18 18:43:19
2 52 CKE0 DQ<31> 159 31 DQ<32> 80 32

DQ<32> 80 32 1 76 S1* DQ<33> 81 33
3 76 S1* DQ<33> 81 33 0 193 S0* DQ<34> 86 34
2 193 S0* DQ<34> 86 34 DQ<35> 87 35
2007
BPAGE DRAWING
DQ<35> 87 35 221 CK2*/RFU DQ<36> 199 36

221 CK2*/RFU DQ<36> 199 36 220 CK2/RFU DQ<37> 200 37
220 CK2/RFU DQ<37> 200 37 138 CK1*/RFU DQ<38> 205 38
138 CK1*/RFU DQ<38> 205 137 CK1/RFU DQ<39> 206 39
38
137 CK1/RFU DQ<39> 206 39 186 CK0* DQ<40> 89 40
186 CK0* DQ<40> 89 40 185 CK0 DQ<41> 90 41
185 CK0 DQ<41> 90 41 DQ<42> 95 42
DQ<42> 95 42 0 188 A0 DQ<43> 96 43
0 188 A0 DQ<43> 96 43 1 183 A1 DQ<44> 208 44
1 183 A1 DQ<44> 208 44 2 63 A2 DQ<45> 209 45
2 63 A2 DQ<45> 209 45 3 182 A3 DQ<46> 214 46
3 182 A3 DQ<46> 214 46 4 61 A4 DQ<47> 215 47

4 61 A4 DQ<47> 215 47 5 60 A5 DQ<48> 98 48
5 6 180 99
CUSTOM TEXT
60 A5 DQ<48> 98 48 A6 DQ<49> 49
2
6 180 A6 DQ<49> 99 49 7 58 A7 DQ<50> 107 50

7 58 A7 DQ<50> 107 50 8 179 A8 DQ<51> 108 51
8 179 A8 DQ<51> 108 51 9 177 A9 DQ<52> 217 52
INTEL
BPAGE
9 177 A9 DQ<52> 217 52 10 70 A10/AP DQ<53> 218 53

10 70 A10/AP DQ<53> 218 53 11 57 A11 DQ<54> 226 54
11 57 A11 DQ<54> 226 12 176 A12 DQ<55> 227 55
CONFIDENTIAL
54
12 176 A12 DQ<55> 227 55 13 196 A13 DQ<56> 110 56
13 196 A13 DQ<56> 110 56 14 174 A14 DQ<57> 111 57
14 174 A14 DQ<57> 111 57 173 A15 DQ<58> 116 58
173 A15 DQ<58> 116 58 2 54 A16/BA2 DQ<59> 117 59
MODULE
2 54 A16/BA2 DQ<59> 117 59 DQ<60> 229 60

DQ<60> 229 60 74 CAS* DQ<61> 230 61
74 CAS* DQ<61> 230 61 192 RAS* DQ<62> 235 62
TP_M_MAA_A15
NAME
192 RAS* DQ<62> 235 62 73 WE* DQ<63> 236 63

73 WE* DQ<63> 236
TP_M1_MAA_A15
63
M_SBS_A<2..0>
xxxxxx
DDRII_240P
M_SCKE_A<3..0>
M_SBS_A<2..0>
M_SCS_A_N<3..0>
DDRII_240P J1MY
M_SBS_A<2..0>
M_SCKE_A<3..0>
CK_M_DDR2_A_DN
CK_M_DDR1_A_DN
CK_M_DDR0_A_DN
M_MAA_A<14..0>
M_SCS_A_N<3..0>
J2MY
M_SBS_A<2..0>
CK_M_DDR2_A_DP
CK_M_DDR1_A_DP
CK_M_DDR0_A_DP
M_MAA_A<14..0>
M_CAS_A_N
M_CAS_A_N
M_RAS_A_N
M_WE_A_N
CK_M_DDR5_A_DP
CK_M_DDR4_A_DP
CK_M_DDR3_A_DP
CK_M_DDR5_A_DN
CK_M_DDR4_A_DN
CK_M_DDR3_A_DN
M_RAS_A_N
M_WE_A_N
REV
DOCUMENT_NUMBER
1
0 X A0
IN
IN
IN
IN
IN
IN
IN
IN
IN
1
BI
BI
BI
BI
BI
0 X A2
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
11
11
11
11
11
11
11
11
11
ADDRESS:
24
11
11
11
11
11
11
11
11
11
11
11
11
11
ADDRESS:
PAGE
11
11
11
11
11
11
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
26
26
26
MODULE REV DETAILS
DATE
000
26
26
26
26
26
26
26
26
3.01
001
26
26
26
26
26
REV
A
C
D
B
A
C
D
B
26
26
25
25
25
25
25
25
12
12
12
12
12
12
BI
BI
BI
BI
BI
BI
CR-25
IO IO
:
8
2 VSS NC 68 2 VSS NC 68 8
5 VSS NC/TEST 102 5 VSS NC/TEST 102
8 VSS NC 19 8 VSS NC 19
11 VSS 11 VSS
14 VSS ODT1 77 3 14 VSS ODT1 77 1
17 VSS ODT0 195 2 17 VSS ODT0 195 0
20 VSS 20 VSS
TP_SB_CB_0 TP_SB_CB0_0
CHANNEL B
23 VSS CB<0> 42 23 VSS CB<0> 42
26 VSS CB<1> 43 26 VSS CB<1> 43
29 VSS CB<2> 48 29 VSS CB<2> 48
M_ODT_B<3..0>
32 VSS CB<3> 49 32 VSS CB<3> 49 M_ODT_B<3..0>
35 VSS CB<4> 161 35 VSS CB<4> 161
38 VSS CB<5> 162 38 VSS CB<5> 162
M_DQS_B_DP<7..0>
M_DQS_B_DP<7..0>
M_DQS_B_DN<7..0>
M_DQS_B_DN<7..0>
41 VSS CB<6> 167 41 VSS CB<6> 167
44 VSS CB<7> 168 44 VSS CB<7> 168
47 VSS 47 VSS
50 VSS DQS<0> 7 0 50 VSS DQS<0> 7 0
65 VSS DQS*<0> 6 0 65 VSS DQS*<0> 6 0
66 VSS 66 VSS
79 VSS DQS<1> 16 1 79 VSS DQS<1> 16 1
7
7
82 VSS DQS*<1> 15 1 82 VSS DQS*<1> 15 1

85 VSS 85 VSS
88 VSS DQS<2> 28 2 88 VSS DQS<2> 28 2
91 VSS DQS*<2> 27 2 91 VSS DQS*<2> 27 2
25
25
94 VSS 94 VSS
97 VSS DQS<3> 37 3 97 VSS DQS<3> 37 3
12
12
100 VSS DQS*<3> 36 3 100 VSS DQS*<3> 36 3

103 VSS 103 VSS
106 VSS DQS<4> 84 4 106 VSS DQS<4> 84 4
BI
BI
109 VSS DQS*<4> 83 4 109 VSS DQS*<4> 83 4

112 VSS 112 VSS
115 VSS DQS<5> 93 5 115 VSS DQS<5> 93 5
118 VSS DQS*<5> 92 5 118 VSS DQS*<5> 92 5
121 VSS 121 VSS
124 VSS DQS<6> 105 6 124 VSS DQS<6> 105 6
86
127 VSS DQS*<6> 104 6 127 VSS DQS*<6> 104 6
130 VSS 130 VSS
82
133 VSS DQS<7> 114 7 133 VSS DQS<7> 114 7
136 113 136 113
86
VSS DQS*<7> 7 VSS DQS*<7> 7
81
139 VSS 139 VSS
6
6
82
142 VSS DQS<8> 46 TP_SB_DQS_8 142 VSS DQS<8> 46 TP_SB_DQS0_8
80
145 VSS DQS*<8> 45 TP_SB_DQSB_8 145 VSS DQS*<8> 45 TP_SB_DQSB0_8
M_DQM_B<7..0>
M_DQM_B<7..0>
81
148 VSS 148 VSS
27
151 VSS DM0/DQS9 125 0 151 VSS DM0/DQS9 125 0
80
25
154 VSS NC/DQS9* 126 154 VSS NC/DQS9* 126

157 VSS 157 VSS
27
24

163 135 163 135
25
VSS NC/DQS10* VSS NC/DQS10*
27
27
19
166 VSS 166 VSS
24
18
25
25
25
27
27
19
201 VSS 201 VSS
19
14
24
24
25
25
18
24
24
BI
BI
IN
IN
210 VSS 210 VSS
25 19
14
[PAGE_TITLE=240P
BI
BI
IN
IN
219 VSS 219 VSS
5
5
V_SM
228 VSS 228 VSS

V_SM
237 VSS 237 VSS
51 VDDQ DM7/DQS16 232 7 51 VDDQ DM7/DQS16 232 7
DIMM_VREF_B
56 VDDQ NC/DQS16* 233 56 VDDQ NC/DQS16* 233

62 VDDQ 62 VDDQ
27
DIMM_VREF_B
72 164 72 164
SMB_CLK_MEM
VDDQ DM8/DQS17 VDDQ DM8/DQS17
27
SMB_DATA_MEM
25
75 VDDQ NC/DQS17* 165 75 VDDQ NC/DQS17* 165

78 78
SMB_CLK_MEM
VDDQ VDDQ
25
24
CONN DDR2,
191 3 191 3
SMB_DATA_MEM
VDDQ DQ<0> 0 VDDQ DQ<0> 0
194 VDDQ DQ<1> 4 194 VDDQ DQ<1> 4
24
1 1
IN
181 VDDQ DQ<2> 9 2 181 VDDQ DQ<2> 9 2

175 VDDQ DQ<3> 10 3 175 VDDQ DQ<3> 10 3
IN
170 VDDQ DQ<4> 122 4 170 VDDQ DQ<4> 122 4
53 VDD DQ<5> 123 5 53 VDD DQ<5> 123 5
59 VDD DQ<6> 128 6 59 VDD DQ<6> 128 6
64 129 64 129
CH B]
VDD DQ<7> 7 VDD DQ<7> 7
197 VDD DQ<8> 12 8 197 VDD DQ<8> 12 8
69 VDD DQ<9> 13 9 69 VDD DQ<9> 13 9
4
4
172 VDD DQ<10> 21 10 172 VDD DQ<10> 21 10
187 VDD DQ<11> 22 11 187 VDD DQ<11> 22 11
184 VDD DQ<12> 131 12 184 VDD DQ<12> 131 12
V_3P3_MEM
M_DATA_B<63..0>
M_DATA_B<63..0>
178 VDD DQ<13> 132 13 178 VDD DQ<13> 132 13

189 VDD DQ<14> 140 14 189 VDD DQ<14> 140 14
V_3P3_MEM
67 VDD DQ<15> 141 15 67 VDD DQ<15> 141 15
TP_CH_B2_RC0_RFU
TP_CH_B1_RC0_RFU
TP_CH_B2_RC1_RCU
TP_CH_B1_RC1_RCU
DQ<16> 24 16 DQ<16> 24 16
BI
BI
18 RC1 DQ<17> 25 17 18 RC1 DQ<17> 25 17

55 RC0 DQ<18> 30 18 55 RC0 DQ<18> 30 18
238 VDDSPD DQ<19> 31 19 238 VDDSPD DQ<19> 31 19
12
12
1 VREF DQ<20> 143 20 1 VREF DQ<20> 143 20

120 SCL DQ<21> 144 21 120 SCL DQ<21> 144 21
25
25
119 SDA DQ<22> 149 22 119 SDA DQ<22> 149 22

101 SA2 DQ<23> 150 23 101 SA2 DQ<23> 150 23
240 SA1 DQ<24> 33 24 240 SA1 DQ<24> 33 24
239 SA0 DQ<25> 34 25 239 SA0 DQ<25> 34 25
DQ<26> 39 26 DQ<26> 39 26
1 190 BA1 DQ<27> 40 27 1 190 BA1 DQ<27> 40 27
0 71 BA0 DQ<28> 152 28 0 71 BA0 DQ<28> 152 28
DQ<29> 153 29 DQ<29> 153 29
3
3
3 171 CKE1 DQ<30> 158 30 1 171 CKE1 DQ<30> 158 30
2 52 CKE0 DQ<31> 159 31 0 52 CKE0 DQ<31> 159 31
Sun Mar 18 18:43:25
DQ<32> 80 32 DQ<32> 80 32
3 76 S1* DQ<33> 81 33 1 76 S1* DQ<33> 81 33
2 193 S0* DQ<34> 86 34 0 193 S0* DQ<34> 86 34
DQ<35> 87 35 DQ<35> 87 35
2007
BPAGE DRAWING
221 CK2*/RFU DQ<36> 199 36 221 CK2*/RFU DQ<36> 199 36

220 CK2/RFU DQ<37> 200 37 220 CK2/RFU DQ<37> 200 37
138 CK1*/RFU DQ<38> 205 38 138 CK1*/RFU DQ<38> 205 38
137 CK1/RFU DQ<39> 206 137 CK1/RFU DQ<39> 206
39 39
186 CK0* DQ<40> 89 40 186 CK0* DQ<40> 89 40
185 CK0 DQ<41> 90 41 185 CK0 DQ<41> 90 41
DQ<42> 95 42 DQ<42> 95 42
0 188 A0 DQ<43> 96 43 0 188 A0 DQ<43> 96 43
1 183 A1 DQ<44> 208 44 1 183 A1 DQ<44> 208 44
2 63 A2 DQ<45> 209 45 2 63 A2 DQ<45> 209 45
3 182 A3 DQ<46> 214 46 3 182 A3 DQ<46> 214 46
4 61 A4 DQ<47> 215 47 4 61 A4 DQ<47> 215 47

5 60 A5 DQ<48> 98 48 5 60 A5 DQ<48> 98 48
6 180 99 6 180 99
CUSTOM TEXT
A6 DQ<49> 49 A6 DQ<49> 49
2
7 58 A7 DQ<50> 107 50 7 58 A7 DQ<50> 107 50

8 179 A8 DQ<51> 108 51 8 179 A8 DQ<51> 108 51
9 177 A9 DQ<52> 217 52 9 177 A9 DQ<52> 217 52
INTEL
BPAGE
10 70 A10/AP DQ<53> 218 53 10 70 A10/AP DQ<53> 218 53

11 57 A11 DQ<54> 226 54 11 57 A11 DQ<54> 226 54
12 176 A12 DQ<55> 227 12 176 A12 DQ<55> 227
CONFIDENTIAL
55 55
13 196 A13 DQ<56> 110 56 13 196 A13 DQ<56> 110 56
14 174 A14 DQ<57> 111 57 14 174 A14 DQ<57> 111 57
173 A15 DQ<58> 116 58 173 A15 DQ<58> 116 58
2 54 A16/BA2 DQ<59> 117 59 2 54 A16/BA2 DQ<59> 117 59
MODULE
DQ<60> 229 60 DQ<60> 229 60

74 CAS* DQ<61> 230 61 74 CAS* DQ<61> 230 61
192 RAS* DQ<62> 235 62 192 RAS* DQ<62> 235 62
M_SBS_B<2..0>
TP_M_MAA_B15
NAME
73 WE* DQ<63> 236 73 WE* DQ<63> 236

TP_M_MAA0_B15
63 63
M_SCKE_B<3..0>
M_SCS_B_N<3..0>
M_SBS_B<2..0>
xxxxxx
DDRII_240P DDRII_240P
M_SCKE_B<3..0>
M_SBS_B<2..0>
M_SBS_B<2..0>
J4MY J3MY
M_CAS_B_N
M_MAA_B<14..0>
CK_M_DDR5_B_DP
CK_M_DDR4_B_DP
CK_M_DDR3_B_DP
CK_M_DDR2_B_DP
CK_M_DDR1_B_DP
CK_M_DDR0_B_DP
CK_M_DDR5_B_DN
CK_M_DDR4_B_DN
CK_M_DDR3_B_DN
CK_M_DDR2_B_DN
CK_M_DDR1_B_DN
CK_M_DDR0_B_DN
M_MAA_B<14..0>
M_SCS_B_N<3..0>
M_CAS_B_N
M_RAS_B_N
M_RAS_B_N
M_WE_B_N
M_WE_B_N
REV
0 X A6
0 X A4
DOCUMENT_NUMBER
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
1
BI
BI
BI
BI
BI
BI
BI
BI
BI
1
BI
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
ADDRESS:
ADDRESS:
12
12
12
12
12
12
12
12
12
25
12
PAGE
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
26
26
26
26
26
26
011
010
26
26
26
26
26
26
26
26
26
MODULE REV DETAILS
DATE
26
3.01
REV
A
C
D
B
8 7 6 5 4 3 2 1
V_SM_VTT 81 27 26 IN
V_SM_VTT MODULE REV DETAILS
81 27 26 IN MODULE NAME REV DATE
14 R2MY
R1MY 33 5%
2
1
14 CH 402
33 5%
2
1
CH 402 13 1
R32MY 2
33 5%
D 13 1
R11MY 2
CH 402
33 5% D
CH 402 12 1
R63MY 2
33 5%
12 1
R47MY 2
CH 402
33 5%
CH 402 11 1
R64MY 2
33 5%
11 1
R54MY 2
CH 402
33
CH
5%
402 R41MY
V_SM_VTT
10 1 2 81 27 26 IN
33 5%
10 1
R17MY 2
CH 402
33 5%
CH 402 9 1
R66MY 2 M_SCS_B_N<3..0>
25 12 IN
33 5%
9 1
R48MY 2
CH 402
V_SM_VTT 3 R31MY
33 5% 1 2
CH 402 81 27 26 IN 8 R57MY
1 2 43 5%
CH 402
33 5%
8 1
R22MY 2
CH 402
33 5%
CH 402 M_SCS_A_N<3..0> 7 1
R65MY 2 2 1
R30MY 2
24 11 IN
C R45MY
33
CH
5%
402
43
CH
5%
402 C
7 1 2
33 5%
CH 402 6 1
R58MY 2
3 R12MY 1 R35MY
1 2 33 5% 1 2
6 R23MY CH 402 43
1 2 43 5% 5%
CH 402 CH 402
33 5%
CH 402 5 1
R56MY 2
33 5%
5 1
R49MY 2 2 1
R8MY 2
CH 402 0 1
R29MY 2
33 5% 43 5% 43 5%
CH 402 CH 402 4 1
R37MY 2
CH 402
33 5%
4 1
R24MY 2
CH 402 M_SCKE_B<3..0>
25 12 IN
1 R13MY
33 5% 1 2
CH 402 3 R38MY
43 5% 1 2
CH 402 3 R60MY
33 5% 1 2
3 R15MY CH 402
1 2 43 5%
CH 402
33 5%
CH 402 0 1
R20MY 2 2 1
R39MY 2
43 5% 33 5%
2 1
R18MY 2
CH 402 CH 402 2 1
R59MY 2
33 5% 43 5%
B CH 402 1 1
R40MY 2
CH 402 B
24 11 IN M_SCKE_A<3..0>
33 5%
1 1
R25MY 2
CH 402
3 R52MY 1 R55MY
33 5% 1 2 1 2
CH 402 0 R42MY
43 5% 1 2 43 5%
CH 402 CH 402
M_MAA_B<14..0> 33 5%
0 1
R5MY 2
CH 402
25 12 IN
M_MAA_A<14..0> 33 5%
CH 402 2 1
R50MY 2 0 1
R61MY 2
24 11 IN
43 5% M_RAS_B_N R27MY 43 5%
CH 402 25 12 IN 1 2 CH 402
33 5% 25 12 IN M_ODT_B<3..0>
M_RAS_A_N 1
R7MY 2
CH 402
24 11 IN
33 5% 1 R51MY 3 R4MY
CH 402 1 2 1 2
43 5% 43 5%
CH 402 CH 402
M_CAS_B_N 1
R28MY 2
25 12 IN
33 5%
M_CAS_A_N R21MY CH 402
24 11 IN 1 2
0 1
R53MY 2 2 1
R3MY 2
33 5%
CH 402 43 5% 43 5%
CH 402 CH 402
24 11 IN M_ODT_A<3..0> R26MY
25 12 IN M_WE_B_N 1 2
33 5%
M_WE_A_N 1
R19MY 2 3 1
R14MY 2
CH 402 1 1
R34MY 2
24 11 IN
A 33 5% 43 5% M_SBS_B<2..0> 1
R43MY
2 43 5% A
25 12 IN
CH 402 CH 402 0 CH 402
33 5%
M_SBS_A<2..0> R36MY
24 11 IN 0
1 2 402 CH
2 1
R9MY 2 0 1
R33MY 2
33 5%
402 CH 43 5% R44MY 43 5%
CH 402 1
1 2 CH 402
33 5%
R6MY
1 2 402 CH
1
1 1
R16MY 2
33 5% 43 5%
402 CH CH 402 R62MY
2
1 2
33 5%
R46MY R10MY
2
1 2 0 1 2
402 CH
[PAGE_TITLE=DDR VTT TERMINATION]
43 5%
33
402
5%
CH
CH 402 BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
INTEL
xxxxxx 26 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

DECOUPLING CAPACITORS FOR DDR TERMINATION RESISTORS MODULE NAME REV DATE
86 82
81 27 26 IN V_SM_VTT 27 25
V_SM
18 14 IN
24 19
1 1 1 1 1 1 1 1 81 80
C40MY C25MY C6MY C41MY C26MY C20MY C21MY C29MY
D 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C14MY C15MY C16MY
20% 20% 20% 20% 20% 20% 20% 20% D
16V 16V 16V 16V 16V 16V 16V 16V 1 2 1 2 1 2
2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V
402 402 402 402 402 402 402 402 1.0UF 20% 1.0UF 20% 1.0UF 20%
10V 10V 10V
Y5V Y5V Y5V
603 603 603
C39MY C17MY C13MY
1 2 1 2 1 2
DESIGN NOTE:
1.0UF 20% 1.0UF 20% 1.0UF 20%
CH A V_SM_VTT DECOUPLING CAPS 10V 10V 10V
Y5V Y5V Y5V
603 603 603
C34MY C35MY C3MY
1 2 1 2 1 2
1.0UF 20% 1.0UF 20% 1.0UF 20%
10V 10V 10V
Y5V Y5V Y5V
603 603 603
C18MY C47MY C4MY
81 27 26 IN V_SM_VTT 1 2 1 2 1 2
1 1 1 1 1 1 1 1 1.0UF 20% 1.0UF 20% 1.0UF 20%
C51MY C24MY C30MY C22MY C9MY C10MY C12MY C8MY 10V 10V 10V
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF Y5V Y5V Y5V
20% 20% 20% 20% 20% 20% 20% 20% 603 603 603
C 2 16V
2 16V
2 16V
2 16V
2 16V
2 16V
2 16V
2 16V C
Y5V Y5V Y5V Y5V Y5V Y5V Y5V Y5V C38MY C46MY C36MY
402 402 402 402 402 402 402 402
1 2 1 2 1 2
1.0UF 20% 1.0UF 20% 1.0UF 20%
10V 10V 10V
Y5V Y5V Y5V
DESIGN NOTE: 603 603 603
C37MY
CH B V_SM_VTT DECOUPLING CAPS 1 2
1.0UF 20%
10V
Y5V
603
DESIGN NOTE:
CH A ADDRESS/CONTROL STITCHING CAPS (V_SM_VTT - V_SM)
92 88 58
V_3P3_EPW 1 R71MY 2
81 27 26 IN V_SM_VTT 38
57
34
56
33
40
28
39
IN
0 5%
VCC3 402 EMPTY
1
C42MY
1
C43MY
1
C23MY
1
C32MY
1
C19MY
1
C11MY V_3P3_MEM OUT 24 25
B 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF R72MY 2 B
20% 20% 20% 20% 20% 20% 1
16V 16V 16V 16V 16V 16V C61MY C62MY
2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 0.1UF 0.1UF
402 402 402 402 402 402 0 5% 20% 20% DESIGN NOTE:
V_SM 402 CH 16V 16V
82 81 80 27 25 24 19 18 14 IN Y5V Y5V
86 CAD NOTE: 402 402 DEFAULT: STUFF R72MY
DESIGN NOTE: OVERLAP PAD
CH B ADDRESS/CONTROL STITCHING CAPS (V_SM_VTT - V_SM)
81 27 26 IN V_SM_VTT
1 1 1 1 1 1
C28MY C49MY C7MY C44MY C53MY C27MY
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 101 70 49 SMB_CLK_RESUME 1 R73MY 2 1 R75MY 2 SMB_CLK_MAIN
16V 16V 16V 16V 16V 16V 28 22 21 IN IN 28 70 97
2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 48 47 33
402 402 402 402 402 402 105 103 102 0 5% 0 5%
V_SM 402 EMPTY 402 CH
82 81 80 27 25 24 19 18 14 IN
86
SMB_DATA_RESUME 1 R74MY 2 1 R76MY 2 SMB_DATA_MAIN

105 103 102 101 70 49 48 47 33 28 22 21 IN IN 28 70 97
0 5% 0 5%
402 EMPTY 402 CH
A A
C63MY
86 82 81 80 27 25 24 19 18 14 IN V_SM 1 2 DESIGN NOTE:
DESIGN NOTE:
10.0UF 20% STUFF R73MY AND R74MY FOR ME SKU
6.3V
EMPTY UNSTUFF FOR NON-ME SKU
1206 STUFF FOR NON-ME SKU
UNSTUFF FOR ME SKU
SMB_CLK_MEM
OUT 24 25
SMB_DATA_MEM
OUT 24 25

INTEL
[PAGE_TITLE=DDR VTT DECOUPLING] frostburg_fabc.sch_1.27
Sun Mar 18 18:43:31 2007 CONFIDENTIAL xxxxxx 27 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
BW_ATX_CORE MODULE REV DETAILS
VCC3 BOM NOTE:
R105CK UNSTUFF R105CK FOR NON AMT R74CK
1 2 28 13 8 7 H_FSBSEL2 1 2 CK_FSBSEL2 28 CK505 ATX BLB 0.0.1 9/7/2006
IN OUT
0 1A R104CK VDD_CK_VDD_PCI 0 5%
603 EMPTY R71CK 402 EMPTY STRAP MODE STUFF UNSTUFF
1 2 1 28 13 8 7 IN
H_FSBSEL0 1 2 CK_FSBSEL0
OUT 28
R10CK 0 1A C10CK LT ENABLED R65CK R66CK
V_3P3_STBY\G 1 2 603 CH .1UF 0 5%
IN 10% 402 EMPTY LTE
LT DISABLED R66CK R65CK
0 1A 16V Q3CK
D 603 CH 2 X7R MBT3904DUAL 3 6 ITP ENABLED (SRC8 DISABLED) R26CK R24CK
603
ITP_EN
D
2 Q2CK R72CK 5 2 SRC8 ENABLED (ITP DISABLED) R24CK R26CK
BOM NOTE: 28 IN VDD_CLK 1 2
S EMPTY R18CK SRC5 ENABLED R4CK R5CK
EMPTY FOR NON AMT 1 2 VDD_CK_VDD_48 1K 5% SRC5_EN
402 CH VCC3 SCR5 DISABLED R5CK R4CK
0 5% 4 1 XSTR
402 CH 1 1
1 C13CK C9CK
SLP_M_CKL_R 4.7UF .1UF
G D 20% 10% R69CK
1 1 16V 16V 28 IN VDD_CLK 1 2
C113CK C112CK 3 2 Y5V 2 X7R 1 R26CK 1 R106CK 1 R4CK 1 R65CK
1.0UF 4.7UF
R100CK 202170-024 1206 603 1K 5%
20% 20% 402 CH GATE2_FSBSEL2 GATE2_FSBSEL0 10K 10K 10K 10K
10V 10V 1 2 CAD NOTE: 5% 5% 5% 5%
2 EMPTY 2 EMPTY
R103CK Q4CK 2 EMPTY 2 CH 2 CH 2 CH
VDD_CLK_R 0 1A VDD_CK_VDD_SRC
603 805 OVERLAP PADS 402 402 402 402 CAD NOTE:
603 EMPTY 1 2 MBT3904DUAL 3 6
BOM NOTE: R9CK 0 1A R73CK 5 DO NOT STUB OFF MORE THEN 250 MILS
603 CH 1 1 H_FSBSEL2 2
DUAL FOOTPRINT 1 2 C2CK C3CK 28 13 8 7 IN 1 2 GATE1_FSBSEL2
FOR C112CK AND C113CK .1UF .1UF
STUFF ONLY ONE OF THEM 0 1A 10% 10% 4.7K 5%
R97CK 603 EMPTY 16V 16V 402 CH R24CK R107CK R5CK 1 R66CK
1 2 X7R 2 X7R XSTR 1 1
0 603 603
4 1 10K 10K 10K 10K
5% DESIGN NOTE: 5% 5% 5% 5%
2 EMPTY COST SAVING
R101CK
R70CK 2 CH EMPTY 2 EMPTY 2 EMPTY
402 VDD_CK_VDD_CPU 28 13 8 7 H_FSBSEL0 1 2 GATE1_FSBSEL0 402 402 402 402
1 2 IN
C SLP_M 4.7K 5% R11CK C
88 0 1A 402 CH 2 1 CK_FSBSEL2 28
39 IN 603 CH 1 IN
86
1 C8CK C4CK 5% 1K
89 .1UF CH 402 R14CK
4.7UF 10%
88 58 20% 16V 2 1 CK_14M_PA OUT 69
40 39
V_3P3_EPW 16V 2 X7R U1CK
33 27 IN 2 Y5V 603 5% 22
38 34 1206 CK505_64PIN R15CK CH 402
57 56 2 1 CK_14M_ICH
92 OUT 28 33
R102CK 2 62 CK_REF_R
VDD_CLK
1 2
VDD_CK_VDD_REF VDD_PCI REF/FSC/TESTSEL 5% 22
28 OUT 9 VDD_48 CH 402 R19CK
0 1A 16 VDD_PLL3 PCIF5/ITP_EN 7 CK_PCI5_R 2 1 CK_P_33M_ICH 28 30
603 CH 1 OUT
C1CK 39 VDD_SRC PCI4/SRC5_EN 6 CK_PCI4_R 5% 10
.1UF 55 VDD_CPU PCI3 5 CK_PCI3_R R20CK CH 402
10%
16V 61 VDD_REF PCI2/LTE 4 CK_PCI2_R 2 1 CK_P_33M_1394 OUT 28 53
2 X7R PCI1/CR_B* 3 CK_PCI1_R
603 5% 10
PCI0/CR_A* 1 CK_PCI0_R CH 402
28 IN CK_PWRGD_R 56 CKPWRGD/PWRDWN*
USB/FSA 10 CK_USB_R
2 R21CK 1 CK_P_33M_TPM OUT 28 68
R12CK SMB_FSBSEL_CK505 57 FSB/TESTMODE
13 8 7 H_FSBSEL1 1 2 VSS_PCI 8 5% 22
IN EMPTY402
1K 5% SMB_DATA_CK505 63 SDA VSS_48 11 R25CK
R60CK 402 CH SMB_CLK_CK505 64 SCL VSS_REF 58 2 1 CK_P_33M_S2 OUT 28 49
97 70 27 BI SMB_DATA_MAIN 1 2 5% 22
B 0 5% 59 XTAL_OUT CH 402 R23CK B
402 CH 60 XTAL_IN 2 1 CK_P_33M_S1 OUT 28 48
103 102 101 R109CK IO_VOUT 48
33 27 22 21 SMB_DATA_RESUME 1 2 5% 22
70 49 48 47
BI R17CK CH 402
105 0 5% 1 of 2 2 1 CK_P_33M_S3 OUT 28 103
402 EMPTY R62CK
SMB_CLK_MAIN 1 2 1.01 IC BOM NOTE: 5% 22
97 70 27 BI CH 402
0 5% STUFF FOR ATX ONLY
402 CH
102 101 R110CK
SMB_CLK_RESUME 1 2 CK505_IO_VOUT_PIN48
R16CK
47 33 27 22 21 BI
70 49 48
0 5% 2 1 CK_P_33M_PA OUT 28 69
105 103
402 EMPTY 5% 22
CH 402
R22CK
Y1CK 2 1 CK_48M_USB_ICH 28 31
14.318MHZ OUT
1 2 5% 33
R13CK CH 402
XTAL 2 1 CK_FSBSEL0 28
SM IN
5% 1K
OSC_CK14M_XTALOUT CH 402
OSC_CK14M_XTALIN 28 VDD_CLK
IN 31 28 IN CK_48M_USB_ICH
2 2 1 R3CK 30 28 IN CK_P_33M_ICH
C12CK C11CK DESIGN NOTE: 15 CK_P_33M_TPM
68 28 IN
A 27PF 27PF 5% A
VDD-CLK_R_3
5% 5% 69 28 IN CK_P_33M_PA
50V 50V ENGINEERING 2 CH CK_P_33M_1394
805 53 28 IN
1 COG 1 COG 3 CK_P_33M_S3
103 28 IN
603 603 TESTING PURPOSE R2CK CK_P_33M_S1
2 1 CK505_IO_VOUT_R 1 Q1CK 48 28 IN
MMBT3904 49 28 IN CK_P_33M_S2
VDD_CLK R67CK 33 5% XSTR
28 IN VDD_CLK 1 2 VDD_CLK_IO 1
28 IN OUT 28 402 CH 2
1 R75CK 1 R77CK 29 C26CK
0 1A 100.0PF
47K 47K 603 EMPTY 5%
5% 5% 50V 1 1 1 1 1 1 1 1
2 CH 2 CH
2 COG C20CK C15CK C6CK C7CK C18CK C17CK C14CK C16CK
402 402 603 22PF 22PF 22PF 10PF 10PF 10PF 10PF 10PF
5% 5% 5% 5% 5% 5% 5% 5%
33 28 IN CK_14M_ICH 50V 50V 50V 50V 50V 50V 50V 50V
CK_48M_USB_ICH R98CK 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY
31 28 IN CK_PWRGD 1 2 CK_PWRGD_R VDD_CLK_IO 402 402 402
33 IN OUT 28 OUT 28 29 402 402 402 402 402
1 R76CK 1 R78CK 1K 5%
33K 33K 402 CH
5% 5% DESIGN NOTE:
2 CH 2 CH
402 402 BSEL BIASING RES INTEL
[PAGE_TITLE=CK505 PAGE 1 OF 2] frostburg_fabc.sch_1.28
ALWAYS STUFF
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
BW_ATX_CORE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

CK505 ATX BLB 0.0.1 9-7-2006
D
R90CK
D
CK_PE_SRC11_R_DN 2 1 CK_PE_100M_LAN_2_DN
5% 33
EMPTY 402 R91CK
CK_PE_SRC11_R_DP 2 1 CK_PE_100M_LAN_2_DP
5% 33
R92CK EMPTY 402
CK_PE_SRC10_R_DN 2 1 CK_1PORT_S2_DN OUT 101
5% 33
CH 402 R93CK CK_1PORT_S2_DP
CK_PE_SRC10_R_DP 2 1 101
OUT
5% 33
R94CK CH 402
CK_PE_SRC9_R_DN 2 1 CK_1PORT_S3_DN OUT 102
5% 33
CH 402 R95CK
CAD NOTE: CK505 VDD_*_IO BULK DCPL: PLACE AROUND CK505 CK_PE_SRC9_R_DP 2 1 CK_1PORT_S3_DP OUT 102
28 IN VDD_CLK_IO 5% 33
R31CK CH 402
1 1 1 1 CK_PE_SRC7_R_DN 2 1 CK_PE_100M_16PORT_DN OUT 21 22
C102CK C108CK C109CK C111CK
10UF 10UF 10UF 10UF 5% 33
20% 20% 20% 20% CH 402 R32CK
C 2 6.3V
2 6.3V
2 6.3V
2 6.3V U1CK CK_PE_SRC7_R_DP 2 1 CK_PE_100M_16PORT_DP 21 22 C
X5R X5R X5R X5R CK505_64PIN OUT
805 805 805 805 5% 33
R45CK CH 402
12 VDD_IO SRC11-/CR_G* 32 CK_PE_SRC6_R_DN 2 1 CK_PE_100M_MCH_DN OUT 10
DESIGN NOTE: 20 33
VDD_PLL3_IO SRC11+/CR_H* 5% 33
STUFF C104CK AND C110CK 26 VDD_SRC_IO CH 402 R46CK
FOR 64 PINS CLOCK ONLY CAD NOTE: CK505 VDD_*_IO DCPL: PLACE (1) PER PIN 45 VDD_SRC_IO SRC10- 35 CK_PE_SRC6_R_DP 2 1 CK_PE_100M_MCH_DP OUT 10
49 VDD_CPU_IO SRC10+ 34 5% 33
36 VDD_SRC_IO R49CK CH 402
1 1 1 1 1 1 1 64 PIN SRC9- 31 2 1 CK_CPU_STOP_N
C104CK C110CK C105CK C106CK C103CK C100CK C21CK CK_PE_SRC5_R_DN OUT 33
46 SRC8-/ITP- PART ONLY SRC9+ 30
.1UF .1UF .1UF .1UF .1UF .1UF .1UF 5% 1K
20% 20% 20% 20% 20% 20% 10% 47 SRC8+/ITP+ EMPTY 402 R43CK
50V 50V 50V 50V 50V 50V 16V 2 1 CK_PCI_STOP_N
2 X7R 2 X7R 2 X7R 2 X7R 2 X7R 2 X7R 2 X7R CK_PE_SRC5_R_DP
OUT 33
805 805 805 805 805 805 603 50 CPU1- 5% 1K
51 CPU1+ R53CK EMPTY 402 CK_PE_100M_PATA_DN
SRC7-/CR_E* 43 CK_PE_SRC4_R_DN 2 1
OUT 98
R27CK 53 44
CK_1PORT_S1_DN 1 2 CPU0- SRC7+/CR_F* 5% 33
47 OUT 54
CK_PE_SRC8_R_DN CPU0+ CH 402 R48CK CK_PE_100M_PATA_DP
5% 33 SRC6- 40 CK_PE_SRC4_R_DP 2 1 98
CH 402 OUT
R37CK 15 VSS_IO SRC6+ 41 5% 33
97 OUT CK_H_XDP_DN 1 2 19 VSS_PLL3 R52CK CH 402
33 5% 23 VSS_SRC CPU_STOP*/SRC5- 37 CK_PE_SRC3_R_DN 2 1 CK_PE_100M_ICH_DN OUT 31
R7CK 402 EMPTY 42 VSS_SRC PCI_STOP*/SRC5+ 38 5% 33
B CK_1PORT_S1_DP 1 2 52 VSS_CPU CH 402
B
47 OUT R50CK
5% 33 29 VSS_SRC SRC4- 28 CK_PE_SRC3_R_DP 2 1 CK_PE_100M_ICH_DP OUT 31
CK_PE_SRC8_R_DP
CH 402 SRC4+ 27 5% 33
R30CK CH
1 2 R51CK 402
97 OUT CK_H_XDP_DP SRC3-/CR_D* 25 CK_PE_SRC2_R_DN 2 1 CK_ICHSATA_DN OUT 32
33 5% SRC3+/CR_C* 24
402 EMPTY 5% 33
CH 402 R38CK
R35CK SRC2-/SATA- 22 CK_PE_SRC2_R_DP 2 1 CK_ICHSATA_DP
CK_H_MCH_DN 1 2 CK_H_MCH_R_DN OUT 32
10 OUT 21
SRC2+/SATA+ 5% 33
33 5% R42CK CH 402
402 CH 18
CK_PE_SRC1_R_DP
2 1 CK_XT_24M_1394
SRC1-/SE2 OUT 53
R36CK SRC1+/SE1 17 5% 33
10 OUT CK_H_MCH_DP 1 2 CK_H_MCH_R_DP CH 402
33 5% SRC0-/DOT96- 14
402 CH SRC0+/DOT96+ 13
R33CK 2 of 2 CK_PE_SRC1_R_DN
6 OUT CK_H_CPU_DN 1 2 CK_H_CPU_R_DN
R41CK
33 5% 1.01 IC 2 1 CK_XT_25M_PATA OUT 98
402 CH
5% 33
R34CK EMPTY 402
6 OUT CK_H_CPU_DP 1 2 CK_H_CPU_R_DP R108CK
33 5% 2 1 CK_XT_25M_LAN OUT 56
402 CH 5% 22
A EMPTY 402 A
R39CK CK_96M_DREF_DN
CK_96M_DOT_R_DN 2 1 13 17
OUT
5% 33
CH 402 R40CK CK_96M_DREF_DP
CK_96M_DOT_R_DP 2 1 13 17
OUT
5% 33
DESIGN NOTE: CH 402
96M DOT CLOCK SIGNALS: STUFF 33 OHM RES STRAPS FOR MCH GRAPHIC SKU'S
EMPTY 33 OHM SITES FOR MCH NON-GRAPHIC SKU'S
[PAGE_TITLE=CK505 PAGE 2 OF 2]
INTEL
xxxxxx 29 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

ICH9 0.2.1 08/30/06
U1LB
D ICH9 P_AD<31..0> 48 49 53 103 106
BI
D
106 103 4853 49 BI P_PAR E3 PAR AD0 C10 0
106 103 53 4850 49 BI P_DEVSEL_N C6 DEVSEL# AD1 C8 1
28 IN CK_P_33M_ICH B3 PCICLK AD2 E9 2
106 103 53 49 48 OUT P_PCIRST_N R2 PCIRST# AD3 C9 3
106 103 53 50 49 48 OUT P_IRDY_N J8 IRDY# AD4 A5 4
103 53 49 48 BI P_PME_N R3 PME# AD5 E12 5
103 53 50 49 48 BI P_SERR_N K5 SERR# AD6 E10 6
106 103 53 50 49 48 BI P_STOP_N F10 STOP# AD7 B7 7
103 50 49 48 BI P_PLOCK_N H8 PLOCK# AD8 B6 8
106 103 53 50 49 48
103 53 50 49 48
BI
BI
P_TRDY_N
P_PERR_N
E6
F5
TRDY#
PERR# PCI AD9
AD10
B4
E7
9
10
106 103 53 50 49 48 BI P_FRAME_N G12 FRAME# AD11 A4 11
AD12 H12 12
AD13 F8 13
AD14 C5 14
106 103 53 49 48 36 OUT P_GNT_N<3..0>
0 H5 GNT0# AD15 D2 15
1 A7 GNT1#/GPIO51 AD16 E5 16
2 C7 GNT2#/GPIO53 AD17 G7 17
3 F7 GNT3#/GPIO55 AD18 E11 18
AD19 G10 19
AD20 G6 20
AD21 D3 21
C 106 103 53 50 49 48 IN P_REQ_N<3..0> C
0 K7 REQ0# AD22 H6 22
1 G13 REQ1#/GPIO50 AD23 G5 23
2 F13 REQ2#/GPIO52 AD24 C1 24
3 G8 REQ3#/GPIO54 AD25 C2 25
AD26 C3 26
AD27 D1 27
AD28 J7 28
103 50 IN P_INTA_N J5 PIRQA# AD29 F3 29
103 50 IN P_INTB_N E1 PIRQB# AD30 G1 30
106 103 50 IN P_INTC_N F1 PIRQC# AD31 H3 31
103 53 50 IN P_INTD_N A3 PIRQD#
P_INTE_N K6 PIRQE#/GPIO2
103 50 49 48 IN
P_INTF_N L7
P_C/BE_N<3..0>
50 49 48 IN PIRQF#/GPIO3 BI 48 49 53 103 106
50 49 48 IN P_INTG_N F2 PIRQG#/GPIO4 C/BE0# F11 0
103 50 49 48 IN P_INTH_N G2 PIRQH#/GPIO5 C/BE1# G9 1
C/BE2# C4 2
C/BE3# E8 3
1OF6
REV=1.00 IC
B B
J1LB
ICH6_HSK
1 NC_1 NC_2 2
4 NC_4 NC_3 3
IC C46655-001
NOTE:
NO PHYSICAL PINS
A ON ALLEGRO MODEL A
J3LB J2LB
1 1
NC NC
HDR HDR
A13494-008 A13494-008
[PAGE_TITLE= ICH9 1 0F 6 CONTROL]

INTEL
xxxxxx 30 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

CAD NOTE: MODULE NAME REV DATE
PLACE ALL NEAR ICH U1LB

ICH9
ICH9 0.2.1 08/30/06
10 IN DMI_MT_IR_0_DN W28 DMI0RXN USBP0N AD6 USB_FRONT1_DN BI 42

HSO1_DP 1
C54LB
2 TP_HSO1_DP 10 IN DMI_MT_IR_0_DP W26 DMI0RXP USBP0P AD5 USB_FRONT1_DP BI 42
31 IN 10 OUT DMI_IT_MR_0_DN V30 DMI0TXN USBP1N AE3 USB_FRONT2_DN BI 42
D DMI_IT_MR_0_DP V29 DMI0TXP USBP1P AE2 USB_FRONT2_DP
.1UF 10% 10 OUT BI 42
10V DMI_MT_IR_1_DN AA26 DMI1RXN USBP2N AD1 USB_FRONT5_DN D
X5R 10 IN BI 44
402 10 IN DMI_MT_IR_1_DP AA28 DMI1RXP USBP2P AD2 USB_FRONT5_DP BI 44
10 OUT DMI_IT_MR_1_DN Y30 DMI1TXN USBP3N AB6 USB_FRONT6_DN BI 44
DMI
HSO1_DN 1
C51LB
2 TP_HSO1_DN 10 OUT DMI_IT_MR_1_DP Y29 DMI1TXP USBP3P AB5 USB_FRONT6_DP BI 44
31 IN 10 IN DMI_MT_IR_2_DN AC26 DMI2RXN USBP4N AC3 USB_FRONT4_DN BI 43
.1UF 10% 10 IN DMI_MT_IR_2_DP AC28 DMI2RXP USBP4P AC2 USB_FRONT4_DP BI 43
10V
X5R 10 OUT DMI_IT_MR_2_DN AB30 DMI2TXN USBP5N AB1 USB_FRONT3_DN BI 43
402 10 OUT DMI_IT_MR_2_DP AB29 DMI2TXP USBP5P AB2 USB_FRONT3_DP BI 43
10 IN DMI_MT_IR_3_DN AF26 DMI3RXN USBP6N Y6 USB_BACK6_DN BI 46
DMI_MT_IR_3_DP AE26 DMI3RXP USBP6P Y5 USB_BACK6_DP
USB
10 IN BI 46
10 OUT DMI_IT_MR_3_DN AD29 DMI3TXN USBP7N AA3 USB_BACK5_DN BI 46
C55LB 10 OUT DMI_IT_MR_3_DP AD30 DMI3TXP USBP7P AA2 USB_BACK5_DP BI 46
31 IN HSO2_DP 1 2 HSO2_C_DP OUT 98 USBP8N Y1 USB_BACK4_DN BI 45
USBP8P Y2 USB_BACK4_DP BI 45
.1UF 10% V6 USB_BACK2_DN
10V USBP9N BI 45
X5R 56 IN HSI6_C_DN D29 PERN6/GLAN_RXN USBP9P V5 USB_BACK2_DP BI 45
402 56 HSI6_C_DP D30 PERP6/GLAN_RXP USBP10N W2 USB_BACK3_DN 46
IN BI
C53LB 31 OUT HSO6_DN E26 PETN6/GLAN_TXN USBP10P W3 USB_BACK3_DP BI 46
31 IN HSO2_DN 1 2 HSO2_C_DN OUT 98 31 OUT HSO6_DP E28 PETP6/GLAN_TXP USBP11N V1 USB_BACK1_DN BI 46
TP_HSI1_DN P30 PERn1 USBP11P V2 USB_BACK1_DP BI 46
.1UF 10% TP_HSI1_DP P29
10V PERp1
X5R 31 OUT HSO1_DN R26 PETn1 OC0#/GPIO59 P5 USB_OC0_R_N IN 31
C 402 31 HSO1_DP R28 PETp1 OC1#/GPIO40 N3 USB_OC1_R_N 31 C
OUT IN
98 IN HSI2_DN M30 PERn2 OC2#/GPIO41 P7 USB_OC2_R_N IN 31
98 IN HSI2_DP M29 PERp2 OC3#/GPIO42 R7 USB_OC3_R_N IN 31
C49LB 31 OUT HSO2_DN N26 PETn2 OC4#/GPIO43 N2 USB_OC4_R_N IN 31
HSO3_DP HSO3_C_DP
PCI-E
1 2 HSO2_DP N28 PETp2 OC5#/GPIO29 N1 USB_OC5_R_N
31 IN OUT 102 31 OUT IN 31
102 IN HSI3_DN K30 PERn3 OC6#/GPIO30 N5 USB_OC6_R_N IN 31
.1UF 10% HSI3_DP K29 M1 USB_OC7_R_N
10V 102 IN PERp3 OC7#/GPIO31 IN 31
X5R 31 OUT HSO3_DN L26 PETn3 OC8#/GPIO44 P3 USB_OC8_R_N IN 31
402 31 HSO3_DP L28 PETp3 OC9#/GPIO45 R6 USB_OC9_R_N 31
OUT IN
HSI4_DN H30 PERn4 OC10#/GPIO46 T7 USB_OC10_R_N
HSO3_DN 1
C48LB
2 HSO3_C_DN
47 IN
HSI4_DP H29 P1 USB_OC11_R_N
IN 31
31 IN OUT 102 47 IN PERp4 OC11#/GPIO47 IN 31
31 OUT HSO4_DN J26 PETn4
.1UF 10% HSO4_DP J28 AG1 USBRBIAS_ICH
10V 31 OUT PETp4 USBRBIAS# IN 37
X5R 101 IN HSI5_DN F30 PERn5 USBRBIAS AG2
402 101 HSI5_DP F29 PERp5
IN
31 OUT HSO5_DN G26 PETn5 CLK48 AG3 CK_48M_USB_ICH IN 28
31 OUT HSO5_DP G28 PETp5
C46LB
31 IN HSO4_DP 1 2 HSO4_C_DP OUT 47 R9LB AF28
V_1P5_FILTER 1 2 DMICOMP DMI_IRCOMP
38 34 32 IN AF30
.1UF 10% 402 CH DMI_ZCOMP
10V 24.9 1%
X5R CK_PE_100M_ICH_DN U26
402 29 IN DMI_CLKN
29 IN CK_PE_100M_ICH_DP U25 DMI_CLKP
B C47LB B
31 HSO4_DN 1 2 HSO4_C_DN 47
2OF6
IN OUT
.1UF 10% REV=1.00 IC
10V
X5R
402 I86 USB_OC0_R_N
52 IN USB_OC_FRONT1_N OUT 31
I85 USB_OC1_R_N
CAD NOTE: ATX: HSO5 ROUTE TO 2ND PCIEX1 OUT 31
C44LB I87 USB_OC2_R_N

31 IN HSO5_DP 1 2 HSO5_C_DP OUT 101 52 IN USB_OC_FRONT3_N OUT 31
.1UF 10% I84 USB_OC3_R_N
10V 31
X5R OUT
402
C45LB I89 USB_OC4_R_N
31 IN HSO5_DN 1 2 HSO5_C_DN OUT 101 52 IN USB_OC_FRONT2_N OUT 31
.1UF 10% I88 USB_OC5_R_N
10V 31
BOM NOTE: X5R OUT
402
STUFF C44LB AND C45LB FOR TEST TOOL
I90 USB_OC6_R_N
91 IN USB_OC_BACK1_N OUT 31
A A
I92 USB_OC7_R_N
C52LB OUT 31
31 IN HSO6_DP 1 2 HSO6_C_DP OUT 56
USB_OC_BACK0_N I99
.1UF 10% 91 IN USB_OC8_R_N OUT 31
10V
X5R
402
TO LAN I139
USB_OC9_R_N OUT 31
C50LB
31 HSO6_DN 1 2 HSO6_C_DN 56
I140
IN OUT 91 IN USB_OC_BACK2_N USB_OC10_R_N OUT 31
.1UF 10% I141
10V USB_OC11_R_N 31
X5R OUT
402
BPAGE DRAWING
[PAGE_TITLE=ICH9 2 OF 6 CONTROL] frostburg_fabc.sch_1.31
INTEL DOCUMENT_NUMBER
xxxxxx
PAGE
31
REV
3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
102 103 105
V_3P3_STBY\G IN 9 21 22 28 33 34 36 37 38 39 47 48 49 53
59 64 69 70 82 84 85 86 87 88 90 92 101
MODULE REV DETAILS
1 R301LB MODULE NAME REV DATE
10K ICH9 0.2.1 08/30/06
5%
2 EMPTY
402
R209LB
53 32 IN 1394_EN 1 2
D 2.2K 5%
402 CH
DESIGN NOTE:
D
STUFF FOR DMI TERMINATION STRAP (DEFAULT) R10LB U1LB

DO NOT EMPTY
38 34 31 V_1P5_FILTER 1 2 GLAN_BIAS ICH9
IN
24.9 1%
402 CH A29 GLAN_COMPO SATA0RXN AK17 SATAHDR_RX0_DN IN 41
B29 GLAN_COMPI SATA0RXP AJ17 SATAHDR_RX0_DP IN 41
13 BI CL_N_CLK G22 CL_CLK0 SATA0TXN AK19 SATAHDR_TX0_DN OUT 41
39 IN TP5_DEBUG C18 TP5 SATA0TXP AJ19 SATAHDR_TX0_DP OUT 41
13 BI CL_N_DATA H21 CL_DATA0 SATA1RXN AJ15 SATAHDR_RX1_DN IN 41
39 IN TP4_DEBUG E19 TP4 SATA1RXP AK15 SATAHDR_RX1_DP IN 41
39 IN CL_N_VREF_ICH C27 CL_VREF0 SATA1TXN AH16 SATAHDR_TX1_DN OUT 41
A16 TP6 SATA1TXP AF16 SATAHDR_TX1_DP
SATA
39 TP6_DEBUG 41
IN OUT
13 IN MCH_CLPWROK_R T6 CLPWROK SATA2RXN AJ13 SATAHDR_RX2_DN IN 41
TP7_DEBUG B16 TP7 SATA2RXP AK13 SATAHDR_RX2_DP IN 41 VCC3
1 C203LB 13 OUT CL_RST G20 CL_RST0# SATA2TXN AH14 SATAHDR_TX2_DN OUT 41
220PF SATA2TXP AF14 SATAHDR_TX2_DP 41
10% OUT
50V SATA3RXN AJ11 SATAHDR_RX3_DN IN 41
2 X7R SATA3RXP AK11 SATAHDR_RX3_DP 41
402 IN
105 77 OUT CPU_FAN_CTRL AJ21 PWM0 SATA3TXN AF12 SATAHDR_TX3_DN OUT 41
R248LB
105 77 OUT FNT_REAR_FAN_CTRL AJ22 PWM1 SATA3TXP AH12 SATAHDR_TX3_DP OUT 41 69 68 32 OUT SER_IRQ 1 2
104 77 OUT REAR_FAN_CTRL AK22 PWM2 10K 5%
C SATA4RXN AJ9 SATAHDR_RX4_DN CH 402 C
IN 41
77 IN CPU_FAN_TACH AH21 TACH0/GPIO17 SATA4RXP AK9 SATAHDR_RX4_DP IN 41
77 IN FRONT_FAN_TACH AK21 TACH1/GPIO1 SATA4TXN AF10 SATAHDR_TX4_DN OUT 41 1 R249LB 2
69 32 A20GATE
77 IN REAR_FAN_TACH AH22 TACH2/GPIO6 SATA4TXP AH9 SATAHDR_TX4_DP OUT 41 OUT
104 36 IN ICH_GP7_PU AK23 TACH3/GPIO7 10K 5%
402 CH
SATA5RXN AJ7 SATAHDR_RX5_DN IN 41
76 BI SST_CTL C19 SST SATA5RXP AK7 SATAHDR_RX5_DP IN 41 1 R250LB 2
69 32 KBRST_N
SATA5TXN AF8 SATAHDR_TX5_DN OUT 41 OUT
SATA5TXP AH7 SATAHDR_TX5_DP OUT 41
10K 5%
402 CH
1 SATA_CLKN AF18 CK_ICHSATA_DN IN 29
DESIGN NOTE: C128LB AJ24 AF19 CK_ICHSATA_DP
220PF 36 IN ICH_SGP22_PU SCLOCK/GPIO22 SATA_CLKP IN 29
10% 36 IN ICH_SGP38_PU AK24 SLOAD/GPIO38
DEFENSIVE PURPOSE 50V ICH_SGP39_PD AH23 SDATAOUT0/GPIO39 SATALED# AE7 ICH_SATA_LED_N
EMPTY 36 IN OUT 36 70
2 402 ICH_SGP48_PU AD20 SDATAOUT1/GPIO48 SATARBIAS# AK6
36 IN SATARBIAS_ICH
AJ25 AJ6 IN 37
53 32 OUT 1394_EN GPIO49 SATARBIAS
SATA0GP/GPIO21 AK25 SATA0GP
IN 36
SATA1GP/GPIO19 AE20 SATA1GP
IN 36
SATA2GP/GPIO36 AE21 SATA2GP
IN 36
SATA3GP/GPIO37 AE22 GP37_MFG_MODE_N
IN 36 37
SATA4GP AF22 SATA4GP
IN 36
SATA5GP AD21 SATA5GP
IN 36
B B
A20GATE P8 A20GATE
IN 32 69
HOST
A20M# AJ28 H_A20M_N
OUT 6
IGNNE# AC22 H_IGNNE_N

OUT 6
INIT3_3V# M3 TP_ICH_INIT_V_3P3
INIT# AE23 H_INIT_N
OUT 6
INTR AH27 H_INTR
OUT 6
FERR# AJ27 H_FERR_N
IN 6 8
NMI AF24 H_NMI
OUT 6
RCIN# L3 KBRST_N
IN 32 69
SERIRQ N6 SER_IRQ
OUT 32 68 69
SMI# AH26 ICH_H_SMI_N
OUT 6
STPCLK# AJ29 H_STPCLK_ICH_N
OUT 33
THRMTRIP# AD24 H_THERMTRIP_N
IN 6 8
PECI AC23 H_PECI_ICH
BI 105
3OF6
REV=1.00 IC
A A
[PAGE_TITLE=ICH9 3 OF 6 CONTROL] BPAGE DRAWING

INTEL DOCUMENT_NUMBER PAGE REV
xxxxxx 32 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

VCC3 VCC3
ICH9 0.2.1 08/30/06
86 87
CAD NOTE: 70 82
53 59
1 39 47
PLACE AT ICH 1 34 36 90
V_3P3_STBY\G 9 21 22
R270LB R15LB IN
D 10K 28 32 88
DESIGN NOTE: 10K 37 38
D
2
5%
EMPTY
48 49
2
5%
5%
5%
CH
DO NOT STUFF CIRCUIT. INTERNAL PULL-UP EXIST IN ICH9. EMPTY 64 69
R313LB
EMPTY
R281LB
402 84 85
2 402 U1LB 92 101
2 102 103
ICH9 105
10K
10K
402
402
L_DRQ1_N J3 LDRQ1#/GPIO23 GPIO0 N7 FP_AUD_DETECT
1
IN 36 64
0 K3 FWH0/LAD0
LPC
1 H1 FWH1/LAD1
2 M7 FWH2/LAD2 GPIO8 A20 TPEV_ICH_GPIO8
IN 36
69 68 L_AD<3..0>
IN 3 J1 FWH3/LAD3 WOL_EN/GPIO9 A18 WOL_ONLY
OUT 37 88
69 IN L_DRQ_N L6 LDRQ0# ALERT#/GPIO10 C17 ICH9_MGP1
OUT 33
69 68 OUT L_FRAME_N L5 FWH4/LFRAME# GPIO12 A8 LAN_DISABLE_N
OUT 56
GPIO13 A19 IO_PME_N
IN 69
64 37 IN AUD_LINK_BCLK_R AH3 HDA_BIT_CLK GPIO14/CLGPIO2 A9 1_WATT_CTRL_2
OUT 36 89
64 37 OUT AUD_LINK_RST_R_N AJ1 HDA_RST# GPIO15 C15 CK_PCI_STOP_N
OUT 29
AUDIO
64 IN AUD_LINK_SDI0 AK3 HDA_SDIN0 GPIO16 M2 BOARDID<0>
IN 37
64 AUD_LINK_SDI1 AH4 HDA_SDIN1 GPIO18 K1 BOARDID<1> 37
IN IN
60 IN AUD_LINK_SDI2 AH1 HDA_SDIN2 GPIO20 AF5 TP_ICH_GP20
TP_AUD_LINK_SDI3 AJ3 HDA_SDIN3 GPIO24/CLGPIO0 A14 GPIO_VSM_AMT_LED
OUT 36 80
64 37 36 OUT AUD_LINK_SDO_R AJ2 HDA_SDOUT GPIO25 B18 CK_CPU_STOP_N
OUT 29
64 37 36 OUT AUD_LINK_SYNC_R AK1 HDA_SYNC S4_STATE#/GPIO26 C11 S4_STATE_N
OUT 70
28 IN CK_14M_ICH M5 CLK14 QRT_STATE0/GPIO27 A11 ICH_QRT0
OUT 51
C QRT_STATE1/GPIO28 G18 ICH_QRT1 C
OUT 51
GPIO32 K2 CDC_DWN_DISABLE
OUT 59
GPIO33 AF6 GP33_SOP
IN 37
CAD NOTE: AH5
GPIO34 ICH_CONFIG_JUMPER
IN 37
PLACE 15 OHM SERIES STRAPS CLOSE TO ICH SATACLKREQ#/GPIO35 L1 2X12_POWER_DETECT
IN 90
R158LB F25 F16
SPI_MOSI 1 2 SPI_MOSI_PRI_SEC_FLSH 56 IN ICH_LAN_JCLK GLAN_CLK GPIO56 ICH_GP56
OUT 36 37
33 IN OUT 40 E14 C12 TP_SATA_HOT_SWAP_POWER_CTRL
56 OUT ICH_LAN_JRST LAN_RSTSYNC GPIO57/CLGPIO5
15 1% LAN_PWROK C21 LAN_RST# CPUPWRGD AD23 H_PWRGD
402 CH 39 IN OUT 6 8
56 IN ICH_LAN_JRX0 G15 LAN_RXD0 LAN100_SLP E21 ICH_LAN100SLP_EN
IN 37
LAN
R159LB H14 AK26
SPI_CLK 1 2 SPI_CLK_PRI_SEC_FLSH 56 IN ICH_LAN_JRX1 LAN_RXD1 THRM# ICH_THRM_N
IN 37
33 IN OUT 40 E13 C22
56 IN ICH_LAN_JRX2 LAN_RXD2 VRMPWRGD ICH_VRMPWRGD
IN 39
15 1% 56 ICH_LAN_JTX0 F15 LAN_TXD0 MCH_SYNC# AH25 ICH_SYNC_R_N 33
402 CH OUT IN
ICH_LAN_JTX1 F14 LAN_TXD1 PWRBTN# T3 SW_ON_N
MISC
56 OUT IN 51
R201LB G14 G19
SPI_CS0_N 1 2 SPI_CS0_ISOLATE_N 56 OUT ICH_LAN_JTX2 LAN_TXD2 RI# ICH_RI_PU
IN 36
33 IN OUT 40 R1
SUS_STAT#/LPCPD LPCPD_N
OUT 68 69
47 5% ICH_RTCX1 A21 RTCX1 SUSCLK R5 SUSCLK
37 IN OUT 69
RTC
402 CH
37 OUT ICH_RTCX2 B21 RTCX2 SYS_RESET# F19 FP_RST_N
IN 7 36 R217LB
37 IN ICH_RTCRST_PULLUP A25 RTCRST# PLTRST# C14 PLTRST_N_R 51 70 97 1 2 PLTRST_N
OUT 13 68 69
37 IN ICH_SRTCRSTB_PULLUP H20 SRTCRST# WAKE# E20 WAKE_N
IN 0 5% 1 98
51 36 IN ICH_PORT80_LED C16 SMBALERT#/GPIO11 INTRUDER# G21 ICH_INTRUDER_HDR_N IN 37 402 CH C202LB
105 103 102 101 70 49 48 47 28 27 22 21 SMB_CLK_RESUME H16 SMBCLK PWROK C25 PWRGD_3V 13 53 70
100PF
BI IN 5%
SMB
105 103 102 101 70 49 48 47 28 27 22 21 BI SMB_DATA_RESUME E16 SMBDATA RSMRST# F22 ICH_RSMRST_N IN 39 70 50V
B SMLALERT_ICH F18 LINKALERT#/GPIO60/CLGPIO4 INTVRMEN E23 ICH_INTVRMEN 2 EMPTY B
36 IN IN 37
A15 N8 SPKR 402
36 IN SMLINK0_ICH SMLINK0 SPKR OUT 33 37 60
36 IN SMLINK1_ICH B15 SMLINK1
SLP_S3# A13 SLP_S3_ICH_N
OUT 33 39
33 OUT SPI_MOSI C26 SPI_MOSI SLP_S4# B13 SLP_S4_N
OUT 80
40 IN SPI_MISO B26 SPI_MISO SLP_S5# G17 TP_SLP_S5_N
SPI
33 OUT SPI_CS0_N E25 SPI_CS0# SLP_M# F17 ICH_SLP_M_N
OUT 39
BOM NOTE: G23 T8
33 OUT SPI_CLK SPI_CLK CK_PWRGD CK_PWRGD
OUT 28
STUFF TO ENABLE NO-REBOOT OPTION AT 36 OUT SPI_CS1_N F23 SPI_CS1#/GPIO58/CLGPIO6 TP0 C13 ICH_BATLOW_PU
IN 36
POWER-UP (CONFIGURATION STRAPPING).
TP1 AK28 TP_DPRSTP
VCC3 TP2 AE24 TP_DPSLP_N
TP3 F20 TP_DFXTEST_N
4OF6
1
R17LB REV=1.00 IC
1K
5% VCC R11LB
EMPTY 39 33 IN SLP_S3_ICH_N 1 2 SLP_S3_N
OUT 70
402 0 5%
2 402 CH VCC3
3 R283LB
ICH9_MGP1 1 2 H_SKTOCC_N
SPKR 1 R18LB 2 CORE_SPKR_R 1 Q1LB 33 OUT IN 6
60 37 33 IN MMBT3904 LS1LB 0 5% 70
1 R222LB
A 1K 5% XSTR XDCR DESIGN NOTE:
402 EMPTY 1K A
402 CH 2 2
R309LB 1 SPKR_OUT 5%
1 C1LB SPKR_OUT_R 1 + STUFF R283LB FOR ME ON CPU PRESENT DETECTION 2 EMPTY
30 5% R12LB 402
1000PF 1 AT-08
10% 402 CH 2 IN 58 57 56 R280LB SPI_MOSI 13 IN ICH_SYNC_N 1 2 ICH_SYNC_R_N
OUT 33
2
50V"X7R" R16LB V_3P3_EPW 2 1

1X2HDR
34 28 27 IN OUT 33 0 5%
2 EMPTY 47 J8LB 40 39 38 10K 5% 402 CH
603 5% 92 88
402 EMPTY
EMPTY EMPTY DESIGN NOTE:
402 R14LB
1
2 H_STPCLK_ICH_N 1 2 H_STPCLK_N
STUFF TO ENABLE ITPM 32 IN OUT 6
0 1A
603 CH
[PAGE_TITLE=ICH9 4 OF 6 - CONTROL]
INTEL
xxxxxx 33 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
A
C
D
B
38
70
101
34
39
82
105
37
37
105
69
92
33
38
76
36
36
103
64
90
103
28 22 21
38
32
37
49 48 47
84 82 70
92 90
69 64 59
88 87 86
34
59
88
9
21
102
36
53
85
102
85
34 33
98
98
98
33
98
98
CR-34
105
58 57 56 40 39
18
IN
101
38
92
92
:
92
92
8
8
38
103
17
82
82
82
82
34
38 34
14
38
38
92 90
102
38
38
32
9
38
38
38
38
32 28 22 21
34
64 59 53 49 48 47 39 38
34
88 87 86 85 84 82 70 69
34
34
53 49 48 47 39
87 86 85 84 82
8
101
38
31
32 31
38
38
38
34
38 33 28 27
17 16 14 13
105 98 86 83
92 88
9
92 82 38 34 9
9
9
34
34
37
37
90 38 37
38
34
84
7
9
9
32 28 22 21 9
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
V_3P3_STBY\G
1
0
402
U1LB
GLCI_PLL
V_REF5V
V_AZSUS
V_1P5_ICH
V_1P5_ICH
V_1P5_ICH
V_1P5_ICH
ICH9
V_AZCORE
V_3P3_EPW
V_1P5_ICH
V_FSB_VTT
R310LB
V_1P25_CORE
CH
V_1P5_FILTER
V_1P5_FILTER
5%
V_3P3_STBY\G
V_1P5_CL_INT
V_REF5V_SUS
2
V_3P3_EPW_R
V_1P05EP_INT
A6
V_3P3_STBY\G
V5REF
7
VCCDMI_PLL_ICH
7
V_1P05_VCCAUX
V_1P5_STBY_INT
VCCSATA_PLL_ICH
V_3P0_BAT_VREG
AF1
V_1P05_ICH_CORE
V5REF_Sus
C204LB
.1UF
603
16V
H10
10%
EMPTY
Vcc1_5_A
H11 Vcc1_5_A
V_AZSUS
2
AC11
Vcc1_5_A
AB23 Vcc1_5_A VccLAN1_05 A10
AC18 Vcc1_5_A VccLAN1_05 B10
AC20 Vcc1_5_A Vcc1_5_A AA7
A26 VccCL1_5 Vcc1_5_A AA8
AC9 VccSusHDA Vcc1_5_A AB7
OUT
AC10 VccHDA Vcc1_5_A AB8
AD10 Vcc3_3 Vcc1_5_A T1
34
AC19 Vcc3_3
AC21 Vcc3_3 Vcc1_5_A AC14
AF21 Vcc3_3 Vcc1_5_A AC15
AH24 Vcc3_3 Vcc1_5_A AC16
VCC3
AK5 VccUSBPLL
Vcc1_05 A24
VCC3
AK20 VccSATAPLL Vcc1_05 B24
6
6
Vcc1_05 C24
T30 VccDMIPLL Vcc1_05 E24
Vcc1_05 F24
A28 VccGLANPLL Vcc1_05 G24
VCC1_05 H23
AF2 VccSus3_3 Vcc1_05 H24
Vcc1_05 J23
C23 VccCL3_3 Vcc1_05 M12
B23 VccCL3_3 Vcc1_05 M13
Vcc1_05 M15
C30 VccGLAN1_5 Vcc1_05 M17
C29 M18
38
32
36
VccGLAN1_5 Vcc1_05
88
82
53
22
48
69
86
C28 VccGLAN1_5 Vcc1_05 M19
21
1
37
B30 N12
34
87
49
28
47
64
85
92
70
VccGLAN1_5 Vcc1_05
101
105
103
102
0
N19
402
Vcc1_05
9
33
39
59
84
90
AA23 Vcc1_5_B Vcc1_05 R12
AA24 Vcc1_5_B Vcc1_05 R19
IN
AA25 Vcc1_5_B Vcc1_05 U12
R311LB
AB24 U19
CH
5%
Vcc1_5_B Vcc1_05
2
AB25 Vcc1_5_B Vcc1_05 V12
5
5
AC25 Vcc1_5_B Vcc1_05 V19

AD25 Vcc1_5_B Vcc1_05 W12
AD26 Vcc1_5_B Vcc1_05 W13
C205LB
.1UF
603
16V
AD28 W15
10%
EMPTY
Vcc1_5_B Vcc1_05
AE28 Vcc1_5_B Vcc1_05 W17
2
AE29 Vcc1_5_B Vcc1_05 W18
V_AZCORE
AE30 W19
V_3P3_STBY\G
Vcc1_5_B Vcc1_05
J24 Vcc1_5_B
J25 Vcc1_5_B V_CPU_IO AH28
2
3
K23 Vcc1_5_B V_CPU_IO AJ30
K24 Vcc1_5_B
OUT
IN K25 Vcc1_5_B Vcc3_3 AH30
EN
VCC3
L24 Vcc1_5_B Vcc3_3 AK4
GND
34
L25 Vcc1_5_B VccGLAN3_3 A27
M23 Vcc1_5_B
M24 Vcc1_5_B Vcc3_3 A2
U1BC
M25 Vcc1_5_B Vcc3_3 B1

MIC5235
N24 Vcc1_5_B Vcc3_3 B9

ADJ
OUT
N25 Vcc1_5_B Vcc3_3 G11

P23 Vcc1_5_B Vcc3_3 G3
4
4
5
P24 Vcc1_5_B Vcc3_3 H7

EMPTY
P25 Vcc1_5_B Vcc3_3 J2

R24 Vcc1_5_B Vcc3_3 K8
R25 Vcc1_5_B Vcc3_3 L8
4 TP_U1BC_PIN4
T23 Vcc1_5_B
T24 Vcc1_5_B
T25 Vcc1_5_B
T26 Vcc1_5_B VccLAN3_3 A12
T28 Vcc1_5_B VccLAN3_3 B12
U24 Vcc1_5_B
2.2UF
6.3V
603
U28
C8BC
10%
EMPTY
Vcc1_5_B
U29 Vcc1_5_B VccSus3_3 U1
V_1P5_STBY
U30 Vcc1_5_B VccSus3_3 U2

V23 Vcc1_5_B VccSus3_3 U3
1
1
V24 Vcc1_5_B VccSus3_3 U5

0
0
V25 U6
603
603
Vcc1_5_B VccSus3_3
W24 Vcc1_5_B VccSus3_3 U7
W25 Vcc1_5_B VccSus3_3 U8
Y23 Vcc1_5_B VccSus3_3 V8
R24BC
R26BC
1A
1A
Y24 Vcc1_5_B VccSus3_3 W7

3
2
2
3
Y25 W8
EMPTY
EMPTY
Vcc1_5_B VccSus3_3
VccSus3_3 Y8
Sun Mar 18 18:43:40
VccSus3_3 A17
VccSus3_3 B20
2007
BPAGE DRAWING
AG29 VccDMI VccSus3_3 C20

V_1P5_CL_INT
AG30 VccDMI VccSus3_3 E17

V_1P5_STBY_INT
VccSus3_3 H15
AC13
Vcc1_5_A
AD11 Vcc1_5_A VccRTC A22
AD12 Vcc1_5_A VCCSUS1_05 AC7 TP_V_1P05_B_STBY
OUT
OUT
AD13 Vcc1_5_A VCCSUS1_05 H17 TP_V_1P05_A_STBY

AE11 Vcc1_5_A
38
34
38
34
AF11 Vcc1_5_A VccCL1_05 A23

AH10 Vcc1_5_A
AH11 Vcc1_5_A
AJ10 Vcc1_5_A VCCSUS1_5 H18

AK10 Vcc1_5_A VCCSUS1_5 AD8
AC17
CUSTOM TEXT
Vcc1_5_A
2
AD17 Vcc1_5_A
AE17 Vcc1_5_A
AF17 Vcc1_5_A
[PAGE_TITLE=ICH
INTEL
BPAGE
AH17 Vcc1_5_A
AH18 Vcc1_5_A
AJ18
CONFIDENTIAL
Vcc1_5_A
AK18 Vcc1_5_A
5OF6
ICH9
MODULE
REV=1.00 MATERIAL=IC
5 OF 6 -
NAME
xxxxxx
0.2.1
REV
DOCUMENT_NUMBER
1
1
CONTROL]
34
PAGE
MODULE REV DETAILS
DATE
08/30/06
3.01
REV
A
C
D
B
A
C
D
B
CR-35
:
8
8
U1LB
ICH9
H13 VSS_099 VSS_100 G30
H19 VSS_098 VSS_101 G29
H2 VSS_097 VSS_102 G25
H22 VSS_096 VSS_103 G16
H25 VSS_095 VSS_104 F9
H26 VSS_094 VSS_105 F6
H28 VSS_093 VSS_106 F28
H9 VSS_092 VSS_107 F26
J29 VSS_091 VSS_108 F21
J30 VSS_090 VSS_109 F12
J6 VSS_089 VSS_110 E30
K26 VSS_088 VSS_111 E29
K28 VSS_087 VSS_112 E22
L2 VSS_086 VSS_113 E2
7
7
L23 VSS_085 VSS_114 E18

L29 VSS_084 VSS_115 E15
L30 VSS_083 VSS_116 D28
M14 VSS_082 VSS_117 B8
M16 VSS_081 VSS_118 B5
M26 B28
VSS_080 VSS_119
M28 VSS_079 VSS_120 B25
M6 VSS_078 VSS_121 B22
M8 VSS_077 VSS_122 B2
N13 VSS_076 VSS_123 B19
N14 VSS_075 VSS_124 B17
N15 VSS_074 VSS_125 B14
N16 VSS_073 VSS_126 B11
N17 VSS_072 VSS_127 AK8
N18 VSS_071 VSS_128 AK30
N23 VSS_070 VSS_129 AK29
N29 VSS_069 VSS_130 AK2
N30 VSS_068 VSS_131 AK16
P12 VSS_067 VSS_132 AK14
P13 VSS_066 VSS_133 AK12
6
6
P14 VSS_065 VSS_134 AJ8

P15 VSS_064 VSS_135 AJ5
P16 VSS_063 VSS_136 AJ26
P17 VSS_062 VSS_137 AJ23
P18 VSS_061 VSS_138 AJ20
P19 VSS_060 VSS_139 AJ16
P2 VSS_059 VSS_140 AJ14
P26 VSS_058 VSS_141 AJ12
P28 VSS_057 VSS_142 AH8
P6 VSS_056 VSS_143 AH6
R13 VSS_055 VSS_144 AH20
R14 VSS_054 VSS_145 AH2
R15 VSS_053 VSS_146 AH19
R16 VSS_052 VSS_147 AH15
R17 VSS_051 VSS_148 AH13
R18 VSS_050 VSS_149 AG28
R23 VSS_049 VSS_150 AF9
R29 VSS_048 VSS_151 AF7
R30 VSS_047 VSS_152 AF29
R8 VSS_046 VSS_153 AF25
5
5
T12 VSS_045 VSS_154 AF23

T13 VSS_044 VSS_155 AF20
T14 VSS_043 VSS_156 AF15
T15 VSS_042 VSS_157 AF13
T16 VSS_041 VSS_158 AE9
T17 VSS_040 VSS_159 AE8
T18 VSS_039 VSS_160 AE6
T19 VSS_038 VSS_161 AE5
T2 VSS_037 VSS_162 AE25
T29 VSS_036 VSS_163 AE19
T5 VSS_035 VSS_164 AE18
U13 VSS_034 VSS_165 AE16
U14 VSS_033 VSS_166 AE15
U15 VSS_032 VSS_167 AE14
U16 VSS_031 VSS_168 AE13
U17 VSS_030 VSS_169 AE12
U18 VSS_029 VSS_170 AE10
U23 VSS_028 VSS_171 AE1
V13 VSS_027 VSS_172 AD9
V14 VSS_026 VSS_173 AD7
4
4
V15 VSS_025 VSS_174 AD3
V16 VSS_024 VSS_175 AD22
V17 VSS_023 VSS_176 AD19
V18 VSS_022 VSS_177 AD18
V26 VSS_021 VSS_178 AD16
V28 VSS_020 VSS_179 AD15
V3 VSS_019 VSS_180 AD14
V7 VSS_018 VSS_181 AC8
W1 VSS_017 VSS_182 AC6
W14 VSS_016 VSS_183 AC5
W16 VSS_015 VSS_184 AC30
W23 VSS_014 VSS_185 AC29
W29 VSS_013 VSS_186 AC24
W30 VSS_012 VSS_187 AC12
W5 VSS_011 VSS_188 AC1
W6 VSS_010 VSS_189 AB3
Y26 VSS_009 VSS_190 AB28
Y28 VSS_008 VSS_191 AB26
Y3 VSS_007 VSS_192 AA6
Y7 VSS_006 VSS_193 AA5
3
3
Vss AA30
Vss AA29
Sun Mar 18 18:43:41
Vss AA1
Vss A30
Vss A1
2007
BPAGE DRAWING
www.advancerepairlaptop.blogspot.com AK27
AH29
AJ4
AF3
B27
VSS_005
VSS_004
VSS_003
VSS_002
VSS_001
CUSTOM TEXT
2
2
INTEL
BPAGE
CONFIDENTIAL
[PAGE_TITLE=ICH
6OF6
REV=1.00
ICH9
IC
MODULE
NAME
xxxxxx
6 OF 6 -
0.2.1
REV
DOCUMENT_NUMBER
1
1
35
PAGE
MODULE REV DETAILS
DATE
08/30/06
GROUND BODY]
3.01
REV
A
C
D
B
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BOM NOTE:
DEFAULT EMPTY: STUFF 10K OHM RES (R54LB) FOR ICH PORT80 LED FEATURE (TDE EXPERIMENT)
ICH9 0.2.1 08/30/06
105 103 102 101 92 V_3P3_STBY\G
49 48 47 39 38 37 36 34 33 32 28 22 21 9 IN
90 88 87 86 85 84 82 70 69 64 59 53
D 1 1 1 1 1 1 1 1 1 1 1
D
R198LB R54LB R51LB R53LB R55LB R52LB R50LB R49LB R44LB R28LB R48LB
10K 10K 10K 10K 10K 10K 1K 10K 10K 220 10K
5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
CH CH CH CH CH CH CH CH CH CH CH
BOM NOTE:
BOOT SELECT STRAPS 2
402
2
402
2
402
2
402
2
402
2
402
2
402
2
402
2
402
2
402
2
402
STUFF FOR
PRODUCT TPEV_ICH_GPIO8 33
OUT
P_GNT_N<3..0> R34LB FP_RST_N
106 103 53 49 48 36 30 OUT 0 2 1 OUT 7 33 51 70
97
1K 5% ICH_GP56 33 37
OUT
402 CH 1_WATT_CTRL_2
OUT 33 89
WAKE_N 21 22 33 47
OUT 98 101 102
2
R32LB 1 ICH_BATLOW_PU
OUT 33
33 OUT SPI_CS1_N SMLALERT_ICH
OUT 33
1K 5%
402 EMPTY SMLINK0_ICH 33
OUT
SMLINK1_ICH 33
OUT
VCC3 ICH_PORT80_LED 33 51
OUT
C ICH_RI_PU
OUT 33 C
2 1 1 1 1 1 1 1 1 1 1 1 1
R46LB R47LB R35LB R36LB R37LB R38LB R39LB R210LB R40LB R41LB R45LB R42LB R43LB
10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
VCC3 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
CH CH CH CH CH CH CH CH CH EMPTY CH CH CH
402 402 402 402 402 402 402 402 402 402 402 402 402
1 2 2 2 2 2 2 2 2 2 2 2 2
ICH_GP7_PU 32 104
OUT
ICH_SGP22_PU 32
2 2 OUT
ICH_SGP38_PU 32
R29LB R33LB OUT
3.24K 3.24K ICH_SGP39_PD
1% 1% OUT 32
EMPTY EMPTY ICH_SGP48_PU 32
402 402
OUT
1 1
1 R19LB
10K
B 5% B
AUD_LINK_SDO_R 2 EMPTY
OUT 33 37 64 402
AUD_LINK_SYNC_R OUT 33 37 64
SATA4GP 32
OUT
2 R30LB 1 P_GNT_N<3..0> OUT 30 36 48 49 53 103 SATA5GP
OUT 32
2 106
5% 1K SATA0GP 32
OUT
EMPTY 402 R31LB SATA1GP
OUT 32
1 2 1 SATA2GP
OUT 32
5% 1K GP37_MFG_MODE_N
EMPTY 402 OUT 32 37
FP_AUD_DETECT 33 64
OUT
ICH_SATA_LED_N 32 70
OUT
V_3P3_STBY\G
IN
1
R229LB
10K DESIGN NOTE:
A 5% A
CH DEFAULT: CRYPTO ENGINE ENABLED
402
GPIO_VSM_AMT_LED 2 STUFF PU (R229LB) AND UN-STUFF PD (R230LB)
33 IN
80 1
R230LB
2.7K
5%
EMPTY
402
2

[PAGE_TITLE=GPIO TERMINATION & RST STRAPS] frostburg_fabc.sch_1.36
INTEL
xxxxxx 36 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

CAD NOTE: ICH9 0.2.1 08/30/06
VCC3
ONLY ROUTE BID<1..0>, NEED TO CLEAN UP SIO 88 33 IN WOL_ONLY AUD_LINK_SDO_R 1 R71LB 2 AUD_LINK_SDO
64 36 33 IN OUT 59
1 33 5% CAD NOTE:
R107LB 402 CH
1 R78LB 1 R67LB 100K SOFT AUDIO TERMINATION: PLACE CLOSE TO ICH
D 10K 10K 5% 64 36 33 AUD_LINK_SYNC_R 1 R72LB 2 AUD_LINK_SYNC 59
5% 5% IN OUT D
CH 33 5%
2 EMPTY 2 EMPTY 402 402 CH
402 402 2
33 AUD_LINK_BCLK 2 R70LB 1
OUT 59 IN AUD_LINK_BCLK_R
OUT 33 64
0 BOARDID<1..0> 33 5%
1 402 CH TERMINATION FOR SOFT AUDIO
AUD_LINK_RST_R_N 1 R192LB 2 AUD_LINK_RST_CDC
64 33 IN OUT 59
J115LB PROTECTED RTC JUMPER 33 5%
1X3HDR 402 CH
1 TP_CLR_RTC
2 ICH_SRTCRSTB_PULLUP 33 37 J5LB
3 NET_CLR_RTC_JUMPER
OUT DESIGN NOTE:
1X2HDR
1 R79LB 1 R66LB
1 INTRUDER HEADER (J5LB): NO SUITCASE JUMPER 1 2
10K 10K EMPTY REMOVE J5LB IF 2X12 BACKSIDE DMI LAI CONN (J10BC) IS STUFFED.
5% 5% R261LB
2 EMPTY 2 EMPTY 4.7K 1-2 NORMAL * R80LB HDR
402 402 5%
90 38 37 34 IN V_3P0_BAT_VREG 1 2 ICH_INTRUDER_HDR_N
OUT 33
EMPTY
402 2-3 CLR RTC 1M 5%
2 402 CH
BOARD ID STRAPS 1 MOHM INTRUDER PULL-UP (R80LB)
* = DEFAULT DESIGN NOTE:
20K RTC PULL-UP (R68LB)
R68LB
C 80 90 38 37 34 IN V_3P0_BAT_VREG 1 2 ICH_RTCRST_PULLUP OUT C
73
69 V_5P0_STBY\G
20K 1% C40LB
51 402 CH 1 2 0
IN
1
66 DESIGN NOTE: 402
70 R285LB
74 1 1UF 20% EMPTY
88 RTC: FLIP-LID XTAL HOLDER (XY1LB) 6.3V
R219LB 5%
2
89 R253LB X5R
90 Q10LB USES STANDARD XTAL (Y1LB) 90 38 37 34 V_3P0_BAT_VREG 1 2 603 ICH_SRTCRSTB_PULLUP 33
91
10
MMBT3904 IN OUT 37
92
5% 3 EMPTY 20K 1% C139LB
CH Y1LB 402 CH 1 2
34 38 1
OUT 402 32.768KHZ
2
2
1UF 20%
V_REF5V_SUS 6.3V
TH X5R
102 BOM NOTE: 603
90 R220LB XY1LB XTAL
86 V_REF5V_SUS_SIO 1 2 RTC XTAL: ADD (MOD-FILE INSERTION)
70 82 IN XTAL_TH_RM VCC3 R300LB
64 XTAL A91451-001 (32.768KHZ) USING
0 5% DESIGN NOTE: 1 2 ICH_GP56
49 48 47 402 EMPTY REV=1 REF-DES W/OUT X (Y1LB) IN 33
36 34 33 V_3P3_STBY\G 1 RM1 RM2 2 0 5% 36
22 21 9 IN VCC3 MFG MODE PADS: J4LB 1 R60LB 402 EMPTY
32 28 1 OF 1 4.7K
39 38
59 53 VCC ICH_RTCX1 5%
70 69 VCC3 RM OUT 33
2 CH
85 84 402
88 87
B 101 92 1 1 R225LB IM_LB_SOP_EN_CNT_Q
B
105 103 R77LB DESIGN NOTE: 4.7K J4LB
R221LB ICH XTAL 1 2 5% JUMPER R302LB
10 Q9LB 10M 5% RTC (10 MOHM RES): DO NOT CHANGE 2 EMPTY 3 1 1 2 GP33_SOP
OUT 33
5% MMBT3904 603 CH 402 Q12LB 37
3 XSTR R77LB TO 0402 PACK_TYPE
R226LB 0 5%
CH EMPTY 2 402 EMPTY
OUT 34 402 1
1 1 SOP_EN_CNT 1 2 IM_LB_SOP_EN_CNT 1
38 2 C42LB C41LB 1K 5% 2
2 18PF 18PF 402 EMPTY EMPTY
R303LB
V_REF5V 5% 5% 1 2 GP37_MFG_MODE_N
OUT 32
50V 50V 726841-001 36
2 COG 2 COG 0 5%
603 603 402 CH
R218LB
70 IN V_REF5V_SIO 1 2
ICH_RTCX2
0 5% OUT 33
402 EMPTY MBT3904DUAL 3 6 RECOVER/CONFIGURE HEADER MODE
IM_LB_CONFIG_CNT
R223LB 5 2 R224LB JUMPER ON 1-2 * NORMAL
USBRBIAS_ICH
1 2 1 2
OUT 31
2.2K 5% 2.2K 5% JUMPER ON 2-3 CONFIGURE
1 R63LB 2 402 EMPTY 402 EMPTY
V_3P0_BAT_VREG CAD NOTE: 402 IM_LB_SPKR_CNT 4 1 EMPTY JUMPER REMOVED RECOVERY
37 34 IN 22.6 1% CH
90 38 R82LB * DEFAULT JUMPER SETTING
2 1 ICH_INTVRMEN USBRBIAS (R63LB): TIE TRACES TOGETHER CLOSE TO PINS, Q11LB
OUT 33
WITH LENGTH NO LONGER THAN 200 MILS TO RESISTOR IM_LB_ICH_CONFIG_JUMPER R227LB CONFIGURE= SAFE MODE
390K 5%
GP33_SOP 1 J7LB 1 2
402 CH 37 33
SATARBIAS_ICH OUT 1X3HDR 4.7K 5%
R83LB OUT 32 1 ICH_CONFIG_JUMPER
A 2 1 ICH_LAN100SLP_EN 1 R81LB 2 R312LB 1 3 402 CH OUT 33 A
DESIGN NOTE: OUT 33
2.2K CR1LB 2 RECOVERY_CONFIGURE_PULLUP
390K 5%
24.9 1% 5% 2
3 1
402 CH CAD NOTE: 402 CH 1
INTVRMEN: ALWAYS STUFF TO ENABLE INTERNAL VRM CH 2 R74LB
LAN100SLP: ALWAYS STUFF TO ENABLE INTERNAL LAN VRM SATARRBIAS (R81LB): TIE TRACES TOGETHER CLOSE TO PINS, 402 BAT54C HDR 20K
EXTERNAL VRM IS NOT SUPPORTED WITH LENGTH NO LONGER THAN 200 MILS TO RESISTOR DIO R73LB 5%
SOT23_C 470
R228LB 5% CH
VCC3 402
VCC3 VCC3 IM_LB_SPKR 1 2 CH 2
ICH_THRM_XSTRGATE2
2.2K 5% 402
DESIGN NOTE: R59LB R214LB Q8LB SPKR 402 CH 2
1 2 1 2 60 33 IN
MBT3904DUAL 3 6
STUFF R212LB TO BYPASS
THERMAL EVENT REPORTING
10K 5% 10K 5% CONFIG / RECOVERY JUMPER
402 CH 402 CH 5 2
FEATURE (DEFAULT EMPTY)
R57LB ICH_THRM_XSTRGATE1
H_PROCHOT_N 1 2 R215LB
8 6
95
IN
10K 5% 1 2 4 1 XSTR [PAGE_TITLE=ICH PIN STRAPS]
402 CH 0 5%
ICH_THRM_N OUT 33 BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
DESIGN NOTE: 402 EMPTY frostburg_fabc.sch_1.37
INTEL
xxxxxx 37 3.01
0-OHM RESISTOR (R212LB) IS IN PLACE SHOULD THE ICH BE MODIFIED TO INCLUDE THRMB PIN ON THE VTT WELL (ON-DIE) Sun Mar 18 18:43:44 2007 CONFIDENTIAL
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

PCI PCI-E USB CLASSIC FILTER MODULE NAME REV DATE
VCC3 105 C17LB ICH9 0.2.1 08/30/06
C12LB 101 92 90 88 87 86 85 84 82
38 37 36 34 33 32 28 22 21 9 V_3P3_STBY\G 1 2
1 2 VCC3 70 69 64 59 53 49 48 47 39
IN
103 102 .022UF 10% 32 31 IN V_1P5_FILTER
.1UF 20% C16LB 50V 38 34 98 86 83 82
25V 1 2 C120LB X7R 1 17 16 14 13 IN V_1P25_CORE
Y5V 603 C112LB 76 34 21 18
D 1 2 105
603 4.7UF
.1UF 20% C18LB 10% D
C13LB 25V .022UF 10% 6.3V
Y5V 50V 1 2 2 X5R 1 1
1 2 603 X7R 603
C137LB C61LB
CAD NOTE: 22UF 0.1UF
603 .022UF 10% 20% 20%
CAD NOTE: 50V
.1UF 20% 6.3V 16V
25V X7R PLACE C112LB 2 X5R 2 Y5V
Y5V PLACE V3P3_STBY DCPL 603 NEAR NE CORNER 1206 402
603 CAPS AT ENDS OF POWER OF ICH
C14LB CORRIDOR (VCCP_USB)
1 2
ICH
VCC3
.1UF 20%
25V
L1LB SATA PLL FILTER PCI-E FILTER
Y5V C15LB 721891-026 10UH
603 1 2 V_1P5_ICH 1 2 VCCSATA_PLL_ICH 34 98 M4LB
IN OUT
C21LB 82 1 2
.1UF 20% IND 34 9 IN V_1P5_ICH V_1P5_FILTER
OUT 31 32 34 38
25V 1 2 38 MULTI
Y5V 1206 92 V_1P5_STBY_INT OUT 34
603 CH 805
10UF 10%
C20LB 6.30V X7R 1
1 C23LB C35LB
1 2 C22LB 220UF DESIGN NOTE: .1UF
10%
PCI EXPRESS DECOUPLING FILTER CAD NOTE: 1 2 20%
16V
.1UF 20% 6.3V DEFAULT M4LB: 0 OHM RES A93552-002 2 X7R
25V 1.0UF 20% 2 ALUM
OPTIONAL WITH 0.5UH FB 656554-026 603
38 34 32 31 IN V_1P5_FILTER Y5V PLACE VCCSATA DCPL 10V RDL
C 603 Y5V C
CAPS AT ENDS OF POWER
CORRIDOR 603
C24LB BOM NOTE: 4.7UF (C34LB) STUFF FOR SIGNAL QUALITY
1 2
CAD NOTE: 22UF 20%

DMI PLL FILTER USB HS (HI-SPEED) FILTER
6.3V M2LB C39LB
X5R 1 2 C19LB
V_1P5-FILTER CAPS: PLACE NEAR 1206
82 38 34 9 IN V_1P5_ICH 1 2 VCCA_PWR_GPLL_PN1_ICH 1 R27LB 2 VCCDMI_PLL_ICH
OUT 34
90 37 34 IN V_3P0_BAT_VREG 98
ENDS OF POWER CORRIDOR C25LB 98 92 MULTI 38 34 9 IN V_1P5_ICH 1 2
0 5% .1UF 20% 92 82
2 1 IND SM 402 CH 25V .1UF 10%
603 Y5V
DESIGN NOTE: C28LB 16V
2.2UF 10% C27LB C38LB X7R
6.3V DEFAULT: 1UH INDUCTOR M2LB
1 2 1 2 1 2 603
X5R 37 34 V_REF5V
603 WITH IPN 201005-546
IN C9LB
1 2
.01UF 20% 10.0UF 20% .1UF 20%
C26LB 50V 6.3V 25V
1 2 X7R X5R Y5V .1UF 10%
603 805 603 16V
X7R
22UF 20% C37LB 603
6.3V 85 38
EMPTY C33LB 85 14 9 8 7 V_FSB_VTT 1 2
V_FSB_VTT IN
1206 82 38 34 9 IN V_1P5_ICH 1 2 14 9
38 34
8 7
17
IN 34 17
85 84 82
98 92
2 1UF 20% 1 2
.1UF 20%
25V 59
38
53
37
49
36
USB VCCUABG
VCC3 Y5V V_3P3_STBY\G
B SATA BG C8LB
1.0UF
20%
6.3V
X5R
603
C29LB
4.7UF
20%
C30LB
.1UF
20%
603 28
34
22
33
21 9
32
IN
B
C11LB 10V 25V C36LB 48 47 39
1 2 10V
1 70 69 64 C32LB CAD NOTE:
1 2 Y5V Y5V Y5V V_REF5V_SUS 1 2 88 87 86
SATA RX/TX 603 805 603 37 34 IN 1 2
92 90
.1UF 20% .1UF 20% 102 101 PLACE DCPL CAP (C32LB)
25V CAD NOTE: 25V 105 103 .1UF 20%
25V AT PIN F3 OF ICH
Y5V Y5V
603 603 Y5V
PLACE 0.1UF DCPL CAPS (C36LB TO 603
M13LB
98 C39LB) WITHIN 40 MILS OF ICH.
1 2 1 R20LB 2 GLCI_PLL
LAN VCCPAUX C31LB
38
92
34
82
9 IN V_1P5_ICH
MULTI
V_1P5_ICH_R
OUT 34
39 38 0 5%
28 27 IN
V_3P3_EPW 1 2 IND SM 402 CH 1 1
34 33 C2LB C3LB V_1P05_VCCAUX V_1P5_CL_INT
10UF 2.2UF 34 IN
56 40 .1UF 20% DESIGN NOTE: 20% 10% OUT 34
58 57 25V 6.3V 6.3V
92 88 EMPTY DEFAULT: 1UH INDUCTOR M13LB WITH IPN 201005-546 X5R 2 2 X5R 1 2
603 805 603
C102LB C10LB
NON-LAN SKU: CHANGE M13LB TO 0OHM RES 0.1UF 1.0UF 1 2
NON-LAN SKU: EMPTY C2LB AND C3LB 20% 20% C4LB C5LB
16V 10V 1.0UF .1UF
2 Y5V 1 Y5V 20% 20%
402 603 10V 25V
2 EMPTY 1 Y5V
603 603
VCC3 DESIGN NOTE:

C126LB DEFAULT STUFFED; 0 OHM 0603 TRAP (R22LB) V_1P05EP_INT
OUT 34
A 1 2 OPTION: EMPTY (R22LB) FOR NON-INTEL LAN
A
.1UF 20% 1 2
25V R22LB 2 C6LB C7LB
Y5V 1 1.0UF .1UF
603 58 57 56 40 39 38 34 33 28 27 IN V_3P3_EPW V_3P3_EPW_R OUT 34 39 20% 20%
92 88 0 1A 10V 25V
C125LB DESIGN NOTE: 603 CH
2 EMPTY 1 Y5V
1 2 2 603 603
GENERAL PURPOSE DCPL CAPS
C111LB 1
.1UF 20% .1UF 1 C201LB
25V 20% 0.1UF
25V R21LB 20%
Y5V Y5V 1 16V
603 603 0 BOM NOTE: 2
1A Y5V
402
EMPTY
603 STUFF R21LB FOR
2 NON-INTEL LAN
[PAGE_TITLE=ICH DECOUPLING]
INTEL
xxxxxx 38 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

105 103 102 101 92 VCC3
49 48 47 39 38 37 36 34 33 32 28 22 21 9 IN V_3P3_STBY\G ICH9 0.2.1 08/30/06
90 88 87 86 85 84 82 70 69 64 59 53
DESIGN NOTE: VCC3 1
VRMPWRGD SEQUENCE CIRCUIT
R92LB 2
1K
5% R93LB
D 105 103 102 101 92 90 88 1 EMPTY 1K
47 39 38 37 36 34 33 32 28 22 21 9 IN V_3P3_STBY\G 402 5%
87 86 85 84 82 70 69 64 59 53 49 48 R91LB 2 CH
D
1 R216LB 10K 402
10K 5% 1
5%
EMPTY ICH_VRMPWRGD
2 CH 402
402 OUT 33 R282LB
R200LB 2
1 2 VCC3_3P3STBY_PIN2
2 39 33 IN SLP_S3_ICH_N
8 7 IN VR_READY 2 101 92 90 88 87 86 85 84 82
2
1
93 0 5% Q2LB C58LB R94LB 38 37 36 34 33 32 28 22 21 9 IN V_3P3_STBY\G 402 EMPTY
402 CH MBT3904DUAL 3 6 1.0UF 70 69 64 59 53 49 48 47 39 22 5%
20% 100K 105 103 102 1
10V 5%
R199LB 2 R90LB 1 5 2 EMPTY 1 CH R99LB
39 33 IN SLP_S3_ICH_N 1 2 SLP_S3_VR_READY 603 402 3.3K
DESIGN NOTE: 5%
0 5% 10K 5% XSTR 1 DEBUG CL FEATURE MCH_CLPWROK_XSTR_GATES
402 EMPTY 402 CH 2 FORCE MEPWR BEFORE PS_ON IS VALID EMPTY
SLP_S3_VR_READY_PIN5 4 1 C59LB 402
.1UF 2 MCH_CLPWROK_DUAL2
20%
25V
EMPTY 1
603 Q3LB
MBT3904DUAL 3 6
R100LB 1 5 2
86 13 IN MCH_CLPWROK 2
1K 5% MCH_CLPWROK_PIN5
C 105 103 102 101 92
402 EMPTY
EMPTY C
49 48 47 39 38 37 36 34 33 32 28 22 21 9 IN V_3P3_STBY\G 4 1
90 88 87 86 85 84 82 70 69 64 59 53
BOM NOTE:
1
EMPTY FOR NON-AMT
R97LB
150
DESIGN NOTE: 5%
EMPTY
CL DEBUG FEATURE, MAY NOT NEED FOR PRODUCT 402 CL VREF
2
R194LB R110LB
SLP_S3_ICH_N 1 2 88 58 57 56 40 38 34 33 28 27 IN V_3P3_EPW 1 2
39 33 IN 92 3.24K 1%
0 5% 402 CH
402 EMPTY SLP_M OUT 28 86 88 89
R111LB CL_N_VREF_ICH
1 2 OUT 32
453 1% C56LB
402 CH 2 1
3
2 R98LB 1 ICH_SLP_M_N_PIN5 Q4LB 20% 0.1UF
33 IN ICH_SLP_M_N 1 16V Y5V
MMBT3904
10K 5% EMPTY 402
402 EMPTY 2 2
B C127LB B
1.0UF
20%
10V
1 EMPTY
603
R87LB
32 IN TP5_DEBUG 1 2
1K 5%
402 EMPTY
BOM NOTE: R88LB
STUFF R203LB & 32 TP4_DEBUG 1 2 DESIGN NOTE:
IN
EMPTY R103LB FOR NON AMT 1K 5%
402 EMPTY
70 33 ICH_RSMRST_N 2 R203LB 1 DEBUG PURPOSE.
IN
0 5%
402 CH
R103LB LAN_PWROK
38 34 IN V_3P3_EPW_R 1 2 OUT 33
15K 1% R108LB
402 EMPTY
1 1 2
1 R105LB C119LB 1K 1%
0 1.0UF 402 EMPTY
A 5% 20% A
2 EMPTY 2 10V 105 103 102 101 92 90 88 87 R109LB TP6_DEBUG
402
EMPTY
603 47 39 38 37 36 34 33 32 28 22 21 9 IN V_3P3_STBY\G 1 2 OUT 32
86 85 84 82 70 69 64 59 53 49 48 3.24K 1% C57LB
BOM NOTE: 402 EMPTY 2 1
STUFF FOR 20% 0.1UF
NON INTEL 16V
LAN EMPTY
402
[PAGE_TITLE=ME & CONTROL BUFFERS/ICH CIRCUITS]

INTEL
xxxxxx 39 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

ICH9 0.2.1 08/30/06
D PRIMARY SERIAL FLASH D
CAD NOTE:
CAD NOTE:
PLACE CLOSE 58 57 56 40 39 38 34 33 28 27 IN V_3P3_EPW OVERLAY SPI PARTS WITH EACH OTHER
TO SPI 1 92 88
C C
R169LB
33 OUT SPI_MISO 1 2 SPI_MISO_FLSH
IN 40
15 1%
402 CH
OUT 40 U3LB
SPI_MOSI_PRI_SEC_FLSH R164LB SPI_FLASH
1 2 OUT 40
33 IN VCC
0 5% SPI_MOSI_FLSH SI
402 CH
SPI_CLK_FLSH SCK
R165LB
33 IN SPI_CLK_PRI_SEC_FLSH 1 2 SPI_WP0_N
CS* SO
40 IN WP*
0 5% SPI_HOLD0_N DESIGN NOTE:
402 CH 40 IN HOLD*
40 33 SPI_CS0_ISOLATE_N VSS SCHEMATICS SPI SOCKET (SOIC8) IPN :D62233-001

IN USE MOD FILE INSERT 8MB WINBOND IPN: D85790-001
IC
USE MOD FILE INSERT 8MB SPI IPN: C96495-006
USE MOD FILE IF 16MB SPI IPN: D23556-001
DESIGN NOTE:
OVERLAPPING PARTS: ONLY STUFF ONE(XU3LB) OR (U2LB)

B B
CAD NOTE:
OVERLAY SPI (XU3LB) & (U2LB) WITH EACH OTHER
58 57 56 40 39 38 34 33 28 27 V_3P3_EPW
92 88
IN
U2LB
AT26DF321
SO 8 SPI_MISO_FLSH
OUT 40
2 VCC
NC 3
V_3P3_EPW 40 IN SPI_MOSI_FLSH 15 SI NC 4
57 56 40 39 38 34 33 28 27 IN 16 5
92 88 58 40 IN SPI_CLK_FLSH SCK NC
40 33 IN SPI_CS0_ISOLATE_N 7 CS* NC 6
40 IN SPI_WP0_N 9 WP* NC 14
40 IN SPI_HOLD0_N 1 NC NC 13
NC 12
10 GND OPTION NC 11
R170LB 1 R163LB 1 V_3P3_EPW
2
1K 1K REV=1 EMPTY
5% 5% IN 27 28 33 34 38 39 40 56 57 58
88 92
A CH 2 CH 2 A
402 402 SPI_WP0_N 40
OUT
R171LB 1 1 1
1K SPI_HOLD0_N 40
OUT C79LB C78LB
5% 1.0UF .1UF
EMPTY 2 20% 20%
402 10V 25V
BOM NOTE:
2 Y5V 2 Y5V
603 603
DEFAULT EMPTY (R171LB)
DESIGN FEATURE
FOR DISABLING EXTERNAL
FLASH PROTECTION
[MODULE=ICH] BPAGE DRAWING DOCUMENT_NUMBER PAGE REV

INTEL
[PAGE_TITLE=SERIAL FLASH PRIMARY] Sun Mar 18 18:43:49 2007 CONFIDENTIAL xxxxxx 40 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BOM NOTE:
DEFAULT 0.01UF, 0402, A36096-008, 10%, 25V, X7R
OPTIONAL 0 OHM, 0402, A36093-001
DESIGN NOTE:
BIOS & SILK SCREEN DENAOTE AS PORT0
D
C202BU DESIGN NOTE: D
SATAHDR_TX0_R_DP 1 2 SATAHDR_TX0_DP IN 32
.01UF 10%
J2BU 25V
1X7HDR X7R 402 SATAHDR_TX4_R_DP C217BU
2 1 SATAHDR_TX4_DP
SATA IN 32
C203BU
TXP 2 SATAHDR_TX0_R_DN 1 2 SATAHDR_TX0_DN IN 32
J6BU .01UF 10%
1 GND 25V
3 .01UF 10% 1X7HDR X7R 402
TXN 25V 402 SATA SATAHDR_TX4_R_DN SATAHDR_TX4_DN
4 GND X7R C216BU
2 2 1
5 TXP IN 32
RXN C204BU 1
7 SATAHDR_RX0_R_DN 1 2 SATAHDR_RX0_DN GND
GND OUT 32 3 .01UF 10%
6 TXN 25V 402
RXP 4 X7R
.01UF 10% GND
25V 402 RXN 5
HDR X7R 7
SATAHDR_RX4_R_DN C214BU
1 2 SATAHDR_RX4_DN
GND OUT 32
C92545-001 C205BU RXP 6
SATAHDR_RX0_R_DP 1 2 SATAHDR_RX0_DP OUT 32 .01UF 10%
25V 402
.01UF 10% HDR X7R
DESIGN NOTE: 25V 402
X7R C92545-001 SATAHDR_RX4_R_DP 1
C215BU
2 SATAHDR_RX4_DP
BIOS & SILK SCREEN DENAOTE AS PORT2 OUT 32
J3BU C206BU .01UF 10%
1X7HDR
SATAHDR_TX1_R_DP 1 2 SATAHDR_TX1_DP IN 32 25V 402
C SATA
.01UF 10%
X7R C
TXP 2 25V 402
X7R
1 GND
TXN 3 C207BU
4
SATAHDR_TX1_R_DN 1 2 SATAHDR_TX1_DN IN 32
GND
RXN 5 .01UF 10%
7 GND 25V 402
6 X7R
RXP
C208BU
SATAHDR_RX1_R_DN 1 2 SATAHDR_RX1_DN OUT 32
HDR
C92545-001 .01UF 10%
25V 402
X7R
C209BU DESIGN NOTE:
SATAHDR_RX1_R_DP 1 2 SATAHDR_RX1_DP OUT 32
.01UF 10%
25V 402
X7R
SATAHDR_TX5_R_DP C221BU SATAHDR_TX5_DP
J5BU 2 1
IN 32
1X7HDR
SATA .01UF 10%
25V 402
DESIGN NOTE: TXP 2 X7R
1 GND
BIOS & SILK SCREEN DENAOTE AS PORT4 3
SATAHDR_TX5_R_DN C220BU
2 1 SATAHDR_TX5_DN
B TXN IN 32 B
C210BU 4 GND
SATAHDR_TX2_R_DP 1 2 SATAHDR_TX2_DP IN 32 5 .01UF 10%
J4BU RXN 25V 402
1X7HDR .01UF 10% 7 GND X7R
SATA 25V RXP 6
EMPTY402
TXP 2
SATAHDR_TX2_R_DN
C211BU
1 2 SATAHDR_TX2_DN SATAHDR_RX5_R_DN C219BU
2 1 SATAHDR_RX5_DN
1 GND IN 32 HDR OUT 32
TXN 3 .01UF 10% C92545-001 .01UF 10%
4 GND 25V 25V 402
EMPTY402 X7R
RXN 5
7 GND SATAHDR_RX2_R_DN
C212BU
1 2 SATAHDR_RX2_DN SATAHDR_RX5_R_DP C218BU
2 1 SATAHDR_RX5_DP
6 OUT 32 OUT 32
RXP
.01UF 10% .01UF 10%
25V 25V 402
EMPTY EMPTY402 X7R
C92545-001 C213BU
SATAHDR_RX2_R_DP 1 2 SATAHDR_RX2_DP OUT 32
.01UF 10%
25V
EMPTY402
SATAHDR_TX3_R_DP C222BU
1 2 SATAHDR_TX3_DP IN 32
A J7BU .01UF 10% A
1X7HDR 25V
SATA EMPTY402
TXP 2
1 SATAHDR_TX3_R_DN
C223BU
1 2 SATAHDR_TX3_DN
GND IN 32
TXN 3
4 .01UF 10%
GND 25V
RXN 5 EMPTY402
7 GND
6
SATAHDR_RX3_R_DN C224BU
1 2 SATAHDR_RX3_DN
RXP OUT 32
.01UF 10%
EMPTY 25V
EMPTY402
C92545-001
SATAHDR_RX3_R_DP
C225BU
1 2 SATAHDR_RX3_DP
OUT 32
.01UF 10%
[PAGE_TITLE=SATA CONNECTORS]
25V
EMPTY402 BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
INTEL
xxxxxx 41 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

FRONT PANEL HEADER #1

CR3BU
TVS6V 6.0V
D
6 1 D
5VDUAL_USB
46 45 44 43 IN 5 2
92 91 88 52
4 3
EMPTY
CAD NOTE: CAD NOTE:
D16982-001
DO NOT CHANGE TO 402 DO NOT CHANGE TO 402
OVERLAPPING FOOTPRINTS OVERLAPPING FOOTPRINTS
1 R14BU 2 1 R16BU 2
0 1A 0 1A
603 CH 603 CH
752402-015 J8BU 752402-015

C L1BU 2X5HDR_9 L2BU C
USB_FRONT1_DN 4 1 1 2 1 4 USB_FRONT2_DN
31 BI BI 31
90OHM USB_FRONT1_R_DN 3 4 USB_FRONT2_R_DN 90OHM
ACM2012 EMPTY USB_FRONT1_R_DP 5 6 USB_FRONT2_R_DP EMPTY ACM2012
L1BU 7 8 L2BU
31 BI USB_FRONT1_DP 3 2 10 USB_OC_FRONT34 2 3 USB_FRONT2_DP BI 31
90OHM 90OHM
ACM2012 EMPTY HDR ACM2012 EMPTY
1 R15BU 2 1 R17BU 2
1
0 1A C226BU 0 1A
603 CH 470PF 603 CH
10%
50V
2 EMPTY
603
DESIGN NOTE:
1 R18BU 2 1 R19BU CAUTION: 0 OHM TO GND
0 1A
0
603 EMPTY
5% BOM NOTE:
B 2 EMPTY B
BOM NOTE: 402 STUFF FOR CUSTOM
FUSED (OPT-P10-GND)
STUFF FOR PRODUCT
FRONT PANEL SUPPORT
WITH FUSE ON
FRONT PANEL
USB_FP1_PWR 1 R20BU 2 USB_OC_FRONT1_R_N

52 IN OUT 52
0 1A
603 CH
BOM NOTE:
STUFF FOR PRODUCT

WITH FUSE ON BOARD
NOT ON FP
A A
[PAGE_TITLE=USB FP HDR 1]
INTEL
xxxxxx 42 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

D
D
CR4BU
TVS6V 6.0V
1 6
2 5 5VDUAL_USB IN 42 44 45 46 52 88 91 92
3 4
EMPTY
C D16982-001 C
CAD NOTE: CAD NOTE:
1 R21BU 2 1 R23BU 2
0 1A 0 1A
603 CH 603 CH
J9BU
L3BU 2X5HDR_9 L4BU
31 BI USB_FRONT4_DN 2 3 1 2 1 4 USB_FRONT3_DN BI 31
ACM2012 EMPTY USB_FRONT4_R_DP 5 6 USB_FRONT3_R_DP ACM2012 EMPTY
L3BU 7 8 L4BU
31 BI USB_FRONT4_DP 1 4 10 USB_OC_FRONT2_PIN10 2 3 USB_FRONT3_DP BI 31
90OHM 90OHM
B 1 R22BU 2 1 R24BU 2 B
1
0 1A C227BU 0 1A
603 CH 470PF 603 CH
10%
50V
2 EMPTY
603
DESIGN NOTE:
1 R26BU 2 CAUTION: 0 OHM TO GND

1 R25BU
0 BOM NOTE:
0 1A 5%
603 EMPTY
2 EMPTY
STUFF FOR CUSTOM
BOM NOTE: 402
FUSED (OPT-P10-GND)
STUFF FOR PRODUCT
FRONT PANEL SUPPORT
WITH FUSE ON
FRONT PANEL
R27BU
USB_FP2_PWR 1 2 USB_OC_FRONT2_R_N
52 IN OUT 52
0 1A
A 603 CH A
BOM NOTE:
STUFF FOR PRODUCT

WITH FUSE ON BOARD
NOT ON FP

[PAGE_TITLE=USB FP HDR 2] frostburg_fabc.sch_1.43
INTEL
xxxxxx 43 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

D
D
CR8BU
TVS6V 6.0V
1 6
2 5 5VDUAL_USB IN 42 43 45 46 52 88 91 92
3 4
EMPTY
C D16982-001 C
CAD NOTE: CAD NOTE:
1 R91BU 2 1 R88BU 2
0 1A 0 1A
603 CH 603 CH
J19BU
L11BU 2X5HDR_9 L12BU
31 BI USB_FRONT6_DN 2 3 1 2 1 4 USB_FRONT5_DN BI 31
ACM2012 EMPTY USB_FRONT6_R_DP 5 6 USB_FRONT5_R_DP ACM2012 EMPTY
L11BU 7 8 L12BU
31 BI USB_FRONT6_DP 1 4 10 USB_OC_FRONT3_PIN10 2 3 USB_FRONT5_DP BI 31
90OHM 90OHM
B 1 R90BU 2 1 R89BU 2 B
1
0 1A C303BU 0 1A
603 CH 470PF 603 CH
10%
50V
2 EMPTY
603
DESIGN NOTE:
1 R86BU 2 CAUTION: 0 OHM TO GND

1 R87BU
0 BOM NOTE:
0 1A 5%
603 EMPTY
2 EMPTY
STUFF FOR CUSTOM
BOM NOTE: 402
FUSED (OPT-P10-GND)
STUFF FOR PRODUCT
FRONT PANEL SUPPORT
WITH FUSE ON
FRONT PANEL
R85BU
USB_FP3_PWR 1 2 USB_OC_FRONT3_R_N
52 IN OUT 52
0 1A
A 603 CH A
BOM NOTE:
STUFF FOR PRODUCT

WITH FUSE ON BOARD
NOT ON FP

[PAGE_TITLE=USB FP HDR 2] frostburg_fabc.sch_1.44
INTEL
xxxxxx 44 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BACK PANEL USB
D
D
C C
CAD NOTE:
DO NOT CHANGE TO 402
OVERLAPPING FOOTPRINTS
R28BU
1 2
0 1A
603 CH
L5BU
USB_BACK4_DN 1 4 USB_BACK4_R_DN CAD NOTE:
31 BI BI 45
B 90OHM
B
ACM2012 EMPTY PLACE CAP AS CLOSE AS POSSIBLE
L5BU TO USB CONNECTOR
31 BI USB_BACK4_DP 2 3 USB_BACK4_R_DP BI 45
90OHM
ACM2012 EMPTY
91 45 IN VREG_USB_BP0_STACK
R29BU 1
1 2 CR5BU C230BU
0 1A
TVS6V 6.0V 470PF
10%
603 CH 50V
2 X7R
402
1 6
52 88
2 5 5VDUAL_USB IN 42 43
CAD NOTE: 44 46
91 92
DO NOT CHANGE TO 402 J21BU
OVERLAPPING FOOTPRINTS 3 4 2 X USB
R30BU 1 9
2 1
45 BI USB_BACK4_R_DN 2
1A 0 EMPTY USB_BACK4_R_DP 3
CH 45 BI
603
D16982-001 4 10
A A
91 45 IN VREG_USB_BP0_STACK 5 11
L6BU 45 BI USB_BACK2_R_DN 6
31 BI USB_BACK2_DN 2 3 USB_BACK2_R_DN BI 45 45 USB_BACK2_R_DP
BI 7
90OHM 8 12
ACM2012 EMPTY
L6BU
USB_BACK2_DP 1 4 USB_BACK2_R_DP CONN
31 BI BI 45
90OHM
ACM2012 EMPTY A91996-001
R31BU [PAGE_TITLE=BACK PANEL USB]

2 1
1A 0
CH 603
INTEL
xxxxxx 45 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

[PAGE_TITLE=BACK PANEL USB WITH ESATA]
DESIGN NOTE:
D CAD NOTE:
MJ/USB DUAL BOM NOTE:
D
DO NOT CHANGE TO 402
CONNECTOR STUFFING OPTIONS:
OVERLAPPING FOOTPRINTS
R32BU RJ45/2 USB - C73572-001 (DEFAULT)
1 2 DOUBLE STACK USB - 749193-001, NOT 642575-124
0 1A
603 CH
DOUBLE-STACK CONNECTOR FOR USB/LAN IS ON OTHER PAGE
WITH THE REST OF THE CONNECTOR
L7BU
31 BI USB_BACK1_DN 1 4 USB_BACK1_R_DN BI 46 57
90OHM CAD NOTE:
J11BU
ACM2012 EMPTY 2 X USB
91 57 46 IN VREG_USB_BP_MJ
L7BU OVERLAP WITH MAGJACK FOOTPRINT 1 9
31 BI USB_BACK1_DP 2 3 USB_BACK1_R_DP BI 46 57 USB_BACK1_R_DN 2
90OHM 57 46 BI
CR6BU 57 46 USB_BACK1_R_DP 3
ACM2012 EMPTY TVS6V 6.0V BI
BOM NOTE: 4 10
R33BU EMPTY, EXCEPT FOR USB W/NO-LAN OPTION 91 57 46 VREG_USB_BP_MJ
1 2
IN
1 6 CONNECTOR STUFFING OPTIONS: 5 11
0 1A RJ45/2 USB - A11509-001 (OLDER DESIGNS, USB_BACK3_R_DN 6
CH 57 46 BI
603 PRE-GIGABIT LAN)
57 46 BI USB_BACK3_R_DP 7
C R34BU 2 5 5VDUAL_USB DOUBLE STACK USB (NO LAN) - 749193-001 8 12 C
IN 42 43 44 45 46 52 88 91 92
1 2
0 1A EMPTY
603 CH 3 4
L8BU EMPTY CAD NOTE:

31 BI USB_BACK3_DN 1 4 USB_BACK3_R_DN BI 46 57
90OHM PLACE CAP AS CLOSE AS POSSIBLE
ACM2012 EMPTY TO USB CONNECTOR
L8BU
31 BI USB_BACK3_DP 2 3 USB_BACK3_R_DP BI 46 57 VREG_USB_BP_MJ
90OHM 91 57 46 IN
ACM2012 EMPTY
1 1
C405BU C229BU
470PF 470PF
R35BU 10% 10%
1 2 50V 50V
2 EMPTY 2 X7R
0 1A 402 402
603 CH
B B
DESIGN NOTE: R36BU

1 2
USB/ESATA DUAL STACK 0 1A
603 CH
CAD NOTE:
L9BU PLACE CAP AS CLOSE AS POSSIBLE

31 BI USB_BACK5_DN 2 3 USB_BACK5_R_DN BI 46 TO USB CONNECTOR
90OHM VREG_USB_BP1_STACK
ACM2012 EMPTY 91 46 IN
L9BU 1
31 BI USB_BACK5_DP 1 4 USB_BACK5_R_DP BI 46 C228BU
90OHM 470PF
10%
ACM2012 EMPTY 50V
CR7BU 2
R37BU 6.0V TVS6V
X7R
402
1 2 J12BU
CAD NOTE: 0 1A 2 X USB
603 CH
DO NOT CHANGE TO 402 6 1
91 46 IN VREG_USB_BP1_STACK 1 9
OVERLAPPING FOOTPRINTS USB_BACK6_R_DN 2
R38BU 46 BI
A 1 2 92 46 BI USB_BACK6_R_DP 3 A
45 44 43 42 IN 5VDUAL_USB 5 2
0 1A 91 88 52 46
4 10
603 CH
4 3
5 11
46 BI USB_BACK5_R_DN 6
46 BI USB_BACK5_R_DP 7
L10BU 8 12
31 BI USB_BACK6_DP 1 4 USB_BACK6_R_DP EMPTY
BI 46
90OHM
ACM2012 EMPTY CONN
L10BU
31 BI USB_BACK6_DN 2 3 USB_BACK6_R_DN BI 46 A91996-001
90OHM
ACM2012 EMPTY
R39BU
1 2
0 1A
603 CH frostburg_fabc.sch_1.46
INTEL
xxxxxx 46 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

D
EXPANSION SLOT 2 D
CAD NOTE:
PCI-E X1 SLOT 1 CLOSEST TO PEGX16
PCI EXPRESS
1-PORT
+12V
C C
J13BU +12V VCC3
3GIO_X1
1.0
B1 12V PRSNT1* A1
B2 12V 12V A2
SMB_CLK_RESUME B3 12V 12V A3
105 103 102 101 70 49 48 33 28 27 22 21 BI B4 A4
GND GND
B5 SMCLK JTAG2 A5 TP_PCIE_JTAG2_1
105 103 102 101 70 49 48 33 28 27 22 21 BI SMB_DATA_RESUME B6 SMDAT JTAG3 A6 TP_PCIE_JTAG3_1
B7 GND JTAG4 A7 TP_PCIE_JTAG4_1
B8 3.3V JTAG5 A8 TP_PCIE_JTAG5_1
VCC3 TP_PCIE_JTAG1_BP_1 B9 A9
105 103 102 101 92 JTAG1 3.3V
49 48 47 39 38 37 36 34 33 32 28 22 21 9 IN V_3P3_STBY\G B10 3.3VAUX 3.3V A10
90 88 87 86 85 84 82 70 69 64 59 53
OUT WAKE_N B11 WAKE* PWRGD A11 PLTRST_PCIE_SLOTS_N IN 21 22 70 101 102
KEY
TP_PCIE_RSVD_B12_1 B12 RSVD GND A12
B13 GND REFCLK+ A13 CK_1PORT_S1_DP IN 29
31 IN HSO4_C_DP B14 HSOP0 REFCLK- A14 CK_1PORT_S1_DN IN 29
31 IN HSO4_C_DN B15 HSON0 GND A15
B16 GND HSIP0 A16 HSI4_DP OUT 31
B TP_PCIE_PRSNT_B16_1 B17 A17 HSI4_DN B
PRSNT2* HSIN0 OUT 31
B18 GND A18
1 OF 1 GND
CONN
1
C304BU
.1UF
CAD NOTE: 20%
25V
2 EMPTY
PLACE AT PCI SLOTS 603
VCC3
C231BU
1 2 VCC3 VCC3 +12V 105 103 102 101 92
49 48 47 39 38 37 36 34 33 32 28 22 21 9 IN V_3P3_STBY\G
.1UF 20% C233BU C234BU 90 88 87 86 85 84 82 70 69 64 59 53
25V 1 2 1 2 C235BU
EMPTY 1 2
603 .1UF 20% .1UF 20% C236BU
.1UF 20% 1 2
25V 25V
C232BU EMPTY Y5V 25V
1 2 603 603 EMPTY .1UF 20%
603 25V
Y5V
.1UF 20% 603
A 25V A
Y5V
603
[PAGE_TITLE=PCI EXPRESS X1 #1]

INTEL
xxxxxx 47 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

EXPANSION SLOT 3 MODULE NAME REV DATE
VCC VCC VCC3
C245BU C246BU C247BU VCC3
1 2 100UF
1 2 470UF
1 2
.1UF 20% C248BU
1 2
25V 20.0% 25V
EMPTY EMPTY 20% 10V
D 603 EMPTY .1UF 20%
PCI SLOT 1 VCC
VCC3
RDL
VCC3 RDL 25V
Y5V D
603
VCC3 VCC +12V -12V VCC VCC3 C249BU C251BU
+12V
1 2 1 2
J20BU C250BU
105 103 102 101 1 2 C52BU
84 82 70 69 64 59 53 .1UF 20% .1UF 20% 1 2
34 33 32 28 22 21 9 IN V_3P3_STBY\G PCI CONN2_2 CONN 25V 25V
49 47 39 38 37 36 Y5V .1UF 20% EMPTY
25V .1UF 20%
92 90 88 87 86 85 603 603 25V
Y5V
C308BU A1 B1 603 Y5V
.1UF TRST* M12V_1 603
20% A2 P12V_1 TCK B2
25V A3 TMS GND1 B3 NOTE: PCI SLOTS= VCC3 SHOULD GET 470UF DECOUPLING,
Y5V
603 A4 TDI TDO B4 TP_PCI1_B4 VCC SHOULD GET 100UF (ALLOWS 1000UF OPTION FOR VCC3)
A5 P5V_2 P5V_0 B5
50 49 30 OUT P_INTF_N A6 INTA* P5V_1 B6
103 50 49 30 OUT P_INTH_N A7 INTC* INTB* B7 P_INTG_N OUT 30 49 50
A8 P5V_3 INTD* B8 P_INTE_N OUT 30 49 50 103
TP_PCI1_A9 A9 RSVD1 PRST1* B9 TP_PCI1_B9
A10 P5V_4 RSVD2 B10 TP_PCI1_B10
A12 GND10 GND2 B12
A13 GND16 GND3 B13
A14 3.3VAUX RSVD5 B14 TP_PCI1_B14
106 103 53 49 30 IN P_PCIRST_N A15 RST* GND4 B15
C A16 P5V_6 CLK B16 CK_P_33M_S1 C
106 103 53 49 36 30 IN P_GNT_N<3..0> A17 B17 IN 28
0 GNT* GND7 P_REQ_N<3..0>
A18 B18 OUT 30 49 50 53 103 106
P_PME_N GND5 REQ* 0
103 53 49 30 OUT A19 PME P5V_11 B19
30 A20 AD30 AD31 B20 31
VCC3 A21 P3_3V AD29 B21 29
DESIGN NOTE: 28 A22 AD28 GND8 B22
26 A23 AD26 AD27 B23 27
A24 GND6 AD25 B24 25
PCI2.2 COMPATIBLE 24 A25 AD24 P3_3V B25
16 A26 IDSEL C_BE3* B26 3
2 2 A27 P3_3V AD23 B27 23
R101BU R100BU 22 A28 AD22 GND12 B28
5.6K 5.6K 20 A29 AD20 AD21 B29 21
5% 5% A30 GND9 AD19 B30 19
EMPTY EMPTY 18 A31 AD18 P3_3V B31
402 402 16 A32 AD16 AD17 B32 17
1 1 A33 P3_3V C_BE2* B33 2
106 103 53 50 49 30 BI P_FRAME_N A34 FRAME* GND14 B34
A35 GND13 IRDY* B35 P_IRDY_N BI 30 49 50 53 103 106
106 103 53 50 49 30 BI P_TRDY_N A36 TRDY* P3_3V B36
A37 GND22 DEVSL* B37 P_DEVSEL_N BI 30 49 50 53 103 106
B 106 103 53 50 49 30 BI P_STOP_N A38 STOP* GND15 B38 P_PLOCK_N B
A39 B39 BI 30 49 50 103
P3_3V LOCK*
I_CLK_RESUME_RES_1 A40 SMB_CLK PERR* B40 P_PERR_N OUT 30 49 50 53 103
I_DATA_RESUME_RES_1 A41 SMB_DAT P3_3V B41
A42 GND25 SERR* B42 P_SERR_N OUT 30 49 50 53 103
106 103 53 49 30 BI P_PAR A43 PAR P3_3V B43
2 15 A44 AD15 C_BE1* B44 1
2 A45 P3_3V AD14 B45 14
R103BU R102BU 13 A46 AD13 GND23 B46
0 11 A47 AD11 AD12 B47 12
5% 0
5% A48 GND17 AD10 B48 10
CH A49 B49
402 CH 9 AD09 GND24
1 402 KEY A50 B50 KEY
SMB_CLK_RESUME 1 KEY A51 B51 KEY
101 70 49 47 33 28 27 22 21 BI A52 B52
105 103 102
0 C_BE0* AD08 8
SMB_DATA_RESUME A53 P3_3V AD07 B53 7 OUT 49 103
101 70 49 47 33 28 27 22 21 BI A54 B54
105 103 102
6 AD06 P3_3V
4 A55 AD04 AD05 B55 5 VCC
VCC A56 GND21 AD03 B56 3
2 A57 AD02 GND19 B57
0 A58 AD00 AD01 B58 1
R41BU A59 P5V_8 P5V_9 B59 ACK64_N R10BU
1 2 REQ64B_N A60 REQ64* ACK64* B60
2.7K 5% A61 P5V_12 P5V_5 B61 2.7K 5%
A 402 CH A62 P5V_10 P5V_7 B62 402 CH A
P_AD<31..0> NC=1,2
106 103 53 49 30 BI
P_C/BE_N<3..0>
106 103 53 49 30 BI
DESIGN NOTE:
IRQ MAP
IRQ MAP A B C D
F G H E
IDSEL 16 [PAGE_TITLE=PCI CONN 1]
REQ/GNT 0 BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
INTEL
xxxxxx 48 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

EXPANSION SLOT 4 (FURTHEST FROM CPU) MODULE NAME REV DATE
VCC VCC VCC3
1 2 100UF
1 2 470UF
1 2
.1UF 20% C312BU
1 2
25V 20.0% 25V
Y5V EMPTY 20% 10V
PCI SLOT 2 VCC
VCC3
RDL
VCC3 RDL 25V
Y5V D
603
+12V
1 2 1 2
J15BU C314BU
105 103 102 101 1 2 C316BU
84 82 70 69 64 59 53 .1UF 20% .1UF 20% 1 2
48 47 39 38 37 36 Y5V .1UF 20% Y5V
25V .1UF 20%
92 90 88 87 86 85 603 603 25V
EMPTY
A1 B1 603 EMPTY
TRST* M12V_1 603
A2 P12V_1 TCK B2
A3 TMS GND1 B3 NOTE: PCI SLOTS= VCC3 SHOULD GET 470UF DECOUPLING,
A4 TDI TDO B4 TP_PCI2_B4 VCC SHOULD GET 100UF (ALLOWS 1000UF OPTION FOR VCC3)
A5 P5V_2 P5V_0 B5
50 48 30 OUT P_INTG_N A6 INTA* P5V_1 B6
103 50 48 30 OUT P_INTE_N A7 INTC* INTB* B7 P_INTF_N OUT 30 48 50
A8 P5V_3 INTD* B8 P_INTH_N OUT 30 48 50 103
A10 P5V_4 RSVD2 B10 TP_PCI2_B10
A12 GND10 GND2 B12
A13 GND16 GND3 B13
A14 3.3VAUX RSVD5 B14 TP_PCI2_B14
C A16 P5V_6 CLK B16 CK_P_33M_S2 C
106 103 53 48 36 30 IN P_GNT_N<3..0> A17 B17 IN 28
1 GNT* GND7 P_REQ_N<3..0>
A18 B18 OUT 30 48 50 53 103 106
P_PME_N GND5 REQ* 1
103 53 48 30 OUT A19 PME P5V_11 B19
30 A20 AD30 AD31 B20 31
VCC3 A21 P3_3V AD29 B21 29
DESIGN NOTE: 28 A22 AD28 GND8 B22
26 A23 AD26 AD27 B23 27
A24 GND6 AD25 B24 25
PCI2.2 COMPATIBLE 24 A25 AD24 P3_3V B25
17 A26 IDSEL C_BE3* B26 3
2 2 A27 P3_3V AD23 B27 23
R159BU R151BU 22 A28 AD22 GND12 B28
5.6K 5.6K 20 A29 AD20 AD21 B29 21
5% 5% A30 GND9 AD19 B30 19
EMPTY EMPTY 18 A31 AD18 P3_3V B31
402 402 16 A32 AD16 AD17 B32 17
1 1 A33 P3_3V C_BE2* B33 2
A39 B39 BI 30 48 50 103
P3_3V LOCK*
106 103 53 48 30 BI P_PAR A43 PAR P3_3V B43
2 15 A44 AD15 C_BE1* B44 1
2 A45 P3_3V AD14 B45 14
R152BU R153BU 13 A46 AD13 GND23 B46
0 11 A47 AD11 AD12 B47 12
5% 0
5% A48 GND17 AD10 B48 10
CH A49 B49
402 CH 9 AD09 GND24
1 402 KEY A50 B50 KEY
101 70 48 47 33 28 27 22 21 BI A52 B52
105 103 102
0 C_BE0* AD08 8
SMB_DATA_RESUME A53 P3_3V AD07 B53 7
101 70 48 47 33 28 27 22 21 BI A54 B54
105 103 102
6 AD06 P3_3V
4 A55 AD04 AD05 B55 5
2 A57 AD02 GND19 B57
0 A58 AD00 AD01 B58 1
R154BU A59 P5V_8 P5V_9 B59
1 2 REQ64INV_N A60 REQ64* ACK64* B60 ACK64_N OUT 48 103
2.7K 5% A61 P5V_12 P5V_5 B61
A 402 CH A62 P5V_10 P5V_7 B62 A
P_AD<31..0> NC=1,2
106 103 53 48 30 BI
P_C/BE_N<3..0>
106 103 53 48 30 BI
DESIGN NOTE:
IRQ MAP
IRQ MAP A B C D
G F E H
INTEL
xxxxxx 49 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

VCC
PCI PULL-UPS
D
D
P_SERR_N 1 R42BU 2
103 53 49 48 30 OUT
2.7K 5%
402 CH
P_DEVSEL_N 1 R43BU 2
106 103 53 49 48 30 OUT
2.7K 5%
402 CH
P_IRDY_N 1 R44BU 2
106 103 53 49 48 30 OUT
2.7K 5%
402 CH
P_PLOCK_N 1 R45BU 2
103 49 48 30 OUT
2.7K 5%
402 CH
P_PERR_N 1 R46BU 2
103 53 49 48 30 OUT
2.7K 5%
402 CH
C C
P_FRAME_N 1 R47BU 2
106 103 53 49 48 30 OUT
2.7K 5%
402 CH
P_TRDY_N 1 R48BU 2
106 103 53 49 48 30 OUT
2.7K 5%
P_STOP_N 1 R49BU 2 402 CH
106 103 53 49 48 30 OUT
2.7K 5%
402 CH
VCC
B B
RP1BU 3 1 R50BU 2
106 103 30 P_INTC_N 6 3 2.7K 5%
OUT
RP1BU 2.7K 5% .063W 402 CH
7 2 SM IC
103 30 OUT P_INTB_N 1 R51BU 2
2
2.7K 5% .063W
SM IC RP1BU 2.7K 5%
103 53 30 P_INTD_N 8 1 402 CH
OUT
2.7K 5% .063W
RP1BU SM IC 1 1 R52BU 2
103 30 P_INTA_N 5 4
OUT 2.7K 5%
2.7K 5% .063W
SM IC 402 CH
RP2BU
P_INTE_N 3 6 0 1 R53BU 2
103 49 48 30 OUT
2.7K 5% .063W 2.7K 5%
RP2BU SM IC
P_INTF_N 1 8 402 CH
49 48 30 OUT
2.7K 5% .063W
SM IC
RP2BU
49 48 30 P_INTG_N 2 7
OUT
2.7K 5% .063W
RP2BU SM IC
103 49 48 30 P_INTH_N 4 5
OUT
2.7K 5% .063W 106 103 53 49 48 30 OUT P_REQ_N<3..0>
SM IC
A A
[PAGE_TITLE=PCI TERMINATION]
INTEL
xxxxxx 50 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

D
D
SW_ON_R_N 1 R71BU 2 SW_ON_N 90 89 88 80 74 73 70 69 66 37 IN V_5P0_STBY\G

51 IN OUT 33 92 91
33 5% J16BU
402 CH 1
C261BU 2X5HDR_10
1.0UF
20% 1 2
10V 3 4
2 Y5V R75BU 1 R74BU 2
VCC 603 5 6 1 2
7 8 470 5% 470 5%
9 402 CH 402 CH
1
C265BU HDR
470PF
1 R72BU 2 10%
VCC 50V
2 EMPTY
330 5% 402
402 CH
VCC_HDLED_PWR GPIO_GRN_BLNK_HDR_R
IN 51
51 IN HD_LED_G_N GPIO_YLW_BLNK_HDR_R
IN 51
SW_ON_R_N 51
FP_RST_N OUT
97 70 36 33 7 OUT
C C
VCC VCC
CP3BU CP3BU CP1BU CP1BU CP1BU CP1BU CP3BU CP3BU

4 470PF 2 470PF 3 470PF 1 470PF 2 470PF 4 470PF 1 470PF 3 470PF
20% 20% 20% 20% 20% 20% 20% 20%
50V 50V 50V 50V 50V 50V 50V 50V
5 EMPTY 7 EMPTY 6 EMPTY 8 EMPTY 7 EMPTY 5 EMPTY 8 EMPTY 6 EMPTY
SM SM SM SM SM SM SM SM
B B
BOM NOTE:
BOM=CORE_STDFNTPNL_E
DEFAULT EMPTY: STUFF 0 OHM RES (R206LB) FOR ICH PORT80 LED FEATURE (TDE EXPERIMENT) VCC
R206LB
ICH_PORT80_LED 1 2
36 33 IN
0 5%
402 EMPTY
402 EMPTY
5%
R104BU
2
ICH_QRT0 1 R11BU 2
33 IN GPIO_GRN_BLNK_HDR_R
OUT 51
0 5% J5LH
330
1
402 EMPTY 1X2HDR
HD_LED_G_N OUT 51 1 2
BOM NOTE: ICH_QRT1_Q
STUFF FOR EL 1 EMPTY

ICH_QRT1_J
3
1 R77BU 2 R79BU R80BU
70 GPIO_GRN_BLNK_HDR 1 2 EL_FET_R 1 Q6BU 0 R9BU 3
IN MMBT3904 ICH_QRT1 1 2 1 Q7BU
0 5% 10K 5% XSTR 5% BOM NOTE: 51 33 IN ICH_QRT1_R
402 CH J18BU 402 CH 2 EMPTY EMPTY
10K 5%
1X3HDR2 402 EMPTY FOR EL 402 EMPTY 2 MMBT3904
1 1 C263BU 2
A 470PF HD_LED_N A
102276-304 3 10% IN 70
2 50V
EMPTY
HDR 603 DESIGN NOTE:
GPIO_YLW_BLNK_HDR 1 R78BU 2
70 IN CUSTOM FEATURE
0 5%
402 CH
1 C264BU
470PF
10%
2 50V
EMPTY
603
[PAGE_TITLE=STD FRONT PANEL HDR]
ICH_QRT1 1 R12BU 2 GPIO_YLW_BLNK_HDR_R
51 33 IN OUT 51
0 5%
402 EMPTY frostburg_fabc.sch_1.51
INTEL
xxxxxx 51 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

D
FRONT PANEL POWER #1
DESIGN NOTE:
D
STUFFING THE THERMISTOR ASSUMES FRONT PANEL CARD
HAS NO FUSE AND DOES NOT PROVIDE OVER-CURRENT PROTECTION
88
1.50
46 RT1BU
44
42 IN 5VDUAL_USB 1 2 USB_FP1_PWR OUT 42
43
THRMSTR R60BU 1 C253BU
1 R54BU 45
52 1 470UF
C92281-001 10K 20%
15K 91
5% 10V
5% 92
2 CH 2 ALUM
2 CH 402 RDL
402 USB_OC_FRONT1_N OUT 31 1 R58BU 2
CAD NOTE:
0 5%
1 R55BU 1206 EMPTY
DUAL FOOTPRINT: PLACE 0 OHM
10K 1206 IN PARALLEL WITH THERMISTOR
5% CAD NOTE:
2 CH BOM NOTE:
PLACE DECOUPLING AS CLOSE AS POSSIBLE
USB_OC_FRONT1_R_N 402
42 STUFF 0 OHM INSTEAD OF THERMISTOR FOR
IN PRODUCT WITH FUSE ON FRONT PANEL TO USB CONNECTOR
C C

DESIGN NOTE:
1.50
92 RT2BU
52
43
46
42 IN 5VDUAL_USB 1 2 USB_FP2_PWR OUT 43
45 44
91 88 THRMSTR R61BU 1 C254BU
1 R56BU 1 470UF
C92281-001 10K 20%
15K 5% 10V
5% 2 CH 2 ALUM
2 CH RDL
402 USB_OC_FRONT2_N
402
OUT 31 1 R59BU 2
CAD NOTE:
0 5%
1 R57BU 1206 EMPTY
B 5% CAD NOTE: B
2 CH BOM NOTE:
402
STUFF 0 OHM INSTEAD OF THERMISTOR FOR
43
USB_OC_FRONT2_R_N PRODUCT WITH FUSE ON FRONT PANEL TO USB CONNECTOR
IN

DESIGN NOTE:
1.50
92 RT8BU
52
43
46
42
5VDUAL_USB 1 2 USB_FP3_PWR
44
45 44
IN OUT
91 88 THRMSTR R84BU 1 C307BU
1 R81BU 1 470UF
C92281-001 10K 20%
15K 5% 10V
5% 2 CH 2 ALUM
2 CH RDL
A 402 USB_OC_FRONT3_N
402 A
OUT 31 1 R83BU 2
CAD NOTE:
0 5%
1 R82BU 1206 EMPTY
5% CAD NOTE:
2 CH BOM NOTE:
402
STUFF 0 OHM INSTEAD OF THERMISTOR FOR
44
USB_OC_FRONT3_R_N PRODUCT WITH FUSE ON FRONT PANEL TO USB CONNECTOR
IN
[PAGE_TITLE=USB_FP_HEADER_POWER]
INTEL
xxxxxx 52 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

TI_1394A_2 1.05.00 12.30.05
1 VCC3
C1FW
22PF
5%
50V
2 EMPTY 1
402
D U1FW
FB1FW
TSB43AB22A FB D
53 1394_GRST 14 G_RST* AVDD<5> 120
IN 2
28 IN CK_P_33M_1394 16 PCI_CLK AVDD<4> 108
103 50 30 OUT P_INTD_N 13 PCI_INTA* AVDD<3> 107
1 P_PCIRST_1394_R_N 85 PCI_RST* AVDD<2> 2 1
C2FW 106
P_PCIRST_N 1 R15FW 2 AVDD<1> 1 VA_3P3_1394 1 C6FW
22PF 49 48 30 IN IN 53 55 C7FW 1000PF
5% 103 0 5% P_AD<31..0>31 22 PCI_AD<31> 10UF 10%
50V 49 48 30 BI 24 100
2 <EMPTY> 402 CH 106 103
30 PCI_AD<30> DVDD<8> 20%
6.3V 2 50V
603 29 25 PCI_AD<29> DVDD<7> 88 2 X7R
X5R 402
1 28 26 PCI_AD<28> DVDD<6> 72 V_3P3_1394_FILTERED
OUT 53 55 805
C10FW 27 28 PCI_AD<27> DVDD<5> 59
0.1UF 26 29 PCI_AD<26> DVDD<4> 51
20%
16V 25 31 PCI_AD<25> DVDD<3> 39
2 EMPTY 24 32 27 BOM NOTE: NEVER STUFF
PCI_AD<24> DVDD<2> BOTH
1394 RESET CONTROL 402
23 37 PCI_AD<23> DVDD<1> 15
92 90 88 87 86 85 84 82 70 22 38 PCI_AD<22> 1 R56FW 2 CK_XT_24M_1394
37 36 34 33 32 28 22 21 9 IN V_3P3_STBY\G 19 1394_PLLVDD IN 29
69 64 59 49 48 47 39 38
21 40 PCI_AD<21> PLLVDD 7
105 103 102 101 20 41 PCI_AD<20> 0 5%
402 CH
2
R10FW 19 42 PCI_AD<19> VDDP<5> 78

R9FW 18 43 PCI_AD<18> VDDP<4> 62 1 R57FW 2
CH 5%
VCC
CH 5% 17 45 PCI_AD<17> VDDP<3> 48
10K 0 5%
10K 16 46 PCI_AD<16> VDDP<2> 35 402EMPTY
402
C 402 15 61 PCI_AD<15> VDDP<1> 20 C5FW C
1 14 63 PCI_AD<14> 1394_XI_R
2
1
1
1394_GRST OUT 53 R13FW

13 65 PCI_AD<13> XI 5 1394_XI
100 12 66 PCI_AD<12> 1 22PF 5%
5% 11 67 PCI_AD<11> XO 6 1394_XO 1 R11FW 2 50VEMPTY
1394_RST_INT1 R7FW 1
CH 10 69 PCI_AD<10> 0 5% 1.0M Y1FW 603
Q1FW 402 9 70 PCI_AD<9> CPS 106 1394_CPS 1 R3FW 2 402EMPTY 5% 24.576MHZ
MBT3904DUAL 3 6 2 8 71 390K SM
PCI_AD<8> 402 5% VCC3 EMPTY
EMPTY
7 74 PCI_AD<7> FILTER0 3 1394_FILTER0 C8FW CH 603 2
PWRGD_3V 2 R8FW 1 5 2 6 76 4 1394_FILTER1 2 1 2 C4FW
33 13 IN PCI_AD<6> FILTER1
2
1
20% 0.1UF
70 10K 1394_RST_INT2 5 77 PCI_AD<5> 402 Y5V
CH 1 R16FW 2 16V 1394_XO_R
5% 402 4 79 PCI_AD<4> PC0 99 1394_PC0
4 1 XSTR 3 80 PCI_AD<3> PC1 98 1394_PC1 402 470 1 R17FW 2 22PF 5%
5% CH EMPTY
50V
2 81 PCI_AD<2> PC2 97 1394_PC2 1 R18FW 2 402 470 5% CH +12V
1394_EN 82 402 CH 603
32 IN 1 PCI_AD<1> 470 5%
0 84 PCI_AD<0> TPA0P 115 1394_TPA0P
BI 54
2 R6FW 1 TPA0M 114 1394_TPA0N
BI 54
0 73 PCI_C_BE0*
EMPTY 0 48 30 IN P_C/BE_N<3..0> 60 124
5% 402 106 103 49 1 PCI_C_BE1* TPA1P 1394_TPA1P
BI 54
2 47 PCI_C_BE2* TPA1M 123 1394_TPA1N
BI 54
3 34 PCI_C_BE3*
TPB0P 113 1394_TPB0P
BI 54
1 R4FW 2 1394_CLKRUN_N 12 PCI_CLKRUN* TPB0M 112 1394_TPB0N 54
B P_DEVSEL_N BI B
10K 5% 103 50 49 48 30 BI 53 PCI_DEVSEL*
402 CH 106 30
BI P_FRAME_N 49 PCI_FRAME* TPB1P 122 1394_TPB1P
BI 54
49 48 36 30 IN P_GNT_N<3> 106 103 50 49 48 18 PCI_GNT* TPB1M 121 1394_TPB1N
BI 54
PCI_IDSEL_1394 36 PCI_IDSEL
106 103 50 49 48 30 BI P_IRDY_N 50 PCI_IRDY* TPBIAS0 116 1394_TPBIAS0
BI 54
106 103 49 48 30 BI P_PAR 58 PCI_PAR TPBIAS1 125 1394_TPBIAS1
BI 54
50 49 48 30 BI P_PERR_N 56 PCI_PERR*
103 49 48 30 P_PME_N 1 R14FW 2 103 P_PME_1394_N 21 PCI_PME* R0 118 1394_R0 1 R12FW 2
BI
0 5% 19 PCI_REQ* R1 119 1394_R1 6.34K 1%
402 EMPTY BI P_SERR_N 57 PCI_SERR* 603 CH
P_REQ_N<3> 106 103 50 49 48 30 BI P_STOP_N 54 PCI_STOP*
50 49 48 30 OUT P_TRDY_N 52 128
106 103 50 49 48 30 BI PCI_TRDY* AGND<7>
AGND<6> 127
126 CAD NOTE:
AGND<5>
55 IN 1394_CNA 96 CNA AGND<4> 117 GROUND REFERENCE TOP LAYER
55 IN 1394_CYCLEIN 87 CYCLEIN AGND<3> 111 UNDER PART INSTEAD OF CREATING AGND PLANE
55 IN 1394_CYCLEOUT 86 CYCLEOUT AGND<2> 110
55 IN 1394_GPIO2 90 GPIO2 AGND<1> 109
55 1394_GPIO3 89 GPIO3
CHIP PWR SUPPLY 55
IN 1394_SCL 91 SCL REG18 93 REG18_93
OUT 1394_SDA
55 BI 92 SDA REG18 30 REG18_30
2 C9FW
VCC3 REG_EN* 9 2 C11FW
DGND<10> 103 .1UF
1 R55FW 2 1394_PIN10_11 .1UF 20%
55 53 IN V_3P3_1394_FILTERED 10 TEST17 DGND<9> 83 25V
A R5FW 20% 1 Y5V A
1A 1K 5% 11 TEST16 DGND<8> 75 25V
1 805
2 94 68 1 Y5V 603
0 CH VA_3P3_1394 53 55
402 CH 1394_TEST_089 TEST9 DGND<7> 603
OUT 95 TEST8 DGND<6> 64
1394_TEST_123 101 55 DESIGN NOTE:
TEST3 DGND<5>
102 TEST2 DGND<4> 44
104 TEST1 DGND<3> 33 IRQ MAP
105 TEST0 DGND<2> 23 A B C D
1 1 DGND<1> 17
2 C3FW D C F G
.1UF R1FW R2FW PLLGND 8
20% 1K 1K
25V 5% 5%
1 Y5V CH CH
NC=129 IC
603 402 402
2 2
[PAGE_TITLE=1394 CONTROLLER]
INTEL
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CAD NOTE: TI_1394A_2 1.05.00 12.30.05
PLACE CLOSE TO CONTROLLER
53 1394_TPBIAS0
BI
1 1
D 1 R19FW
C12FW R34FW R25FW 1 2 D
1UF 54.9 54.9
20% 1% 1% 0 1A
6.3V 603 CH
2 X5R CH CH
603 402 402
2 2
L2FW
53 BI 1394_TPA0N 2 3 TPA0M_1394
90OHM
ACM2012 EMPTY J1FW
L2FW 2X5HDR_9 A91836-021
53 1394_TPA0P 1 4 TPA0P_1394 1 2
BI
90OHM 3 4
ACM2012 EMPTY 5 6
1394_TPB0_PD
CAD NOTE: R20FW 7 8
1 1 2 10
PLACE CLOSE TO CONTROLLER 1
C14FW R31FW 0 1A
220PF 5.11K 1 1 603 CH HDR
10% 1%
50V R27FW R29FW
2 X7R CH R21FW
402 402 54.9 54.9 1 2
2 1% 1%
CH CH 0 1A
402 402 603 CH 55 IN 1394_PWR0
C 2 2
C
L1FW
53 BI 1394_TPB0N 2 3 TPB0M_1394
90OHM
ACM2012 EMPTY
L1FW
53 1394_TPB0P 1 4 TPB0P_1394
BI
90OHM EMPTY
CAD NOTE: ACM2012
CAD NOTE:
R22FW
TRACE WIDTH = 3.9 MIL 1 2 TRACE WIDTH = 3.9 MIL
SPACING = 8.1 MIL
0 1A SPACING = 8.1 MIL
SPACING TO OTHER 603 CH SPACING TO OTHER
LINES = 15 MIL
LINES = 15 MIL
CAD NOTE:
PLACE CLOSE TO 1394 HDR
CAD NOTE:
1394_TPBIAS1 PLACE CLOSE TO CONTROLLER
53 BI
B 1 1 B
1 R42FW
C15FW
1UF
R37FW
54.9
R38FW
54.9
1 2 FW
20% 1% 1% 0 1A
2
6.3V
CH CH
603 CH 1394
X5R
603 402 402
2 2 J12FW
L5FW 1394VERT_6PIN
53 BI 1394_TPA1N 2 3 TPA1M_1394 5 TPA- TPB- 3
90OHM
ACM2012 EMPTY 6 TPA+ TPB+ 4
L5FW
53 BI 1394_TPA1P 1 4 TPA1P_1394 1 PW R GND 2
90OHM
ACM2012 EMPTY CASE_GND 7
1394_TPB1_PD
CAD NOTE: R43FW CASE_GND 8
1 1 2 CASE_GND 9
PLACE CLOSE TO CONTROLLER 1
C16FW R41FW 0 1A
220PF 5.11K 1 1 603 CH CONN
10% 1%
50V R39FW R40FW
2 X7R CH R44FW
402 402 54.9 54.9 1 2
2 1% 1% 1394_PWR1
CH CH 0 1A IN 55
603 CH
A 402 402 A
2 2 1
C17FW
L6FW 470PF
10%
53 BI 1394_TPB1N 2 3 TPB1M_1394 50V
90OHM 2 X7R
ACM2012 EMPTY 402
L6FW
53 BI 1394_TPB1P 1 4 TPB1P_1394
90OHM CAD NOTE:
ACM2012 EMPTY
CAD NOTE:
R45FW
CAD NOTE: PLACE CAP AS CLOSE AS POSSIBLE
1 2 TO CONNECTOR
TRACE WIDTH = 3.9 MIL TRACE WIDTH = 3.9 MIL
SPACING = 8.1 MIL 0 1A SPACING = 8.1 MIL
603 CH CAD NOTE:
SPACING TO OTHER SPACING TO OTHER
LINES = 15 MIL PLACE CLOSE TO 1394 HEADER LINES = 15 MIL
[PAGE_TITLE=1394 BP REV1]
INTEL
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TI_1394A_2 1.05.00 12.30.05
1394_SDA BI 53 CR3FW
MRA4003T3 RT3FW
1 2 1 1394_PWR0_DIO 1 2 1394_PWR0
+12V OUT 54
R53FW
D 220 SM 1.5 THRMSTR
5% DIO 657448-018 1 1
C48FW C49FW D
CH
402 .1UF 100PF
2 20%
50V
5%
50V
2 X7R 2 <EMPTY> CAD NOTE:
805 402
PLACE NEAR
THE HEADER
53 IN 1394_SCL CR1FW
1 MRA4003T3 RT2FW
2 1 1394_PWR1_DIO 1 2 1394_PWR1
R52FW +12V OUT 54
220 1.5 THRMSTR
5% SM
DIO 657448-018 1
CH 1 C18FW
402 C19FW 100PF
2 .1UF 5%
20% 50V
BOM NOTE: 2 50V 2 <EMPTY> CAD NOTE:
X7R 402
STUFF BOTH RESISTORS FOR

1394 DOWN W/O EEPROM
EEPROM 805
PLACE NEAR
THE HEADER
C C
V_3P3_1394_FILTERED
IN 53 55
VA_3P3_1394
IN 53
1 1 1 1 1 1 1 1
C45FW C26FW C27FW C29FW C28FW C23FW C32FW
10UF C30FW 1000PF 1000PF 1000PF 0.1UF 0.1UF 0.1UF
20% 10UF 10% 10% 10% 20% 20% 20%
6.3V 20% 50V 50V 50V 16V 16V 16V
2 EMPTY 2 6.3V 2 X7R 2 X7R 2 X7R 2 Y5V 2 Y5V 2 Y5V
1 1 1 805 EMPTY 402 402 402 402 402 402
805
R46FW R49FW R47FW
4.7K
4.7K 4.7K
55
5%
5% 5%
CH
CH CH
53
402
402 402 2 VCC3
2 2 OUT
B B
53 OUT 1394_CNA V_3P3_1394_FILTERED FB2FW
53 OUT 1394_CYCLEIN 1 2
53 OUT 1394_CYCLEOUT 1 1 FB
C43FW C39FW 1 1
1 .01UF 1 0.1UF C44FW
10% 20% 0.1UF C41FW
C34FW 20% 0.1UF
R48FW 1 C42FW 25V 0.1UF 16V 20%
100UF
2 X7R 20% 2 Y5V 2 16V
16V
220 402 16V 402 Y5V 2
5% BOM NOTE: 20.0% 1 1 2 Y5V 1 1 402 1 Y5V
25V C38FW C47FW C36FW 402
EMPTY 402 C31FW C35FW
402 2 EMPTY
RDL
10UF
20%
0.1UF
20% 0.1UF 0.1UF
0.1UF
20%
2 STUFF FOR CARDBUS MODE 2 6.3V
2 16V 20%
16V
20%
16V 2 16V
X5R Y5V 2 2 Y5V
805 402 Y5V Y5V 402
402 402
VCC
1 R51FW 2
53 OUT 1394_GPIO2
220 5%
402 CH
A 1 2 A
R50FW 1 1 1 1 1
53 OUT 1394_GPIO3 C22FW
.001UF
C33FW
.001UF
C46FW
.001UF
C40FW
.001UF
C37FW
.001UF
220 5% 20% 20% 20% 20% 20%
402 CH 50V 50V 50V 50V 50V
2 X7R 2 X7R 2 X7R 2 X7R 2 X7R
603 603 603 603 603
-
-
-
GLOBAL RESET IS A POWER ON RESET
1394 CONTROLLER IS COMPLETELY NON-FUNCTIONAL
ALL REGISTERS ARE SET TO THEIR DEFAULT STATES,
WHEN ASSERTED
INCLUDING ONES NOT RESET BY PCI_RST
1394 DECOUPLING
INTEL
[PAGE_TITLE=1394 PWR/DCPL] Sun Mar 18 18:44:11 2007 CONFIDENTIAL xxxxxx 55 3.01
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BOM NOTE:
FOR EKRON USE IPN D23402-001
D20909-002 BL_INTEL_LAN 01.03.00 12-08-06
U1LN
EKRON MODE SELECT OPTIONS: FOLLOW BELOW FOR
NINEVEH0P99B BOM NOTE:
RESISTOR STUFFING CONFIGURATION
56 OUT HSI6_DP H2 GLAN_TXP/NC MDI_PLUS0/TDP B8 LAN_MDI0_DP BI 57
D HSI6_DN J2 GLAN_TXN/NC MDI_MINUS0/TDN B9 LAN_MDI0_DN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4
56 OUT BI 57
HSO6_C_DP J4 GLAN_RXP/NC MDI_PLUS1/RDP D9 LAN_MDI1_DP D
31 IN BI 57 TESTEN NOT SUPPORTED 0 (EXTERNAL) 1 (EXTERNAL) 1 (EXTERNAL) 1 (EXTERNAL)
31 IN HSO6_C_DN H4 GLAN_RXN/NC MDI_MINUS1/RDN D8 LAN_MDI1_DN BI 57
F9 LAN_MDI2_DP ISOL_TCK NOT SUPPORTED 0 (INTERNAL) 0 (EXTERNAL) 0 (INTERNAL) 1 (EXTERNAL)
BOM NOTE:
MDI_PLUS2/NC BI 57
TP_LAN_J6 J6 RSVD_J6/NC MDI_MINUS2/NC F8 LAN_MDI2_DN BI 57 ISOL_TI NOT SUPPORTED 1 (EXTERNAL) 0 (EXTERNAL) 1 (EXTERNAL) 0 (INTERNAL)
TP_LAN_J7 J7 RSVD_J7/NC MDI_PLUS3/NC H8 LAN_MDI3_DP BI 57
STUFF FOR NINEVEH H9 LAN_MDI3_DN ISOL_EXEC NOT SUPPORTED 1 (EXTERNAL) 1 (EXTERNAL) 1 (EXTERNAL) 0 (INTERNAL)
MDI_MINUS3/NC BI 57
EMPTY FOR EKRON
56 IN KMRN_RCOMP_DP G7 KBIAS_P/RBIAS100 33
V_3P3_EPW
56 IN KMRN_RCOMP_DN H7 KBIAS_N/RBIAS10 JTXD0 D1 ICH_LAN_JTX0 IN 33
27
28
IN
R5LN JTXD1 F3 ICH_LAN_JTX1 IN 33 34 1 R36LN 1 R37LN 1 R45LN 1 R41LN
2 1 LAN_RBIAS_P E7 RBIAS_P/NC JTXD2 F1 ICH_LAN_JTX2 38
IN 33 39 220 220 220 220
1.4K 1% E6 RBIAS_N/NC JRXD0 D3 ICH_LAN_JRX0 OUT 33 40 5% 5% 5% 5%
402 CH JRXD1 D2 ICH_LAN_JRX1 OUT 33 56 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY
TP_LAN_1P0_CTRL C3 C1 ICH_LAN_JRX2 57 402 402 402 402
CTRL_10/NC JRXD2 OUT 33 58
58 OUT LAN_1P8_CTRL B2 CTRL_18/NC JKCLK/JCLK E2 ICH_LAN_JCLK_R OUT 56 88
01.03.00 JRSTSYNC E3 ICH_LAN_JRST IN 33 92 LAN_TESTEN OUT 56
INTEL_LAN TP_LAN_THERM_DP A2 THERM_D_P/NC
R6LN TP_LAN_THERM_DN A3 THERM_D_N/NC LED0/LINK_UP* A4 LAN_LED0 OUT 57
RES_TESTPROBE LED1/ACT_LED* B4 LAN_LED1 OUT 57 LAN_ISOL_TCK_R
OUT 56
IEEE_TEST_LAN_P A7 IEEE_TEST_P/NC LED2/SPEED_LED* A5 LAN_LED2 OUT 57
B7 IEEE_TEST_N/NC
1 A B 2 IEEE_TEST_LAN_N H6 LAN_XTL_DP
XTAL1/X1 IN 56 LAN_ISOL_TI_R
OUT 56
56 IN LAN_ISOL_TCK_R G1 JTAG_TCK/ISOL_TCK XTAL2/X2 H5 LAN_XTL_DN OUT 56
C 56 IN LAN_ISOL_TI_R H1 JTAG_TDI/ISOL_TI C
1 EMPTY TP_LAN_JTDO_G3 G3 JTAG_TDO/TOUT TEST_EN B6 LAN_TESTEN LAN_ISOL_EXEC_R
IN 56 OUT 56
56 IN LAN_ISOL_EXEC_R G2 JTAG_TMS/ISOL_EXEC RSVD B5 TP_LAN_TEST0
RSVD_A6/ADV10-LAN_DIS* A6 LAN_DISABLE_N_R IN 56 2 R39LN 2 R40LN 2 R11LN
RSVD_C5/NC C5 TP_LAN_C5 1K 1K 100
5% 5% 5%
1 of 2 1 EMPTY 1 EMPTY 1 CH
402 402 402
1 IC
BOM NOTE:
STUFF R11LN FOR NINEVEH
ALL OTHERS ARE EMPTY
R38LN
33 IN LAN_DISABLE_N 1 2 LAN_DISABLE_N_R
OUT 56
0 1A BOM NOTE:
603 EMPTY
BOM NOTE: PLACE JCLK TERMINATION (R16LN) CLOSE TO LAN
92 R1LN D20909-002
56 OUT LAN_V_1P0 1 2
STUFF 0 OHM STRAP (BETWEEN LAN_DISABLE_N AND LAN_DISABLE_N_R FOR EKRON 58 0 1A U1LN R16LN
EMPTY FOR NINEVEH 603 CH NINEVEH0P99B 33 ICH_LAN_JCLK 1 2 ICH_LAN_JCLK_R 56
OUT IN
B 33 5% B
92
LAN_V1P0_OUT B1 V1P0_OUT/NC VSS/NC A1 TO ICH 402 CH FROM LAN
C1LN LAN_V_1P0 D7 VDD1P0/VCCR VSS C4
56 IN HSI6_DP 1 2 HSI6_C_DP OUT 31
56
58
IN
D4 E1
VCC VSS/VSSP
.1UF 10% E4 VCC/VCC VSS/VSS F4 LAN CRYSTAL
10V E8 VDD1P0/VCCT VSSA/NC J9
X5R
402 E5 VCCF1P0/VCC VSSA/NC J8 R46LN
G4 VCC1P0/VCCA2 VSSA/VSSA2 J5 LAN_XTL_DP_R LAN_XTL_DP OUT 56
C2LN F7 VDD1P0/VCCA VSSA/VSS J3
56 IN HSI6_DN 1 2 HSI6_C_DN OUT 31 H3 J1
0 5%
C35LN R47LN
VCCFC1P0/VCC VSSA/NC 402 CH CK_XT_25M_LAN_R
CK_XT_25M_LAN
G9 IN 29
.1UF 10% VSSA/VSS
CAD NOTE: 10V BOM NOTE: 57 IN LAN_V_1P8 C2 VCC1P8/NC VSSA/VSS G8 10PF 5% C36LN 33 5%
X5R 402 EMPTY
402 58 D5 VCC1P8/NC VSSA/VSS G6 50V 10PF
EMPTY FOR EKRON 88 EMPTY 5%
57 F5 VCC1P8/NC VSSA/VSS F6 402 50V
PLACE NEAR LAN / NINEVEH CONTROLLER STUFF FOR NINEVEH 40 G5 VCC1P8/NC VSSA/VSS E9 EMPTY
38 402
33 VSSA/VSS D6 BOM NOTE:
27 IN V_3P3_EPW F2 VCC3P3/VCCP VSSA/VSS C9
KMRN_RCOMP_DP OUT STUFF R46LN FOR CRYSTAL, EMPTY FOR CLK GEN
28 B3 VCC3P3/VCC VSSA/VSS C8
1 34 C7 STUFF C35LN, EMPTY FOR CRYSTAL
39 VSSA/VSS
R2LN 1 56 VSSA/VSSR C6
58 VSSA/NC A9
649 R7LN 92
1% 1.4K VSSA/VSS A8
EMPTY 1% 2 of 2
402 CH C22LN
1 1 2
A 2 402 IC A
2
KMRN_RCOMP_DN 27PF 5%
OUT 56 50V
Y1LN COG
25.000MHZ 402
BOM NOTE: C23LN
BOM NOTE: 1 2 1 2
STUFF (A93548-011) 649 OHM FOR EKRON EMPTY FOR EKRON
EMPTY FOR NINEVEH STUFF FOR NINEVEH SM A93545-056 27PF 5%
50V
XTAL COG
402
01.03.00
1 INTEL_LAN 56 IN LAN_XTL_DN
R3LN
619
1%
EMPTY
402 BOM NOTE:
2 BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
STUFF 619 1% FOR EKRON
INTEL
EMPTY 619 OHM FOR NINEVEH [PAGE_TITLE= LAN NINEVEH] Sun Mar 18 18:44:12 2007 CONFIDENTIAL xxxxxx 56 3.01
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BOM NOTE:
BL_INTEL_LAN 01.03.00 12-08-06
DEFAULT: STUFF C24LN FOR NINEVEH
EMPTY (UN-STUFF) CAP FOR EKRON
58 56 IN LAN_V_1P8
D 1 C24LN
1000PF
D
10%
50V
2 X7R
402
LAN CONNECTOR JA1LN

DEFAULT GIGABIT GBE_MAGJACK3_10
57 56 BI LAN_MDI0_DP 10 TD0+ R27LN
MAGJACK BI-COLOR SPEED LED 57 56 BI LAN_MDI0_DN 11 TD0- VCT 9 LAN_VCT 1 2
0 1A
57 56 BI LAN_MDI1_DP 12 TD1+ SGND 18 805 CH
10 MBPS OFF 57 56 BI LAN_MDI1_DN 13 TD1-
CAD NOTE:
LAN_MDI2_DP
57 56 BI 14 TD2+ PLACE CAP/RES NEAR MAGJACK_PIN9
100 MBPS GREEN 57 56 BI LAN_MDI2_DN 15 TD2- 1 C27LN
470PF
57 56 BI LAN_MDI3_DP 16 TD3+ 10%
1000 MBPS YELLOW 57 56 BI LAN_MDI3_DN 17 TD3- 2 50V
X7R
C 402
C
IO
USB STACK GND=23..30 BOM NOTE:
BOM NOTE: BOM NOTE:
C73572-005 DEFAULT: STUFF FOR NINEVEH
STUFF RES (R23LN, R25LN) STUFF RES (R24LN, R26LN)
JA1LN EMPTY (UN-STUFF) CAP/RES FOR EKRON
BOM NOTE: FOR NINEVEH FOR EKRON
2 X USB
57 46 IN VREG_USB_BP_MJ DEFAULT (JA1LN): C73572-005 (NINEVEH)
91 1 1000 OPTIONAL(JA1LN): C51242-005 (EKRON-N)
JA1LN
USB_BACK3_R_DN 2 R23LN GRN_LED
46 BI
46 BI USB_BACK3_R_DP 3 IN V_3P3_EPW 1 2 V_3P3_R_LAN 20 19 LAN_LED0 OUT 56
4 0 5%
402 CH 1 IO 1
57 46 IN VREG_USB_BP_MJ 92
88 R24LN C29LN C28LN
91 57 56 58 LAN_LED1 1 2 470PF 470PF
5 57
IN 10% 10%
USB_BACK1_R_DN 6 0 5% 50V 50V
46 BI 56
40 402 EMPTY
2 X7R JA1LN 2 X7R
46 BI USB_BACK1_R_DP 7 402 402
8 39 GRN_LED
38
33 R26LN
27 IN V_3P3_EPW 1 2 LAN_R_LED1 22 21 LAN_LED2 BI 56
IO 28
34 R25LN 0 5%
402 EMPTY 1 IO 1
56 IN LAN_LED1 1 2 C26LN C25LN
B 57 470PF YLW_LED 470PF B
0 5% 10% 10%
402 CH
2 50V
2 50V
X7R X7R
402 402
LAN_MDI0_DP 57 56 BI LAN_MDI2_DP
57 56 BI
LAN_DIFF_TAP_0
1 R35LN 1 R31LN
49.9 LAN_DIFF_TAP_2
1% 49.9
1 CH 1%
C33LN 2 1 2 CH
.1UF 402 C31LN 402
10% .1UF
10V 10%
2 X5R 1 R34LN 2 10V
402 49.9 X5R 1 R30LN
402 49.9
1%
1%
2 CH
2 CH
57 56 BI LAN_MDI0_DN 402
LAN_MDI2_DN 402
57 56 BI
57 56 BI LAN_MDI1_DP LAN_MDI3_DP
57 56 BI
LAN_DIFF_TAP_1
1 R33LN 1 R29LN
49.9 LAN_DIFF_TAP_3
1% 49.9
1 1%
C32LN 2 CH 1 2 CH
.1UF 402 C30LN 402
A 10% .1UF A
10V 10%
2 X5R 1 R32LN 2 10V
402 49.9 X5R 1 R28LN
402 49.9
1%
1%
2 CH
2 CH
402
402
57 56 BI LAN_MDI1_DN LAN_MDI3_DN
57 56 BI
BOM NOTE:
BOM NOTE: BOM NOTE:
DEFAULT: STUFF (4) RES WITH 49.9 OHM
DEFAULT: STUFF FOR NINEVEH (A93548-045) FOR NINEVEH DEFAULT: STUFF FOR NINEVEH
EMPTY (UN-STUFF) CAPS FOR EKRON CHANGE (4) RES TO 54.9 OHM EMPTY (UN-STUFF) CAPS, RESISTORS FOR EKRON
(A93548-279) FOR EKRON
DIFFERENTIAL PAIR TERMINATONS

INTEL
[PAGE_TITLE= LAN NINEVEH] xxxxxx 57 3.01
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BL_INTEL_LAN 01.03.00 12-08-06
D
D
DESIGN NOTE:
92 0 OHM BYPASS RESISTOR: REQUIRED AS 0603, PER DESIGN ENGINEER
88
58 BOM NOTE:
57
56 EMPTY (UN-STUFF) 0 OHM BYPASS RESISTOR FOR NINEVEH LAN
40 STUFF 0 OHM BYPASS RESISTOR FOR EKRON
38
33 1
R14LN 2 92 88
V_3P3_EPW
27 IN V_3P3_EPW 38
58
34
57
33
56
28
40
27
39
IN
28 1A 0
34 1 1
EMPTY 603
39 C6LN C13LN
4.7UF 0.1UF
BOM NOTE: 20% 20%
10V 16V
2 Y5V 2 Y5V
NINEVEH LAN; STUFF C15LN, C16LN, C17LN 402
805
EKRON LAN: STUFF ALL LAN_V_1P0
OUT 56 92
C C
1 1 1 1 1 1 1
C20LN C18LN C15LN C9LN C17LN C16LN C8LN
0.1UF 4.7UF 470PF 0.1UF 0.1UF 4.7UF 10UF
20% 20% 10% 20% 20% 20% 20%
16V 10V 50V 16V 16V 10V 6.3V
2 EMPTY 2 EMPTY 2 X7R EMPTY 2 Y5V 2 Y5V 2 EMPTY 2
402 805 402 402 402 805 805
39 38
V_3P3_EPW
28
34
56
27
33
40
IN
1P8 VOLT VREG
58 57 1 1 R8LN 1 R44LN 1
B 92 88 C12LN C5LN B
4.7UF 0.1UF 1.5 1.5
20% 20% 1% 1%
10V 16V
2 Y5V 2 Y5V CH 2 CH 2
805 402 2010 2010
CAD NOTE: 1
C34LN
PLACE V_3P3_EPW DECOUPLING
.01UF LAN_V3P3_EPW_XSTR_DRAIN
10%
CAPS NEAR XSTR 25V
2 X7R
402
3
56 LAN_1P8_CTRL 1 Q1LN
IN BCP69T1
XSTR
2 4
CAD NOTE: LAN_V_1P8 OUT 56 57
0.5INCH X 0.5INCH THERMAL RELIEF 1 1 1 1 1 1
C21LN C4LN C3LN C7LN C10LN C11LN
PAD NEEDS ON TRANSISTOR 470PF 470PF 10UF 0.1UF 4.7UF 4.7UF
10% 10% 20% 20% 20% 10%
PLACE C34LN NEAR XSTR 50V 50V 6.3V 16V 10V 6.3V
2 X7R 2 X7R 2 X5R 2 Y5V 2 Y5V 2 X5R
402 402 805 402 805 603
A BOM NOTE: A
BOM NOTE:
NINEVEH LAN; STUFF CAPACITORS, RESISTOR, XSTR
EKRON LAN: UN-STUFF CAPACITORS, RESISTOR, XSTR EKRON LAN: UN-STUFF CAPACITORS

INTEL
[PAGE_TITLE= LAN NINEVEH] xxxxxx 58 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BOM NOTE: MODULE NAME REV DATE
ALC268- D72688-001 BL AUDIO 0.06.00 10-12-06
60 IN AUD_CODEC_VREF ALC888- D72853-001
STAC9271D- D35875-004
2
C4AU 1 U1AU SURR REAR L/R LINE IN / SURR SIDE
5% 10PF
ALC885 PORT F PORT C
D 50V REV=1
COG 27 VREF PORT_A_L 39 AUD_PORT_A_L CEN / LFE D
402 BI 64
FRONT / LINE OUT
PORT_A_R 41 AUD_PORT_A_R 64
PORT G PORT D
AUD_LINK_BCLK BI
37 OUT 6 BCLK
60 AUD_LINK_SDI2_R 8 SDATA_IN PORT_B_L 21 AUD_PORT_B_L 64
S/PDIFF OUT MIC IN
OUT BI PORT F/E
37 IN AUD_LINK_SDO 5 SDATA_OUT PORT_B_R 22 AUD_PORT_B_R BI 64
37 AUD_LINK_SYNC 10 SYNC FACING BACK PANEL

IN AUD_PORT_C_L
1 PORT_C_L 23 BI 62
C98AU 59 IN AUD_LINK_RST_N 11 RESET*
10PF PORT_C_R 24 AUD_PORT_C_R 62
HEADPHONE PORT A SIGMATEL, REALTEK
5% BI
50V
2 MIC PORT B
EMPTY 60 IN AUD_PC_BEEP 12 BEEP DESIGN NOTE:
402 AUD_PORT_D_L
PORT_D_L 35 BI 62
AZALIA:
TP_AUD_CD_IN_L 18 CD_L PORT_D_R 36 AUD_PORT_D_R SIGMATEL-STAC9271D (5 STACKS)
BI 62
REALTEK- ALC268/888 (3 STACKS)
TP_AUD_CD_GND 19 CD_GND
PORT_E_L 14 AUD_PORT_E_L BI 62
TP_AUD_CD_IN_R 20 CD_R DESIGN NOTE: CODEC DOWN DISABLE CIRCUIT
C PORT_E_R 15 AUD_PORT_E_R BI 62 101 C
84 82 70 69 64 53 49
34 33 32 28 22 21 9 IN V_3P3_STBY\G
TP_AUD_SPDIF_IN 47 SPDIFI/EAPD 48 47 39 38 37 36
PORT_F_L 16 AUD_PORT_F_L BI 62 63 92 90 88 87 86 85
67 61 OUT AUD_SPDIF_OUT 48 SPDIFO 105 103 102 1 R71AU
PORT_F_R 17 AUD_PORT_F_R 62 63 1 R70AU 1K
BI 1K 5%
AUD_SENSE_A 13 DESIGN NOTE: 5% 2 EMPTY
64 62 60 OUT SENSE_A 2 EMPTY 402
PORT_G_L 43 AUD_PORT_G_L BI 63 GPIO LOW=CODEC DOWN ENABLE 402
63 62 60 OUT AUD_SENSE_B 34 SENSE_B GPIO HIGH=CODEC DOWN DISABLE AUD_LINK_RST_N
PORT_G_R 44 AUD_PORT_G_R BI 63 OUT 59
BOM NOTE:
AUD_LINK_RST_N_PIN3
45 TP_AUD_PORT_H_L STUFF:MEDIA SKU
PORT_H_L
EMPTY:CLASSIC SKU
Q4AU
PORT_H_R 46 TP_AUD_PORT_H_R EMPTY 3
3
R74AU R73AU
1 2 1
VRP 37 TP_AUD_VREF_37 37 IN AUD_LINK_RST_N_PIN5 1 1 2
100 5% 2 AUD_LINK_RST_N_PIN2
402 EMPTY
2 100 5%
PORT_B_VREFO 28 AUD_VREF_28 OUT 65
EMPTY 402 EMPTY
Q3AU
PORT_C_VREFO 29 TP_AUD_VREF_29 33 IN
B CDC_DWN_DISABLE B
PORT_D_VREFO 32 AUD_VREF_32 OUT 65
PORT_E_VREFO 31 AUD_VREF_31 OUT 65 R75AU

AUD_LINK_RST_CDC 1 2
PORT_F_VREFO 30 AUD_VREF_30 OUT 65 0 5%
402 CH
BOM NOTE: 33 AUD_FILTER_33
PORT_A_VREFO/DCVOL OUT 60
DEFAULT: STUFF 0 OHM (108506-004, 0603) R148AU BOM NOTE:
OPTIONAL: FERRITE BEAD (693286-014, 0603)
V_AUD_ANALOG JDREF 40 AUD_DVDD_CORE_40 1 2 V_AUD_DIGITAL IN 59
66 60 IN 25 AVDD1 0 5% STUFF:CLASSIC SKU
402 EMPTY EMPTY:MEDIA SKU
VCC3 38 AVDD2 AVSS1 26
M17AU TP_AUD_GPIO1
1 2 3 GPIO1 AVSS2 42 1 R149AU
OUT 59 AUD 20K
MULTI 1%
V_AUD_DIGITAL 1 DVDD GPIO0 2 TP_AUD_VOL_2
CH 603 2 CH
402 BOM NOTE:
9 DVDD_IO DVSS 4
DEFAULT: ALC268/888- R148AU= EMPTY, R149AU=STUFF
1 OF 1 DVSS 7 OPTION: STAC9271D- R148AU=STUFF, R149AU=EMPTY
2 2 2 2 IC
AUD
C1AU C5AU C3AU C110AU
A 10UF .1UF .1UF 10UF A
20% 10% 10% 20%
6.3V 16V 16V 6.3V
1 X5R 1 X7R 1 X7R 1 X5R
805 603 603 805
CAD NOTE:
PLACE NEXT
TO PIN 1
CAD NOTE:
PLACE NEXT TO
PINS 9
[PAGE_TITLE=AUDIO CODEC]
INTEL
xxxxxx 59 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL AUDIO 0.06.00 10-12-06
CAD NOTE: PLACE NEAR CDC PINS JACK DETECT NETWORK
D
D
R14AU
AUD_LINK_SDI2_R 1 2 AUD_LINK_SDI2 66 60 59 IN V_AUD_ANALOG
59 IN OUT 33
33 5%
402 CH 1 R9AU
5.11K
1%
BOM NOTE:
2 EMPTY
AUD_FILTER_33 59 DEFAULT:ALC268/888 EMPTY 402
OUT
OPTION:STAC9271D STUFF
AUD_SENSE_B OUT 59 62 63
BOM NOTE: CAD NOTE: 1
C10AU
1 DEFAULT: ALC268/888 EMPTY PLACE NEAR PIN 34 1000PF
C9AU OPTION: STAC9271D STUFF 10%
10UF 2 50V
20% CAD NOTE: EMPTY
6.3V 402
2 EMPTY PLACE CIRCUIT NEXT TO PIN 33
805
AUD
60 59 IN V_AUD_ANALOG
C AUD 66 C
1 R11AU
5.11K
1%
2 EMPTY
402
BOM NOTE:
DEFAULT:ALC268/888 EMPTY
OPTION:STAC9271D STUFF
AUD_SENSE_A OUT 59 62 64
CAD NOTE: 1
C15AU
1000PF
AUD_CODEC_VREF PLACE NEAR PIN 13 10%
OUT 59
50V
1 1 2 EMPTY
C20AU C19AU 402
.1UF 10UF
10% 20%
10V 6.3V
X5R 2 X5R 2
VREF SUPPLY AUD
402 805
CAD NOTE:
PLACE NEAR PIN 27
R13AU
B C18AU B
AUD 37 33 IN SPKR 1 2 AUD_PC_BEEP_PN1 1 2 AUD_PC_BEEP
OUT 59
CAD NOTE: CAD NOTE: 10K 5% .1UF 10%
402 CH
1
R12AU 2 10V
PLACE NEXT TO PIN 25 PLACE NEXT TO PIN 38 100 C8AU X5R
5% .01UF 402
10%
V_AUD_ANALOG OUT 59 60 66 2 CH 25V
402 1 EMPTY
402
C13AU 1 C16AU 1
1 1
C11AU C17AU AUD AUD
2
10UF
20%
6.3V
X5R 2
.1UF
10%
10V
X5R 2
10UF
20%
6.3V
X5R 2
.1UF
10%
10V
X5R
PC BEEP
805 402 805 402
AUD
A A
SUPPLY DECOUPLING [PAGE_TITLE=AUDIO DECOUPLING & JACK SENSE]

INTEL
xxxxxx 60 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL AUDIO 0.06.00 10-12-06
D
D
BOM NOTE:
OPTIONNAL: 5-STACK STUFF
DEFAULT: 3-STACK EMPTY
BOM NOTE:
DEFAULT: ALC268/888: 10 OHM
OPTIONAL:9271D: 33 OHM(A93549-005)
CAD NOTE: VCC

C C
PLACE NEXT TO PIN 48
JA5AU
DFP_AUD5STK
67 59 AUD_SPDIF_OUT 1 R88AU 2 AUD_SPDIF_VIN F3 VIN
IN
33 5%
402 EMPTY F2 VCC
F1 GND
1 C76AU
EMPTY
470PF
10% NC=40,41
2 50V GND=36,37,38,39,42,43
X7R
402
R108AU
1 2 1 C84AU
10K 5% 470PF
B 402 EMPTY 10%
50V
B
2 EMPTY
402
A A
[PAGE_TITLE=AUDIO SPDIF]

INTEL
xxxxxx 61 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
BOM NOTE: MODULE REV DETAILS

DEFAULT: STUFF JA5AU WITH C94525-001 5-STACK MODULE NAME REV DATE
OPTIONAL: STUFF JA6AU WITH C73570-001 3-STACK
BOM NOTE:
BL AUDIO 0.06.00 10-12-06
ALC268:STUFF C113AU, C114AU JA5AU

ALC888/9271D:STUFF C102AU, C103AU DFP_AUD5STK C94525-001
32
CAD NOTE:
D
DUAL SITE C113AU WITH C102AU. AUD_JACK_33 33 TOP D
DUAL SITE C114AU AND C103AU R45AU
1 2 34
PORT C
AUD_JACK_34
C113AU AUD
1 2 10K 1%
BOM NOTE: 35
AUD_PORT_F_L
R91AU FB OPTION: 0.2AMP (693286-014), 0603
402 CH
63 62 59 BI 1 2 4.7UF 20%
6.3V RES OPTION: 0 OHM (108506-004), 0603
0 5% 1
EMPTY
402 EMPTY 805 600
0.2A
R93AU EMPTY
1 2 AUD_SENSE_A
OUT 59 60 62 64
BROAD
R31AU AUD_PORT_LINE_L_C M7AU 0 5%
C102AU 402 CH R104AU
59 BI AUD_PORT_C_L 1 2 AUD_PORT_C_L_PN1 1 2
BI 62 62 BI AUD_PORT_LINE_L_C 1 2 AUD_L_LINEOUT_C
1 2
0 5%
MULTI AUD_SENSE_B
OUT 59 60 62 63
402 CH 4.7UF 20.0% 0 5%
16V FB C41AU
ALUM 2 1 JA6AU 402 EMPTY
TH 600
0.2A 470PF 10% 3 STACK AUDIOJACK_SW
BROAD 50V 32
M4AU X7R
R30AU C103AU AUD_PORT_LINE_R_C AUD 402
59 BI AUD_PORT_C_R 1 2 AUD_PORT_C_R_PN1 1 2
BI 62 62 BI AUD_PORT_LINE_R_C 1 2 AUD_R_LINEOUT_C 35
0 5%
MULTI
402 CH 4.7UF 20.0% 33
16V FB
ALUM R43AU C34AU
TH 1 2 2 1
34
C R92AU 470PF 10%
C
AUD_PORT_F_R C114AU 20K 5%
1 2 1 2 402 EMPTY 50V 1
63 62 59 BI X7R
0 5% AUD 402
402 EMPTY 4.7UF 20%
R36AU JACK
6.3V
EMPTY 1 2
805 BOM NOTE:
20K 5% AUD
402 EMPTY JA5AU
DEFAULT: ALC888 STUFF 470PF
OPTIONAL: 9271D STUFF 0.01UF(A36096-045) DFP_AUD5STK C94525-001
C37AU 22
R38AU AUD 600
59 AUD_PORT_D_L 1 2 1 2 AUD_PORT_LINE_L_D 62 0.2A
BI AUD_PORT_LINE_CPL_L_D
BI 62
0 5% BROAD 59 OUT AUD_SENSE_A 23
402 CH M6AU 60 R46AU MIDDLE
100UF BOM NOTE: 64
25V 20.0% 62 BI AUD_PORT_LINE_L_D 1 2 AUD_L_LINEOUT_D 1 2 AUD_JACK_24 24
MULTI AUD
ELEC
RDL
C36AU
NON DOLBY: STUFF A93544-018
DOLBY:STUFF A93540-076(470UF)
FB 1
C40AU
2
5.11K
402
1%
CH 25 PORT D
R39AU 100UF 600
470PF 10% 1
59 BI AUD_PORT_D_R 1 2 AUD_PORT_LINE_CPL_R_D AUD_PORT_LINE_R_D
BI 62 0.2A 50V
0 5% 1 2 BROAD X7R EMPTY
402 CH 25V 20.0% M3AU 402
ELEC AUD_PORT_LINE_R_D 1 2 AUD_R_LINEOUT_D AUD
RDL 62 BI JA6AU
MULTI
B FB 3 STACK AUDIOJACK_SW B
C44AU
1 2 22
R42AU
1 2 470PF 10%
BOM NOTE: 50V 25
20K 5% X7R
ALC268/9271D:STUFF C115AU, C116AU 402 CH 402
ALC888:STUFF C104AU, C105AU AUD 23
CAD NOTE: R48AU AUD 24
1 2
DUAL SITE C115AU WITH C104AU.
63 DUAL SITE C116AU AND C105AU 20K 5% 1
62 AUD_PORT_F_L
R150AU 402 CH
59 1 2 C115AU
BI 1 2
63 62 60 59 OUT JACK
0 5% JA5AU
402 CH 4.7UF 20% 600 DFP_AUD5STK
6.3V AUD 0.2A
C94525-001
EMPTY 2
805 BROAD
R35AU M8AU
C104AU AUD_SENSE_B 3
59 BI AUD_PORT_E_L 1 2 AUD_PORT_EB_L
1 2 AUD_PORT_LINE_L_MIC
BI 62 65 65 62 BI AUD_PORT_LINE_L_MIC 1 2 AUD_L_MIC
5.10 5%
MULTI BOTTOM
4.7UF 20.0% AUD_JACK_4 4
402 EMPTY 16V FB C43AU
ALUM
TH 600
0.2A
2
470PF 10%
1
5 PORT F/E
BROAD 50V 1
M5AU X7R
402
A 65 62 AUD_PORT_LINE_R_MIC 1 2 AUD_R_MIC AUD EMPTY A
R34AU C105AU BI MULTI
AUD_PORT_E_R 1 2 1 2 AUD_PORT_LINE_R_MIC
59 BI AUD_PORT_EB_R
BI 62 65 C38AU
FB 2 1
5.10 5% 4.7UF 20.0%
402 EMPTY 16V R44AU 470PF 10% JA6AU
ALUM C116AU 1 2 50V AUD
TH 1 2
20K 5% X7R 3 STACK AUDIOJACK_SW
402 EMPTY
AUD 402 2
63 AUD_PORT_F_R
R151AU 4.7UF 20%
59 1 2 6.3V R47AU
62
BI EMPTY R37AU 1 2 5
0 5% 805 1 2 AUD
402 CH 20K 1%
20K 5% 3
BOM NOTE: 402 CH
402 EMPTY
BOM NOTE: 4
DEFAULT: ALC268/888 STUFF A93548-181(20K 1%)
DEFAULT: ALC268/888 STUFF R150AU, R151AU OPTION:STAC9271D STUFF A93548-124 (39.2K 1%)
OPTION:STAC9271D STUFF R34AU, R35AU AUD 1 JACK
[PAGE_TITLE=AUDIO JACK (BLUE GREEEN PINK] frostburg_fabc.sch_1.62
INTEL
xxxxxx 62 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BOM NOTE:
STUFF THIS PAGE FOR 5-STACK BOM NOTE: BL AUDIO 0.06.00 10-12-06
FB OPTION: 0.2AMP (693286-014), 0603
RES OPTION: 0 OHM (108506-004), 0603
BOM NOTE:
D
5STACK:STUFF C106AU,C107AU D
3STACK:EMPTY ALL
C117AU
1 2
4.7UF 20%
6.3V
EMPTY
805 600 JA5AU
0.2A
BROAD DFP_AUD5STK C94525-001
D1
R60AU M12AU
C106AU 62
62 59 BI AUD_PORT_F_L 1 2 AUD_PORT_F_C_L 1 2 AUD_PORT_REAR_L
BI 63 BI AUD_PORT_REAR_L 1 2 AUD_PORT_REAR_L_JACK 59 OUT AUD_SENSE_B D2
0 5%
MULTI 60 R62AU
402 EMPTY 4.7UF 20.0% 63 1 2 AUD_JACK_D3 D3
16V EMPTY C54AU AUD
EMPTY
TH
600
0.2A
1
470PF 10%
2
20K 1%
402 EMPTY D4 PORT F
BROAD 50V TOP
EMPTY G1
R61AU C107AU
M14AU AUD 402
62 59 AUD_PORT_F_R 1 2 AUD_PORT_F_C_R 1 2 AUD_PORT_REAR_R 63 AUD_PORT_REAR_R 1 2 AUD_PORT_REAR_R_JACK EMPTY
BI BI BI MULTI
0 5% 4.7UF 20.0%
402 EMPTY EMPTY C51AU
C 16V 1 2 C
EMPTY R66AU
TH 1 2 470PF 10%
20K 5% 50V
EMPTY
402 EMPTY 402
C118AU R64AU
1 2 AUD 1 2
4.7UF 20% 20K 5%
6.3V 402 EMPTY
EMPTY
805 AUD AUD
B B
BOM NOTE:
5STACK:STUFF C108AU,C109AU
3STACK:EMPTY ALL
C119AU
1 2
4.7UF 20% JA5AU

6.3V 600
EMPTY 0.2A DFP_AUD5STK
805 BROAD
C94525-001
E1
R59AU C108AU
M11AU
AUD_SENSE_B E2
59 BI AUD_PORT_G_L 1 2 AUD_PORT_FG_L 1 2 AUD_PORT_CNT_L 1 2 AUD_PORT_CNT_L_JACK OUT
0 5%
MULTI R67AU
4.7UF 20.0% C53AU 1 2 AUD_JACK_E3 E3
402 EMPTY 16V EMPTY 1 2 AUD
EMPTY 600 10K 1%
A
TH 0.2A
BROAD
470PF 10%
50V
402 EMPTY E4
PORT G A
AUD EMPTY G1 BOTTOM
R58AU C109AU
M13AU 402
59 AUD_PORT_G_R 1 2 AUD_PORT_FG_R 1 2 AUD_PORT_LFE_R 1 2 AUD_PORT_LFE_R_JACK EMPTY
BI MULTI
0 5% 4.7UF 20.0%
402 EMPTY EMPTY C56AU
16V 1 2
EMPTY R114AU
TH 1 2 470PF 10%
C120AU 20K 5% 50V
1 2 EMPTY
402 EMPTY 402
4.7UF 20% R130AU
6.3V AUD 1 2
EMPTY
805 20K 5% AUD
402 EMPTY
[PAGE_TITLE=AUDIO JACK (BLACK ORANGE]
AUD
INTEL
xxxxxx 63 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

C100AU V_3P3_STBY\G MODULE NAME REV DATE
CAD NOTE: 2 1 IN
EMI CAP VCC3 +12V BL AUDIO 0.06.00 10-12-06
10PF 5%
1 R80AU 2 PLACE NEXT TO PIN 1 50V
EMPTY
33 5% 402 J7AU
402 EMPTY
2X8HDR12
37 33 AUD_LINK_BCLK_R
D IN AUD_LINK_BCLK_HDR 1 2
1 R69AU 2 AUD_LINK_RST_HDR 3 4 D
37 33 AUD_LINK_RST_R_N
IN 33 5% 5 6 BOM NOTE:
AUD_LINK_SYNC_R
402 EMPTY AUD_LINK_SYNC_HDR 7 8
37 36 33 IN 9 10
AUD_LINK_SDO_HDR ALC268/888- EMPTY
AUD_LINK_SDO_R
11
37 36 33 IN TP_AUD_RSVD3 13 14 STAC9271D-STUFF
1 R81AU 2 TP_AUD_RSVD2 15 16
33 5% AUD_SENSE_A OUT 59 60 62
402 EMPTY EMPTY
A91836-016
1 R72AU 2 2
AUD_LINK_R
1 R156AU 2 AUD_LINK_SDI1 C57AU
OUT 33 220PF
33 5% 10%
402 EMPTY 0 5% 50V
BOM NOTE: 402 EMPTY EMPTY 1
402
AUD_LINK_SDI0
DEFAULT: EMPTY FOR CLASSIC SKU OUT 33
AUD J6AU AUD
OPTION: STUFF FOR MEDIA SKU 2 R94AU
1
2X5HDR_8 AUD_FP_DETECT_HDR FP_AUD_DETECT OUT 33 36
65 64 AUD_PORT_B_L_HDR 1 2 0 5%
BI AUD_PORT_B_R_HDR 402 CH
65 64 BI 3 4
64 AUD_PORT_A_R_HDR 5 6 AUD_FP_SENSE_MIC
C BI C
7
64 AUD_PORT_A_L_HDR 9 10 AUD_FP_SENSE_HP
BI
HDR
1 1
R95AU R96AU
39.2K 20K
1% 1%
BOM NOTE: CH CH
402 402
ALC26/888- 0OHM A93549-001 2 2 2
2 2 R143AU
STAC9271D- 5.1OHM A93549-060 2
R145AU R144AU 20K
R146AU 20K 20K 5%
R89AU C67AU 20K 5% 5% EMPTY AUD AUD
AUD_PORT_B_R 1 2 AUD_PORT_B_R_C_HDR 1 2 AUD_PORT_B_R_HDR 5%
59 BI BI 64 65 402
CH EMPTY
0 5% 4.7UF 20%
CH 402 402 1
402 CH 6.3V 402 1 1
X5R 1
805
B AUD AUD AUD AUD B
2 2 2 2 2 2 2
C60AU C65AU C58AU C59AU C66AU C64AU C61AU
470PF 470PF 220PF 220PF 220PF
10% 10% 10% 10% 220PF 220PF 10%
50V 50V 50V 50V 10% 10% 50V
R85AU C70AU 1 X7R 1 X7R 1 X7R 1 X7R 1 50V
1 50V 1 EMPTY
AUD_PORT_B_L 1 2 AUD_PORT_B_L_C_HDR 1 2 AUD_PORT_B_L_HDR 402 402 402 402 X7R EMPTY 402
59 BI BI 64 65 402 402
0 5% 4.7UF 20%
402 CH 6.3V AUD
X5R AUD AUD AUD AUD AUD
805 AUD
BOM NOTE:
BOM NOTE:
NON DOLBY: STUFF A93544-018
DOLBY:STUFF A93540-076(470UF)
DEFAULT: ALC888 STUFF 470PF
OPTION: 9271D STUFF 0.01UF(A36096-045)
C93AU
R90AU 100UF
59 AUD_PORT_A_R 1 2 AUD_PORT_A_R_HDR 64
BI AUD_PORT_A_R_C_HDR
BI
5.10 5% 1 2
402 CH 25V 20.0%
A ELEC A
RDL
CAD NOTE:
C94AU PLACE 220PF CAPS CLOSE TO 2X5 AUDIO FRONT PANEL CONNECTOR
R86AU 100UF
59 AUD_PORT_A_L 1 2 AUD_PORT_A_L_C_HDR AUD_PORT_A_L_HDR 64
BI BI
5.10 5% 1 2
402 CH 25V 20.0%
ELEC
RDL
[PAGE_TITLE=AUDIO FP HEADERS & HDA HEADER]
INTEL
xxxxxx 64 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

REAR MIC BIAS BL AUDIO 0.06.00 10-12-06
D R153AU
BOM NOTE: 1 2 D
ALC268/888: STUFF R152AU EMPTY R113AU 0 5%
9271D: STUFF R113AU, EMPTY R152AU 402 CH
AUD_MIC2_DIODE
R121AU
1 2 AUD_PORT_LINE_R_MIC OUT 62
R152AU 2.2K 5%
402 CH
59 IN AUD_VREF_30 1 2
CR1AU
1K 5%
402 CH 1
R113AU Q1AU
59 AUD_VREF_31 1 2 6
AUD_MIC1_DIODE_MIC_BIAS
3
IN
2
1K 5%
402 EMPTY 2
MMBT3906
EMPTY BAW56S
1
SOT363
AUD_VREF_31_R_BASE DIO
AUD_VREF_31_R
2
5%
2
EMPTY
R141AU
C80AU
4.7UF R117AU AUD_PORT_LINE_L_MIC
20% 33K 1
AUD_MIC1_DIODE 2
6.3V 402 OUT
X5R 2.2K 5%
1
805 402 CH
1
C C
62
AUD
AUD
B B
FRONT MIC BIAS
R154AU
59 IN AUD_VREF_32 1 2
1K 5%
402 EMPTY 2
C112AU
4.7UF
20%
6.3V
EMPTY 1
805
CR1AU
R110AU AUD_PORT_B_R_HDR
A 4
AUD_VREF_FP_MIC_R
1 2 OUT 64 A
R107AU AUD 2.2K 5%
59 IN AUD_VREF_28 1 2 3 402 CH
1K 5% R111AU
402 CH
AUD_VREF_FP_MIC
5 AUD_VREF_FP_MIC_L 1 2 AUD_PORT_B_L_HDR OUT 64
BAW56S
2
2.2K 5%
SOT363 402 CH
C83AU DIO
4.7UF
20% R155AU
6.3V 1 2
X5R
805 0 5%
1
402 EMPTY
AUD

[PAGE_TITLE=AUDIO MIC BIAS] frostburg_fabc.sch_1.65
INTEL
xxxxxx 65 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BOM NOTE:
BL AUDIO 0.06.00 10-12-06
ONLY STUFF CR2AU IF U2AU IS STUFF

CR2AU
1N4148
88 80 74 73 70 69 51 37 IN V_5P0_STBY\G 1 3
D 92 91 90 89
SOT23 D
EMPTY
BOM NOTE:
CAD NOTE:
OPTION FOR FERRITE
M15AU BEAD (693286-014, 0603)
PLACE ETCH RESISTORS UNDER CODEC
1 2
MULTI
CH 603
1 R140AU 2
CR4AU 0OHM
1N4148 SM
1 3 BOM NOTE:
CHANGE THIS TO 78L05
SOT23 IF NEED TO STUFF
1 R138AU 2
EMPTY
BOM NOTE: 3 1 0OHM
SM
CR3AU- C79228-001 U3AU
CR3AU 2N3904
C MBRA130 2 EMPTY C
2 1
AUD AUD
SM
EMPTY CAD NOTE:
+12V U2AU USE LARGE SHAPE UNDER VREG FOR THERMALS
C83150-001 ADD VIAS FOR THERMAL RELIEF TO OTHER LAYERS
LD1117DT
M18AU
V_AUD_12V OUT 59
1 2 2 IN OUT 3 V_AUD_FILTERED 1 R134AU 2 V_AUD_ANALOG 60
MULTI 0OHM
EMPTY 603 GND SM
BOM NOTE: 1 1 C75AU CAD NOTE:
1 EMPTY 1 R136AU 1 C72AU
C71AU 1UF 100UF
DEFAULT: STUFF 0 OHM (A93552-004, 0603) 150 0.1UF 20% 20.0% ADD SEVERAL VIAS AFTER ETCH RESISTOR
OPTIONAL: FERRITE BEAD (693286-014, 0603) 1% 20% 6.3V 25V TO V_AUD_ANALOG
16V 2 X5R ELEC
2 EMPTY 2 Y5V 603 2 RDL
AUD_VREG_OPT_GND
402 402
1 AUD AUD
C74AU AUD
0.1UF 1 R137AU
20% 453
16V
1
B 2 EMPTY 1% B
C73AU 402 2 EMPTY
4.7UF 402
20%
16V
CAD NOTE: EMPTY
1206
2
PLACE GROUND::12V DECOUPLING SITE AS

CLOSE AS POSSIBLE TO AUDIO VREG AUD
C85AU C86AU C87AU

1 2 1 2 1 2
.01UF 10% .01UF 10% .01UF 10%

25V 25V 25V
X7R X7R X7R
402 402 402
AUD AUD AUD
C88AU C90AU C91AU
1 2 1 2 1 2
1 1
C77AU
A 470PF C111AU .01UF 10% .01UF 10% .01UF 10% A
10% 470PF 25V 25V 25V
50V 10% X7R X7R X7R
2 X7R 2 50V 402 402 402
402 X7R
402
AUD AUD AUD
CAD NOTE:
DISTRIBUTE THREE NEAR THE REAR AUDIO JACK.
CAD NOTE: AUD ONE NEAR THE FRONT PANEL AUDIO CONNECTOR.
REMAINING ALONG ANTI-ETCH BETWEEN ANALOG / DIGITAL GROUND
PLACE GROUND::AUD-GROUND DECOUPLING SITE AS
CLOSE AS POSSIBLE TO AUDIO TRIPLE-STACK CONNECTOR
[PAGE_TITLE=AUDIO VREG]
INTEL
xxxxxx 66 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL AUDIO 0.06.00 10-12-06
D
D
ATX CUSTOM SPDIF HEADER
61 59 AUD_SPDIF_OUT 1 R150BU 2 AUD_SPDIF_OUT_C VCC

IN
0 5%
402 EMPTY
1 C96BU
470PF
J1BU
10% 1X3HDR
50V 1
C 2 EMPTY 2 C
402 3
EMPTY
1
C97BU
SPDIF OUT 0.1UF CAD NOTE:
20%
16V
2 Y5V PLACE CLOSE TO HDR
402
B B
A A
[PAGE_TITLE=SPDIF HEADER]
INTEL
xxxxxx 67 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

TPM 1.2 MODULE
TPM1.2
NAME REV
1.2.0
DATE
41.4.06
BOM NOTE:
VCC3 TPM FEATURE:
ST-MICRO: C6TM EMPTY
D
ATMEL & SINOSUN: C6TM .1UF
D
1
C7TM
1 C8TM
2
C4TM
1 C6TM
.1UF .1UF .1UF .1UF BOM NOTE:
20% 20% 20% 20%
2 25V
2 25V
1 25V
2 25V
TPM FEATURE:
VCC3
EMPTY EMPTY EMPTY EMPTY
603 603 603 603 ST-MICRO: R7TM, R6TM, R10TM EMPTY
ATMEL & SINOSUN: R7TM, R6TM, R10TM 0 OHM R10TM
1 2
CAD NOTE: VCC3 0 5%
402 EMPTY
TPM VCC3 DECOUPLING: 0.1UF CAPS.
PLACE ONE PER TPM POWER PIN (10,19,24,5) R7TM 1 R6TM
1 2 TPM_NC_R_10 0
5%
0 5% 2 EMPTY
402 EMPTY
402
CAD NOTE: VCC3 VCC3 TPM_NC_R_5
OVERLAP THE PIN 1 PAD V3P0_BAT_TPM

28 IN CK_P_33M_TPM
C R15TM U1TM R13TM C

1 2
10
19
12
24
1 2 CK_P_33M_PATA2 WPCT200
5
OUT 106
0 5%
0 5% 402 EMPTY
402 EMPTY
NC
BOM NOTE:
VDD
VDD
VSB
VBAT
R16TM
1 2 TPM FEATURE:
ST-MICRO AND SINOSUN: R13TM EMPTY
0 5% ATMEL: R13TM 0 OHM
402 EMPTY NC 13 XTALIN_TPM
CK_P_33M_TPM_R 21 LCLK NC 14 TP_TPM_PIN_14
98 69 33 13 IN PLTRST_N 16 LRESET* VCC3
R3TM DESIGN NOTE:
1 2
69 33 BI L_AD<3..0> GPIO0/XOR_OUT 1 TP_TPM_PIN_1 TPM FEATURE:
0 26 LAD0 GPIO1 2 TP_TPM_PIN_2 4.7K 5% 1 PULL-UP STRAPPING FOR
402 EMPTY
1 23 LAD1 R5TM ENABLING TEST-MODE ON SINOSUN
2 20 LAD2 BOM NOTE: 4.7K
3 17 LAD3 GPIO2/GPX 6 TP_TPM_PIN_6 5%
TPM FEATURE:
EMPTY
ST-MICRO: R3TM EMPTY 402
L_FRAME_N 22 LFRAME* TEST 8 TPM_TESTIO ATMEL AND SINOSUN: R3TM 4.7K 2
69 33 IN
69 32 BI SER_IRQ 27 SERIRQ GPIO3/BADD 9 BADDR
B 1 BOM NOTE:
B
LPCPD_PN1_N 28 LPCPD* PP 7 TPM_PRESENCE
R4TM TPM FEATURE:
4.7K
ST-MICRO AND SINOSUN: EMPTY
5%
TPEV_TPM_CLKRUN_N 15 CLKRUN*/GPIO4 NC 3 TP_TPM_PIN_3 ATMEL: STUFF 4.7K
EMPTY
402
VSS
VSS
VSS
1 2
NC
VCC3 1 OF 1
R14TM R11TM
C9TM
1 2 4.7K REV=1
5% EMPTY .1UF
10K 5% 10%
4
18
25
11
EMPTY EMPTY 16V
402 402 R2TM EMPTY
2 TPM_NC_25_R 1 2 402
R12TM
LPCPD_N 1 2 0
BOM NOTE: 402 5%
33 IN EMPTY
69 0 5% BOM NOTE:
402 EMPTY TPM FEATURE:
DESIGN NOTE:
ST-MICRO: R2TM EMPTY STUFF FOR
VCC3
TPM FEATURE: DEFAULT STUFF R12TM, EMPTY R14TM ATMEL AND SINOSUN: R2TM 0 OHM WINBOND ONLY DESIGN NOTE: J2TM
STUFFING OPTION TO ISOLATE LPCPD* FROM ICH 1X3HDR
TPM FEATURE: DEFAULT EMPTY. 1
STRAPS FOR PHYSICAL PRESENCE. 2
3
VCC3
EMPTY
A R8TM R9TM A91829-001
A
2 1 1 2
BOM NOTE:
1K 5% 0 5%
402 EMPTY 402 EMPTY TPM FEATURE: DEFAULT EMPTY
CUSTOMER OPTION FOR PHYSICAL
PRESENCE HEADER.
[PAGE_TITLE=TPM 1.2]
INTEL
xxxxxx 68 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

SIO TRIPLE SITE (SMSC LPC47M182, WINBOND PC8347L, WINBOND WPCD376I) MODULE NAME
SIO_CIR_ICH9
REV
1.01.00
DATE
01.22.07
VCC3
U1LH
PORT ANGELES 3.0 BOM NOTE:
D
VCC3<5> 123 D
71 PA_FDD_DRVDEN0 22 60 U1LH STUFFING GUIDE
OUT 21
DRVDEN0 VCC3<4>
49 103 105
71 PA_FDD_DRVDEN1
OUT 19
DRVDEN1 VCC3<3>
31 85 86 87 88 MFGR PART # INTEL IPN DESCRIPTION
71 PA_FDD_MTR0_N
OUT 18
MTR0* VCC3<2>
6
69 70
71 PA_FDD_DS0_N 49 53
OUT 17
DS0* VCC3<1>
38 39 SMSC LPC47M182 C81714-001 PORT ANGELES 1.6
71 PA_FDD_DIR_N
OUT 16
DIR*
107 V_3P3_STBY\G
33 34 92
71 PA_FDD_STEP_N 9 21 22
OUT 15
STEP* V_3P3_STBY<3>
93
IN
71 OUT PA_FDD_WDATA_N 28 32 90 WINBOND PC8374L C76238-001 PORT ANGELES 3.0
FLOPPY
WDATA* V_3P3_STBY<2>
PA_FDD_WGATE_N 14 76 36 37
71 OUT WGATE* V_3P3_STBY<1> 47 48
71 OUT PA_FDD_HDSEL_N 10 HDSEL* 59 64
71 PA_FDD_INDEX_N 20 82 84 WINBOND WPCD376I D76793-001 PORT ANGELES 3.0 + CIR
IN 13
INDEX*
102 101 102
71 PA_FDD_TRK0_N TP_SIO_PIN_102
IN 12
TRK0* SER_CLK/GPIO17
103
71 PA_FDD_WRTPRT_N SIO_GPIO0_103 80
IN 11
WRTPRT* SER_DATA/GPIO0 OUT
71 PA_FDD_RDATA_N
IN 9
RDATA*
111 R86LH
71 PA_FDD_DSKCHG_N TP_SIO_PIN_111
IN DSKCHG* FANTACH1/GPIO6
1 2
FAN/GPIO
FANTACH2/GPIO7 112 TP_SIO_PIN_112
FANTACH3/GPIO1 104 TP_SIO_PIN_104 10K 5% 92 101 102 103 105
402 CH V_3P3_STBY\G
IN 9 21 22 28 32 33 34 36 37 38 39 47 48
33 OUT IO_PME_N 99 IO_PME* FANTACH4/GPIO2 105 TP_SIO_PIN_105
49 53 59 64 69 70 82 84 85 86 87 88 90
105 0 62 LAD<0> FANPWM1/GPIO3 106 SIO_PIN_106
OUT 9
101 92 90 61 108
86 85 84 1 LAD<1> FANPWM2/GPIO4 SIO_PIN_108
OUT 9
69 64 59 2 59 LAD<2> FANPWM3/GPIO5 109 SIO_GPIO5_109
OUT 80
48 47 39 68 33 BI L_AD<3..0>
3 57 R87LH
C LAD<3>
1 2 C
LPC
36 34 33 R11LH
22 21 9 V_3P3_STBY\G 2 1
32 28
IN 56 4 10K 5%
10K 5% 68 33 L_FRAME_N PA_KBDATA 72
38 37 CH 402 IN 54
LFRAME* KDAT
3
BI 402 CH
33 L_DRQ_N PA_KBCLOCK 72
53 49 OUT 1
R8LH
2 63
LDRQ* KCLK
2
BI
82 70 68 33 13 IN PLTRST_N PA_PLTRST_N PCI_RESET* MDAT PA_MSDATA
BI 72
PS/2
88 87 98 LPCPD_N 52 1 PA_MSCLOCK
103 102 68 33 IN 0 5% LPCPD* MCLK
BI 72
CH 402
28 IN CK_P_33M_PA 55 PCI_CLK KBDRST* 7 KBRST_N
OUT 32
68 32 BI SER_IRQ 53 SER_IRQ GA20M 5 A20GATE
OUT 32
C7LH 1
.1UF
74 IN PA_COM_RXD1 25 RXD1
20%
25V 74 OUT PA_COM_TXD1 27 TXD1 INITP* 48 PA_LPT_INIT_N
BI 73
EMPTY 2 74 IN PA_COM_DSR1_N 24 DSR1* SLCTIN* 47 PA_LPT_SLCTIN_N
OUT 73
603
1
74 OUT PA_COM_RTS1_N 26 RTS1*
"Y5V" PA_COM_CTS1_N 28 44 TP_PA_LPT_PD0
74 IN CTS1* PD<0>
30 43
SERIAL
PA_COM_DTR1_N TP_PA_LPT_PD1
PARALLEL
74 OUT DTR1* PD<1>
74 IN PA_COM_RI1_N 32 RI1* PD<2> 42 TP_PA_LPT_PD2
74 IN PA_COM_DCD1_N 23 DCD1* PD<3> 41 TP_PA_LPT_PD3
PD<4> 40 TP_PA_LPT_PD4
PD<5> 39 TP_PA_LPT_PD5
CLOCK
28 IN CK_14M_PA 65 CLOCKI14 PD<6> 38 TP_PA_LPT_PD6
33 IN SUSCLK 91 CLOCKI32/GPIO16 PD<7> 37 TP_PA_LPT_PD7
B 110 VSS<7> SLCT 33 PA_LPT_SLCT

IN 73 B
96 VSS<6> PE 34 PA_LPT_PE
IN 73
78 VSS<5> BUSY 35 PA_LPT_BUSY
IN 73
58 VSS<4> ACK* 36 PA_LPT_ACK_N
IN 73
46 VSS<3> ERROR* 45 PA_LPT_ERR_N
IN 73
29 VSS<2> ALF* 50 PA_LPT_ALF_N
OUT 73
8 VSS<1> STROBE* 51 PA_LPT_STROBE_N
OUT 73
73 IN CIR_RX 119 RXD2

73 IN CIR_BLTX2_SENSE 120 TXD2
73 IN CIR_BLTX1_SENSE 121 DSR2*
TP_PA_COM_RTS2_N 122 SERIAL 2 128 CIR_BLTX1_TIP
RTS2* IRTX2
OUT 73
73 OUT CIR_FP_LED 124 CTS2* IRRX2 127 TP_PA_SIR_RX
TP_PA_COM_DTR2_N 125 DTR2*
73 OUT CIR_BLTX2_TIP 118 RI2*
73 IN CIR_LEARN_IN 126 DCD2*
1 OF 2
NC=129
IC
DECOUPLING
A VCC3 A
53 59 64 69 70 82 84
V_3P3_STBY\G 9 21 22 28 32 33 34
IN 36 37 38 39 47 48 49 89 90
85 86 87 88 90 92 101 102 103 105 73 74
V_5P0_STBY\G IN 37 51
66 70
80 88
91 92
1 1 1 1 1 1 1 1 C13LH
C8LH C1LH C9LH C6LH C10LH C12LH C11LH 470UF 1
.1UF .1UF .1UF .1UF .1UF .1UF .1UF 20% C17LH
20% 20% 20% 20% 20% 20% 20% 10V .1UF
25V 25V 25V 25V 25V 25V 25V ALUM 20%
2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 RDL 2 25V
603 603 603 603 603 603 603 Y5V
603
CAD NOTE:
CAD NOTE: [PAGE_TITLE=PORT ANGELES 1 OF 2]
PLACE 0.1UF CAPS
NEAR DEVICE PINS - 6,31,49,60,76,93,107 PLACE NEAR PIN 71 BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
INTEL
xxxxxx 69 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

SIO_CIR_ICH9 1.01.00 01.22.07
NOTE: DEFAULT TYPE IS LISTED FIRST
SEE PORT ANGELES SPEC P. 16 FOR TYPE DESCRIPTION
PIN FUNCTION TYPE
1 TEST_EN 3IPD
D
2 AUD_LINK_RST* 5I D
3 CDC_DWN_ENAB/GPIO12* 5I/O12
70 PRIMARY_HD* 3ISPU_400
71 SECONDARY_HD* 3ISPU_400
72 SCSI* 3ISPU_400
VCC3 75 FPRST* 3ISPU_400
80 PWRGD_PS 3ISPU_400
103 102 101 92 90 88 87 86 85 81 CPU_PRESENT* 3ISPU_400

39 38 37 36 34 33 32 28 22 21 9 IN V_3P3_STBY\G 105 103 102 101 92
V_3P3_STBY\G
84 82 70 69 64 59 53 49 48 47 49 48 47 39 38 37 36 34 33 32 28 22 21 9 IN 83 SLP_S3* 3IS_400
105 1 1 1 1 90 88 87 86 85 84 82 70 69 64 59 53
R22LH R23LH R13LH R21LH 84 SLP_S5* 3IS_400
1
2.7K 2.7K 8.2K 8.2K R20LH 87 SMB_CLK_M 3IOD6
5% 5% 5% 5%
CH CH CH CH 1K 88 SMB_CLK_R 3IOD6
402 402 402 402 5%
89 SMB_DAT_M 3IOD6
2 2 2 2 CH
SMB_CLK_MAIN 402 90 SMB_DAT_R 3IOD6
97 28 27 BI U1LH 2
124 5V_DDCSDA/GPIO8 5IOD6/3IO8
PORT ANGELES 3.0
C 49 48 47 33 28 27 22 21 BI SMB_CLK_RESUME 87 71 V_5P0_STBY\G 125 5V_DDCSCL/GPIO9 5IOD6/3IO8 C
105 103 102 101 SMB_CLK_MAIN V_5P0_STBY IN 37 51 66 69 73 74 80 88 89 90
88 72 V_REF5V_SUS_SIO 91 92 37
POWER
SMB_DATA_MAIN 89
SMB_CLK_RESUME REF_5V_STBY
70 V_REF5V_SIO
OUT 126 3V_DDCSDA/GPIO10 3IOD6/3IO8
97 28 27 BI SMB_DAT_MAIN REF_5V
OUT 37
90 127 3V_DDCSCL/GPIO11 3IOD6/3IO8
49 48 47 33 28 27 22 21 BI SMB_DATA_RESUME SMB_DAT_RESUME
84 PWRGD_3V
105 103 102 101 PWRGD_3V
OUT 13 33 53
VGA_SIO_DDCSDA_5V 116 82 PWRGD_PS
VGA DDC VT
20 BI 5V_DDCSDA/GPIO8 PWRGD_PS
IN 90
20 BI VGA_SIO_DDCSCL_5V 114 5V_DDCSCL/GPIO9 R19LH 2
20 VGA_MCHSIO_DDCSDA 115 73 PLTRST_PCIE_SLOTS_R_N 1 PLTRST_PCIE_SLOTS_N 21 22 47 101 102
BI VGA_MCHSIO_DDCSCL 113
3V_DDCSDA/GPIO10 PCIRST_OUT*
74 TP_PCIRST_OUT2_R_N
OUT
20 BI 3V_DDCSCL/GPIO11 PCIRST_OUT2* 0 5%
IDE_RSTDRV* 64 TP_IDE_RST_N 402 CH 1
GPIO_GRN_BLNK_HDR 94 92 ICH_RSMRST_N C16LH
51 OUT GRN_LED RSMRST* OUT 33 39 100PF
51 OUT GPIO_YLW_BLNK_HDR 95 YLW_LED 5%
HD_LED_N 66 77 50V
51 OUT BACKFEED_CUT
OUT 75 80 82 2
PWR SEQ
HD_LED* BACKFEED_CUT* COG
LED
107 99 IN IDE_PRI_ACT_N 67 HDD_ACT_1* LATCHED_BF_CUT 79 LATCHED_BACKFEED_CUT
OUT 89 85 89 90 402
36 32 IN ICH_SATA_LED_N 68 HDD_ACT_2* SCK_BJT_GATE 80 TP_SCK_BJT_GATE
70 IN SCSI_ACT_N 69 HDD_ACT_3* PS_ON* 81 PS_ON_SIO_N
OUT 90
FP_RST_N 75 83 H_SKTOCC_R_N 1 R64LH 2 H_SKTOCC_N
97 51 36 33 7 IN FPRST*/GPIO14 CPU_PRESENT* IN 6 33
1 0 5%
33 IN SLP_S3_N 85 SLP_S3* GPIO12 100 TP_SIO_PIN_100 402 CH
33 IN S4_STATE_N 86 SLP_S4*/S5* GPIO13 101 TP_SIO_PIN_101 R65LH
GPO11 117 TP_SIO_PIN_117 10K
98 5%
TP_PA_TESTEN_1 VBAT
R72LH EMPTY
B 402 B
8.2K 2
PA_F_CAP 97 5%
F_CAP/GPIO15
2 OF 2 CH
402
NC=129 IC
1 C14LH C15LH
1
CAD NOTE:
4.7UF .1UF
20% 10%
2 16V 16V
2 PLACE AS CLOSE TO
Y5V X7R
1206 603 PIN AS POSSIBLE
A A
SCSI ACTIVITY HEADER
J2LH
1X2HDR
70 OUT SCSI_ACT_N 1 2 TP_SCSI_ACT_PIN2
EMPTY
[PAGE_TITLE=PORT ANGELES 2 OF 2]
INTEL
xxxxxx 70 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

SIO_CIR_ICH9 1.01.00 01.22.07
D
VCC D
CAD NOTE:
1 1
PLACE NEAR FDD CONN
R25LH R27LH
1K 1K
5% 5%
CH CH
402 402
2 2
1 1 1
R24LH R26LH R28LH
1K 1K 1K
5% 5% 5%
CH CH CH
402 402 402 J4LH
2 2 2
2X17HDR_3_5
C 1 P1
C
69 IN PA_FDD_DRVDEN0 2 P2
KEY
TP_301S 4 P4
KEY
69 IN PA_FDD_DRVDEN1 6 P6
7 P7
69 OUT PA_FDD_INDEX_N 8 P8
9 P9
69 IN PA_FDD_MTR0_N 10 P10
11 P11
TP_302S 12 P12
13 P13
69 IN PA_FDD_DS0_N 14 P14
15 P15
TP_303S 16 P16
17 P17
69 IN PA_FDD_DIR_N 18 P18
19 P19
69 IN PA_FDD_STEP_N 20 P20
21 P21
69 IN PA_FDD_WDATA_N 22 P22
B 23 P23 B
69 IN PA_FDD_WGATE_N 24 P24
25 P25
69 OUT PA_FDD_TRK0_N 26 P26
27 P27
69 OUT PA_FDD_WRTPRT_N 28 P28
29 P29
69 OUT PA_FDD_RDATA_N 30 P30
31 P31
69 IN PA_FDD_HDSEL_N 32 P32
33 P33
69 OUT PA_FDD_DSKCHG_N 34 P34
HDR
A A
[PAGE_TITLE=FDD CONN]
INTEL
xxxxxx 71 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

SIO_CIR_ICH9 1.01.00 01.22.07
D
D
91 IN VREG_PS2
1 1 1 1 1
R30LH R32LH R36LH R29LH C19LH
2.2K 2.2K 2.2K 2.2K 1UF
20%
5% 5% 5% 5%
2 6.3V
CH CH CH CH X5R J9LH
402 402 402 402 603 A92011-001
2 2 2 2 PS2 STACK
69 PA_KBDATA 1 R33LH 2 SIO_KBDATA_FB 1 P1
BI
0 5% TP_401S 2 P2
402 CH 3 P3 KEYBOARD
4
69 PA_KBCLOCK 1 R31LH 2 SIO_KBCLOCK_FB 5
P4
P5
BI TP_402S
0 5% 6 P6
1
402 CH
C53LH C52LH P13 13
470PF 470PF P14 14
C 10% 10% C
50V 50V P15 15
X7R X7R P16 16
402 402
2
P17 17
69 PA_MSDATA 1 R34LH 2 SIO_MSDATA_FB 7 P7

BI TP_403S
0 5% 8 P8
402 CH 9 P9
10
69 PA_MSCLOCK 1 R35LH 2 SIO_MSCLOCK_FB 11
P10
P11 MOUSE
BI TP_404S
0 5% 12 P12
1
402 CH
C55LH C54LH
470PF 470PF CONN
10% 10% 1
50V 50V C20LH
X7R X7R 470PF
402 402 10%
2
DESIGN NOTE: 2 50V 1

X7R C21LH
402 470PF 1
STUFF CAPS IF SEEING 10%
50V
C23LH
NOISE PROBLEMS ON PS2 2 470PF
X7R 10%
402 50V 1
2 X7R C18LH
402 470PF 1
B 10%
50V
C22LH B
CAD NOTE: 1 3 4 6 CRP1LH 2 X7R
470PF
10%
TVS6_2V 402 50V
2 X7R
PLACE NEAR 6.2V 402
PS/2 CONN 2 5 EMPTY
CAD NOTE:
PLACE AS CLOSE TO PS/2

CONNECTOR AS POSSIBLE
A A
[PAGE_TITLE=PS/2 CONNECTOR]
INTEL
xxxxxx 72 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

LPT PULLUPS BOM NOTE:
STUFF FOR CONSUMER IR SUPPORT 1.01.00 01.22.07
STUFF ONLY WITH WINBOND -376I DEVICE SIO_CIR_ICH9
VCC FRONT PANEL RECEIVERS

VCC VCC3
D 2 2 2 2 R98LH
J10LH R85LH 1 2 D
R37LH R48LH R43LH R40LH 2X4HDR_7 CIR_FP_LED_R 1 2 CIR_FP_LED
IN 69
2.7K 2.7K 2.7K 2.7K 22K 5%
5% 5% 5% 5% 1 2 0 5%
402 EMPTY
402 EMPTY
CH CH CH CH 3 4 CIR_LEARN_IN
OUT 69
89 88 80
402 402 402 402 66 51 37 IN V_5P0_STBY\G 5 6
1 1 1 1 74 70 69 8 CIR_RX 69
92 91 90 IN
PA_LPT_STROBE_N EMPTY
69 IN
IPN: A91836-074
69 PA_LPT_ALF_N BACK PANEL BLASTERS

IN
VCC3
69 PA_LPT_INIT_N
IN R66LH
1 2 CIR_BLTX1_SENSE
OUT 69 73 J11LH
10K 5% 2X3HDR_4
603 EMPTY
73 OUT CIR_BLTX1_TIP_DRIVE 1 2 CIR_BLTX2_TIP_DRIVE
OUT 73
C 69 IN PA_LPT_SLCTIN_N R67LH 3 C
1 2 CIR_BLTX2_SENSE
OUT 69 73
73 69 OUT CIR_BLTX1_SENSE 5 6 CIR_BLTX2_SENSE
OUT 69 73
VCC 10K 5%
603 EMPTY
EMPTY
2 2 2 2 2
R52LH R51LH R50LH R39LH R47LH
10K 10K 10K 10K 10K
5% 5% 5% 5% 5%
CH CH CH CH CH VCC
402 402 402 402 402
1 1 1 1 1
69 OUT PA_LPT_ACK_N
69 OUT PA_LPT_BUSY
69 PA_LPT_PE VCC3 BOM NOTE:
OUT 1 R88LH 1 R89LH 1 R90LH
69 OUT PA_LPT_SLCT 324
1%
324
1%
324
1% MOD R88LH, R89LH, R90LH,
69 OUT PA_LPT_ERR_N 1 R97LH 2 EMPTY 2 EMPTY 2 EMPTY
TO A93551-036 (300 OHM,1/10W,5%)
1K 603 603 603
5%
2 EMPTY CIR_BLTX1_TIP_DRIVE
OUT 73
B 402 SIO_CIR B
3
R96LH
69 CIR_BLTX1_TIP 1 2 1 Q1LH
IN MMBT3904
1K 5% CIR_BLTX1_TIP_BASE EMPTY
402 EMPTY 2
VCC
BOM NOTE:
MOD R93LH, R94LH, R95LH,
VCC3 TO A93551-036 (300 OHM,1/10W,5%)
1 R93LH 1 R94LH 1 R95LH
324 324 324
1% 1% 1%
1 R92LH 2 EMPTY 2 EMPTY 2 EMPTY
1K 603 603 603
5%
2 EMPTY CIR_BLTX2_TIP_DRIVE 73
402 SIO_CIR OUT
A 3
A
R91LH
69 CIR_BLTX2_TIP 1 2 1 Q2LH
IN MMBT3904
CIR_BLTX2_TIP_BASE
1K 5% EMPTY
402 EMPTY 2
[PAGE_TITLE=LPT SIGNALS]
INTEL
xxxxxx 73 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BOM NOTE:
SIO_CIR_ICH9 1.01.00 01.22.07
DO NOT USE NATIONAL OR
GOLDSTAR PARTS OF THIS BASE PN
U2LH
D 92 91 90 GD75232S SERIAL PORT A
88 80 74
V_5P0_STBY\G 20 VCC J7LH D
66 51 37 IN
73 70 69 SERIAL PORT
89 PA_COM_DCD1_N 19 2
69 OUT RY1 RA1 2X5HDR_10
69 OUT PA_COM_DSR1_N 18 RY2 RA2 3 SIO_COM_DCD1_232 1
69 OUT PA_COM_RXD1 17 RY3 RA3 4 SIO_COM_RXD1_232_N 2
P1
69 OUT PA_COM_CTS1_N 14 RY4 RA4 7 SIO_COM_TXD1_232_N 3
P2
69 OUT PA_COM_RI1_N 12 RY5 RA5 9 SIO_COM_DTR1_232 4
P3
69 IN PA_COM_RTS1_N 16 DA1 DY1 5
5
P4
69 IN PA_COM_TXD1 15 DA2 DY2 6 SIO_COM_DSR1_232 6
P5
69 IN PA_COM_DTR1_N 13 DA3 DY3 8 SIO_COM_RTS1_232 7
P6
1 VDD+ VDD- 10 P7
SIO_COM_CTS1_232 8 P8
SIO_COM_RI1_232 9
GND 11 1 1 1 1 1 1 1 1
P9
C41LH C42LH C43LH C46LH C48LH C44LH C45LH C47LH KEY
NOTE DIRECTION 470PF 470PF 470PF 470PF 470PF 470PF 470PF 470PF
10% 10% 10% 10% 10% 10% 10% 10% HDR
IC 2 50V 2 50V 2 50V 2 50V 2 50V 2 50V 2 50V 2 50V
X7R X7R X7R X7R X7R X7R X7R X7R
402 402 402 402 402 402 402 402
+12V DESIGN NOTE:
-12V
CAD NOTE:
TAIWANESE TYPE HEADER
C C
+12V -12V 73 70 69 66 51
92
37 V_5P0_STBY\G PLACE NEAR CONNECTOR
91 90 89 88 80 74
IN
1 C50LH
1 C51LH
1 C49LH
.1UF .1UF .1UF
20% 20% 20%
25V 25V 25V
2 Y5V 2 Y5V 2 Y5V
603 603 603
202341-017 202341-017 202341-017
CAD NOTE:
PLACE DECOUPLING NEAR IC PINS

1, 10, AND 20 RESPECTIVELY
B B
A A
[PAGE_TITLE=SERIAL PORT A]
INTEL
xxxxxx 74 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

SUPER_IO 1.08.01 2.10.06
D
D
C C
PASSIVE BLEED CIRCUIT

VCC
RP1LH 1 RP1LH 2 RP1LH 3 RP1LH 4

22 22 22 22
5% 5% 5% 5%
.5W .5W .5W .5W
EMPTY EMPTY EMPTY EMPTY
SM 8 SM 7 SM 6 SM 5
PASSIVE_BLEED_PATH
B 3 B
Q3LH
BACKFEED_CUT EMPTY
82 80 70 1
90 89 85
IN
2
A A
[PAGE_TITLE=STUDIES PURPOSE]
INTEL
xxxxxx 75 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

SST SENSORS MODULE
SST
NAME REV
1.3.0
DATE
41.3.06
DESIGN NOTE:
CPU/CPU VREG TEMP SENSOR.
VCC3
D
D
2
C5TH 1
VCC3
25V 20% .1UF
CAD NOTE: EMPTY 603 1 R7TH
1K
U2TH 5%
PLACE CAP NEAR 2
ADT7484 EMPTY
SST SENSOR PINS. 402
1 VCC SST 8 SST_CTL BI 32 76
R8TH
2 GND ADD0 7 SST_ADD0 2 1
1K 5%
NW_ZONE_TDP 3 D+ RSVD 6 TP_SST_PIN6 402 EMPTY
VCC3
NW_ZONE_TDM 4 D- ADD 5 SST_ADD1
1
C13TH REV=1 EMPTY 1 R9TH
100.0PF
5% CAD NOTE: 1K
3 50V 5%
2 EMPTY 2
1 Q10TH 603 PLACE TEMP ONLY SST
EMPTY
MMBT3904 402
EMPTY SENSOR NEAR CPU VREG. R10TH
2 2 1
C C
1K 5%
402 EMPTY
DESIGN NOTE:
VOLTAGE/SYSTEM AMBIENT/MEM TEMP SENSOR.
VCC3
C6TH
2 1
25V 20% .1UF VCC3

Y5V 603
B R52TH B
105 BI H_TEMP_SRC_DP_HEC1 2 U3TH
0 5% 1 R11TH
402 EMPTY ADT7485 1K
CAD NOTE: 5%
REV=1
1 VCC SST 10 SST_CTL 2 EMPTY
BI 32 76 402
PLACE CAP NEAR
R50TH 2 GND 9 SST_ADD
H_TEMP_SRC_DP 1 2 SST SENSOR PINS. ADD
6 BI
0 5% H_TEMP_SRC_DP_R 3 DP 2P5V 8 V_1P25_CORE 13 14 16 17 18 21 34
402 CH 1 IN 38 82 83 86 98 105
C1TH R12TH
100.0PF H_TEMP_RET_DN_R 4 DM VCCP 7 2
5% 1K
50V +12V 5 6 VCC 5%
R51TH 2 COG 12V 5V
1 EMPTY
1 2 603
6 BI H_TEMP_RET_DN 1 OF 1 402
0 5% IC
402 CH
CAD NOTE: 95 94 6 IN VCCP
105 96
R53TH PLACE TEMP/VOLTAGE COMBO

105 BI H_TEMP_RET_DN_HEC 1 2 SST SENSOR NEAR DIMMS.
0 5% CAD NOTE:
402 EMPTY
A PLACE TRANSISTOR SOUTH OF ICH A
AND WEST OF MCH.
[PAGE_TITLE=SST SENSOR]
INTEL
xxxxxx 76 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

FAN CONFIGURATION CAD NOTE:
MODULE
SST
NAME REV
1.3.0
DATE
41.3.06
CPU FAN:
BTX/ATX: PLACE BELOW/RIGHT OF CPU SOCKET
+12V +12V
D J3TH
1X4HDR D
VCC3 1
CPU_FAN_DRIVER 1
VCC3 2
BOM NOTE: R18TH
BOM NOTE: 1 3 3.3K
STUFF FOR 3-PIN FAN 1 4
1 R37TH C7TH 5%
EMPTY FOR 3-PIN FAN 1 EMPTY FOR 4-PIN FAN R14TH .1UF
STUFF FOR 4-PIN FAN 2.2K 0 20% CH
IF PWM BUFFER IS NOT 5% R17TH
1A 25V HDR 402
2 2 EMPTY 2
5.25V TOLERANT CH 2.2K CH 603 R309BU
402 805 1 R13TH 2 CPU_FAN_TACH
3 5%
2
CPU_TACH_OUT CPU_FAN_TACH_R 1 2 OUT 32
CPU_FAN_CTRL_GATE 1 Q9TH EMPTY C80741-001 15K 5% 0 5%
MMBT3904 402 3 402 CH 1 402 CH
XSTR 2 Q2TH 1
R36TH 2 1 2 EMPTY R15TH C10TH
CPU_FAN_CTRL_EMIT R16TH 1
CPU_FAN_DRIVER_GATE
6.2K .01UF
0 5% 5% 220 2 BOM NOTE: 5% 20% R310BU CPU_FAN_TACH_HEC
402 CH EMPTY 402 CH 2 50V 1 2 OUT 105
STUFF FOR 4-PIN FAN EMPTY
EMPTY FOR 3-PIN FAN 402 603 0 5%
2 402 EMPTY
R34TH
105 32 IN CPU_FAN_CTRL 1 2 CPU_FAN_CTRL_OUT
0 5%
1
402 EMPTY
C14TH
C 47PF C
BOM NOTE: 5% BOM NOTE:
105
50V
DEFENSIVE DESIGN EMPTY EMPTY FOR 3-PIN FAN CAD NOTE:
OPTION FOR 4PIN EMPTY FOR 4-PIN FAN
2
402
FAN CIRCUIT. IF PWM BUFFER IS NOT
FRONT/REAR CHASSIS FAN:
104
5.25V TOLERANT
R306BU
IN REAR_FAN_CTRL_HEC 1 2 BTX: PLACE ABOVE/RIGHT OF CPU SOCKET
0 5%
EMPTY
ATX: PLACE NEAR BACKPANEL
402 BOM NOTE: VCC3
STUFF R40TH, EMPTY R41TH FOR SHARED CTRL
IN STUFF R41TH,
R41TH
EMPTY R40TH FOR INDEPENDANT CTRL
REAR_FAN_CTRL 1 2
0 5% R24TH +12V
FNT_REAR_FAN_CTRL R307BU 402 EMPTY 2.2K
105 32 IN 1 2 5% +12V
0
402
5%
CH
CH
402
J4TH 1
R40TH 1X4HDR
FNT_REAR_FAN_CTRL_R 1 R31TH 2
REAR_FAN_TACH_DRIVER 1 R23TH
0 5% 0 5% 3 1
2 3.3K
402 CH 402 CH Q3TH 3 5%
R20TH 1
FET R21TH 4 CH
C9TH
105
1 2 REAR_FAN_PWM_R 1 0 .1UF 402

VCC3 2 1A 20% 2
FNT_REAR_FAN_CTRL_HEC
R308BU
5% 0
25V HDR R311BU
B CH 402 C80741-001 EMPTY 2 Y5V
1 R19TH 2 REAR_FAN_TACH_R 1 2 REAR_FAN_TACH B
IN 1 2 805 603
REAR_TACH_OUT
OUT 32
2 15K 5% 0 5%
0 5%
1 R33TH 1 402 CH
402 EMPTY 402 CH
2.2K FRONT_REAR_FAN_CTRL_REAR R22TH
1 R32TH 5% 6.2K 1
5%
C8TH R312BU REAR_FAN_TACH_HEC
1K 2 EMPTY .01UF
VCC3 5% 402 CH 20% 1 2 OUT 105
BOM NOTE: 50V
2 EMPTY FNT_REAR_FAN_CTRL_INV 402 2 X7R 0 5%
402 STUFF FOR 4-PIN FAN 2 603 402 EMPTY
BOM NOTE: BOM NOTE: EMPTY FOR 3-PIN FAN
Q6TH
STUFF R42TH FOR R42TH MBT3904DUAL 3 6 EMPTY FOR 4-PIN FAN +12V +12V
INDEPENDANT CTRL 2.2K
5% STUFF FOR 3-PIN
EMPTY FNT_REAR_FAN_CTRL_BASE_1
5 2 J5TH
402 1X4HDR 1
FRONT_FAN_TACH_DRIVER 1 R26TH
BOM NOTE: 4 1 EMPTY 2
3 1 3.3K
EMPTY FOR 3-PIN FAN Q4TH 3 5%
STUFF FOR 4-PIN FAN R43TH FET R29TH 4
1 R27TH 2 1 1 CH
FRONT_FAN_PWM_R
0 C12TH 402
0 5% 5% 0 2 1A .1UF
HDR 2
402 CH CH 402 C80741-001 EMPTY
20%
1 R25TH 2 R313BU
FNT_REAR_FAN_CTRL_HEC_R
2 25V FRONT_TACH_OUT FRONT_FAN_TACH_R 1 2 FRONT_FAN_TACH OUT 32
805 EMPTY
2 603 15K 5% 1
VCC3 0 5%
402 CH R28TH 1 402 CH
6.2K C11TH
A 5% .01UF A
20%
1 R38TH 1 R39TH CH 50V R314BU
1K 2.2K FRONT_REAR_FAN_CTRL_FRONT 402 2 X7R FRONT_FAN_TACH_HEC
5% 5% 2 603 1 2 OUT 105
2 EMPTY 2 EMPTY 0 5%
402 402 FNT_REAR_FAN_CTRL_B_COL_2 402 EMPTY
Q7TH
MBT3904DUAL 3 6
CAD NOTE:
5 2
FNT_REAR_FAN_CTRL_BASE_2 REAR/FRONT CHASSIS FAN:
BTX/ATX: PLACE BELOW/LEFT OF DIMMS
4 1 EMPTY
[PAGE_TITLE=FAN CONFIGURATION]
INTEL
xxxxxx 77 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

DESIGN NOTE: MODULE NAME REV DATE
PB MOUNTING HOLE
J1PB J8PB J9PB
MTG_HOLE MTG_HOLE MTG_HOLE
D NC9 9 NC9 9
NC9 D
EMPTY EMPTY EMPTY
J2PB J7PB J10PB

NC9 9 NC9 9 NC9
EMPTY EMPTY EMPTY
J4PB J6PB J11PB

NC9 CHINA_ROHS
NC9 9 NC9 9 LB25PB
EMPTY LABEL B2_SILK
EMPTY EMPTY LB19PB
LABEL
1
C EMPTY C
1
J3PB J5PB
MTG_HOLE MTG_HOLE EMPTY
NC9 9 NC9 9
VCCI_SILK SILK
EMPTY EMPTY LB17PB LB9PB
LABEL 1
C-TICK
1
EMPTY EMPTY
E210882_LB
LB16PB BSMI_SILK
LABEL LB10PB
LABEL
1
EMPTY
1
EMPTY
DESIGN NOTE:
UL_LABEL
B LABELS LB15PB E2_SILK B
LABEL LB18PB
LABEL
1
EMPTY
1
EMPTY
MIC_CPU
LB13PB E1_SILK
LABEL LB2PB
LABEL
1500X150_TARGET
CAD NOTE:
1
LB6PB EMPTY
1
LABEL DESIGN NOTE:
LB6PB: PLACE KOZ TARGET NEAR CPU AND DIMMS FOR BUILD/WOC NOTES EMPTY
A30094-001 FCCSILK
1
LB12PB
LABEL PB_FREE_2LI
DESIGN NOTE: 200956-001 (NO CONCEPT MODEL): CE MARK SHOULD BE COVERED WITH BLANK WHITE LABEL UNTIL CERTIFIED (MAY NOT BE ON RVP DESIGNS)
LB3PB
LABEL
1
DESIGN NOTE: 628492-001: FCC MARK SHOULD BE COVERED WITH BLANK WHITE LABEL UNTIL CERTIFIED (MAY NOT BE ON RVP DESIGNS)
EMPTY
DESIGN NOTE:
1
622954-001: C-TICK MARK SHOULD BE COVERED WITH BLANK WHITE LABEL UNTIL CERTIFIED (MAY NOT BE ON RVP DESIGNS)
DESIGN NOTE: KOREAN CERT (NO IPN, NO CONCEPT MODEL) SHOULD BE COVERED WITH BLANK WHITE LABEL UNTIL CERTIFIED (NOT ON RVP DESIGNS)
CE_LABEL EMPTY
A LB11PB A
LABEL
1375X250_TARGET
LB5PB DESIGN NOTE:
CANADA
1
LABEL
EMPTY LB21PB
LABEL
A19177-001 LB5PB: ISN BLANK LABEL AND KOZ EMPTY
1
LB7PB
1
LABEL
EMPTY
EMPTY DESIGN NOTE: INTEL_LOGO
LB20PB
1
LABEL
SILK TARGET FOR PRODUCT CODE LABEL [PAGE_TITLE=MTG HOLES/LABELS]
1000X187
1

INTEL
xxxxxx 78 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL_B_ATX 06.12.2 2/8/07
D
CORE VR MODULE D
V_SM POWERED BY 5VDUAL

V_SM_VTT POWERED BY V_SM
V_1P5_ICH POWERED BY V_SM OR VCC3
V_1P25_CORE POWERED BY V_1P5_ICH
V_1P05_ICH_CORE POWERED BY VCC3
V_FSB_VTT POWERED BY VCC3
C
V_1P25_CL_MCH POWERED BY V_SM C
5VDUAL_USB POWERED BY V_5P0_STBY\G AND VCC

5VDUAL POWERED BY V_5P0_STBY\G AND VCC
V_3P3_STBY\G POWERED BY V_5P0_STBY\G
V_3P3_EPW POWERED BY V_3P3_STBY\G
B
VCC V_5P0_STBY\G VCC3 B
5VDUAL_USB 5VDUAL V_3P3_STBY\G
V_SM V_3P3_EPW
V_1P05_ICH_CORE V_FSB_VTT
A A
V_1P25_CL_MCH V_SM_VTT V_1P5_ICH
V_1P25_CORE
INTEL
xxxxxx 79 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
18 14 IN V_SM
L1BV
1UH
MODULE REV DETAILS
24 19 BOM NOTE: CAD NOTE:
R158BV 1 5VDUAL 1 2 BV_5V_DUAL_FILTERED MODULE NAME REV DATE
27 25 IN
81 80 75 STUFF LED CIRCUIT FOR AMT PLACE NEXT
86 82 5% EMPTY FOR NON AMT TO DIMMS IND BL_B_ATX 06.12.2 2/8/07
EMPTY 2 CR7BV 1 C8BV 1 1 1 C26BV 1 1
402 3300UF C281BV C282BV 3300UF C283BV C284BV
BV_SM_PWR_LED_XSTR_SOURCE 2 1 BV_SM_PWR_LED_XSTR_END
20% 10UF 10UF 20% 10UF 10UF
CAD NOTE: 6.3V 10% 10% 6.3V 10% 10%
92 ALUM 10V 10V ALUM 10V 10V
89 88 R176BV
RED 2 RDL 2 EMPTY 2 EMPTY 2 RDL 2 EMPTY 2 EMPTY
EMPTY PLACE CLOSE
D 73 70
V_5P0_STBY\G 1 2 805 805 805 805
51 37 IN BV_SM_PWR_LED_B2
TO FET
69 66 D
80 74 10K 5% MBT3904DUAL 3 6 1
91 90 402 EMPTY C14BV
1UF DESIGN NOTE: DESIGN NOTE:
5 2 10%
25V
BV_SM_PWR_LED_B1
DUAL SITE THE MLCC'S WITH DUAL SITE THE MLCC'S WITH
X5R 2
603 THE BULK CAPACITOR THE BULK CAPACITOR
Q42BV
90 89 R196BV R147BV
1 2 1 2 EMPTY
75 70 IN BACKFEED_CUT 4 1
85 82 2.2K 5% 1K 5%
402 EMPTY 402 EMPTY
GPIO_VSM_AMT_LED DESIGN NOTE:
36 33 IN
DUAL SITE WITH L2BV
V_SM 82
25
14
86
27
18
92 91 90
OUT 19 24
V_5P0_STBY\G
70 69 66 51 37 IN +12V 3 Q47BV 80 81
89 88 80 74 73
R258BV D L3BV
1 2 DESIGN NOTE: 1.25UH
1 R255BV BV_DRV_12V_OPTION
1 2
0 0 1A CR2BV
+12V 5% 603 CH 1 SEPARATE DIODE PACKS USED
1 R213BV 2
2 TO MINIMIZE VOLTAGE DROP BV_UGATE2_R 1 FET EMPTY
2 EMPTY G S
D37424-001
402 IN S3 FROM 5VDUAL 4.7 5%
1 R183BV 3 2
BV_DRV_5VDUAL
805 CH
R254BV 0 Q3BV DESIGN NOTE:
1 2 5% BAT54C 3 D
C 2 EMPTY SOT23_C
BV_DRV_BOOT_VSM V_SM ROD INDUCTOR: CAD NOTE: C
0 5% 402 DIO 86 C56005-002
1 2 402 CH OUT ONE NEAR OUTPUT
1 R26BV 2 ONE NORTH OF DIMMS
CR3BV
BV_DRV_HDRV_VSM BV_UGATE_R
1 G S
FET
D37424-001 L2BV DUAL SITE ONE NORTH
4.7 5%
BAT54C
805 CH 2 1UH OF DIMMS WITH C198BV
3 1
C21BV
2 BV_PHASE_NODE_VSM 1 2
SOT23_C
DIO IND
.1UF 10% 1 C12BV
M245BV 16V 1 C5BV
X7R 1 R13BV 3300UF
BV_DRV_VCC
1 20% 3300UF
2 1 603 0 20%
MULTI U1BV
1A 1 R14BV 3 Q4BV 3 Q2BV R17BV 2
6.3V
ALUM 6.3V
2 CH 20K RDL 2 ALUM
2.2
EMPTY 603 SC2608A 603 1% D D 5%
RDL
BV_DRV_PH_VSM 2 EMPTY
CH
402
1 BST PHASE 8 805 CAD NOTE:
1 2 7 2
DH COMP/SS 1 R18BV 2 1
R27BV
3 GND SENSE 6
BV_LGATE_R
1 G S G S BV_PHASE_NODE_S_RC DUAL FOOTPRINT
4 5 2.2 5%
0 DL VCC D37424-001 2 2 FET 1
5%
603 CH FET C10BV
D37424-001 4700PF
CH IC 20%
2
402
BV_DRV_LDRV_VSM 1 R16BV 2 BV_LGATE2_R 2
50V 1 1 C24BV
X7R C292BV C11BV 1 C23BV
B BV_DRV_VCC_VSM 2.2 5% 603 10UF 10.0UF 4.7UF B
603 CH 20% 20% 20% .1UF
6.3V 6.3V 10V 20%
2 2 25V
1
X5R
805
EMPTY
1206
EMPTY
805
2 EMPTY
C9BV BV_OPS_VSM 603
1.0UF
CAD NOTE: 10% V_5P0_STBY\G
16V IN 37 51 66 69 70 73 74 80 88 89 CAD NOTE:
PLACE NEAR X5R 2 90 91 92
CONTROLLER VCC 805 PLACE NEAR DRAIN AND CAD NOTE:
1 R25BV 1 1 R173BV SOURCE OF LS FET
1K C19BV 5.6K BOM NOTE:
5% 100.0PF 5% PLACE NEAR OUTPUT INDUCTOR
5% STUFF FOR AMT
2 CH 50V 2 EMPTY
CAD NOTE: BV_V_SM_DRV_COMP_R 603 2 COG 402 EMPTY FOR NON AMT
603
BV_V_5P0_STBY_B1
PLACE NEAR
CONTROLLER 1 MBT3904DUAL 3 6
C17BV
M239BV
.068UF C197BV 1 C198BV 1 C199BV 1 C200BV
10% 5 2 BV_SLP_S4_B1 1 R19BV 2 SLP_S4_N 1 470UF 470UF 470UF 470UF
2 1 16V IN 33 20% 20% 20% 20%
MULTI 2 X7R
603 Q5BV
10K 5% 10V 10V 10V 10V
1 R204BV 1 402 EMPTY 2 ALUM

2 EMPTY
2 EMPTY
2 ALUM
EMPTY 603 EMPTY C242BV RDL RDL RDL RDL
47.5K 1 R211BV 2
4 1 1.0UF
1% 20%
10V
2 CH 0 5% 2 EMPTY
402 BV_V_SM_DRV_C2R 402 EMPTY 603
DESIGN NOTE:
A 1 R212BV A
0 OVERLAPPING PADS 1 C201BV 1 C202BV
BOM NOTE: R501BV 5% 470UF
20%
470UF
20%
2 CH BV_V_SM_DRV_FB 1 R23BV 2 BV_V_SM_RC 1 R172BV 2 10V 10V
R500BV -A93548-267, 6.49K(P SKU ONLY) R500BV 1 20K 402 EMPTY EMPTY
0 825 1% 0OHM 2 RDL 2 RDL
1% 402 CH SM
5% EMPTY 1
GPIO0 GPIO5 V_SM EMPTY 2 402
402 C16BV 2 CAD NOTE:
R21BV 1 R22BV 2 1
1 0 1.85V BV_V_SM_DRV_FB_R1 649 BV_V_SM_RC_FB
SENSE ON DIMM PIN 51 OR
CAD NOTE:
1% 0 1A
MBT3904DUAL 3 6 .1UF 10% AS FAR NORTH OF DIMM
CH 603 EMPTY 16V PLACE V_SM DECOUPLING NEAR DIMMS
FIELD AS POSSIBLE
0 1 1.9V 5 2
SIO_GPIO0_103_R 1 R503BV 2
SIO_GPIO0_103
2
402 EMPTY
603
IN 69 DESIGN NOTE:
1.0K 0.1%
Q10BV 402 EMPTY
USE FOR ADDITIONAL COMPENSATION
R502BV 4 1 EMPTY
69 IN SIO_GPIO5_109 1 2
1.0K 0.1% SIO_GPIO5_109_R
402 EMPTY frostburg_fabc.sch_1.80
INTEL
xxxxxx 80 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL_B_ATX 06.12.2 2/8/07
D
D
86 82 81 80 27 25 24 19 18 14 IN V_SM
1 1 C134BV
C140BV
.1UF 470UF
86 82 10% 20%
27 25 10V 10V
18 14 IN V_SM 2 X5R ALUM
24 19 1 402 2 RDL
81 80
R135BV
1K
1%
CH
402
2 EU6BV
RT9199
BV_V_MEM_VTT_REF_PIN3 3 REFEN VIN 1
5 NC VOUT 4
V_SM_VTT 26
C CAD NOTE: OUT C
BV_V_VCNTL_N 6 VCNTL 27
MAXIMIZE GROUND SHAPE 7 NC 1
AND VIAS 8 NC GND 2 1
1 FOR THERMAL RELIEF R136BV C137BV 1 C143BV 1 C142BV 1 C133BV 1 C144BV
1K .1UF 470UF 470UF 470UF 1000UF
R134BV 2 C139BV 1 IC 1% 10% 20% 20% 20% 20%
1K 10V 10V 10V 10V 6.3V
1% .1UF EMPTY 2 X5R ALUM
2 RDL 2 ALUM EMPTY
2 RDL EMPTY
2 TH
10% 1 1 1 603 402 RDL
CH 10V C135BV C141BV C136BV 2
402 1 X5R 10UF .1UF .1UF 1 1
2 402 20%
6.3V
10%
10V
10%
10V
C227BV C228BV
2 2 2 4.7UF 4.7UF
EMPTY X5R EMPTY CAD NOTE: 10% 20%
805 402 402 CAD NOTE: 10V 10V
KEEP CLOSE TO OUTPUT 2 EMPTY 2 Y5V
1206 805
DUAL SITE
R162BV
PUT NEAR OUTPUT
88 OF REGULATOR
80 5VDUAL 1 2
86
IN
0 1A CAD NOTE:
603 EMPTY
VCC PLACE 4.7UF CAPS FOR CH B

AT LEFT AND RIGHT ENDS
R163BV 1 1
B 1 2 C229BV
4.7UF
C230BV
4.7UF
OF VTT ISLANDS B
0 1A 10% 20%
CH 10V 10V
603 2 X5R 2 EMPTY BOM NOTE:
1206 805
BOM NOTE:
CHANGE THE C228BV TO 644066-033
FOR AMT: STUFF R162BV, EMPTY R163BV CAD NOTE:
FOR NON AMT: STUFF R163BV, EMPTY R162BV
PLACE 4.7UF CAPS FOR CH A
AT LEFT AND RIGHT ENDS
OF VTT ISLANDS
A A
[PAGE_TITLE=VREG_SM_VTT]

INTEL
xxxxxx 81 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL_B_ATX 06.12.2 2/8/07
CAD NOTE:
AT LEAST 300 MDLS OF
V_SM ETCH TO FET Q48BV
D
V_SM D
80 27 25 24 19 18 14 IN
86 81
1
C263BV 1 C264BV
105 103 .1UF 470UF
86 85 84 70 69 64 59 V_3P3_STBY\G +12V 10% 20%
36 34 33 32 28 22 21 9 IN 16V
53 49 48 47 39 38 37 CAD NOTE: 2 X7R
10V
102 101 92 90 88 87
D37424-001
3
Q52BV 603 2 EMPTY
RDL
PLACE CLOSE
D
TO PIN 4
1 1
C256BV
R214BV 1.0UF
1
28.7K 10% FET CAD NOTE:
1% 2 16V G S
X5R PLACE CLOSE TO
CH 805 2
402 4 1P5_ICH FET
2 D71406-001 D Q48BV
U9BV
4 FDB8878
BV_V_1P5_ICH_OPAMP_PLUS 12 CAD NOTE:
+ 1
V+ 14 BV_V_1P5_ICH_OPAMP_OUT
13 G S DUAL SITE
C
V- EMPTY C
1 1 11 LM324D 3
R215BV C252BV IC
1UF -12V
24.3K 20% CAD NOTE:
1%
2 6.3V 2 R216BV 1
CH X5R PLACE CLOSE
603 1K 5%
402 TO PIN 11
2 402 CH
V_1P5_ICH
1
C262BV OUT 9 34 38 92 98
1.0UF
CAD NOTE: 10% 1 C265BV 1 1
16V 1 C286BV 1 C266BV C267BV C268BV
2 EMPTY 1000UF .1UF
PLACE DECOUPLING CAP 1000UF 20% .1UF 10%
805 20% 10UF
AS CLOSE AS POSSIBLE 6.3V 10% 16V
6.3V
2 ALUM 20%
2 16V 2 X7R
TO PIN 12 EMPTY 6.3V X7R
2 TH
TH 2 X5R 603
603
805
CAD NOTE: CAD NOTE:

PLACE CLOSE TO PLACE CLOSE TO
Q53BV FET
B B
1
R217BV 3
22.1K D37424-001 D Q53BV
1%
CAD NOTE:
CH
402 DECOUPLING CAP IS
2
SHARED ON V_1P5_ICH 1
G S
+12V FET
4 2
BV_V_1P25_CORE_DIS_B1
BACKFEED_CUT 3 D71406-001 D Q49BV
1 R226BV 2 1 Q51BV
85 80 75 70 IN MMBT3904
90 89 U9BV
10K 5% XSTR 4 FDB8878
402 CH 2 BV_V_1P25_CORE_OPAMP_PLUS 10
+ 1 CAD NOTE:
V+ 8
9 V- BV_V_1P25_CORE_OPAMP_OUT G S EMPTY DUAL SITE
11 LM324D 3
1 IC
R205BV 1 -12V
13.7K C251BV 2 R206BV 1
A 1% 1UF A
20% 1K 5%
CH
402 2 6.3V
X5R 402 CH V_1P25_CORE 76 83 86 98
OUT 13 14 16 17
2 603 18 21 34 38
105
1 C253BV 1 C254BV
CAD NOTE: 1000UF 1000UF
20% 20%
PLACE DECOUPLING CAP 6.3V 10V
ALUM ALUM
AS CLOSE AS POSSIBLE 2 TH 2 TH
TO PIN 10
[PAGE_TITLE=VREG_1P25_CORE MCH]
INTEL
xxxxxx 82 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

CAD NOTE: BL_B_ATX 06.12.2 2/8/07
98
83 CORE EDGE CAP DECOUPLING
76 PLACE IN PCIE BREAKOUT
34
18
16 V_1P25_CORE
13 IN
D 14
17 D
21 1 1 1 1 1 1 1 1 1
38 C210BV C211BV C212BV C213BV C214BV C215BV C216BV C217BV C218BV
82 10UF 10UF 10UF 10UF 1UF 1UF 1UF 1UF .1UF
86 20% 20% 20% 20% 20% 20% 20% 20% 10%
105 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 16V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X7R
805 805 805 805 603 603 603 603 603
C CAD NOTE: CAD NOTE: C

CORE DECOUPLING CAPS FOR MCH 98
83 DECOUPLING CAPS AT OUTPUT OF REGULATOR
PLACE NEXT TO PWR CORRIDOR 76
34
V_1P25_CORE 18
IN 16 V_1P25_CORE
13 IN
14
1 1 1 1 1 17
C219BV C220BV C221BV C222BV C224BV 21
10UF 10UF 22.000UF 22.000UF 22.000UF 38
20% 20% 82 1 1 C103BV 1 C96BV
6.3V 6.3V 20% 20% 20%
86
C97BV
2 X5R 2 X5R 2 6.3V
2 6.3V
2 6.3V
105
10.0UF 4.7UF .1UF
805 805 EMPTY EMPTY EMPTY 20% 20% 20%
805 805 805 6.3V 10V 25V
2 EMPTY 2 EMPTY 2 EMPTY
805 805 603
B B
DESIGN NOTE:
BACKSIDE CAPS FOR SPECIFIC CORE MCH
98 86 83
18 17 16 14 13 V_1P25_CORE
82 76 38 34 21
IN
105
1 1 1 1 1 1
C255BV C257BV C258BV C259BV C260BV C261BV
10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY
805 805 805 805 805 805
A A
[PAGE_TITLE=MCH DCPL]

INTEL
xxxxxx 83 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL_B_ATX 06.12.2 2/8/07
+12V
D
D
CAD NOTE:
+12V DECOUPLING CAP IS
SHARED ON V_1P5_ICH
U9BV
4
5
+
BV_SC_INPUT_OPAMP5 V+ 7
6 V-
11 LM324D
IC -12V
CAD NOTE:
-12V DECOUPLING CAP IS
C C
SHARED ON V_1P5_ICH
+12V VCC3
CAD NOTE:
+12V DECOUPLING CAP IS
SHARED ON V_1P5_ICH
B 1 B
C85BV 1 C72BV
.1UF 470UF
20% 20%
105 25V 10V
102 2 Y5V 2 ALUM
92 D-PAK 3 603 RDL
87 86
70 69 D Q14BV CAD NOTE:
53 49
39 38 U9BV PLACE CLOSE 1P05_ICH_CORE FET
34 33 V_3P3_STBY\G 1 R65BV 2 BV_V_1P05_ICH_OPAMP5_PLUS 4 C83236-001
22 21 9 3
32 28
IN +
V+ 1 1
1% 29.4K BV_1P05_ICH_GATE_DRIVE
37 36 G S
48 47 CH 402 2 V- FET
64 59 1 11 LM324D -12V 2
85 82
R66BV 1 IC
90 88 C83BV
101 14K 1UF
103 1% 20%
6.3V R67BV 1
CH
402
2 X5R
603 CAD NOTE:
2 V_1P05_ICH_CORE OUT 34
2 1K 5% 1 1 1
-12V DECOUPLING CAP IS 402 CH 1 C67BV C68BV C74BV C75BV
1000UF 4.7UF .047UF .022UF
SHARED ON V_1P5_ICH 20% 20% 10% 10%
6.3V 6.3V 16V 50V
2 ALUM 2 X5R 2 EMPTY 2 X7R
TH 805 603 603
CAD NOTE:
A PLACE DECOUPLING CAP A
AS CLOSE AS POSSIBLE TO
PIN 3

INTEL
xxxxxx 84 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

VCC3
BL_B_ATX 06.12.2 2/8/07
D
CAD NOTE: +12V D
PLACE DECOUPLING CAP
105 AS CLOSE AS POSSIBLE TO 3
102
92 PIN 3 D Q50BV
86 84 82
59 53 49
38 37 36 V_3P3_STBY\G R207BV 8 U2BV C83236-001
28 22 21 9 IN 1 2 BV_2P2_OPAMP_PLUS_12 3
+ LM358
34 33 32 6.49K 1% V 1 BV_2P2_OPAMP_OUT_14 1
48 47 39 1 G S
70 69 64 603 CH
C246BV
2 G
IC FET
90 88 87 1 R208BV 1UF 4 2
101 17.4K 20% R209BV
103 1% 6.3V 1 2
2
2 X5R
CH 603 -12V 1K 5%
402
402 CH BV_2P4_FET_DRAIN_FSB_VTT
1 1 C249BV 1 C250BV
C53BV
4.7UF 470UF 1000UF
R230BV 20% 20% 20%
16V 10V 6.3V
1 2 2 Y5V EMPTY ALUM
2 RDL 2 TH
0 5% VCC3 1206
402 EMPTY
C C
34 VCC
8 7 IN V_FSB_VTT 1 R47BV
17 14 9 17.4K CAD NOTE:
85 38 1%
1 2 CH CAD NOTE: 4 3 DUAL SITE
R186BV
1K 1 R54BV 402 RP4BV RP4BV 2 RP4BV 1 RP4BV
5% 1K PLACE DECOUPLING CAP 0 0 0 0
5% AS CLOSE AS POSSIBLE TO 5% 5% 5% 5%
2 CH
2 1 R53BV 2 .063W .063W .063W .063W
402 CH PIN 5 +12V
BV_FSB_VTT_SEL_B3_TO_R53BV
402 EMPTY EMPTY EMPTY EMPTY

7 VTT_SEL 66.5K 1% 5 SM 6 SM 7 SM 8 SM
IN 402 CH CAD NOTE:
1 R185BV 1 PLACE CLOSE
1K TO PIN 8
5% R45BV 1
10K C48BV 1
2 CH
1% 1UF C247BV
402 BV_FSB_VTT_SEL_B2 20% 1UF
CH 6.3V
MBT3904DUAL 3 6 402 2 X5R
20%
CAD NOTE:
16V
2 603 2 Y5V 3
5 2
805 DUAL SITE
D
Q9BV
BV_FSB_VTT_SEL_B1
C83236-001 4
Q46BV D Q56BV
XSTR
B DESIGN NOTE: 4 1 1 B
G S
STUFF FOR PENRYN CORE
U2BV
FET NTB18N06L
BASED CPUS SUPPORT BV_VTT_CORE_OPAMP_PLUS_3 5
8 2 1
+ LM358
V 7 G S
BV_VTT_CORE_OPAMP_OUT_7 EMPTY
6 G 3 A68810-001
4
IC
R38BV V_FSB_VTT 34 38
-12V 1 2 7 8 9
OUT
BV_V_VTT_CORE_OPAMP_MINUS_6
1K 5% 14 17
85
402 CH
CAD NOTE:
PLACE CLOSE
TO PIN 4
1 1 1 1 1 C269BV 1 1 1
C204BV C205BV C206BV C42BV 1000UF C207BV C208BV C209BV
1 1UF 1UF 1UF 1UF 20% 2.2UF 2.2UF 2.2UF
C248BV 10% 10% 10%
1UF 20% 20% 20% 20% 6.3V
6.3V ALUM 6.3V 6.3V 6.3V
20% 6.3V 6.3V 6.3V 2 X5R 2 TH
2 EMPTY 2 EMPTY 2 X5R
3 16V X5R 2 X5R 2 X5R 2 603 603 603
1 R184BV 2
2 Y5V 603 603 603 603
80 75 70 BACKFEED_CUT 1 Q45BV 805
90 89 82
IN BV_FSB_VTT_DIS_B1
MMBT3904
10K 5% XSTR
402 CH 2
R41BV CAD NOTE: CAD NOTE: CAD NOTE:

A 2 1 A
PLACE NEAR MCH PLACE CAP NEAR PLACE NEAR CPU
0 5%
SOURCE OF FET
402 CH
1 R39BV
499
1%
2 EMPTY
402
[PAGE_TITLE=VREG_FSB VTT & SFR]

INTEL
xxxxxx 85 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

88
5VDUAL 1 R210BV 2 BV_V_1P25_CL_OPAMP_VPLUS MODULE NAME REV DATE
80 IN OUT 86
81 0 5% BL_B_ATX 06.12.2 2/8/07
402 EMPTY
82 81 80 27 25 24 19 18 14 IN
V_SM
CR8BV
D BV_DRV_BOOT_VSM 2 1 1
80 IN C114BV C119BV D
+12V 4.7UF .1UF
3 20% 10%
6.3V 16V
BV_V_1P25_CL_OPAMP_VPLUS 2 EMPTY 2 EMPTY
1 86 805 603
IN
BAT54C 1
SOT23_C C113BV
EMPTY 1UF
10%
25V CAD NOTE: 3
2 EMPTY
603 PLACE CLOSE D Q21BV
TO PIN 8
V_3P3_STBY\G 2 R85BV 1 8 U5BV C83236-001
BV_1P25_CL_CONTROL_INPUT 3 LM358
IN +
V 1 1
24.3K 1% BV_1P25_CL_358_OUT_7
1 G S
402 EMPTY 2 G
EMPTY EMPTY
R87BV 1 4 2
15.4K C112BV
1% 1UF
20%
EMPTY 6.3V
402 2 EMPTY
2 603
C C
CAD NOTE:
PLACE DECOUPLING CAP 2
R92BV 1 V_1P25_CL_MCH 14 16
AS CLOSE AS POSSIBLE TO OUT 19 86
1K 5%
PIN 3
402 EMPTY
1 1 C192BV 1 C116BV 1 1 1
C115BV
C118BV
C226BV C225BV
.1UF 470UF 1000UF 10UF 10UF
89 R154BV 3 10% 20% 20% .1UF 20% 20%
86 2 1 Q41BV 16V 10V 6.3V 10% 6.3V 6.3V
28 IN SLP_M BV_SLP_M_1P25_FET 1 2 EMPTY EMPTY EMPTY 16V 2 X5R 2 X5R
39 MMBT3904
603
2 RDL 2 TH 2 EMPTY 805 805
88 10K 5% EMPTY CAD NOTE: 603
402 EMPTY 1 C241BV 2
1.0UF PLACE 0.1UF CAP NEAR
20% SOURCE PIN OF FET ON
10V DESIGN NOTE:
DESIGN NOTE:
V_1P25_CL_MCH
2 EMPTY
603 DECOUPLING CAPS
DUAL SITE
PLACE NEAR MCH
B B
R93BV R95BV R96BV

86 19 16 14 IN V_1P25_CL_MCH 1 2 1 2 1 2 MCH_CLPWROK OUT 13 39
105 98 3.24K 1% 82.5K 1% 475 1%
82 76 1 C185BV 1 R97BV
21 18
RP3BV 402 EMPTY 402 EMPTY 402 EMPTY 1K
14 13 IN V_1P25_CORE 8 1 V_1P25_CL_MCH OUT 14 16 19
1.0UF
20%
1%
17 16 0 5% .063W 86 10V 2 EMPTY
38 34 SM IC 2 EMPTY 402
83 603
RP3BV
7 2
0 5% .063W 105 BV_V_1P25_CL_OPAMP_VPLUS
SM IC 103 102 101 86 IN
92 90 88 87
RP3BV 86 85 84 82 8 U5BV
6 3 70 69 64 59 BV_PWROK_1P25_OPAMP3 5 LM358
53 49 48 47 +
0 5% .063W R94BV V 7
39 38 37 36
SM IC 28 22 21 9 IN V_3P3_STBY\G 1 2 BV_PWROK_3P3_OPAMP2 6 G BV_MCH_CLPWROK_OPAMP1
RP3BV 34 33 32 4
EMPTY
20K 1% 3
5 4 402 EMPTY R98BV
DESIGN NOTE: 1 R91BV 1 2 Q22BV
0 5% .063W 10K 39 28 IN SLP_M BV_MCH_CLPWROK_XSTR_BASE 1
BOM NOTE: SM IC 89 88 86 MMBT3904
MCH_CLPWROK: DEFAULT THRESHOLD = 1.1V (2.5K SERIES) 1% 1K 5% EMPTY
A 2 EMPTY 402 EMPTY 2 A
STUFF RP3BV, C225BV, C226BV FOR NON AMT SYSTEM BOM NOTE: 402
EMPTY EVERYTHING ELSE ON PAGE FOR NON AMT
USE DEFAULT STUFFING ON PAGE FOR AMT SYSTEM
CHANGE SERIES RESISTOR
TO SET THRESHOLD TO 1.0VOLT
ON NEGATIVE PIN TO 2.7K
CL PWROK GENERATION

INTEL
[PAGE_TITLE=VREG 1.25 MCH CL] frostburg_fabc.sch_1.86
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL_B_ATX 06.12.2 2/8/07
D
D
+12V
8 U11BV
BV_SFR_OPAMP_SC_3_2 3 LM358
+
V 1
2 G
4
IC
-12V
C C
+12V
VCC3
B B
1
C288BV
1.0UF
10%
16V
2 X5R
805
105 103 102 101 92 R238BV BV_SFR_OPAMP_PLUS_5

48 47 39 38 37 36 34 33 32 28 22 21 9 IN V_3P3_STBY\G
90 88 86 85 84 82 70 69 64 59 53 49 28.7K 1% 3 V_SFR_OUT
402 CH 8 U11BV Q57BV
1 R239BV 5
+ LM358 BV_SFR_OPAMPOUT_7 FET
24.3K V 7 1 OUT 9 87
1% 6 G 2
2 CH
4
IC
402 1 1
C289BV C290BV
1.0UF 4.7UF
20% 20%
-12V 2 10V
2 10V
Y5V Y5V
603 805
R242BV
1 2
1K 5%
R240BV BV_SFR_OPAMP_MINUS_6
402 CH
87 9 IN V_SFR_OUT 1 2
A 0 5% A
402 CH 1
1 R241BV C287BV
1.0UF
499 10%
1% 16V
2 EMPTY
2 X5R
805
402
[PAGE_TITLE=CORE VREG]
INTEL
xxxxxx 87 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

3
5V_DUAL D
BL_B_ATX 06.12.2 2/8/07
BOM NOTE:
1
NON AMT STUFF G S Q34BV
D 2 PMOSFET
Q34BV Q35BV C77877-001 D
105 103 102 101 92 90 88 87
V_3P3_EPW
86 85
39
84
38
82
37
70
36 34 33 32
69 64 59 53
28
49
22
48
21
47
9 IN V_3P3_STBY\G
Q36BV IN V_3P3_STBY\G
FDC638P
89 IN VREG_5VDUAL_PCH 3 GATE DRN 1 2

74 DRN 2 Q31BV VCC3
70
DRN 5 1
R137BV 2 S EMPTY
66 SLP_M BOM NOTE:
37 IN V_5P0_STBY\G 4 SOURCE DRN 6 89 86 39 28 IN
51 1K 5% 1 1 STUFF FOR NON-INTEL
69 402 EMPTY
73
80 BOM NOTE:
EMPTY BV_SLP_M_R 1
G D
R140BV
0
R139BV
0
LAN OR M0 ONLY
88
89
90
(DEFAULT) AMT STUFF 1.0 R138BV 2 3 1C233BV 3
D32396-001
1A
CH
1A
EMPTY
91 Q36BV Q35BV 1 1UF 805 805
92 37 33 WOL_ONLY 1 Q30BV 20% 2 2
IN MMBT3904 6.3V
5VDUAL OUT 80 81 86 88
10K
402
5%
EMPTY 2
EMPTY 2 EMPTY
603 V_3P3_EPW
57
38
58
39
BV_WOL_CNTL_BASE
OUT 27 28
33 34
2 40 56
BOM NOTE: 92
BOM NOTE:
D Q35BV STUFF FOR
C CAD NOTE:
STUFF FOR NINEVEH + AMT C
NON AMT
0.1 INCH COPPER ON
89 IN VREG_5VDUAL_NCH 1 DRAIN AND SOURCE
G S
FET
3
VCC
D37438-001
CAD NOTE:
OVERLAPPING SITE BOM NOTE:
U7BV
STUFF FOR 10/100 LAN SKUS
86
5VDUAL LD1117DT
80 IN EMPTY FOR GB LAN SKUS
81
88 1 1 1 1 1 1 1 1 1 2 3
IN OUT
R235BV R143BV 4 RP2BV 3 RP2BV 2 RP2BV 1 RP2BV
R224BV R225BV R234BV R231BV R232BV R233BV R236BV
0 0 0 0 0 GND
0 1A 5% 5% 5% 5% 0 0 0 0 0 0 0
5%
CH .063W .063W .063W .063W
5% 1A 5% 5% 5% 5% 5% 1 EMPTY
B CH 603 IC IC IC IC CH CH CH CH CH CH CH B
402 2 SM SM SM SM 402 603 402 402 402 402 402
2 5 6 7 8 2 2 2 2 2 2 2
R237BV
CH 402
2
1
92
BOM NOTE: 5VDUAL_USB OUT 42 43 44 45 46 52 88 91 92 0 5% 90 U8BV
88 AD1086
STUFF ONLY IF 5V_DUAL USB VR IS EMPTY 74
70 103 105
66 V_5P0_STBY\G 2 3 V_3P3_STBY\G 53 59 64 69 70 82 84
37 IN IN OUT OUT 9 21 22 28 32 33 34
51 36 37 38 39 47 48 49
69 GND 1 C183BV 85 86 87 88 90 92 101 102
3 Q32BV BOM NOTE: 73 1 220UF
D
80 C182BV 1 SM 20.0%
5V_DUAL USB VR NON AMT STUFF R143BV, RP2BV, R224BV, R225BV 89
91
1.0UF
20% 1 R142BV 25V
ELEC
10V 2 274 2 RDL
EMPTY Q32BV, Q33BV Y5V 1%
603
89 IN VREG_USB_PCH 1
S
(DEFAULT) AMT STUFF Q32BV, Q33BV
BV_V_STBY_ADJ
2 EMPTY
402
G EMPTY R143BV, RP2BV, R224BV, R225BV
2 EMPTY 1 1 R141BV BOM NOTE:
C184BV 0
C77877-001 .1UF
70 69
92
66
91
51
90
37 IN V_5P0_STBY\G 20%
25V 2
5%
CH
STUFF FOR LD1117
EMPTY FOR EZ1086
(10/100 LAN SKUS)
(GB LAN SKUS)
89 88 80 74 73 2
EMPTY 402
5VDUAL_USB OUT 42 43 44 45 46 52 88 91 92 603
A Q33BV A
2
CAD NOTE: BOM NOTE:
D
0.1 INCH COPPER ON STUFF 453 OHM (A93548-165) FOR LD1117 (10/100 LAN SKUS)
DRAIN AND SOURCE STUFF O OHM (A93549-001) FOR EZ1086 (GB SKUS)
89 IN VREG_USB_NCH 1
S
G EMPTY
3
VCC
D37438-001
INTEL
xxxxxx 88 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL_B_ATX 06.12.2 2/8/07
D
D
89 88 80 74 73 70 69 66 51 37 IN V_5P0_STBY\G
92 91 90
CAD NOTE: +12V

DUAL FOOTPRINT
DESIGN NOTE: R244BV
1 R108BV 8.2K 89 88 80 74 73 70 69 66 51 37 IN V_5P0_STBY\G
8.2K 5% 89 70 LATCHED_BACKFEED_CUT 92 91 90 CAD NOTE:
DEFENSIVE DESIGN IN
R243BV 5% CH
DEFAULT EMPTY (R105BV)
8.2K 2 EMPTY 402 CAD NOTE: +12V DUAL FOOTPRINT
1 R100BV
603
5% 8.2K DUAL FOOTPRINT
89 85 CH 5%
75 70 BACKFEED_CUT CAD NOTE:
82 80
IN 402 2 EMPTY R245BV
90 603 DUAL FOOTPRINT BOM NOTE: R246BV 1 R126BV 1 R127BV 8.2K
89 85 BACKFEED_CUT 8.2K 8.2K 8.2K 5%
75 70 IN STUFF FOR NO 1-WATT 5% 5% 5%
C 82 80 EMPTY 2 EMPTY 2 EMPTY
EMPTY C
SUPPORT IN S3 ONLY 402
1 90 402 603 603
R121BV, R122BV
1 R103BV AND EMPTY R120BV
R105BV 10K 1 1 1
10K 5% BOM NOTE: 1
VREG_5VDUAL_NCH OUT 88 R119BV R120BV R121BV R122BV VREG_USB_NCH OUT 88
5% EMPTY
EMPTY 402 EMPTY R103BV BOM NOTE: 10K 10K 10K
70 IN 2 VREG_5VDUAL_PCH 10K 5% 5% 5% VREG_USB_PCH
89 402 FOR NON AMT OUT 88 5% OUT 88
2 EMPTY R119BV
EMPTY
EMPTY EMPTY EMPTY
FOR 1-WATT 402 402 402
Q23BV 402 2 2 2 Q29BV
S3, S4, S5 2
MBT3904DUAL 3 6 MBT3904DUAL 3 6
BV_5VDUAL_MBT3904DUAL5 BV_5VDUAL_MBT3904DUAL2 BV_USB_MBT3904DUAL_5 BV_USB_MBT3904DUAL_2
1 1 R106BV 2 5 2 1 R104BV 2 1 R123BV 2 5 2 1 R124BV 2
LATCHED_BACKFEED_CUT
R178BV 4.7K 5% 4.7K 5% 4.7K 5% 4.7K 5%

10K 402 CH 402 CH 402 EMPTY 402 EMPTY
5% XSTR EMPTY
CH
4 1 4 1
402 BOM NOTE:
2
EMPTY FOR NON AMT
BV_5VDUAL_BACKFEED_CUT_L 1 R107BV 2 BV_USB_BACKFEED_CUT_L 1
R125BV 2
0 5%
B 402 EMPTY 0 5% B
402 EMPTY
BV_SLP_CTRL_BASE1 BOM NOTE: BV_1_WATT_CTRL_2_BASE1

1 3 3
86 R109BV R118BV
28 SLP_M 1 2 1 Q24BV EMPTY FOR NON AMT 36 33 1_WATT_CTRL_2 1 2 1 Q28BV
R177BV 39
IN MMBT3904 IN MMBT3904 BOM NOTE:
10K 88 10K 5% EMPTY 4.7K 5% EMPTY
5% 402 EMPTY 2 402 EMPTY 2
CH LATCHED_BACKFEED_CUT STUFF FOR 1-WATT
70 IN LATCHED_BACKFEED_CUT
402 89 89 70 IN S3, S4, S5
2
BV_5VDUAL_BACKFEED_CUT_R BV_USB_BACKFEED_CUT_R
BOM NOTE:
STUFF FOR NON AMT
A A

INTEL
xxxxxx 89 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL_B_ATX 06.12.2 2/8/07
D
D
-12V VCC3 VCC +12V
92
89 88
73 70
51 37 IN V_5P0_STBY\G PWRGD_PS OUT 70
69 66
80 74 1 R33BV
91 90 J2BV
10K 1
5% 2X12 PWR C145BV
2 CH 470PF
402
13 1 10%
14 2 2 50V
X7R
R37BV 15 3 402
70 IN PS_ON_SIO_N 1 2 BV_PS_ON_HEADER_N 16 4
0 5% 17 5
402 CH VCC 18 6
1 1 19 7
C37BV C35BV TP_MINUS5V 20 8
1UF 470PF V_5P0_STBY\G
20% 10% 21 9 OUT 37 51 66 69 70 73 74 80 88 89
2 6.3V 2 50V 22 10 90 91 92
Y5V X7R
402 603 23 11 1 1 1
24 12 2X12_DETECT
OUT 90 C30BV C32BV C41BV 90 IN 2X12_DETECT
1.0UF .1UF .1UF
C 20% 20% 20% C
CONN 2 10V
2 25V 2 25V 1 R35BV 2
Y5V Y5V Y5V
603 603 603
1K 5%
402 CH
2X12_POWER_DETECT OUT 33
1
DESIGN NOTE: R32BV
DESIGN NOTE:
POWER CONNECTOR DECOUPLING 2.2K
5% USED TO DETECT 2X12 PRESENCE
CH CONNECT TO GPIO
VCC VCC3 +12V -12V 402
2
92
89 88
73 70 V_5P0_STBY\G
51 37 IN
69 66
80 74
91 90
1 R34BV VCC3
750
5%
2 CH 1C31BV 2 C231BV
1 2 1C40BV 2
402
B BV_VREG_MAIN_STBY_LED_R .1UF 20% .1UF 20% .1UF 20% B
25V 25V 25V VCC3_BLEEDING_CIRCUIT
Y5V Y5V Y5V
603 603 603
2 06.12.02 06.12.02 06.12.02 06.12.02 06.12.02 06.12.02
CR5BV C34BV C33BV C39BV 1 1
BL_B_ATX 1
BL_B_ATX 1
BL_B_ATX 1
BL_B_ATX BL_B_ATX
1
GREEN 100UF 100UF 100UF BL_B_ATX
1 2 1 2 1 2 1C36BV 2 R247BV R248BV R249BV R250BV R251BV R252BV
1 LED 150
5%
150
5%
150
5%
150
5%
150
5% 150
20.0% 25V 20.0% 25V 20.0% 25V .1UF 20% 5%
25V CH CH CH EMPTY EMPTY
ELEC ELEC ELEC Y5V 603 603 603 603 603 EMPTY
RDL RDL RDL 603 2 2 2 2 2 603
2
BATTERY CR6BV PASSIVE_BLEED_PATH_VCC3

06.12.02
102 101 92 88 87 86 85 84 82 1 BL_B_ATX
38 37 36 34 33 32 28 22 21 9 IN V_3P3_STBY\G 2
70 69 64 59 53 49 48 47 39 06.12.02 R253BV
105 103 3 V_3P0_BAT_VREG 34 37 38 3 BL_B_ATX 0
OUT 85 Q58BV 1A
R36BV 80 EMPTY
1 2 BV_VBAT_VREG_R_CR 1 1 70 IN BACKFEED_CUT 1 CH
603 BOM NOTE:
1K 5% BAT54C C38BV 75 2 2
A 402 CH SOT23_C 1.0UF 82 STUFF R253BV FOR CBT A
20% 89
DIO 10V
XBT1BV 2 Y5V STUFF Q58BV FOR ENERGY SAVING
603
BV_VREG_VBAT_R 1 2
BOM NOTE:
CAD NOTE:
THROUGH-HOLE 2PCOIN BATTERY ADDED IN MOD FILE
PLACE NEAR ICH
CAD NOTE:
DO NOT PLACE BATTERY NEAR
MOUNTING HOLES, GROUND OR VIAS

INTEL
xxxxxx 90 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

2 R62BU 1 USB_OC_BACK2_N OUT 31

15K 5%
402 CH 2
R63BU
D 10K
5%
CAD NOTE:
D
CH
402
1 PLACE AS CLOSE AS POSSIBLE
RT3BU TO USB CONNECTOR
45 44 43 42
5VDUAL_USB 1 2 VREG_USB_BP_MJ 46 57
92 88 52 46
IN OUT
1 C317BU THRMSTR 2 1
1000UF 1 C255BU C256BU
20% R64BU 470UF 470PF
6.3V 1.50 10K 20% 10%
ALUM 5% 10V 50V
2 TH CH 2 EMPTY 2 X7R
RDL 603
1 2 3 4 RP3BU 402
0
1
5%
.063W
IC
8 7 6 5 SM VREG_USB MUST BE SPLIT
AMONGST ALL USB CHANNELS.
DO NOT DAISY CHAIN
C C
DO NOT CHANGE TO 402 SITE
RT4BU M1BU
1 2 IM_BV_VREG_PS2_FB 1 2 VREG_PS2 72
MULTI OUT
EMPTY CH 603
1.50 DECOUPLING ON CONNECTOR PAGE,
92 BOM NOTE: PLACED NEAR PS2 CONNECTOR.
89 88 RT5BU THERMISTOR OPTION (PER CUSTOMER REQUEST):
FERRITE BEAD OPTION:
73
51
70
37 V_5P0_STBY\G 1 2 STUFF SITE AND EMPTY 0 OHM R-PACK A51464-001
69 66
IN DEFAULT:0 OHM 108506-004
80 74 EMPTY
91 90 1.50 2 R65BU 1
BOM NOTE: USB_OC_BACK1_N OUT 31
STUFF THERMISTOR FOR WAKE FROM 15K 5%
402 CH
S5 BY USING PS2 2
R66BU
10K CAD NOTE:
5%
CH
402 PLACE AS CLOSE AS POSSIBLE
1
RT6BU TO USB CONNECTOR
B 1 2 B
VREG_USB_BP1_STACK OUT 46
THRMSTR 2 1 C257BU 1
R67BU 470UF C258BU
1.50 20% 470PF
10K 10V 10%
5% EMPTY 50V
CH
2 RDL 2 X7R
603
VREG_USB MUST BE SPLIT 1
402
V_5P0_STBY\G AMONGST ALL USB CHANNELS.
88 80 74 73 70 69 66 51 37
DO NOT DAISY CHAIN
92 91 90 89
IN
1 C407BU
470UF
20%
10V
2 EMPTY
RDL 2 R68BU 1 USB_OC_BACK0_N OUT 31
15K 5%
402 CH
2
R69BU
10K CAD NOTE:
5%
CH PLACE AS CLOSE AS POSSIBLE
402
A 1 TO USB CONNECTOR A
RT7BU
1 2 VREG_USB_BP0_STACK
OUT 45
THRMSTR 2 1 C259BU 1
R70BU 470UF C260BU
1.50 20% 470PF
10K 10V 10%
5% EMPTY 50V
CH
2 RDL 2 X7R
603
VREG_USB MUST BE SPLIT 1
402
AMONGST ALL USB CHANNELS.
DO NOT DAISY CHAIN

[PAGE_TITLE=WAKE CONTROL SWITCH PS2/USB (BP RIGHT)] frostburg_fabc.sch_1.91
INTEL
xxxxxx 91 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
+12V MODULE REV DETAILS

CAD NOTE:
C323BU
+12V VCC VCC VCC3 MODULE NAME REV DATE
DESIGN NOTE: 1 2 C324BU
EMI CAPS 1 2
PLACE CLOSE BP AUDIO CONN
BOARD GENERAL DCPL CAPS AUD_GND
.1UF 20%
25V .1UF
25V
20% C402BU
1 2
C403BU
1 2
IN Y5V
603 Y5V CAD NOTE:
603 .1UF 10% .1UF 10%
C79BU 10V 10V CAD NOTE:
1 2 X5R X5R
CAD NOTE: USB AND CLOCK
D +12V 402 402 BP USB
.1UF 20%
PEG SLOT 25V PLACE NEAR THE JA1LN 5VDUAL_USB D
Y5V OUT 42 43 44 45 46 52 88
C53BU C15BU 91 92
1 2 603 1 2
C350BU DESIGN NOTE:
V_5P0_STBY\G 98 82 38 34 9 IN V_1P5_ICH 1 2
+12V
.1UF 20% 80 74 73 70 69 66 51 37 IN .1UF 20% C320BU
VCC 25V 92 91 90 89 88 VCC VCC3 .1UF 20% 25V 1 2
C388BU
EMPTY
603
C401BU
1 2
C352BU
1 2
25V
EMPTY
603
STITCHING CAPS Y5V
603
C8BU
.1UF 20%
25V
1
.1UF 20%
2
1 2 Y5V 25V
603 Y5V
C41BU
.1UF 10% .1UF 10% +12V 603
1 2 10V 10V .1UF 20% C321BU VCC
1 C169BU X5R C413BU EMPTY C353BU 25V 1 2 +12V
CAD NOTE: 22UF 402 1 2 402 1 2 Y5V
DESIGN NOTE: CAD NOTE:
.1UF 20% 20.0% C148BU 603 C389BU
25V 25V 1 2 .1UF 20% 1 2
EMPTY PWR CONN GNR BULK DCPL .1UF 10% .1UF 10% FOR ICH_LAN_JCLK 25V
ELEC 10V 10V C5BU
603 2 RDL EMPTY EMPTY .1UF 20%
PLACE BELOW Y1LN 1 2 Y5V
.1UF 10%
603
"THMNT ALUM ELEC"
402 402 25V 10V
C42BU 105 103 102 101
Y5V .1UF 20% X5R
1 2 CAD NOTE: V_3P3_STBY\G 603 25V 402
49 48 47 39 38 37 36 34 33 32 28 22 21 9 IN
90 88 87 86 85 84 82 70 69 64 59 53 Y5V
.1UF 20% PCI SLOT 603 CAD NOTE:
25V -12V CAD NOTE: C152BU
Y5V 1 2 FP USB STITCHING CAPS
603
PLACE CLOSE TO J8BU AND J9BU
C43BU CAD NOTE: C178BV

2 1
VCC3 AZ HDR EMI CAPS .1UF 20%
C 1 2 CAD NOTE: PLACE NEAR J7AU 25V +12V VCC C
EMPTY
.1UF 20%
PCI SLOT .1UF 20%
PWR CONN 1
C25BU
2
603
+12V C409BU
1 2
+12V
25V CAD NOTE: C19BU LAN_V_1P0
25V EMPTY 1 2 C66BU
Y5V 603 VCC3 OUT 56 58 1 2 C410BU
603 .1UF 20% .1UF 10% 1 2
25V FOR HSYNC & VSYNC ABOVE 10V
C167BU
C173BV
1 2 EMPTY +12V NORTH OF MCH TRANSITION
.1UF 20%
.1UF 20% X5R
1 2 C406BU 603 25V 402 .1UF 10%
CAD NOTE: CAD NOTE: Y5V 25V
1 2 603 Y5V C67BU C411BU 10V
.1UF 20% C333BU 603 1 2 1 2 X5R
.1UF 20% 25V 1 2 CAD NOTE: 402
25V FP HDR EMPTY PCI SLOT .1UF 10%
EMPTY C20BU .1UF 20% .1UF 10%
603 10V .1UF 10% CLOSE TO PATA 1 2
603 EMPTY CAD NOTE: 25V 10V
402 10V Y5V EMPTY
X5R .1UF 20% 603 402
402 25V GCL STITCHING CAPS
Y5V
603 PLACE NEAR LEFT SIDE OF U1LN
92
DESIGN NOTE: V_5P0_STBY\G 74 80 88
V_3P3_EPW
OUT 37 51 66 DESIGN NOTE: DESIGN NOTE:
69 70 73 OUT 27 28 33 34 38 39 40 56 57 58
CLOCK STITCHING CAPS C334BU
89 90 91 C335BU
1 2
88
+12V PCIEX1 STITCHING CAPS AZALIA STITCHING CAPS
1 2
VCC3
CAD NOTE: VCC3 CAD NOTE:
+12V +12V
0.1UF 20% C385BU CAD NOTE:
0.1UF 20% 16V 1 2 C330BU C287BU
PLACE CLOSE TO Q50BV FOR CK_PE_100M_PATA 16V Y5V
Y5V 1 2
C331BU 402 PLACE NEAR SOUTH OF U1FW
1 2 402 .1UF 10%
B 10V VCC 0.1UF 20% 0.1UF 20%
B
C299BU 92 91 88 5VDUAL_USB C354BU X5R C386BU 16V 16V
.1UF 20% 1 2
44 43 42
1 2 +12V 402 1 2
C38BU CAD NOTE: Y5V EMPTY
25V
52 46 45
IN 1 2 402 402
Y5V C356BU
603 .1UF 20% 0.1UF 20% 1 2 .1UF 10% PLACE NEAR SOUTH OF Y1PT
25V 16V 10V .1UF 10%
Y5V EMPTY C355BU C387BU X5R 10V
603 402 1 2 .1UF 20% 1 2 402 X5R VCC +12V
25V 402 C408AU
EMPTY C305BU 1 2
.01UF 10% 603 .1UF 10% C34BU
25V 10V 1 2 1 2
EMPTY X5R C278BU 470PF 10%
1 2
402 402 C412BU .1UF 10% 0.1UF 20% 50V
CAD NOTE: 1 2 X7R
AUD
10V .1UF 10% 16V 402
X5R 10V Y5V
CK_P_33M_PA +12V CAD NOTE:
.1UF 10% 402 X5R 402
PLACE NEXT TO SOUTH OF U1CK 10V C275BU 402
X5R 1 2
C271BU CK_1PORT_S3_DN/S2_DN VCC3 402
VCC3 1 2 PLACE NEAR LEFT SIDE OF U1LN C71BU
VCC3 .1UF 10% C279BU
1 2
VCC3
1 2 10V CAD NOTE: C102BU
C70BU .1UF 10% X5R 1 2
C332BU .1UF 10%
1 2 10V 402
X5R C31BU .1UF 10% 1 2 DESIGN NOTE: 10V 1394 STITCHING CAPS 0.1UF 20%
C276BU X5R
402 1 2 16V 1 2
PLACE NEXT TO J33LB 16V
.1UF 10% X7R .1UF 10% 402 Y5V
16V BOM NOTE: 603 10V PATA STITCHING CAPS C280BU 402
X7R .1UF 20%
VCC3 X5R .1UF 10% 1 2
VCC3 +12V
603 25V STUFF FOR ATX ONLY 402 10V C103BU
Y5V X5R 1 2
603 CAD NOTE: 402 .1UF 10% C61BU
A C26BU 10V 1 2 A
1 2 X5R 0.1UF 20%
PLACE BETWEEN JIPT AND U1PT
402 16V
VCC .1UF 20%
CAD NOTE:
+12V C281BU
.1UF 20%
+12V Y5V
1 2 25V 402
25V CK_14M_ICH Y5V
Y5V 603 C104BU
CAD NOTE: 603 PLACE NEAR C244BU 1 2
C400BU C30BU .1UF 10%
1 2
CK_P_33M_TPM\PA 1 2 10V VCC
X5R 0.1UF 20%
PLACE NEAR C72BV 402 C329BU 16V
.1UF 10% .1UF 10% 1 2 Y5V
10V VCC3 VCC VCC3 VCC 10V CAD NOTE: 402
X5R EMPTY
VCC 402 402 .1UF 20%
C146BU C282BU 25V STITCHING CAPS
C277BU Y5V
1 2 1 2 C33BU 603 FOR CK505
2 1 1 2
C351BU
1 2
.1UF 10% CAD NOTE: .1UF 10% .1UF 10% .1UF 10%
CAD NOTE:
.1UF 10%
10V
10V
X5R
10V
X5R
10V
X5R
10V
EMPTY [PAGE_TITLE=VREG: DECOUPLING AND STITCHING]
402 CK_PE_33M_TPM 402 402 402
X5R
402 PLACE NEAR C12BV
CK_P_33M_TPM BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
PLACE NEXT TO C12BV
INTEL
xxxxxx 92 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
VCC MODULE REV DETAILS
VTT_OUT_RIGHT DESIGN NOTE:
7 6 IN MODULE NAME REV DATE
105 97 8 R223VR
1 2 EMPTY R237VR FOR 2 PHASE
BL_CPUVR 5.9.3 03-02-07
0 1A CAD NOTE:
603 CH
1 1 1 1 1 1 1 1 CAD NOTE:
PLACE C278VR CLOSE TO PIN 29
R1VR R2VR R3VR R4VR R5VR R6VR R7VR R8VR 1 C280VR PLACE C279VR CLOSE TO PIN 42 VCC/VSS_SENSE RESISTORS: POSSIBLE TO OVERLAP PADS (SAVE SPACE) ON FUTURE DESIGNS
680 680 680 680 680 680 680 680 .1UF R237VR OPTION FOR R11VR TO OVERLAP W/R12VR & R13VR TO OVERLAP W/14VR
D 5% 5% 5% 5% 5% 5% 5% 5% 10% VREG_12V_POWER 1 2
95 94 IN
CH CH CH CH CH CH CH CH 2 16V 96 VCC_SENSE R11VR D
402 402 402 402 402 402 402 402 X7R
603
0
603
1A
CH 6 IN 2 1
2 2 2 2 2 2 2 2
1 C279VR 0 5%
402 EMPTY VCC_VRM_SENSE OUT 93
1UF
10% R12VR DESIGN NOTE:
1 C278VR 2 25V VCC_PKGSENSE 2 1
3
0
7
1
93 6 X5R 6 IN EMPTY R11VR <ENG EXP>

IN H_VID<7..0> 1UF 603 0 5%
10% 402 CH
EU10VR 2 25V
ISL6312A X5R
603 VSS_SENSE R13VR
6 IN 2 1
93 OUT VCC_IN_CPU_VREG 10 VCC PVCC1_2 29 0 5%
VSS_VRM_SENSE
402 EMPTY OUT 93
1 R202VR 2 R14VR DESIGN NOTE:

BOM NOTE:
CPU_VREG_OFS 12 OFS PVCC3 42 6 IN VSS_PKGSENSE 2 1
CPU_VREG_PVCC3 EMPTY R13VR <ENG EXP>
LL STUFFING (DEFAULT IS 1.23MOHM LL)
562K 1% 0 5%
1.23MOHM LL: R202VR - 562K A93548-198 STUFFED 402 CH 402 CH
1.23MOHM LL: R201VR EMPTIED
1.00MOHM LL: R201VR 24.3K A93548-245 STUFFED
1.00MOHM LL: R202VR EMPTIED 1 R201VR 2 8 6 IN VRD_VIDSEL 6 VRSEL BOOT3 40 CPU_VREG_BST3
24.3K 1% 7 46 VID7
402 EMPTY 27 CPU_VREG_BST2
BOOT2
C 6 47 VID6 C
5 48 VID5 BOOT1 31 CPU_VREG_BST1
1 1 1
C208VR C209VR C210VR
4 1 VID4 .22UF .22UF .22UF
10% 10% 10%
3 2 33 2 16V 16V 16V
H_VID<7..0> VID3 PHASE1 X7R 2 X7R 2 X7R
93 6 IN 603 603 603
93 IN VCC_VRM_SENSE
2 3 VID2
PHASE2 25
1 4 VID1
0 5 VID0 PHASE3 38 VREG_SW3_OUT OUT 95
R238VR
J1VR CPU_VREG_ISEN1P 1 2 IN 94 VREG_SW2_OUT OUT 94
1X2HDR 0 5%
1 VRD_ENABLE 1 R215VR
1 CPU_VREG_ISEN1P_R
VREG_SW1_OUT
6 IN 36 EN ISEN1+ 35 1K 1 402 CH OUT 94
2 C211VR
1% .1UF C212VR
1 2 EMPTY 10% .1UF
EMPTY C220VR VR_READY 37 34 402 16V 10%
.1UF 39 8 7 OUT PGOOD ISEN1- 2 X7R 2 16V CAD NOTE:
A91829-020 CAD NOTE: 10% 603 X7R
10V CPU_VREG_ISEN1M 603 PLACE ALL COMPONENTS
2 EMPTY R203VR R216VR CLOSE TO CONTROLLER
PLACE ALL COMPONENTS
CLOSE TO CONTROLLER 402 1 2 CPU_VREG_FS 45 FS ISEN2+ 19 1 2 CPU_VREG_SENSE1 OUT
B B
DESIGN NOTE: 82.5K 1% 5.11K 1% R239VR
C201VR 402 CH 402 CH
1 2 CPU_VREG_ISEN2P 1 2 CPU_VREG_ISEN2P_R
IN 94
VSS/VCCSENSE: 1X2 CPU_VREG_REF 11 REF ISEN2- 20 1 R217VR
1 1 0 5%
HEADER (J1VR): NEVER CPU_VREG_ISEN2M 1K C213VR C214VR 402 CH
BOM NOTE: .012UF 10% 1%
STUFF SUITCASE JUMPER 50V R204VR .1UF .1UF
FMB STUFFING X7R 1 2 CPU_VREG_SS 9 SS ISEN3+ 44 2 EMPTY 10% 10%
65W: R207VR - 22.1K A93548-147 603 16V 16V
95W: R207VR - 17.4K A93548-239 (DEFAULT) 100K 1% R236VR 402 2 X7R 2 X7R
105W: R207VR - 15.4K A93548-205
40293 CH IN VCC_IN_CPU_VREG 1 2 603 603
ISEN3- 43 R218VR
49.9K 1%
402 EMPTY CPU_VREG_ISEN3M
1 2 CPU_VREG_SENSE2 OUT 94
R205VR
1 2 CPU_VREG_DRSEL 7 DRSEL 5.11K 1%
93 IN VSS_VRM_SENSE 402 CH R240VR
0 5% ISEN4+ 21 TP_CPU_VREG_ISEN4P
CPU_VREG_ISEN3P 1 2 CPU_VREG_ISEN3P_R 95
402 CH R206VR IN
C202VR R209VR 1 2 CPU_VREG_OVPSEL 8 OVPSEL 1 R219VR 1 1 0 5%
1 2 1K C215VR C216VR 402 CH
CPU_VREG_VDIFF_PN1 1 2 0 5% ISEN4- 22 TP_CPU_VREG_ISEN4M .1UF .1UF
1% 10% 10%
22.1 1% R207VR 402 CH
470PF 10% 402 CH 1 2 CPU_VREG_IOUT 15 IOUT 2 EMPTY
2 16V
2 16V
50V 402 X7R X7R
X7R 17.4K 1% 603 603
603 R210VR R212VR 32
1 2 1 2 402 CH
CPU_VREG_VDIFF UGATE1 CPU_VREG_UGATE1
OUT 94 R220VR
CPU_VREG_VDIFF_PN2
1 2 CPU_VREG_SENSE3 OUT 95
750 1% 750 1% 16 VDIFF UGATE2 26 CPU_VREG_UGATE2 94
402 CH 402 CH OUT 5.11K 1%
402 CH
1 1 R211VR RT1VR 39
C206VR C207VR 1 2 CPU_VREG_VDIFF_PN3
1 2 UGATE3 CPU_VREG_UGATE3
OUT 95
1500PF 1500PF CPU_VREG_FB 14 FB
A 5% 5% 562 1% THRMSTR A
25V 25V 402 CH C14407-001 C203VR
2 EMPTY 2 EMPTY LGATE1 30 CPU_VREG_LGATE1
OUT 94
603 603 CAD NOTE: 1 2 CPU_VREG_COMP 13 COMP
LGATE2 28 CPU_VREG_LGATE2
OUT 94
PLACE THERMISTOR RT1VR 22PF 5%
CLOSE TO IND1, NEEDS TO BE 50V
GROUND REFERENCED AND
AWAY FROM PHASE NODE COG 18 VSEN LGATE3 41 CPU_VREG_LGATE3
OUT 95
> 10MILS SO IT DOES NOT 603
PICK UP NOISE
R213VR C204VR 1 1 1
1 2 1 2 17 23 C219VR C218VR C217VR
CPU_VREG_COMP_PN1 RGND EN_PH4 VCC_IN_CPU_VREG
IN 1000PF 93 1000PF 1000PF
17.4K 1% 10% 10% 10%
820PF 5% 24 50V 50V 50V
402 CH 50V PWM4 2 EMPTY 2 EMPTY 2 EMPTY
COG 402 402 402
603 49 GND 1 OF 1
1 C205VR TP_CPU_VREG_PWM4
1500PF
5%
25V
REV=1 IC
BPAGE DRAWING
[PAGE_TITLE=VCCP VREG]
EMPTY DOCUMENT_NUMBER PAGE REV
2 603 frostburg_fabc.sch_1.93
INTEL
xxxxxx 93 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL_CPUVR 5.9.3 03-02-07
96 95 94 93 IN VREG_12V_POWER
D
D
1 1 1
2SK4080 4.7UF 4.7UF 4.7UF
20% 20% 20%
CAD NOTE: 3 16V 16V 16V
D79653-001 D Q11VR 2 X5R 2 X5R 2 X5R
PHASE RESISTORS: PLACE ALL 1206 1206 1206
GATE RESISTORS CLOSE TO FET
R224VR
93 CPU_VREG_UGATE1 1 2 CPU_VREG_HS_GATE1 1
IN G S
2.2 5% FET
603 CH 2
BOM NOTE:
FMB STUFFING
65W: Q11VR D79718-001 (IPD135N03L_G)
65W: Q12VR EMPTY
95W: DEFAULT
105W: Q11VR - D79716-001 (IPD090N03L_G) L1VR
105W: Q12VR & Q13VR C92515-001 (FDD8896) STUFFED 315NH
93 IN VREG_SW1_OUT 2 1 VCCP OUT 6 76 94 95 96 105
1 IND
NTD4808 NTD4808 1
3 3 R225VR 1
C D53747-001 D Q12VR D53747-001 2.2 R233VR C
D Q13VR 5% R226VR 0OHM CAD NOTE:
CH 0OHM
805 PLACE R226VR AND R233VR NEAR INDUCTOR
2 SM
93 CPU_VREG_LGATE1 1 1 SM 2
IN G S
CPU_VREG_SNUB1
2
FET G S 1 CPU_VREG_ISEN1P_R
OUT 93
CAD NOTE: 1 2 FET C221VR
C282VR 2 4700PF
PLACE LGATE CAP CLOSE TO MOSFET GATE PIN 2200PF 20%
10% 50V
SHARE THE SAME GND WITH MOSFET SOURCE PIN 50V 2 X7R
2 EMPTY 603 CPU_VREG_SENSE1
OUT 93
603
BOM NOTE:
FMB STUFFING
65W: C282VR STUFFED
95W & 105W: DEFAULT
96 95 94 93 IN VREG_12V_POWER
2SK4080
SOT 3 1 1 1
CAD NOTE: C226VR C227VR C228VR
D79653-001 D Q14VR 4.7UF 4.7UF 4.7UF
PHASE RESISTORS: PLACE ALL 20% 20% 20%
B GATE RESISTORS CLOSE TO FET 2 16V
2 16V
2 16V B
X5R X5R X5R
1206 1206 1206
R227VR
IN G S
2.2 5% FET
603 CH 2
L2VR
315NH
BOM NOTE: 93 IN VREG_SW2_OUT 2 1 VCCP OUT 6 76 94 95 96 105
FMB STUFFING 1 IND
65W: Q14VR - D79718-001
65W: Q16VR EMPTY
(IPD135N03L_G) NTD4808 NTD4808
95W: DEFAULT 3 3 R228VR
105W: Q14VR - D79716-001 (IPD090N03L_G) D53747-001 D Q15VR D53747-001 2.2 1
105W: Q15VR & Q16VR C92515-001 (FDD8896) STUFFED D Q16VR 5% 1
CH R229VR R234VR
805 0OHM CAD NOTE:
2 0OHM
93 CPU_VREG_LGATE2 1 1
PLACE R229VR AND R234VR NEAR INDUCTOR
IN G S
CPU_VREG_SNUB2
FET G S 1 SM
CAD NOTE: 2 FET C225VR SM 2
1 2 4700PF 2
C283VR 20%
A PLACE LGATE CAP CLOSE TO MOSFET GATE PIN 2200PF 50V A
10% 2 CPU_VREG_ISEN2P_R 93
SHARE THE SAME GND WITH MOSFET SOURCE PIN
50V X7R OUT
2 EMPTY 603
603
BOM NOTE:
CPU_VREG_SENSE2 93
FMB STUFFING OUT
65W: C283VR STUFFED
95W & 105W: DEFAULT
INTEL
xxxxxx 94 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL_CPUVR 5.9.3 03-02-07
D
D
96 94 93 IN VREG_12V_POWER
1 1 1
2SK4080 4.7UF 4.7UF 4.7UF
3 20% 20% 20%
D79653-001 Q17VR 2 16V
2 16V
2 16V
CAD NOTE: D X5R X5R X5R
1206 1206 1206
PHASE RESISTORS: PLACE ALL
GATE RESISTORS CLOSE TO FET
R230VR
IN G S
2.2 5% FET
603 CH 2
L3VR
315NH
C 93 IN VREG_SW3_OUT 2 1 VCCP OUT 6 76 94 96 105 C
BOM NOTE:
1 IND
FMB STUFFING NTD4808
65W: Q17VR - D79718-001 (IPD135N03L_G) 3 Q18VR R231VR 1 1
65W: Q19VR EMPTIED D53747-001 2.2
95W: DEFAULT D NTD4808 5% R235VR
105W: Q17VR - D79716-001 (IPD090N03L_G) 3 Q19VR R232VR 0OHM
105W: Q18VR & Q19VR C92515-001 (FDD8896) STUFFED D53747-001 CH 0OHM
D 805 CAD NOTE:
2
93 CPU_VREG_LGATE3 1 SM PLACE R232VR AND R235VR NEAR INDUCTOR
IN S
CPU_VREG_SNUB3
SM 2
G FET 1 C229VR 2
CAD NOTE: 1 2 1
C284VR G S
4700PF
PLACE LGATE CAP CLOSE TO MOSFET GATE PIN 2200PF FET 20%
SHARE THE SAME GND WITH MOSFET SOURCE PIN 10% 2 2 50V
X7R
CPU_VREG_ISEN3P_R
OUT 93
50V
2 EMPTY 603
BOM NOTE: 603
CPU_VREG_SENSE3 93
FMB STUFFING OUT
65W: C284VR EMPTIED
95W & 105W: DEFAULT
VCC
VR HOT
B B
H_PROCHOT_N 6 8 37
1 R59VR OUT
680
5%
R58VR 2 EMPTY
402 H_FORCEPH_N 6
CPU_VREG_VRHOT_OPAMP_PLUS 1 2 OUT
49.9K 1%
402 EMPTY
Q10VR
R56VR MBT3904DUAL 3 6
8 U1VR
1 2 5
+ LM358 R60VR R61VR R62VR
V 7 CPU_VREG_VRHOT 1 2 1 2 CPU_VREG_VRHOT_PN5 5 2 CPU_VREG_VRHOT_PN2 1 2
10K 1%
402 EMPTY 6 G 100K 1% 130 1% 130 1%
4
EMPTY 402 EMPTY 402 EMPTY 402 EMPTY
D69827-001 4 1 EMPTY
1 R55VR 1 R57VR 1
10K 4.99K C82VR
1% 1% .1UF
10%
2 EMPTY 2 EMPTY
2 16V
402 402 EMPTY
603
A A
CPU_VREG_VRHOT_R
CPU_VREG_VRHOT_OPAMP_MINUS
1 CAD NOTE:
RT2VR PLACE NEAR PHASE 3 INDUCTOR 1
EMPTY C83VR
C14407-003 .1UF
10%
16V
2 2 EMPTY
603
DESIGN NOTE: THIS IS FOR VRHOT

INTEL
xxxxxx 95 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL_CPUVR 5.9.3 01-12-07
CAD NOTE:
D PLACE ALL (14) 1206 CAPS INSIDE

CPU SOCKET CAVITY CAD NOTE:
D
105 96 95 94 76 6 IN VCCP PLACE ON TOP NORTH/NORTHEAST SIDE OF SOCKET

105 96 95 94 76 6 IN VCCP
1 C233VR
1 C234VR
1 C235VR
22UF 22UF 22UF
20% 20% 20% 1 C263VR 1 C264VR 1 C265VR 1 C266VR 1 C267VR
6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 150UF 560UF 560UF 560UF 560UF
1206 1206 1206 20% 20% 20% 20% 20%
2V 2.5V 2.5V 2.5V 2.5V
2 EMPTY
7343
EMPTY
2 RDL EMPTY
2 RDL ALUM
2 RDL ALUM
2 RDL
BOM NOTE:
1 1 1 NIPPON (PCS 2.5VB 560QH08)
C236VR
22UF
C237VR
22UF
C238VR
22UF
628955-074
20% 20% 20%
C 6.3V 6.3V 6.3V C
2 X5R 2 X5R 2 X5R
1206 1206 1206
CAD NOTE:
PLACE ON EAST/SOUTHEAST SIDE OF SOCKET
1 C239VR
1 C240VR
1 C241VR
22UF 22UF 22UF
20% 20% 20% 1 C268VR 1 C269VR 1 C270VR 1 C271VR
6.3V 6.3V 6.3V
2 EMPTY 2 EMPTY 2 X5R 560UF 560UF 560UF 560UF
1206 1206 1206 20% 20% 20% 20%
2.5V 2.5V 2.5V 2.5V
ALUM ALUM EMPTY
2 RDL 2 RDL 2 RDL 2 EMPTY
RDL
B B
BOM NOTE:
1 C242VR
1 C243VR
1 C244VR FMB STUFFING
22UF 22UF 22UF 65W : EMPTY C269VR
20% 20% 20%
6.3V 6.3V 6.3V 95W & 105W: DEFAULT
2 EMPTY 2 EMPTY 2 X5R
1206 1206 1206
BOM NOTE:
J2VR
2X2HDR RUBICON (16MHZ680M INL)
1 2 A46887-048
1 C281VR 1 C247VR VREG_12V_POWER 3 4
100UF 95 94 93 IN
20% 22UF
2V 20%
6.3V CONN
2 ALUM
7343
2 X5R A91848-001 1 C273VR C274VR C275VR
1206 680UF 680UF 680UF
20% 20% 20%
16V 16V 16V
ALUM ALUM EMPTY
1 C276VR 1 C277VR 2 RDL RDL RDL
A .1UF .1UF A
10% 10%
16V 16V
2 EMPTY 2 EMPTY
402 402
1 C250VR
BOM NOTE: 22UF
20%
FMB STUFFING 6.3V
65W & 95W: DEFAULT 2 EMPTY
1206
105W: STUFF C250VR
[PAGE_TITLE=VREG: VCCP DECOUPLING / 2X2 CONN]

INTEL
xxxxxx 96 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
BW_ATX_CORE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

10 8 6 H_CPURST_N 1 R95PR 2 TPEV_H_CPURST_XDP_R_N 97
IN OUT
1K 5% BW_ATX_CORE 1.06.00 5-5-06
402 EMPTY
105 97 93 8 7 6 VTT_OUT_RIGHT
IN
D
D
CAD NOTE: CAD NOTE:
PLACE TCK/TDI/TMS PLACE TDO TERMINATION 1
2 2 2 1 TERMINATION NEAR CPU 1 NEAR XDP CONNECTOR 105 97 93 8 7 6 IN VTT_OUT_RIGHT
R98PR R94PR R92PR R99PR R93PR
R126PR 62
62 62 62 62 5%
5% 5% 5% 5% 62
5% EMPTY 1 1 1 1 1 2
CH CH CH CH 402
402 402 402 402 CH 2
1 1 1 2 402 R103PR R102PR R101PR R100PR R96PR R97PR
CAD NOTE: 2 51 51 51 51 51 51
XDP_TESTIN_N OUT 97 5% 5% 5% 5% 5% 5%
PLACE TRST* TERMINATION TERMINATION IDEALLY TO BE PLACED
CAD NOTE: H_TDO CH CH CH CH CH CH
ANYWHERE ON ROUTE. NEXT TO IT OR WITHIN 1.5 OF CPU. IN 7 97 402 402 402 402 402 402
H_TDI
OUT 7 97 2 2 2 2 2 1
H_TMS 7 97
H_TCK
OUT
OUT 7 97
H_TRST_N
5
1
3
OUT 7 97
H_BPM_N<5..0> BI 7 97
CAD NOTE:
R109PR
97 7 BI H_BPM_N<3> 1 2 H_BPM3_2
BI 6 97 PLACE BPM TERMINATION NEAR CPU
C 0 5% C
402 EMPTY
8 7 6 VTT_OUT_LEFT
IN
R110PR
97 7 BI H_BPM_N<2> 1 2 H_BPM2_2
BI 6 97 1 R58PR 1 R61PR 1 R77PR 1 R78PR
51 51 51 51
0 5% 5% 5% 5% 5%
402 EMPTY
2 CH 2 CH 2 CH 2 CH
R111PR 402 402 402 402 H_BPM0_2 6 97
2 1
OUT
97 7 BI H_BPM_N<0> H_BPM0_2 BI 6 97 H_BPM1_2
OUT 7 97
0 5% H_BPM3_2 6 97
H_BPM2_2
OUT
402 EMPTY OUT 6 97
R113PR
97 7 BI H_BPM_N<1> 1 2 H_BPM1_2 BI 7 97
0 5% 5
402 EMPTY 4
3
2
1
0 H_BPM_N<5..0>
OUT 7 97
B BOM NOTE:
B
97 IN
J2BC STUFF FOR CRB BOARD 97 IN
XDP_SSA
9 BPM0* TDO 23 H_TDO IN 7 97

7 BPM1* TDI 29 H_TDI OUT 7 97
6 BPM2* TMS 31 H_TMS OUT 7 97
4 BPM3* TCK 30 H_TCK OUT 7 97
3 BPM4* TRST* 25 H_TRST_N OUT 7 97
1 BPM5*
PWRGOOD 10 XDP_PWRGD
16 100M_CLK_DP RESET* 19 TPEV_H_CPURST_XDP_R_N
18 100M_CLK_DN DBR* 21 FP_RST_N OUT 7 33 36 51 70
TESTIN* 12 XDP_TESTIN_N
97 IN CK_XDP_R_DP 13 XDP_H_CLK_DP
CK_XDP_R_DN 15 2 97 IN
97 IN XDP_H_CLK_DN GND
GND 5
105 97 93 8 7 6 IN VTT_OUT_RIGHT SMB_CLK_MAIN 22 8
70 28 27 BI SCL GND
70 28 27 BI SMB_DATA_MAIN 24 SDA GND 11
1 GND 17
R108PR 105 97 93 8 7 6 IN VTT_OUT_RIGHT 14 VTT GND 20
1.5K GND 26
5% 28 NC GND 27
A EMPTY
A
29 CK_H_XDP_DN 1 R106PR 2 2
402 1 EMPTY
IN
0 5% XDP_PWRGD 97
402 EMPTY OUT
29 CK_H_XDP_DP 1 R107PR 2
IN
0 5%
402 EMPTY
7 XDP_CLKOUT_DN 1 R104PR 2
IN
0 5%
402 EMPTY
I102 CK_XDP_R_DN 97
OUT
7 IN XDP_CLKOUT_DP 1 R105PR 2 I103 CK_XDP_R_DP
OUT 97
[PAGE_TITLE=PRIMARY XDP-LITE]
0 5% BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
402 EMPTY
INTEL
xxxxxx 97 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

PCIE/PATA 105 86 83
BRIDGE
82 76 38 34 21 18 17 16 14 13 IN V_1P25_CORE 1
M48PT
MULTI
2
MODULE
PCIE_PATA
NAME REV
1.2.7
DATE
39.2.06
FB 1 1 1 1 1 1
C1PT C2PT C3PT C4PT C5PT C6PT
.1UF .1UF .1UF .1UF .1UF 2.2UF
10% 10% 10% 10% 10% 10%
VCC3 2 10V
2 10V
2 10V
2 10V
2 10V
2 6.3V
D X5R X5R X5R X5R X5R X5R
402 402 402 402 402 603
D
M44PT
1 2 V_PATA_VDDIO
MULTI
FB 1 1 1 1 1
C26PT C7PT C8PT C9PT C10PT
10UF .1UF .1UF .1UF 2.2UF
20% 10% 10% 10% 10%
6.3V 10V 10V 10V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
805 402 402 402 603
M54PT
1 2 V_PATA_VAA1
MULTI
FB 1 1 1 1 V_VDD_N
C11PT C12PT C13PT C14PT
1000PF .01UF .1UF 2.2UF
10% 10% 10% 10%
50V 25V 10V 6.3V
2 X7R 2 X7R 2 X5R 2 X5R
402 402 402 603
EU1PT
88SE6101
M55PT REV=2
C 92 82 38 34 9 V_1P5_ICH 1 2 6 VDD H_DD15 57 IDE_DD15_N 99 C
IN MULTI BI
14 VDD H_DD14 60 IDE_DD14_N
BI 99
FB 1 1 1 1 45 VDD H_DD13 63 IDE_DD13_N
BI 99
C15PT C16PT C17PT C18PT
1000PF .01UF .1UF 2.2UF 55 VDD H_DD12 1 IDE_DD12_N
BI 99
10% 10% 10% 10% 62 VDD H_DD11 5 IDE_DD11_N
BI 99
50V 25V 10V 6.3V 8
2 X7R 2 X7R 2 X5R 2 X5R H_DD10 IDE_DD10_N
BI 99
402 402 402 603 25 VAA1 H_DD9 11 IDE_DD9_N
BI 99
H_DD8 15 IDE_DD8_N
BI 99
10 VDDIO H_DD7 16 IDE_DD7_N
BI 99
59 VDDIO H_DD6 13 IDE_DD6_N
BI 99
M53PT H_DD5 9 IDE_DD5_N 99
1 2
BI
TP_PATA_AVDD 37 AVDD H_DD4 7 IDE_DD4_N
BI 99
MULTI H_DD3 4 IDE_DD3_N 99
1 1 1 1 BI
FB V_AVDDT_N 39 AVDDT H_DD2 64 IDE_DD2_N
BI 99
C19PT C20PT C21PT C22PT V_AVDDL_N 42 61
1000PF .01UF .1UF 2.2UF AVDDL H_DD1 IDE_DD1_N
BI 99
10% 10% 10% 10% H_DD0 58 IDE_DD0_N
BI 99
50V 25V 10V 6.3V 43
2 X7R 2 X7R 2 X5R 2 X5R CLK-
402 402 402 603 44 CLK+ H_RESET* 47 IDE_RESET_N
OUT 99
36 PTX- H_DMARQ 56 IDE_DMARQ_N
OUT 99
38 PTX+ H_DIOW* 2 IDE_DIOW_N
OUT 99
40 PRX- H_DIOR* 12 IDE_DIOR_N
OUT 99
41 PRX+ H_IORDY 3 IDE_IORDY_N
IN 99
TP_PATA_HSDAC_N 34 HSDAC- H_DMACK* 54 IDE_DMACK_N
IN 99
B TP_PATA_HSDAC_P 35 HSDAC+ H_INTRQ 53 IDE_INTRQ_N B
CK_PE_100M_PATA_DN IN 99
29 IN 52
H_DA1 IDE_DA1_N
OUT 99
TP_PATA_GPIO2 19 GPIO2 H_DA0 51 IDE_DA0_N
OUT 99
1 R49PT 2 H_CS0* 50 IDE_CS0_N
OUT 99
46 WAKE* H_CS1* 48 IDE_CS1_N
OUT 99
100 5% 18 PERST* H_DA2 49 IDE_DA2_N 99
402 EMPTY OUT
H_CBLID* 17 IDE_CBLID_N
IN 99
29 IN CK_PE_100M_PATA_DP 26 XTLIN_OSC
C29PT 27 XTLOUT ISET 33 IDE_ISET_N
HSI2_DN 2 1 HSI2_C_DN
31 OUT 21 28
CFG0 S_ISET IDE_S_ISET_N
10% .1UF HSI2_C_DP 22 CFG1
10V UAO 23 TP_PATA_UAO
X5R 31 IN HSO2_C_DN
402 UAI 24 TP_PATA_UAI
31 IN HSO2_C_DP 20 TESTMODE VSS 30 1 1
C30PT 29 TP NC 31
HSI2_DP 2 1
31 OUT 32 R40PT R41PT
NC
10% .1UF
6.04K 6.04K
10V WAKE_N 65 1% 1%
X5R
102 101 47 36 33 22 21 OUT 1 OF 1 GND CH CH
402 1 R50PT 2 402 402
69 68 33 13 IN PLTRST_N P_PLTRST_N IC 2 2
0 5%
TP_PATA_TP VCC3
TP_PATA_TESTMODE
402 CH P_XTLIN_N
BOM NOTE:
A NEVER STUFF BOTH A93545-011 A

Y1PT 1 1
M56PT 25.000MHZ
1 2 1 R57PT 2 1 2 R35PT R36PT
29 IN CK_XT_25M_PATA CK_XT_25M_PATA_R P_XTLOUT_N 10K 10K
MULTI 0 5% 5% 5%
EMPTY 402 402 CH SM EMPTY EMPTY
XTAL 402 402
1 1 2 2
C23PT C24PT P_CFG1_N
18PF 18PF
5% 5%
50V 50V P_CFG0_N
2 COG 2 COG 1
603 603
C25PT
47PF 1 1
5%
50V R37PT R38PT
2 EMPTY
402 10K 10K
5% 5%
CH
402 CH
402
BOM NOTE:
2 2 BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
INTEL
Y1PT: USE MOD FLE TO REPLACE WITH IPN:A93545-001 xxxxxx 98 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

PATA CONNECTOR MODULE
PCIE_PATA
NAME REV
1.2.7
DATE
39.2.06
98 BI IDE_DD15_N
98 BI IDE_DD14_N
98 BI IDE_DD13_N
98 BI IDE_DD12_N
D 98 BI IDE_DD11_N
98 BI IDE_DD10_N D
98 BI IDE_DD9_N
98 BI IDE_DD8_N
98 BI IDE_DD7_N
98 BI IDE_DD6_N
98 BI IDE_DD5_N 1 1 1 1 1 1 1 1
98 BI IDE_DD4_N R9PT R10PT R11PT R12PT R13PT R14PT R15PT R16PT
98 BI IDE_DD3_N 33 33 33 33 33 33 33 33
98 BI IDE_DD2_N 5% 5% 5% 5% 5% 5% 5% 5%
98 BI IDE_DD1_N CH CH CH CH CH CH CH CH
98 BI IDE_DD0_N 402 402 402 402 402 402 402 402
2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1 1
R1PT R2PT R3PT R4PT R5PT R6PT R7PT R8PT
R30PT 33 33 33 33 33 33 33 33
10K 5% 5% 5% 5% 5% 5% 5% 5%
5%
CH CH CH CH CH CH CH CH
CH 402 402 402 402 402 402 402 402
402 2 2 2 2 2 2 2 2
2
C C
VCC3
IDE_C_DD10
IDE_C_DD9
1 PATA IDE_C_DD8
R31PT
5.6K J1PT
5% 2X20HDR_20
CH 107 IDE_C_RST 1 2
402 IDE_C_DD7 3 4
2 IDE_C_DD6 5 6
98 IDE_RESET_N 2 R17PT 1 IDE_C_DD5 7 8
IN IDE_C_DD4 9 10 IDE_C_DD11
33 5%
IDE_DMARQ_N 1 R18PT 2 402 CH IDE_C_DD3 11 12 IDE_C_DD12
1
98 IN IDE_C_DD2 13 14 IDE_C_DD13 C41PT
80.6 1% IDE_C_DD1 15 16 IDE_C_DD14 27PF
5%
IDE_DIOW_N 402 CH 1 R19PT 2 IDE_C_DD0 17 18 IDE_C_DD15 50V
98 IN 19 2 COG
22 5% 402
IDE_DIOR_N 1 R20PT 2 402 CH IDE_C_DMARQ 21 22
98 IN IDE_C_DIOW_N 23 24
22 5% IDE_C_DIOR_N 25 26
B IDE_IORDY_N 402 CH 1 R21PT 2 IDE_C_IORDY 27 28 B
98 OUT
80.6 1% IDE_C_DMACK_N 29 30
IDE_DMACK_N 1 R22PT 2 402 CH IDE_C_INTRQ 31 32 TP_IDE_PRI_32
98 OUT IDE_C_DA1 33 34 1 R46PT 2
22 5% IDE_C_DA0 35 36 10K 5%
IDE_INTRQ_N 402 CH 1 R23PT 2 IDE_C_CS0_N 37 38 402 CH
98 OUT
80.6 1% 39 40
98 IDE_DA1_N 2 R24PT 1 402 CH
IN HDR
33 5%
98 IDE_DA0_N 402 CH 2 R25PT 1
IN
33 5% IDE_PRI_ACT_N 70 107
2 R26PT 1 402 CH OUT
98 IN IDE_CS0_N
33 5%
98 IDE_CS1_N 402 CH 2 R27PT 1 IDE_C_CS1_N
IN
33 5%
98 IDE_DA2_N 2 R28PT 1 402 CH IDE_C_DA2
IN
33 5%
IDE_CBLID_N 402 CH 1 R29PT 2 IDE_DMA66_DETECT_PRI
98 OUT
1 1 80.6 1%
402 CH
R33PT R32PT 1 1 1 1 1
5.6K 10K C50PT C42PT C43PT C44PT C48PT 1 C49PT
A 5% 5% 22PF 22PF 22PF 22PF 22PF A
5% 5% 5% 5% 5% 22PF
CH CH 50V 50V 50V 50V 50V 5%
402 402 2 COG 2 COG 2 COG 2 COG 2 COG 2 50V
2 2 402 402 402 402 402 COG
402
1
C27PT CAD NOTE:
.047UF
10%
1 1 1 2 16V PLACE CLOSE AS POSSIBLE
C45PT C46PT C47PT EMPTY
22PF 22PF 22PF 603 TO IDE CONNECTOR
5% 5% 5%
50V 50V 50V
2 COG 2 COG 2 COG
402 402 402

INTEL
xxxxxx 99 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
CR-100
8: @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE100
7 6 5 4 3 2 1
MODULE REV DETAILS

D
D
TP_TESTCAP1_1
TP_TESTCAP4_1 TP_TESTCAP7_1
TP_TESTCAP10_1
1 1 1
C289BU C292BU C295BU
47PF 2.7PF 0.1UF
5% 9.25% 20% 1
50V 25V 16V C298BU
2 EMPTY 2 EMPTY 2 Y5V 100PF
402 402 402 5%
50V
TP_TESTCAP1_2 TP_TESTCAP4_2 TP_TESTCAP7_2 2 COG
TP_TESTCAP10_2 402
TP_TESTCAP5_1
1 1
C290BU C293BU
3.3PF 1
C .01UF .25% C296BU C
10% 50V 22PF
2 25V 2 COG 5%
X7R 402 50V
402 2 EMPTY
TP_TESTCAP5_2 402
TP_TESTCAP2_2
TP_TESTCAP8_2
+12V +12V
TP_TESTCAP3_1
1 R124BU 2 1 R128BU 2
1 1 1K 1% 1K 1%
1 C294BU C297BU
10PF 1000PF 1206 EMPTY 1206 EMPTY
C291BU 5% 10%
27PF 50V 50V
5% 2 COG 2 X7R
2 50V 402 402 +12V +12V
COG
402 TP_TESTCAP6_2
TP_TESTCAP9_2 1 R129BU 2
TP_TESTCAP3_2 1 R125BU 2
1K 1%
1K 1% 1206 EMPTY
1206 EMPTY
B B
+12V +12V
1 R126BU 2 1 R130BU 2
DESIGN NOTE: 1K 1%
1K 1% 1206 EMPTY
1206 EMPTY
FOR DFM
CORNER PROTECTION +12V
+12V
TP_DFMCAP1_1 1 R131BU 2
1 R127BU 2
1K 1%
1K 1% 1206 EMPTY
1 1206 EMPTY
C302BU
10.0UF
20%
10V
2 EMPTY DESIGN NOTE:
1206
TP_DFMCAP1_2 LOADING RESISTORS FOR 12V

A A
[PAGE_TITLE=TEST SITE CAPS]

INTEL
xxxxxx 100 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
CR-101
7 6 5 4 3 2 1
MODULE REV DETAILS

D
EXPANSION SLOT 5 D
CAD NOTE:
PCI-E X1 SLOT 2
PCI EXPRESS
1-PORT
+12V
C C
J26BU +12V VCC3
3GIO_X1
1.0
B1 12V PRSNT1* A1
B2 12V 12V A2
105 103 102 70 49 48 47 33 28 27 22 21 BI B4 A4
GND GND
105 103 102 101 92 90 88 87 86 85 84 82 JTAG1 3.3V
70 69 64 59 53 102 98 47 36 33 22 21 OUT WAKE_N B11 WAKE* PWRGD A11 PLTRST_PCIE_SLOTS_N IN 21 22 47 70 102
KEY
B18 GND A18
1 OF 1 GND
CONN
1
C373BU
.1UF
CAD NOTE: 20%
25V
2 EMPTY
CAD NOTE: VCC3

STICHING CAPS FOR TRACE OF PCIE SLOT 2 AND 3
C390BU
+12V +12V VCC 1 2 VCC3 VCC3 +12V 105 103 102 101 92 V_3P3_STBY\G
49 48 47 39 38 37 36 34 33 32 28 22 21 9 IN
.1UF 20% C360BU C361BU 90 88 87 86 85 84 82 70 69 64 59 53
C363BU C337BU C343BU 25V 1 2 1 2 C377BU
1 2 1 2 1 2 EMPTY 1 2
603 .1UF 20% .1UF 20% C357BU
.1UF 10% .1UF 10% .1UF 10% .1UF 20% 1 2
25V 25V
10V 10V 10V C380BU Y5V Y5V 25V
EMPTY EMPTY X5R 1 2 603 603 Y5V .1UF 20%
402 402 402 603 25V
Y5V
A +12V +12V VCC VCC .1UF 20% 603 A
25V
EMPTY
C344BU 603
C338BU C339BU C340BU 1 2
1 2 1 2 1 2
.1UF 10%
.1UF 10% .1UF 10% .1UF 10% 10V
10V 10V 10V X5R VCC VCC +12V +12V VCC3 VCC3
EMPTY X5R X5R 402
402 402 402
1 C345BU 1 C346BU 1 C347BU 1 C348BU 1 C349BU 1 C399BU

470UF 470UF 470UF 470UF 100UF 100UF
20% 20% 20% 20% 20.0% 20.0%
10V 10V 10V 10V 25V 25V
2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY
RDL RDL RDL RDL RDL RDL
INTEL
xxxxxx 101 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
CR-102
7 6 5 4 3 2 1
MODULE REV DETAILS

D
EXPANSION SLOT 6 D
CAD NOTE:
PCI-E X1 SLOT 3
PCI EXPRESS
1-PORT
+12V
C C
J23BU +12V VCC3
3GIO_X1
1.0
B1 12V PRSNT1* A1
B2 12V 12V A2
105 103 101 70 49 48 47 33 28 27 22 21 BI B4 A4
GND GND
105 103 101 92 90 88 87 86 85 84 82 JTAG1 3.3V
70 69 64 59 53 101 98 47 36 33 22 21 OUT WAKE_N B11 WAKE* PWRGD A11 PLTRST_PCIE_SLOTS_N IN 21 22 47 70 101
KEY
B18 GND A18
1 OF 1 GND
CONN
1
C374BU
.1UF
CAD NOTE: 20%
25V
2 EMPTY
VCC3
C358BU
1 2
.1UF 20%
25V
Y5V
603
C359BU
1 2
.1UF 20%
A 25V A
EMPTY
603 VCC3 VCC3 +12V
C383BU C375BU
C362BU
.1UF 20% .1UF 20%

25V 25V .1UF 20%
EMPTY Y5V 25V
603 603 EMPTY
603

INTEL
xxxxxx 102 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
CR-103
7 6 5 4 3 2 1
MODULE REV DETAILS

EXPANSION SLOT 7 (FURTHEST FROM CPU) MODULE NAME REV DATE
VCC VCC VCC3
1 2 100UF
1 2 470UF
1 2
CAD NOTE: C368BU
.1UF 20% 1 2
25V 20.0% 25V
STICHING CAP ACROSS VCC AND VCC3 Y5V EMPTY 20% 10V
PCI SLOT 3 VCC
VCC3
RDL
VCC3 RDL 25V
Y5V D
603
+12V
1 2 1 2
J24BU C370BU
105 102 101 92 1 2 C372BU
82 70 69 64 59 53 49 .1UF 20% .1UF 20% 1 2
48 47 39 38 37 36 Y5V .1UF 20% Y5V
25V .1UF 20%
90 88 87 86 85 84 603 603 25V
Y5V
A1 B1 603 EMPTY
TRST* M12V_1 603
A2 P12V_1 TCK B2 NOTE: PCI SLOTS= VCC3 SHOULD GET 470UF DECOUPLING,
A3 TMS GND1 B3
R315BU A4 TDI TDO B4 TP_PCI3_B4 VCC SHOULD GET 100UF (ALLOWS 1000UF OPTION FOR VCC3)
P_INTA_N 1 2 A5 P5V_2 P5V_0 B5 R317BU
50 30
103
OUT P_INTC_N A6 B6 1 2 P_INTD_N OUT 30 50 53
0 5% 50 30 OUT INTA* P5V_1
402 EMPTY 106 A7 INTC* INTB* B7 SLOT3_INTB_N 0 5% R318BU
402 CH
A8 P5V_3 INTD* B8 SLOT3_INTD_N 1 2 P_INTH_N OUT 30 48 49 50
R316BU SLOT3_INTC_N TP_PCI3_A9 A9 RSVD1 PRST1* B9 TP_PCI3_B9
50 30 OUT P_INTB_N 1 2 A10 B10 TP_PCI3_B10
0 5%
P5V_4 RSVD2 R319BU
402 EMPTY
0
402
5%
CH
TP_PCI3_A11 A11 RSVD3 PRST2* B11 TP_PCI3_B11 1 2 P_INTA_N
A12 B12 OUT 30 50 103
GND10 GND2
A13 GND16 GND3 B13 0 5% R320BU
402 CH
A14 3.3VAUX RSVD5 B14 TP_PCI3_B14 1 2 P_INTE_N OUT 30 48 49 50
CK_P_33M_S3 0 5%
C R161BU A16 P5V_6 CLK B16 402 EMPTY C
IN 28
106 49 48 36 30 IN P_GNT_N<2> 1 2 P_GNT_N_2_R A17 GNT* GND7 B17 R162BU
P_PME_N 0 5% A18 GND5 REQ* B18 P_REQ_N_2_R 1 2 P_REQ_N<2> OUT 30 48 49 50 106
53 49 48 30 OUT 402 CH A19 PME P5V_11 B19 0 5%
30 A20 AD30 AD31 B20 31 402 CH
VCC3 A21 P3_3V AD29 B21 29
106
103 28 A22 AD28 GND8 B22
49 R163BU 26 A23 AD26 AD27 B23 27
30 BI P_AD<18> 1 2 A24 B24
48 GND6 AD25 25
53 0 5% 24 A25 AD24 P3_3V B25
402 CH P_AD_18_20_R A26 B26
103
R164BU IDSEL C_BE3* 3
49 A27 P3_3V AD23 B27 23
30 BI P_AD<20> 1 2 A28 B28
48
22 AD22 GND12
53 0 5% 20 A29 AD20 AD21 B29 21
106 402 EMPTY R117BU R160BU A30 B30
DESIGN NOTE:
GND9 AD19 19
5.6K 5.6K 18 A31 AD18 P3_3V B31
5% 5% A32 B32
PCI2.2 COMPATIBLE
EMPTY EMPTY
16 AD16 AD17 17
402 402
A33 P3_3V C_BE2* B33 2
A39 B39 BI 30 48 49 50
P3_3V LOCK*
106 53 49 48 30 BI P_PAR A43 PAR P3_3V B43
2 15 A44 AD15 C_BE1* B44 1
2 A45 P3_3V AD14 B45 14
R105BU R106BU 13 A46 AD13 GND23 B46
0 11 A47 AD11 AD12 B47 12
5% 0
5% A48 GND17 AD10 B48 10
CH A49 B49
402 CH 9 AD09 GND24
1 402 KEY A50 B50 KEY
70 49 48 47 33 28 27 22 21 BI A52 B52
105 102 101
0 C_BE0* AD08 8
SMB_DATA_RESUME A53 P3_3V AD07 B53 7
70 49 48 47 33 28 27 22 21 BI A54 B54
105 102 101
6 AD06 P3_3V
4 A55 AD04 AD05 B55 5
2 A57 AD02 GND19 B57
0 A58 AD00 AD01 B58 1
R107BU A59 P5V_8 P5V_9 B59
1 2 REQ64C_N A60 REQ64* ACK64* B60 ACK64_N OUT 48 49
2.7K 5% A61 P5V_12 P5V_5 B61
A 402 CH A62 P5V_10 P5V_7 B62 A
P_AD<31..0> NC=1,2
106 103 53 49 48 30 BI
P_C/BE_N<3..0>
106 53 49 48 30 BI
DESIGN NOTE:
IRQ MAP
IRQ MAP A B C D
C D B A
INTEL
xxxxxx 103 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
CR-104
7 6 5 4 3 2 1
MODULE REV DETAILS

AUX FAN CONFIGURATION MODULE NAME REV DATE
D
D
CAD NOTE:
AUX FAN:
C C
+12V +12V
J25BU
1X4HDR
VCC3 1
AUX_FAN_DRIVER 1
VCC3 2
BOM NOTE: R114BU
BOM NOTE: 1 3 3.3K
STUFF FOR 3-PIN FAN 1 4
1 R108BU C378BU 5%
EMPTY FOR 3-PIN FAN 1 EMPTY FOR 4-PIN FAN R110BU .1UF
STUFF FOR 4-PIN FAN 2.2K 0 20% CH
IF PWM BUFFER IS NOT 5% R112BU
1A 25V HDR 402
2 2 EMPTY 2 R302BU
5.25V TOLERANT CH 2.2K CH 603
402 805 1 R115BU 2 ICH_GP7_PU_R 1 2 ICH_GP7_PU
3 5% AUX_TACH_OUT
OUT 32 36
2
AUX_FAN_CTRL_GATE 1 Q9BU EMPTY C80741-001 15K 5% 0 5%
MMBT3904 402 3 402 CH 1 402 CH
2 Q8BU
R116BU 1
R109BU XSTR
2 1 R113BU 2 EMPTY C379BU
1 2 AUX_FAN_CTRL_EMIT AUX_FAN_DRIVER_GATE 1 6.2K .01UF
5% 20% R303BU
0 5% 5% 220 2 BOM NOTE: 50V 1 2 AUX_FAN_TACH_HEC OUT 105
402 CH EMPTY 402 STUFF FOR 4-PIN FAN CH 2 EMPTY
EMPTY FOR 3-PIN FAN 402 603 0 5%
2 402 EMPTY
R300BU R111BU
B 32 IN REAR_FAN_CTRL 1 2 REAR_FAN_CTRL_R 1 2 AUX_FAN_CTRL_OUT B
77 0 5% 0 5%
1
402 CH 402 EMPTY

C382BU
BOM NOTE: 47PF
5% BOM NOTE:
DEFENSIVE DESIGN 50V
OPTION FOR 4PIN EMPTY EMPTY FOR 3-PIN FAN
2
FAN CIRCUIT. 402 EMPTY FOR 4-PIN FAN

IF PWM BUFFER IS NOT
5.25V TOLERANT
105 R301BU
77 IN REAR_FAN_CTRL_HEC 1 2
0 5%
402 EMPTY
A A

[PAGE_TITLE=AUX FAN CONFIGURATION] frostburg_fabc.sch_1.104
INTEL
xxxxxx 104 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
CR-105
7 6 5 4 3 2 1
CAD NOTE: CAD NOTE:

D
SOUTHEAST THERMAL ZONE SENSOR D
PLACE BELOW DIMMS 10MIL TRACE ON SE_ZONE_TDN AND _TDP CPU_FAN_CTRL 32 77
OUT
103 102 101 70 49 48 47 33 28 27 22 21 BI SMB_DATA_RESUME
103 102 101 70 49 48 47 33 28 27 22 21 IN SMB_CLK_RESUME
PRELIMINARY VCC +12V
76 BI H_TEMP_SRC_DP_HEC U4TH
C16TH HECETA6E
1 24 23 VCCP
100.0PF PWM1/NTESTOUT VCCP_IN IN 6 76 94 95 96
5% 2.5V 22 V_1P25_CORE IN 13 14 16 17 18 21 34 38 76
50V 1 SDA 5V 20 82 83 86 98
2 EMPTY
76 BI H_TEMP_RET_DN_HEC 603 2 SCL 3.3SBY 4 H6_V_3P3STBY
IN 105
12V 21
18 REMOTE1+
17 REMOTE1-/NTESTIN PWM2 10 REAR_FAN_CTRL_HEC
OUT 77 104
TP_SE_ZONE_TDP 16 REMOTE2+ PWM3 13 FNT_REAR_FAN_CTRL_HEC
OUT 77
TP_SE_ZONE_TDN 15 REMOTE2-
1 R54TH TACH1 11 CPU_FAN_TACH_HEC
1 2 IN 77
C19TH 97 93 8 7 6 BI VTT_OUT_RIGHT
TP_HECETA6_19 19 12 AUX_FAN_TACH_HEC
100.0PF VID4 TACH2 IN 104
5% 0 5% R56TH HECETA6_8 8 VID3 TACH3 9 FRONT_FAN_TACH_HEC
402 EMPTY IN 77
3 50V 1 2 7 14
2 EMPTY
HECETA6_7 VID2 TACH4 REAR_FAN_TACH_HEC
IN 77
1 Q11TH 603 0 5% TP_HECETA6_6 6 VID1
C MMBT3904
402 EMPTY TP_HECETA6_5 5 VID0 GND 3 C
EMPTY 1 R57TH BOM NOTE:
2 H_PECI 10K
6 BI 5%
EMPTY STUFF FOR UATX
1 C17TH 2 EMPTY EMPTY FOR ATX
402
.1UF
1 R55TH 20%
0 2 25V
5% EMPTY R60TH
603 V_3P3_STBY\G 1 2 H6_V_3P3STBY
2 CH IN OUT 105
402 0 5%
402 EMPTY
BOM NOTE:
32 BI H_PECI_ICH 1 C18TH
STUFF FOR
S3 SUPPORT .1UF
20%
+12V 2 25V
EMPTY
603 BIOS DETECTS ADDRESS WITHOUT STUFFING.
C15TH
1 2 VCC3 GPIO CONFIGURATION STRAP @ POWER-ON
.1UF 20% BOM NOTE: R58TH

25V 1 2
EMPTY DEFAULT FOR 2 R59TH 1
603
NO WAKE 0 5% 77 32 FNT_REAR_FAN_CTRL
402 EMPTY OUT
B 4.7K 5% B
402 EMPTY
A A
DRAWING
[PAGE_TITLE=HARDWARE MANAGEMENT: HECETA]
DOCUMENT NUMBER PAGE REV
SORRENTO SANDUSKY FAB C.SCH_1.68 INTEL
Sun Mar 18 18:45:26 2007 68 3.0
D13430
CONFIDENTIAL
8 7 6 5 4 3 2 1
CR-106
7 6 5 4 3 2 1
MODULE REV DETAILS

VCC3
D
D
C31PT 1 C32PT C33PT 1 C34PT
1 .1UF 1
U2PT .1UF 20% .1UF .1UF
IT8211F 20% 16V 20% 20%
16V EMPTY 16V 16V
2 EMPTY 2 402 2 EMPTY 2 EMPTY
P_AD<18> 7 50 IDE2_RESET_N 402 402 402
106 103 53 49 48 30 BI IDSEL PRST* OUT 107
103 53 50 49 48 30 BI P_FRAME_N 20 FRAME* PCS1* 51 IDE2_CS1_N OUT 107
103 53 50 49 48 30 OUT P_IRDY_N 21 IRDY* PCS0* 53 IDE2_CS0_N OUT 107
103 53 50 49 48 30 BI P_TRDY_N 22 TRDY* PINT 56 IDE2_INTRQ_N IN 107
103 53 50 49 48 30 BI P_DEVSEL_N 23 DEVSEL* PDACK* 57 IDE2_DMACK_N IN 107
103 53 50 49 48 30 BI P_STOP_N 24 STOP* PDRQ* 58 IDE2_DMARQ_N OUT 107
103 53 49 48 30 BI P_PAR 25 PAR PIOW* 67 IDE2_DIOW_N OUT 107
68 BI CK_P_33M_PATA2 120 PCICLK PIORDY 69 IDE2_IORDY_N IN 107 VCC3
103 50 30 BI P_INTC_N 121 INTA* PIOR* 76 IDE2_DIOR_N OUT 107
103 53 49 48 30 OUT P_PCIRST_N 122 RESET* PCBLID* 113 IDE2_CBLID_N IN 107
103 49 48 36 30 BI P_GNT_N<2> 123 PCIGNT*
103 50 49 48 30 BI P_REQ_N<2> 124 PCIREQ* PDD15 59 IDE2_DD15_N BI 107
PDD14 61 IDE2_DD14_N 1 C35PT 1 C36PT 1 C37PT
BI 107
103 53 49 48 30 P_C/BE_N<3> 6 CBE3* PDD13 63 IDE2_DD13_N 107
.1UF .1UF .1UF
BI P_C/BE_N<2>
BI 20% 20% 20%
103 53 49 48 30 BI 19 CBE2* PDD12 66 IDE2_DD12_N BI 107 16V 16V 16V
103 53 49 48 30 P_C/BE_N<1> 26 CBE1* PDD11 71 IDE2_DD11_N 107 2 EMPTY 2 EMPTY 2 EMPTY
BI P_C/BE_N<0>
BI 402 402 402
C 103 53 49 48 30 BI 38 CBE0* PDD10 73 IDE2_DD10_N BI 107 C
PDD9 75 IDE2_DD9_N BI 107
31 125 PAD31 PDD8 79 IDE2_DD8_N BI 107
30 126 PAD30 PDD7 80 IDE2_DD7_N BI 107
29 127 PAD29 PDD6 78 IDE2_DD6_N BI 107
28 128 PAD28 PDD5 74 IDE2_DD5_N BI 107
27 2 PAD27 PDD4 72 IDE2_DD4_N BI 107
26 3 PAD26 PDD3 70 IDE2_DD3_N BI 107
25 4 PAD25 PDD2 65 IDE2_DD2_N BI 107
24 5 PAD24 PDD1 62 IDE2_DD1_N 107
VCC3
BI
23 9 PAD23 PDD0 60 IDE2_DD0_N BI 107
22 11 PAD22
21 12 PAD21 SA2 82 TP_IDE2_SA2 1 R61PT
20 13 PAD20 SA0 84 TP_IDE2_SA0 4.7K
19 14 PAD19 SA1 85 TP_IDE2_SA1 5%
18 16 PAD18 2 EMPTY
17 17 PAD17 SCS1* 81 TP_IDE2_SCS1_N 402
16 18 PAD16 SCS0* 83 TP_IDE2_SCS0_N
15 28 PAD15 SINT 86 IDE2_SINT_N
14 29 PAD14 SDACK* 87 TP_IDE2_SDACK_N
13 31 PAD13 SDRQ 88 IDE2_SDRQ_N
12 32 PAD12 SIORDY 91 IDE2_SIORDY_N R60PT R59PT
1 1
11 33 PAD11 SIOR* 93 TP_IDE2_SIOR_N 5.6K 10K
B 10 35 PAD10 SIOW* 98 TP_IDE2_SIOW_N 5% 5%
B
9 36 PAD9 SCBLID* 114 TP_IDE2_SCBLID_N 2 EMPTY 2 EMPTY
8 37 PAD8 SRST* 115 TP_IDE2_STRST_N 402 402
7 39 PAD7
6 41 PAD6 SDD15 90 TP_IDE2_SDD15_N
P_AD<31..0> 0 49 PAD0 SDD9 107 TP_IDE2_SDD9_N
106 103 53 49 48 30 BI 112 TP_IDE2_SDD8_N
SDD8
107 OUT IDE2_DA2_N 52 PA2 SDD7 111 IDE2_SDD7_N
107 OUT IDE2_DA1_N 55 PA1 SDD6 106 TP_IDE2_SDD6_N
107 OUT IDE2_DA0_N 54 PA0 SDD5 104 TP_IDE2_SDD5_N 1 R62PT
SDD4 102 TP_IDE2_SDD4_N 10K
VCC3 FSC 109 100 TP_IDE2_SDD3_N 5%
106 IN PCK66ME SDD3 2 EMPTY
SDD2 96 TP_IDE2_SDD2_N
402
10 VCC3 SDD1 94 TP_IDE2_SDD1_N
1 R58PT 30 VCC3 SDD0 89 TP_IDE2_SDD0_N
33 43 VCC3
5% VCC3
68 VCC3 AVSS 118
2 EMPTY 92 VCC3 AVCC 117 IDE2_AVCC_N
402
108 VCC3 VCC3
A FSC A
OUT 106 116 VCC3 1 C38PT 1 C39PT
EMPTY .1UF 10.0UF L1PT
1 R63PT REV=1 20% 20% 1 2
33 16V 10V
5% GND=1,8,15,27,34,40,47,64,77,99,110,119 2 EMPTY2 EMPTY 10UH EMPTY
402 1206
2 EMPTY
402
[PAGE_TITLE=ITE IT8211F 1 OF 2]
INTEL
xxxxxx 106 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
CR-107
7 6 5 4 3 2 1
MODULE REV DETAILS

PATA 2ND CONNECTOR MODULE NAME REV DATE
106 BI IDE2_DD15_N
106 BI IDE2_DD14_N
106 BI IDE2_DD13_N
106 BI IDE2_DD12_N
D 106 BI IDE2_DD11_N
106 BI IDE2_DD10_N D
106 BI IDE2_DD9_N
106 BI IDE2_DD8_N
106 BI IDE2_DD7_N
106 BI IDE2_DD6_N
106 BI IDE2_DD5_N 1 1 1 1 1 1 1 1
106 BI IDE2_DD4_N R73PT R74PT R75PT R76PT R77PT R78PT R79PT R80PT
106 BI IDE2_DD3_N 33 33 33 33 33 33 33 33
106 BI IDE2_DD2_N 5% 5% 5% 5% 5% 5% 5% 5%
106 BI IDE2_DD1_N EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY
106 BI IDE2_DD0_N 402 402 402 402 402 402 402 402
2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1 1
R65PT R66PT R67PT R68PT R69PT R70PT R71PT R72PT
R64PT 33 33 33 33 33 33 33 33
10K 5% 5% 5% 5% 5% 5% 5% 5%
5%
EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY
EMPTY 402 402 402 402 402 402 402 402
402 2 2 2 2 2 2 2 2
2
VCC
C C
VCC
IDE2_C_DD10
1 IDE2_C_DD9
R81PT 1 IDE2_C_DD8
8.2K
5% R82PT
EMPTY 4.7K J2PT
402 5% 2X20HDR_20
2 EMPTY 99 1 2
402 IDE2_C_DD7 3 4
2 IDE2_C_DD6 5 6
106 IDE2_RESET_N 2 R83PT 1 IDE2_C_DD5 7 8
IN
33 5% IDE2_C_DD4 9 10 IDE2_C_DD11
1 R84PT 2 402 EMPTY IDE2_C_DD3 11 12 IDE2_C_DD12
106 IN IDE2_DMARQ_N IDE2_C_DD2 13 14 IDE2_C_DD13
80.6 1% IDE2_C_DD1 15 16 IDE2_C_DD14
IDE2_DIOW_N 402 EMPTY 1 R85PT 2 IDE2_C_DD0 17 18 IDE2_C_DD15
106 IN
22 5% 19
1 R86PT 2 402 EMPTY IDE2_C_DMARQ 21 22
106 IN IDE2_DIOR_N IDE2_C_DIOW_N 23 24
22 5% IDE2_C_DIOR_N 25 26
B IDE2_IORDY_N 402 EMPTY 1 R87PT 2 IDE2_C_IORDY 27 28 B
106 OUT
80.6 1% IDE2_C_DMACK_N 29 30
1 R88PT 2 402 EMPTY IDE2_C_INTRQ 31 32 TP_IDE2_PRI_32
106 OUT IDE2_DMACK_N 1 R98PT 2
IDE2_C_DA1 33 34
22 5% IDE2_C_DA0 35 36
402 EMPTY 1 R89PT 2 10K 5%
106 OUT IDE2_INTRQ_N IDE2_C_CS0_N 37 38 402 EMPTY
80.6 1% 39 40
106 IDE2_DA1_N 2 R90PT 1 402 EMPTY
IN EMPTY
33 5%
106 IDE2_DA0_N 402 EMPTY 2 R91PT 1
IN
33 5% IDE_PRI_ACT_N 70 99
2 R92PT 1 402 EMPTY OUT
106 IN IDE2_CS0_N
33 5%
106 IDE2_CS1_N 402 EMPTY 2 R93PT 1 IDE2_C_CS1_N
IN
33 5%
106 IDE2_DA2_N 2 R94PT 1 402 EMPTY IDE2_C_DA2
IN
33 5%
IDE2_CBLID_N 402 EMPTY 1 R95PT 2 IDE2_DMA66_DETECT_PRI
106 OUT
80.6 1%
402 EMPTY
1 1
A R96PT A
R97PT 10K
5.6K 5%
5%
EMPTY
EMPTY 402
402 2
2 1
C40PT CAD NOTE:
.047UF
10%
2 16V PLACE CLOSE AS POSSIBLE
EMPTY
603 TO IDE CONNECTOR
[PAGE_TITLE=PATA 2ND CONNECTOR]

INTEL
xxxxxx 107 3.01
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE

Trung Tâm Máy Tính AV - AV Computer Center: Bearlake-B ATX

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Trung Tâm Máy Tính AV - AV Computer Center: Bearlake-B ATX

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Trung Tâm Máy Tính AV - AV Computer Center

PAGE # COMPONENT/FUNCTION PAGE # COMPONENT/FUNCTION REVISIONS

[29. CK505 PAGE 2 OF 2] [77. FAN CONFIGURATION] POWER SYMBOLS USED:

MODULE REV DETAILS

LGA775 CK_505 CLOCK

PCI E 1X16 GMCH: DUAL DATA RATE SDRAM

USB PORT 1 5 & 6 ICH9: I/O

USB PORT 6 SM BUS S3

BROADWATER HIGH DEF AUDIO LINK HD AUDIO

PORT TPM: SECURITY HD 10 CH PC_SPKR

MODULE REV DETAILS

PORT ANGELES TPM (SECURITY)

RESET* H_CPURST* RES: 1394_PCI_RST* P_PCIRST*

FRONT PANEL CONN H_PWRGD

MODULE REV DETAILS

33MHZ PCICLK ICH

100/133/167/200 MHZ CPU_CK CHAN B

HOST CLOCK PAIRS 100/133/167/200 MHZ CPU_CK

ICH GPIO SIGNALS NOT USED: GP40-47

MODULE REV DETAILS

H_VCCPLL H_COMP1 OUT 6

MODULE REV DETAILS

MODULE REV DETAILS

9 GTLREF_FET0 1 EMPTY 9 GTLREF_FET1 1 EMPTY

[PAGE_TITLE=CPU PLL FILTERED SUPPLY]

MODULE REV DETAILS

BA33 DDR_A_WEB DDR_A_DQ_8 AV4 8

0 BB35 DDR_A_ODT_0 DDR_A_DQ_22 BC7 22

2 BA15 DDR_B_MA_2 DDR_B_DM_0 AR7 0

1 AY17 DDR_B_BS_1 DDR_B_DQ_13 AU9 13

DDR_B DDR_B_DQ_50 AF35 50

TP_B_RCVEN_N AM21 AC36 7

AL4 DDR_RCOMPXPD DDR_B_DQ_57 AC33 57

BA40 DDR_RCOMPYPU DDR_B_DQ_60 AD34 60

DO NOT TESTPOINT (U1UB_PIN

U1UB MODULE REV DETAILS

TP_MCH_L17 L17 RSVD CRT_DDC_DATA L13 VGA_MCH_DDCSDA BI 17 20

BOM NOTE: CL_N_DATA AD12 H18 TPEV_PM_EXTTS_N

AE23 VCC VCC W 27 D27 VTT_FSB VCC_CL AL12

VCC F11 B16 VCCA_DAC

U1UB MODULE REV DETAILS

AR21 VSS VSS Y35 H29 VSS

MODULE REV DETAILS

[PAGE_TITLE=PLL & CRT FILTERS]

R38UB MODULE REV DETAILS

UN-STUFF 39 OHM SERIES RES (R52UB, R51UB) FOR NON-GRAPHICS SKUS

TERMINATION 402 402 DESIGN NOTE:

[PAGE_TITLE=MCH DECOUPLING AND COMP]

MODULE REV DETAILS

MCH MEMORY DECOUPLING

PCI-E SIGNAL TRANSITION STICHING CAPS

[PAGE_TITLE=MCH DCPL & VGA TERMINATION]

[PAGE_TITLE=MCH VREFS & TERMINATION]

MODULE REV DETAILS

Q2UB R80UB R82UB 2 10V

VCC3 +12V +12V VCC3 MODULE REV DETAILS

VCC3 +12V +12V VCC3 MODULE REV DETAILS

23 21 EXP_A_TX_4_C_DP B33 HSOP4 RSVD A33 TP_3G16_RSVD_A33 21

23 21 IN EXP_A_TX_8_C_DP B50 HSOP8 RSVD A50 TP_3G16_RSVD_A50 21

MODULE REV DETAILS

STUFF ALL THE CAPS

[PAGE_TITLE=PCI EXPRESS X16 COUPLING]

79 VSS DQS<1> 16 1 82 VSS DQS*<1> 15 1

82 VSS DQS<1> 15 1 82 VSS DQS<1> 15 1

100 VSS DQS<3> 36 3 100 VSS DQS<3> 36 3

109 VSS DQS<4> 83 4 109 VSS DQS<4> 83 4

145 VSS DQS<8> 45 TP_SB_DQSB_8 145 VSS DQS<8> 45 TP_SB_DQSB0_8

221 CK2/RFU DQ<36> 199 36 221 CK2/RFU DQ<36> 199 36