Ethernet Management Information Base (MIB) Core Databook SA14-2434-11

IBM Ethernet Management Information Base (MIB)
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Core Databook
SA14-2434-11
Revision 11
April 10, 2007 - IBM Confidential
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SA14-2434-11
April 10, 2007 - IBM Confidential
IBM Core Databook
Revision 11 Ethernet Management Information Base (MIB)
Table of Contents
Contents
Preface ............................................................................................................................. 7
About this Book ....................................................................................................................................... 7
Who Should Use this Book ..................................................................................................................... 7
Revision Log ........................................................................................................................................... 7
Notation Conventions ............................................................................................................................ 14
Terms and Abbreviations ...................................................................................................................... 15
1. Overview .................................................................................................................... 17
1.1 Introduction ..................................................................................................................................... 17
1.2 Features .......................................................................................................................................... 17
1.3 Typical Applications ........................................................................................................................ 19
1.4 References ...................................................................................................................................... 19
1.5 Additional Required Elements ......................................................................................................... 20
2. Functional Description ............................................................................................. 21
3. Software Interface ..................................................................................................... 23

3.1 Registers ......................................................................................................................................... 23
3.1.1 aFramesTransmittedOK ........................................................................................................ 29
3.1.2 aSingleCollisionFrames ......................................................................................................... 30
3.1.3 aMultipleCollisionFrames ...................................................................................................... 30
3.1.4 aFramesReceivedOK ............................................................................................................ 31
3.1.5 aFrameCheckSequenceErrors .............................................................................................. 32
3.1.6 aAlignmentErrors ................................................................................................................... 32
3.1.7 aOctetsTransmittedOK .......................................................................................................... 33
3.1.8 aFramesWithDeferredXmissions ........................................................................................... 34
3.1.9 aLateCollisions ...................................................................................................................... 34
3.1.10 aFramesAbortedDueToXSColls .......................................................................................... 35
3.1.11 aFramesLostDueToIntMACXmitError .................................................................................. 36
3.1.12 aCarrierSenseErrors ............................................................................................................ 37
3.1.13 aOctetsReceivedOK ............................................................................................................ 38
3.1.14 aFramesLostDueToIntMACRcvError ................................................................................... 39
3.1.15 aMulticastFramesXmittedOK ............................................................................................... 40
3.1.16 aBroadcastFramesXmittedOK ............................................................................................. 40
3.1.17 aFramesWithExcessiveDeferral .......................................................................................... 41
3.1.18 aMulticastFramesReceivedOK ............................................................................................ 41
3.1.19 aBroadcastFramesReceivedOK .......................................................................................... 42
3.1.20 aInRangeLengthErrors ........................................................................................................ 42
3.1.21 aOutOfRangeLengthField .................................................................................................... 43
3.1.22 aFrameTooLongErrors ........................................................................................................ 43
3.1.23 aSQETestErrors .................................................................................................................. 44
3.1.24 aSymbolErrorDuringCarrier ................................................................................................. 45
3.1.25 aMACControlFramesTransmitted ........................................................................................ 46
3.1.26 aMACControlFramesReceived ............................................................................................ 46
3.1.27 aUnsupportedOpcodesReceived ......................................................................................... 47
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Core Databook IBM
Ethernet Management Information Base (MIB) Revision 11
3.1.28 aPAUSEMACCtrlFramesTransmitted .................................................................................. 47

3.1.29 aPAUSEMACCtrlFramesReceived ...................................................................................... 48
3.1.30 aShortEvents ....................................................................................................................... 48
3.1.31 aRunts .................................................................................................................................. 49
3.1.32 aBursts ................................................................................................................................. 50
3.1.33 etherStatsOctets .................................................................................................................. 51
3.1.34 etherStatsPkts ...................................................................................................................... 51
3.1.35 etherStatsBroadcastPkts ..................................................................................................... 52
3.1.36 etherStatsMulticastPkts ....................................................................................................... 52
3.1.37 etherStatsCRCAlignErrors ................................................................................................... 53
3.1.38 etherStatsOversizePkts ....................................................................................................... 53
3.1.39 etherStatsJabbers ................................................................................................................ 54
3.1.40 etherStatsCollisions ............................................................................................................. 54
3.1.41 etherStatsPkts64Octets ....................................................................................................... 55
3.1.42 etherStatsPkts65to127Octets .............................................................................................. 55
3.1.43 etherStatsPkts128to255Octets ............................................................................................ 56
3.1.44 etherStatsPkts256to511Octets ............................................................................................ 56
3.1.45 etherStatsPkts512to1023Octets .......................................................................................... 57
3.1.46 etherStatsPkts1024to1518Octets ........................................................................................ 58
3.1.47 ReceivedInLoopBackMode .................................................................................................. 59
3.1.48 RXVLANTaggedFrame ........................................................................................................ 59
3.1.49 RXVLANUserPriorityField .................................................................................................... 60
3.1.50 RXUnicastAddr .................................................................................................................... 60
3.1.51 RXFIFOOverrun ................................................................................................................... 61
3.1.52 TXPkts64Octets ................................................................................................................... 61
3.1.53 TXPkts65to127Octets .......................................................................................................... 62
3.1.54 TXPkts128to255Octets ........................................................................................................ 62
3.1.55 TXPkts256to511Octets ........................................................................................................ 63
3.1.56 TXPkts512to1023 ................................................................................................................ 63
3.1.57 TXPkts1024toMaxSizeOctets .............................................................................................. 64
3.1.58 TXBadFCS ........................................................................................................................... 65
3.1.59 TXFramePausedByControlPacket ....................................................................................... 65
3.1.60 TXUnicastAddr ..................................................................................................................... 66
3.1.61 TXFIFOUnderrun ................................................................................................................. 66
3.1.62 MIB_INTERRUPT_STATUS_A ........................................................................................... 67
3.1.63 MIB_INTERRUPT_STATUS_B ........................................................................................... 69
3.1.64 MIB_ENABLE_INTERRUPT_STATUS_A ........................................................................... 71
3.1.65 MIB_ENABLE_INTERRUPT_STATUS_B ........................................................................... 71
3.1.66 ReceivedWithCodeError ...................................................................................................... 72
3.1.67 TXLocalFault ........................................................................................................................ 72
3.1.68 TXRemoteFault .................................................................................................................... 73
3.1.69 CoreConnect Revision ID Register ...................................................................................... 73
3.2 Interrupt Handling ............................................................................................................................ 74
3.3 Software Implementation ................................................................................................................. 75
4. Hardware Interface .................................................................................................... 77

4.1 EMAC Interface ............................................................................................................................... 77
4.1.1 Content of Transmit Status Word for 10/100/100 Applications .............................................. 79
4.1.2 Content of Receive Status Word for 10/100/1000 applications ............................................. 81
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4.1.3 Content of Transmit Status Word for 10 G Applications ........................................................ 84

4.1.4 Content of Receive Status Word for 10 G Applications ......................................................... 86
4.2 OPB Interface .................................................................................................................................. 88
4.3 Power Management Interface ......................................................................................................... 90
5. Core Integration ........................................................................................................ 91

5.1 Configurability ................................................................................................................................. 91
5.1.1 Interconnect ........................................................................................................................... 92
5.2 Initialization Sequence .................................................................................................................... 92
5.3 Synthesis Guidelines and Requirements ........................................................................................ 93
5.3.1 User-Defined Synthesis Options ........................................................................................... 93
5.3.2 Timing Information ................................................................................................................. 93
5.3.2.1 Clocking .......................................................................................................................... 93
5.3.2.2 Timing Definitions for Interfacing Pins ............................................................................ 93
5.3.2.3 EMAC MIB Interface ....................................................................................................... 94
5.3.2.4 MIB OPB Interface ......................................................................................................... 96
5.3.2.5 MIB Clocks ..................................................................................................................... 97
5.3.2.6 Supplied Timing Constraints .......................................................................................... 98
5.3.2.7 User-Defined Timing Constraints for Asynchronous Clock Domain Crossings .............. 98
5.4 Test Interface Requirements ........................................................................................................... 99
5.5 Physical Design Requirements ..................................................................................................... 100
5.5.1 Size ...................................................................................................................................... 101
5.5.2 Technology .......................................................................................................................... 101
5.6 Cell Names and Associated Library Elements .............................................................................. 101
5.7 Performance and Operating Environment ..................................................................................... 101
5.7.1 Clock Frequencies ............................................................................................................... 101
5.7.2 Voltages and Temperature Ranges ..................................................................................... 102
5.7.3 Nominal Power Dissipation .................................................................................................. 102
5.7.4 CoreConnect™ Device Compliance .................................................................................... 102
Appendix A. Asynchronous Interface ....................................................................... 104

A.1 Assertion for Synopsys Tools ....................................................................................................... 104
A.2 EinsTimer Assertions .................................................................................................................... 104
A.3 User-Defined Timing Constraints for Asynchronous Clock Domain Crossings ............................ 105
A.3.1 Synchronizer Flip-Flop Pairs ............................................................................................... 106
A.3.2 Asynchronous Clock Domain Crossings (of Control and Status Signals) ........................... 107
SA14-2434-11
Core Databook IBM
SA14-2434-11
IBM Core Databook
Preface
About this Book

This book describes the functionality, registers, interfaces, signals, timing specifications, core integration,
clocking guidelines, testing and physical design requirements, and the performance and operating environ-
ment of the Ethernet Management Information Base (MIB).
This document is available to anyone with access to the Design Kit for the core. If you need access, contact
your IBM representative.
Who Should Use this Book

This book is for hardware, software, and application developers who need to understand the Ethernet
Management Information Base (MIB).
Revision Log
Note: Changes from previous versions of this document are marked with blue change bars throughout the
text. Italicized text and page numbers in this table are hypertext links. Change bars apply only to the most
recent version of the document.
Version Date Description of Revision Page
Revision 11 April 10, 2007 Changed “flip flop” to “flip-flop”. 98, 106
Added additional instruction to chip-level timing engineer in Section Appendix A. , 104

Asynchronous Interface.
Added alternate Einstimer Assertion example in Section A.1 , Assertion for Synop- 104
sys Tools.
Fixed typos in first bullet in Section A.2 , EinsTimer Assertions. 104
Added additional indications to add a third synchronizer flip-flop, if necessary, for 106
the technology in Section A.3.1 , Synchronizer Flip-Flop Pairs.
SA14-2434-11 Preface
Core Databook IBM
Revision 10 January 6, 2006 Changed RMON RFC document version number from RFC1754 to RFC2819. 17, 23
Changed minimum OPB frequency supported to be that used by the EMAC. See 18, 101
Section 1.2, Features and also Section 5.7.1, Clock Frequencies
Changed paragraph to Note, to emphasis need for RESET_ON_READ must be 24, 92

turned off when counter(s) are set to max width (32 bits)
AddedCoreConnect Revision ID Register table. and Section 3.1.69, CoreConnect 28, 73

Revision ID Register description.
Changed RESET_ON_READ to 0 for default configuration. 92
Added to description for Section 5.3.2.5 , MIB Clocks 97
Changed description of minimum reset requirement in Section 5.2, Initialization 92

Sequence
Changed paragraph to Note to emphasize requirement for PHY clocks to be running 92

for reset initialization in Section 5.2, Initialization Sequence
Clarified description for Section 5.7.3, Nominal Power Dissipation 102
Added clarification that register bits will be removed during synthesis with DC. See 91
Section 5. , Core Integration
Added reference to need to substitute instance of 2-way and in module 101

MIB_SPECIAL_AND2. See Section 5.6, Cell Names and Associated Library Ele-
ments
Added description of and chip timing requirements for asynchronous crossing logic. 105
See Section A.3 , User-Defined Timing Constraints for Asynchronous Clock Domain
Crossings
Added description of User-Defined Timing Constraints (UDT) for asynchronous 105

clock domain crossings in Appendix A Asynchronous Interface
Revision 9 April, 2004 Reversed the bit order in the definition table for Section 3.1.62 67
MIB_INTERRUPT_STATUS_A.
Reversed the bit order in the definition table for Section 3.1.63 69
MIB_INTERRUPT_STATUS_B.
Updated Section 5.7.1 Clock Frequencies and changed minimum OPB clock fre- 101
quency for 10 Gbps mode in Table 10 Clock Frequencies.
Updated Section 5.7.3 Nominal Power Dissipation. 102
Revision 8 March, 2003 Changed aOctetsReceivedOK application to All Applications in Section 3.1.13 aOc- 38
tetsReceivedOK.
Added qualification to aPAUSEMACCTrlFramesTransmitted in Section 3.1.28 47

aPAUSEMACCtrlFramesTransmitted.
Changed the word ‘incremented’ to ‘loaded’ on RXVLANUserPriorityField in 60

Section 3.1.49 RXVLANUserPriorityField.
Added cc -E -C alternative to cpp for invoking C preprocessor in Section 5.1 Config- 91

urability.
Added Cu-11 information in Section 5.5.2 Technology and Section 5.7 Performance 101, 101
and Operating Environment.
Changed timing on EMAC interface Status signals in Table 7 EMAC MIB Interface 94
Signals.
In Section 5.3.2.6 Supplied Timing Constraints, added variables to EinsTimer 98
PHASE file definition.
Preface SA14-2434-11
IBM Core Databook
Revision 7 March, 2003 Added 3 counters for 10G applications: Section 1.2 Features, Section 3.1.66 17, 72, 72,
ReceivedWithCodeError, Section 3.1.67 TXLocalFault, Section 3.1.68 TXRemote- 73, 74, 91
Fault, Section 3.2 Interrupt Handling, Section 5.1 Configurability.
Updated references in Section 1.4 References to support 10G. 19
Updated Section 1.5 Additional Required Elements to support 10G. 20
Added indication of application to Table 1 MIB Counters and Registers Summary. 25

Added Write definition to Section 3.1.7 aOctetsTransmittedOK and Section 3.1.13 33, 38
aOctetsReceivedOK.
Added 10G information to Section 3.1.24 aSymbolErrorDuringCarrier. 45
Commented use of MIB_TX(RX)_RDY and OPB Sequential Address operations in 77, 88

Section 4.1 EMAC Interface and Section 4.2 OPB Interface.
Added Table 4 Transmit Status Word for 10 G Applications and Table 5 Receive 84, 86
Status Word for 10 G Applications to support 10G applications.
Updated text in Section 5 Core Integration. 91
Revision 6 June, 2002 Updated reference for etherStatsOctets in Table 1 MIB Counters and Registers 25
Summary.
Added Section 3.1.33 etherStatsOctets. 51

Added etherStatsOctets to Section 3.3 Software Implementation. 75
Revision 5 March, 2001 Revised Section 5.3.2.6 Supplied Timing Constraints. 98
Revision 5 February, 2001 Updated bullet #5 in Section 3.2 Interrupt Handling. 74

Revision 5 January, 2001 Revised text throughout the book for clarity. —
Removed all references to Class 1 Power Management. —
Added Notation Conventions to the Preface. 14

Revised Section 1.2 Features. 17
Removed Transfer Size table from Section 4.2 OPB Interface. 88
Added Table 6 MIB - OPB Interface Signals to Section 4.2 OPB Interface. 89
Added Table 10 Clock Frequencies to Section 5.7.1 Clock Frequencies. 101
Updated information in Table 11 Extended Voltages and Extended Temperature 102

Ranges in Section 5.7.1 Clock Frequencies.
Core Databook IBM
Revision 4 November 2000 Replaced “58 counters” with “60 counters” in Section 3.1 Registers, and 23
added two paragraphs.
Updated “Notes” column in Table 1 MIB Counters and Registers Summary. 25
Added paragraph to Section 3.1.7 aOctetsTransmittedOK. 33
Added paragraph to Section 3.1.13 aOctetsReceivedOK. 38
Removed sentence from Section 3.1.35 etherStatsBroadcastPkts. 52
Removed sentence from Section 3.1.36 etherStatsMulticastPkts. 52
Replaced "Receive OK” with “Bad FCS in the received frame” in Section 3.1.38 53
etherStatsOversizePkts.
Changed “Optional” to “RFC Mandatory” for ether registers from Section 3.1.34 51—58
etherStatsPkts through Section 3.1.46 etherStatsPkts1024to1518Octets.
From Section 3.1.1 aFramesTransmittedOK through Section 3.1.46 29 - 58

etherStatsPkts1024to1518Octets, updated the status of “optional” or “mandatory”
for each register.
In Section 5.1 Configurability: 91

Replaced MIB0 with MIB.
Added DetherStatsBroadcastPkts_width=32 -DetherStatsMulticastPkts_width=32.
Removed last 2 sentences of paragraph 3.
Added paragraph.
In Section 5.5.1 Size: 101

Replaced “62 registers” with “64 registers”.
Replaced “2,155 latches” with “2,196 latches.”
Changed “width + 1 (interrupt status bit)” to “width + 1.”
Added bullet “60 interrupt status bits.”
Changed “TBD control logic latches” to “117 control logic latches.”
IBM Core Databook
Revision 3 October 2000 Changed EMACOPLE3 to EMACOPLE in Figure 1 Ethernet (RMON) MIB Core 19
Typical Application.
Changed each register from “Read” to “Read/Write” (with the exception of the 23
INTERRUPT, aOctetsTransmittedOK, and aOctetsReceivedOK registers) and
added further “Write” or “Read Only” information Section 3 Software Interface.
Added incrementation information to each register’s description in Section 3 Soft- 23

ware Interface.
Added “Minimum 0” to each register description of width.
Updated Section 3.1 Registers. 23

In Table 1 MIB Counters and Registers Summary, changed Optional to N/A in the 25
Notes column for last four registers.
Updated register description in Section 3.1.7 aOctetsTransmittedOK. 33
Updated register description in Section 3.1.13 aOctetsReceivedOK. 38

Updated Section 3.1.35 etherStatsBroadcastPkts. 52
Updated Section 3.1.37 etherStatsCRCAlignErrors. 53
In Section 3.1.62 MIB_INTERRUPT_STATUS_A and Section 3.1.63 67—69

MIB_INTERRUPT_STATUS_B, removed “Optional”, removed interrupt handling
paragraph, changed access from “Read” to “Read Only,” added further “Read” infor-
mation, and a section 4.3 cross reference.
In Section 3.1.64 MIB_ENABLE_INTERRUPT_STATUS_A and Section 3.1.65 71, 71

MIB_ENABLE_INTERRUPT_STATUS_B, removed “Optional”, removed interrupt
handling paragraph and inserted a section 4.3 cross reference.
In Section 3.1.65 MIB_ENABLE_INTERRUPT_STATUS_B, removed “Optional”. 71
Added Section 3.2 Interrupt Handling. 74
In Section 4.1 EMAC Interface, added text to the end of the section. 77
Updated, and added text to Section 5.1 Configurability. 91
Updated Section 5.5.1 Size. 101
Added Section 5.3.2.6 Supplied Timing Constraints. 98
In Section 5.2 Initialization Sequence, replaced MIB_MASK_INTERRUPT with 92

MIB_ENABLE_INTERRUPT_STATUS_A(_B) and inserted a section 4.3 cross ref-
erence.
Updated Table 9 MIB Clocks. 97
Added text to Section 5.4 Test Interface Requirements and Section 5.1.1 Intercon- 99
nect.
Changed MIB_INTERRUPT_STATUS_ENABLE_A(_B) to Entire
MIB_ENABLE_INTERRUPT_STATUS_A(_B). book
Core Databook IBM
Revision 2 August 2000 In Section 3.1 Registers, added information from the IEEE spec regarding multiple 23
error statuses.
Added text to counter sections, Section 3.1.1 aFramesTransmittedOK through 29—39
Section 3.1.14 aFramesLostDueToIntMACRcvError.
Added statement to end of Section 3.1.5 aFrameCheckSequenceErrors. 32
Added statement to end of Section 3.1.6 aAlignmentErrors. 32

Added statement to end of Section 3.1.20 aInRangeLengthErrors. 42
Added aRunts and aBursts (bits 30 and 31), and renumbered bits 6 - 31 in 67
Section 3.1.62 MIB_INTERRUPT_STATUS_A.
Removed aRunts and aBursts from Section 3.1.63 MIB_INTERRUPT_STATUS_B 69

(to be added to MIB_INTERRUPT_STATUS_A register), and renumbered the
remaining bits.
Changed offset address from 0xEC to 0xFC in Section 3.1.63 69
Changed offset address from 0xF0 to 0x100 in Section 3.1.64 71

MIB_ENABLE_INTERRUPT_STATUS_A.
Changed offset address from 0xF4 to 0x104 in Section 3.1.65 71

MIB_ENABLE_INTERRUPT_STATUS_B.
Added bullet # 6 in Section 4.2 OPB Interface. 88

Added Transfer Size table to Section 4.2 OPB Interface. 88
Added percentages to “Timing” column in Table 7 EMAC MIB Interface Signals, and 94
moved Inputs below Outputs in the table.
Updated Table 8 MIB OPB Interface Signals with Timing. 96
In Section 5.2 Initialization Sequence, added reset information. 92
Added 2 paragraphs to Section 5.1.1 Interconnect. 92
Added phrase “for the maximum configuration” to Section 5.7.3 Nominal Power Dis- 102
sipation.
Replaced all references to “EMAC3” with “EMAC”. Entire

book
IBM Core Databook
Revision 1 June 2000 In Section 1.2 Features, changed 12.5 MHz to 25 MHz for 100 Mpbs medium, and 17
changed 1.25 MHz to 2.5 MHz for 10 Mbps medium.
Updated Figure 2 Ethernet MIB Block Diagram. 21
Added information re aOctetsTransmittedOK and aOctetsReceivedOK registers to 23

Section 3.1 Registers.
In Table 1 MIB Counters and Registers Summary, MIB Register Summary, renum- 25
bered Address Offsets.
Added Section 3.1.7 aOctetsTransmittedOK and Section 3.1.13 aOctetsReceive- 33, 38

dOK.
From Section 3.1.7 aOctetsTransmittedOK through Section 3.1.59 TXFrameP- 33—65

ausedByControlPacket, renumbered Address Offsets.
Renumbered bits and Address Offsets in Section 3.1.62 67

MIB_INTERRUPT_STATUS_A.
Renumbered bits and Address Offsets in Section 3.1.63 69

Added EMC_TX(RX)_FRAME_BYTES to Figure 3 EMAC - MIB Interface and Fig- 77

ure 4 EMAC - MIB Timing Diagram.
Added text to Section 4.2 OPB Interface. 88
Added aOctetsTransmittedOK and aOctetsReceivedOK register information to 101

Section 5.5.1 Size.
Updated pin names in Table 7 EMAC MIB Interface Signals. 94
Updated inputs in Table 9 MIB Clocks. 97
Added name clarification to Section 5.1.1 Interconnect. 92
In Section 5.7.1 Clock Frequencies, changed 12.5 MHz to 25 MHz at 100 Mbps, 101
and 1.25 MHz to 2.5 MHz at 10 Mbps.
Preliminary Copy March 2000 Initial release. —
Core Databook IBM
Notation Conventions
Unless otherwise specified, the notation used throughout this document is consistent with IBM PowerPC®
processor family notation, except when discussing the EMAC interface. These conventions include the fol-
lowing:
Term Description
byte Refers to an 8-bit entity.
halfword Refers to a 16-bit entity.
fullword Refers to 32-bit entity.
word Refers to a 32-bit entity.
doubleword Refers to a 64-bit entity.
quadword Refers to a 64-bit entity.
most significant bit (MSb) When describing multiple bit entities, bit 0 refers to the most significant bit (MSb).
least significant bit (LSb) When describing multiple bit entities, the highest numbered bit is the least significant bit (LSb).
most significant byte (MSB) When referring to halfword (16-bit) entities, byte 0 refers to the most significant byte (MSB) or the
high byte of the halfword. It is accessed at an even address location.
least significant byte (LSB) When referring to halfword (16-bit) entities, byte 1 refers to the least significant byte (LSB) of the
halfword, or the low byte. It is accessed at an odd address location.
byte significance - 32 bit entities For 32-bit entities, the byte significance is from most significant to least significant as follows:
Byte 0 (MSB)
Byte 1
Byte 2
Byte 3 (LSB)
IBM Core Databook
Terms and Abbreviations
Term/Abbreviation Definition
EMAC In this book EMAC refers to both EMAC3 and EMAC4.
FCS Frame Check Sequence
FIFO First-in First-out memory element. Can be of various sizes. Used for data buffering.
Framing bits The part of the receiving/transmitting frame that contains the preamble and the start-of-frame delimiter
fields.
FrameSize The number of octets of receiving/transmitting frame excluding preamble and start-of-frame delimiters
fields.
minFrameSize is equal to 64.
maxFrameSize is equal:
-1518 octets for standard frame (with no VLAN and jumbo packet support)
-1522 octets for standard frame (with VLAN support)
-9018 octets for standard frame (with jumbo packet support)
-9022 octets for standard frame (with VLAN and jumbo packet support)
MBps Megabytes per second
Mbps Megabits per second
Medium The 802.3 standard uses the word medium to refer to the wire (or fiber) that links nodes.
Packet A unit of data and control signals that is transmitted as a composite whole.
Physical Layer Device (PHY) Official term for Ethernet transceiver. The PHY contains the analog circuitry necessary to communi-
cate with the physical medium.
POR Power-On Reset

RMON Remote Network Monitoring Management Information Base. RMON is a Simple Network Management
Protocol (SNMP) Management Information Base (MIB) for remote management of networks. In con-
trast with other MIBs, typically created to support a network device whose primary function is other
than management, RMON’s primary function is network management.
Rx Receive. Refers to the data flow direction, from the media and into the IBM application.
Tx Transmit. Refers to the data flow direction, from the IBM application and into the media.
Core Databook IBM
IBM Core Databook
1. Overview
1.1 Introduction
The Ethernet Management Information Base core (MIB) contains a set of statistical counters that, as an On-
Chip Peripheral Bus (OPB) slave, are read via the OPB. It is a highly configurable synthesizable core that
interfaces with the Ethernet Media Access Controller (EMAC) core and the OPB. It consists of a set of statis-
tical counters used by software to keep track of events on the Ethernet bus.
The MIB implements various MACEntity managed object class counters listed in Section 1.2 Features, in
addition to other optional statistical counters.
1.2 Features
• Implements the IEEE Standard 802.3 Clause 30 MACEntity managed object class, the MACControlEntity
managed object class, the PHYEntity managed object class, and the PAUSEEntity managed object class
of the IEEE Standard 802.3 Clause 30 of statistical counters, for a total of 27 counters.
• Implements the following etherStats statistical counters of the RFC 2819 RMON MIB. (Counters not listed
in this category are not implemented.)
— etherStatsPkts
— etherStatsBroadcastPkts
— etherStatsMulticastPkts
— etherStatsCRCAlignErrors
— etherStatsOversizePkts
— etherStatsJabbers
— etherStatsCollisions
— All of the etherStatsPktsxxOctets counters
• Uses the extensive error/status vectors from the EMAC.
• Each counter can be read via an address on the OPB.
• Can be customized by using its available configurable options:

— Individual counters can be chosen for implementation by the user according to the application.
— Width of the counters can be chosen for implementation by the user according to the application, up
to a maximum width equal to the OPB width (32 bits). This allows for a combined hardware/software
solution.
— Optional reset on Read across all counters
• Implements 21 optional statistical counters:

— aShortEvents (in the IEEE 802.3 RepeaterPort managed object class)
— aRunts (in the IEEE 802.3 RepeaterPort managed object class)
— aBursts (in the IEEE 802.3 RepeaterPort managed object class)
— ReceivedInLoopBackMode
SA14-2434-11 Overview
Core Databook IBM
— RXVLANTaggedFrame
— RXVLANUserPriorityField (this is a register, not a counter)
— RXUnicastAddr
— RXFIFOOverrun
— TXPkts64Octets
— TXPkts65to127Octets
— TXPkts1024toMaxSizeOctets
— TXBadFCS
— TXFramePausedByControlPacket
— TXUnicastAddr
— TXFIFOUnderrun
— ReceivedWithCodeError
— TXLocalFault
— TXRemoteFault
• No embedded arrays required: the counters are implemented as latches.
• IBM CoreConnect™ support of the OPB at a width of 32 bits

— Supports 2-clock-cycle access
• OPB interface operates from 33 MHz (10 MHz in 1 Gbps mode) to 133 MHz.
• EMAC interface operates at the PHY clock rate:

— For 10 Gbps medium - 156 MHz
— For 100 Mbps medium - 25 MHz
— For 10 Mbps medium - 2.5 MHz
• Synthesis scripts and timing assertions available.
Overview SA14-2434-11
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IBM Core Databook
1.3 Typical Applications

Figure 1. Ethernet (RMON) MIB Core Typical Application
PLB
MAL OPB Bridge
MAL Interface OPB Interface
RX TX1 TX0
Rx FIFO
Control Logic
(EMACOPLE)
Tx FIFO
EMAC
Ethernet MAC
RMON/MIB
(GMAC)
MII/GMII/XGMII Interface
Physical
Layer Device
The MIB is used with the Ethernet Media Access Controller (EMAC) in a superstructure design.
1.4 References
IEEE 802.3 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method & Physical
Layer Specifications, 2002 Edition
Request For Comment 2819, Remote Network Monitoring Management Information Base, May 2000
On-Chip Peripheral Bus Architecture Specifications, SA14-2528-02, Version 2.1, April 2001
Ethernet Media Access Controller3 (EMAC3), SA14-2322-02, Revision 2, 2/25/2002
Ethernet Media Access Controller4 (EMAC4), SA14-2480-03, Revision 3, 9/30/2002
Ethernet 10 Gbps MAC Extended (XEMAC), SA15-5717-00, Preliminary, 11/6/2002
SA14-2434-11 Overview
Core Databook IBM
1.5 Additional Required Elements

The following elements are required according to the required application.
• Ethernet 10/100 (EMAC3)
• Ethernet 10/100/1000 (EMAC4)
• Ethernet 10Gbps Extended MAC (XEMAC)
• All elements required by the selected EMAC
Overview SA14-2434-11
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IBM Core Databook
2. Functional Description
The MIB acts as a temporary storage area that records a statistical history of data activity performed by the
interfacing EMAC core. This statistical data is stored in configurable statistical counters that accumulate a
historical record of the data activity and is read by the OPB.
The MIB consists of an EMAC interface that provides the communication between the MIB and EMAC. The
statistical data is fed through the EMAC interface and stored in the statistical counters. When the data is
requested by the OPB, the data is read out of the statistical counters, routed through the OPB slave, and read
by the OPB.
Each counter can be read via an address on the OPB. Due to the high configurability options of the MIB
implementation, a strategic set of statistical data can be accumulated to fine tune the database to the desired
application.
The MIB core utilizes CoreConnect support of the OPB at a width of 32 bits.
Figure 2. Ethernet MIB Block Diagram
MIB
Statistical Statistical Counters

Read
Data (REGFILE) Data
EMAC
interface
(EMACMIB) OPB
Slave OPB
RX (MIBOPB)
TX
To
EMAC
OPB Clock Domain
PHY Clock Domain
SA14-2434-11 Functional Description

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Functional Description SA14-2434-11

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IBM Core Databook
3. Software Interface
The MIB behaves as a standard OPB slave in compliance with the On-Chip Peripheral Bus Architecture
Specifications (see Section 1.4 References on page 19). It is a set of statistical counters that, as an OPB
slave, are read via the OPB.
The 23 most significant bits of the OPB address are compared with the content of the OPB_HRDW_ADDR
bus to distinguish between transactions targeted for the MIB and those intended for other OPB slave devices.
The nine least significant bits of the OPB address define the specific counters within the MIB. In full configura-
tion, the MIB supports the sequential address mechanism for more efficient utilization of the OPB interface.
3.1 Registers
Because the MIB counters are accessed through the OPB, access to the counters must be full-word aligned.
The reason for this is because smaller accesses could reset the counters (that is, after one byte is read, the
counter can change values before another is read, affecting all bytes). A byte or halfword operation to any
counter is treated by the MIB as a fullword operation. All counters are read only and have a power-on-reset
value of 0x0000_0000. All counters can be optionally reset by read operations by changing the configuration
in the Verilog defines file. Read operations from unused addresses return zeros.
The width of each counter can be selected at synthesis by the user according to the application, up to a
maximum width equal to the OPB width (32 bits - exception: see Section 3.1.7 aOctetsTransmittedOK on
page 33, Section 3.1.13 aOctetsReceivedOK on page 38, and Section 3.1.49 RXVLANUserPriorityField on
page 60). This allows for a combined hardware/software solution. For software implementation, a counter
width of 1 bit provides indications of an event. The interrupt register records which counters wrapped. A read
of a nonexistent counter (width of 0) returns a 0.
In Table 1 on page 25, “MIB Register Summary,” counters listed as “mandatory” are required by either the
IEEE specification or the RFC specification, and MUST be implemented in either hardware or in software.
Please reference the respective specifications. The choice, however, of hardware or software is application
dependent. Counters listed as “optional” need not be implemented in either hardware or software unless
required by the application. The “mandatory” and “optional” terms in the referenced specifications indicate the
requirement for a Full Function Ethernet NIC design with Universal Device Driver support.
Counters with names of type ‘aXXXX’ and marked “mandatory” are required according to IEEE 8.2.3 Clause
30, but can be implemented in hardware or software, or a combination, according to the application. Counters
with names of type ‘etherStatsXXXX’ and marked ‘mandatory’ are required according to RFC 2819 RMON
MIB, but can be implemented in hardware or software, or a combination, according to the application. All
other counters are optional and can be implemented in hardware or software, or a combination, according to
the application. If all counters are synthesized, there are a total of 60 counters in the MIB, with an additional 2
counters already implemented in the EMAC. See the EMAC3 specification for further details, Section 4.21,
“Transmit Octets,” and Section 4.22, “Receive Octets.”
The OPB address for a counter remains the same no matter what size counter is implemented.
If a counter is implemented in software, a read at the OPB address reserved for that counter in hardware will
return all 0s. The read address for the software implemented counter will depend on the individual applica-
tion.
If a counter is implemented both in hardware and software, a read at the OPB address for the hardware
section of the counter will return a number that must be added to that portion of the counter value imple-
mented in software to obtain the full counter value.
SA14-2434-11 Software Interface

Core Databook IBM
Note: If an IEEE-specified counter (‘aXXX’ type) is to be 32 bits in hardware, it cannot be reset when
read, according to the referenced specification. In this case, the MIB must be configured with the reset on
read function disabled.
From the IEEE Specification, Section 30.2.2.2.1 DTE MAC Sublayer Functions: “. . . with regard to reception-
related error statistics a hierarchical order has been established such that when multiple error statuses can
be associated with one frame, only one status is returned . . . .” This hierarchy in descending order is as
follows:
• frame Too Long
• alignment Error
• frameCheckError
• lengthError
“The counters are primarily incremented based on the status returned to the MAC client; therefore, the hierar-
chical order of the counters is determined by the order of the status.” For the MIB core, this means that if
multiple status events occur for received frames on the EMC_RX_STATUS bus, the following priority is used
to increment the counters:
• FrameTooLong
• AlignmentError
• BadFCSReceivedFrame
• InRangeLengthError
For example, the alnRangeLengthErrors counter will be incremented only if FrameTooLong, AlignmentError,
and BadFCSReceivedFrame are not reported on the EMC_RX_STATUS bus at the same time. See further
details in Section 3.1.5 aFrameCheckSequenceErrors on page 32, Section 3.1.6 aAlignmentErrors on
page 32, and Section 3.1.20 aInRangeLengthErrors on page 42.
Software Interface SA14-2434-11

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IBM Core Databook
Table 1. MIB Counters and Registers Summary (Page 1 of 4)
Register Name Address Specification Application See

Offset Requirements
aFramesTransmittedOK 00 IEEE Mandatory All Section 3.1.1 aFramesTransmittedOK on

page 29
aSingleCollisionFrames 04 IEEE Mandatory 10/100/1000 Section 3.1.2 aSingleCollisionFrames on

page 30
aMultipleCollisionFrames 08 IEEE Mandatory 10/100/1000 Section 3.1.3 aMultipleCollisionFrames on

page 30
aFramesReceivedOK 0C IEEE Mandatory All Section 3.1.4 aFramesReceivedOK on

page 31
aFrameCheckSequenceErrors 10 IEEE Mandatory All Section 3.1.5 aFrameCheckSequenceEr-

rors on page 32
aAlignmentErrors 14 IEEE Mandatory 10/100 Section 3.1.6 aAlignmentErrors on page 32
aOctetsTransmittedOKLOW 18 IEEE Optional All Section 3.1.7 aOctetsTransmittedOK on

aOctetsTransmittedOKHIGH 1C page 33
aFramesWithDeferredXmissions 20 IEEE Optional 10/100/1000 Section 3.1.8 aFramesWithDeferredXmis-

sions on page 34
aLateCollisions 24 IEEE Optional 10/100/1000 Section 3.1.9 aLateCollisions on page 34
aFramesAbortedDueToXSColls 28 IEEE Optional 10/100/1000 Section 3.1.10 aFramesAbortedDueToX-

SColls on page 35
aFramesLostDueToIntMACXmitError 2C IEEE Optional All Section 3.1.11 aFramesLostDueToInt-

MACXmitError on page 36
aCarrierSenseErrors 30 IEEE Optional 10/100/1000 Section 3.1.12 aCarrierSenseErrors on

page 37
aOctetsReceivedOKLOW 34 IEEE Optional All Section 3.1.13 aOctetsReceivedOK on

aOctetsReceivedOKHIGH 38 page 38
aFramesLostDueToIntMACRcvError 3C IEEE Optional All Section 3.1.14 aFramesLostDueToInt-

MACRcvError on page 39
aMulticastFramesXmittedOK 40 IEEE Optional All Section 3.1.15 aMulticastFramesXmittedOK

on page 40
aBroadcastFramesXmittedOK 44 IEEE Optional All Section 3.1.16 aBroadcastFramesXmitte-

dOK on page 40
aFramesWithExcessiveDeferral 48 IEEE Optional 10/100/1000 Section 3.1.17 aFramesWithExcessiveDe-

ferral on page 41
aMulticastFramesReceivedOK 4C IEEE Optional All Section 3.1.18 aMulticastFramesReceive-

dOK on page 41
aBroadcastFramesReceivedOK 50 IEEE Optional All Section 3.1.19 aBroadcastFramesReceive-

dOK on page 42
aInRangeLengthErrors 54 IEEE Optional All Section 3.1.20 aInRangeLengthErrors on

page 42
aOutOfRangeLengthField 58 IEEE Optional All Section 3.1.21 aOutOfRangeLengthField on

page 43

Core Databook IBM

Offset Requirements
aFrameTooLongErrors 5C IEEE Optional All Section 3.1.22 aFrameTooLongErrors on

page 43
aSQETestErrors 60 IEEE Optional 10 Section 3.1.23 aSQETestErrors on page 44
aSymbolErrorDuringCarrier 64 IEEE Optional All Section 3.1.24 aSymbolErrorDuringCarrier

on page 45
aMACControlFramesTransmitted 68 IEEE Optional All Section 3.1.25 aMACControlFramesTrans-

mitted on page 46
aMACControlFramesReceived 6C IEEE Optional All Section 3.1.26 aMACControlFramesRe-

ceived on page 46
aUnsupportedOpcodesReceived 70 IEEE Optional All Section 3.1.27 aUnsupportedOpcodesRe-

ceived on page 47
aPAUSEMACCtrlFramesTransmitted 74 IEEE Optional All Section 3.1.28 aPAUSEMACCtrl-

FramesTransmitted on page 47
aPAUSEMACCtrlFramesReceived 78 IEEE Optional All Section 3.1.29 aPAUSEMACCtrlFramesRe-

ceived on page 48
aShortEvents 7C IEEE Optional 10/100/1000 Section 3.1.30 aShortEvents on page 48
aRunts 80 IEEE Optional All Section 3.1.31 aRunts on page 49
aBursts 84 IEEE Optional 1000 Section 3.1.32 aBursts on page 50
etherStatsDropEvents - Not supported -

RFC Mandatory
etherStatsOctets - Implemented in All Section 3.1.33 etherStatsOctets on page 51

EMAC RFC
Mandatory
etherStatsPkts 88 RFC Mandatory All Section 3.1.34 etherStatsPkts on page 51
etherStatsBroadcastPkts 8C RFC Mandatory All Section 3.1.35 etherStatsBroadcastPkts on

page 52
etherStatsMulticastPkts 90 RFC Mandatory All Section 3.1.36 etherStatsMulticastPkts on

page 52
etherStatsCRCAlignErrors 94 RFC Mandatory All Section 3.1.37 etherStatsCRCAlignErrors on

page 53
etherStatsUndersizePkts - Not supported -

RFC Mandatory
etherStatsOversizePkts 98 RFC Mandatory All Section 3.1.38 etherStatsOversizePkts on

page 53
etherStatsFragments - Not supported -

RFC Mandatory
etherStatsJabbers 9C RFC Mandatory All Section 3.1.39 etherStatsJabbers on

page 54
etherStatsCollisions A0 RFC Mandatory 10/100/1000 Section 3.1.40 etherStatsCollisions on

page 54

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IBM Core Databook

Offset Requirements
etherStatsPkts64Octets A4 RFC Mandatory All Section 3.1.41 etherStatsPkts64Octets on

page 55
etherStatsPkts65to127Octets A8 RFC Mandatory All Section 3.1.42 etherStatsPkts65to127Octets

on page 55
etherStatsPkts128to255Octets AC RFC Mandatory All Section 3.1.43

etherStatsPkts128to255Octets on page 56
etherStatsPkts256to511Octets B0 RFC Mandatory All Section 3.1.44



etherStatsPkts1024to1518Octets on
page 58
ReceivedInLoopBackMode BC Optional All Section 3.1.47 ReceivedInLoopBackMode

on page 59
RXVLANTaggedFrame C0 Optional All Section 3.1.48 RXVLANTaggedFrame on

page 59
RXVLANUserPriorityField C4 Optional All Section 3.1.49 RXVLANUserPriorityField on

page 60
RXUnicastAddr C8 Optional All Section 3.1.50 RXUnicastAddr on page 60
RXFIFOOverrun CC Optional All Section 3.1.51 RXFIFOOverrun on page 61
TXPkts64Octets D0 Optional All Section 3.1.52 TXPkts64Octets on page 61
TXPkts65to127Octets D4 Optional All Section 3.1.53 TXPkts65to127Octets on

page 62
TXPkts128to255Octets D8 Optional All Section 3.1.54 TXPkts128to255Octets on

page 62
TXPkts256to511Octets DC Optional All Section 3.1.55 TXPkts256to511Octets on

page 63
TXPkts512to1023Octets E0 Optional All TXPkts512to1023 figure
TXPkts1024toMaxSizeOctets E4 Optional All Section 3.1.57 TXPkts1024toMaxSizeOctets

on page 64
TXBadFCS E8 Optional All Section 3.1.58 TXBadFCS on page 65
TXFramePausedByControlPacket EC Optional 10/100/1000 Section 3.1.59 TXFramePausedByControl-

Packet on page 65
TXUnicastAddr F0 Optional All Section 3.1.60 TXUnicastAddr on page 66
TXFIFOUnderrun F4 Optional All Section 3.1.61 TXFIFOUnderrun on page 66
MIB_INTERRUPT_STATUS_A F8 Optional All Section 3.1.62

MIB_INTERRUPT_STATUS_A on page 67
MIB_INTERRUPT_STATUS_B FC Optional All Section 3.1.63

MIB_INTERRUPT_STATUS_B on page 69

Core Databook IBM

Offset Requirements
MIB_ENABLE_INTERRUPT_STATUS_A 100 Optional All Section 3.1.64

MIB_ENABLE_INTERRUPT_STATUS_A on
page 71
MIB_ENABLE_INTERRUPT_STATUS_B 104 Optional All Section 3.1.65

MIB_ENABLE_INTERRUPT_STATUS_B on
page 71
ReceivedWithCodeError 84 Optional 10G Section 3.1.66 ReceivedWithCodeError on

page 72
TXLocalFault 04 Optional 10G Section 3.1.67 TXLocalFault on page 72
TXRemoteFault 08 Optional 10G Section 3.1.68 TXRemoteFault on page 73
CoreConnect Revision ID Register 108 All All Section 3.1.69, CoreConnect Revision ID
Register, on page 73

120
IBM Core Databook
3.1.1 aFramesTransmittedOK
Address Offset: 0x00
Width: Minimum 1, maximum is width of OPB (32)
Reset Value: 0x0000_0000
Access: Read/Write
IEEE Mandatory
All applications
This counter gives the number of frames that are transmitted successfully. It is incremented when EMAC
EMC_TX_STATUS (0), TransmitOK is set and activates if none of the following events are discovered during
transmission:
• Collision
• Late collision
• Loss of carrier sense
• Excessive deferral
• Bad FCS
• Tx FIFO Handler interrupted transmit process
• SQE error (for HDX 10 Mbps only)
This counter is not incremented if aFramesLostDueToIntMACXmitError is to be incremented at the same

time.
If a write is done during normal operation, the existing value will be over written. A write to this counter is only
for bring-up and testing of the counters and interrupt mechanism. Only a Fullword write can be used on the
OPB via the OPB protocol.

Core Databook IBM
3.1.2 aSingleCollisionFrames
Access: Read/Write
IEEE Mandatory
10/100/1000 Applications
This counter gives the number of frames that are involved in a single collision and are then transmitted
successfully. It is incremented when the transmitted frame collides with other data on the bus just once. This
increment only applies in half-duplex mode. This counter is not incremented if aFramesLostDueToInt-
MACXmitError is to be incremented at the same time.
3.1.3 aMultipleCollisionFrames
Access: Read/Write
IEEE Mandatory
This counter gives the number of frames that are involved in more than one collision and are then transmitted
successfully. It is incremented when the transmitted frame collides with other data on the bus more than
once, but less than16 times. This is applicable only in half-duplex mode.

time.

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IBM Core Databook
3.1.4 aFramesReceivedOK
Address Offset: 0x0C
Access: Read/Write
IEEE Mandatory
All applications
This counter gives the number of frames that are received successfully (receiveOK). It increments if none of
the following events is discovered during reception:
• Receive FIFO Handler interrupted receive process
• FCS error Length mismatch error
• Frames too long
• Alignment errors
• Received with symbol error
• Short event
This counter is not incremented if aFramesLostDueToIntMACRcvError is to be incremented at the same time.

Core Databook IBM
3.1.5 aFrameCheckSequenceErrors
Access: Read/Write
IEEE Mandatory
All applications
This counter gives the number of receive frames that are an integral number of octets in length and do not
pass the FCS check. This does not include frames received with frame-too-long, or frame-too-short error. The
counter is incremented when a received frame has an FCS value which does not match the FCS value calcu-
lated by EMAC.
This counter is not incremented if aFramesLostDueToIntMACRcvError is to be incremented at the same time,

or if FrameTooLong and AlignmentError are reported at the same time. See Section 3.1 Registers on
page 23 for a description of priority.
3.1.6 aAlignmentErrors
Access: Read/Write
IEEE Mandatory
10/100 Applications
This counter gives the number of frames that are not an integral number of octets in length and do not pass
the FCS check. It is incremented when the received frame does not have an integral number of octets in
length. It is applicable only on 10/100 Mbps medium.
This counter is not incremented if aFramesLostDueToIntMACRcvError is to be incremented at the same time,

or if FrameTooLong is reported at the same time. See Section 3.1 Registers on page 23.

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IBM Core Databook
3.1.7 aOctetsTransmittedOK
aOctetsTransmittedOKLOW
aOctetsTransmittedOKHIGH
Address Offset: 0x18, 0x1C
Width: Minimum 14, maximum width of each is width of OPB (32), overall maximum is 64 bits
Reset Value: 0x0000_0000, 0x0000_0000
Access: Read/Write
IEEE Optional
All applications
aOctetsTransmittedOKLOW is bits (31 down to 0) of aOctetsTransmittedOK. aOctetsTransmittedOKHIGH is

bits (63 down to 32) of aOctetsTransmittedOK.
This counter gives the number of data and padding octets of frames that are successfully transmitted. This
counter is updated when the TransmitStatus is reported as transmitOK, by adding the value on
EMC_TX_Frame_Bytes to the value in this counter. This counter is not incremented if aFramesLostDueToInt-
If a write is done during normal operation, the existing value is overwritten. A write to this counter is only for
bring-up and testing of the counters and interrupt mechanism. Only a Fullword write can be used on the OPB
via the OPB protocol. A write to the HIGH address, offset 0x1C, causes the OPB value to be written into the
LOW part of the counter and all 0’s to the HIGH part of the counter. This allows for testing of the carry over
from the LOW part of the counter to the HIGH part of the counter. It also allows for the reset of the counter
during testing. A write to the LOW address, offset 0x18, causes the OPB value to be written into the LOW part
of the counter and all 1’s to the HIGH part of the counter. This allows for testing of the overflow from the
counter, and setting of the corresponding interrupt status bit.

Core Databook IBM
3.1.8 aFramesWithDeferredXmissions
Access: Read/Write
IEEE Optional
This counter gives the number of frames whose first transmission attempt was delayed because the medium
was busy. It is incremented when the current frame transmission is deferred due to activity on the medium on
its first transmission attempt. (Note that if EMAC waits until the end of the IFG period without indicating an
active medium, the frame is not considered a deferred frame.) This is applicable only in half-duplex mode.

time.
3.1.9 aLateCollisions
Access: Read/Write
IEEE Optional
This counter gives the number of times that a collision is detected later than one slotTime from the start of the
packet transmission. A late collision is counted twice, that is, both as a collision and as a lateCollision. This
counter is incremented when the frame collided with other data outside of the collision window. This is appli-
cable only in half-duplex mode.

time.

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IBM Core Databook
3.1.10 aFramesAbortedDueToXSColls
Access: Read/Write
IEEE Optional
This counter gives the number of frames that are not transmitted successfully due to excessive collisions. It is
incremented when the current frame transmission had ended with a collision at the 16th consecutive attempt.
This is applicable only in half-duplex mode.

time.

Core Databook IBM
3.1.11 aFramesLostDueToIntMACXmitError
Access: Read/Write
IEEE Optional
All applications
This counter gives the number of frames that could not be transmitted by the station because of an internal
MAC sublayer transmit error. If this counter is incremented, none of the other counters in this section are
incremented. Counters “in this section” refer to the MACEntity Managed Object Class as defined in IEEE
802.3 Clause 30 in both Table 30-1 and Section 30.3.1 MAC entity managed object class:
aFramesTransmittedOK
aSingleCollisionFrames
aMultipleCollisionFrames
aFramesReceivedOK
aFrameCheckSequenceErrors
aAlignmentErrors
aOctetsTransmittedOK
AFramesWithDeferredXmissions
aLateCollisions
aFramesAbortedDueToXSColls
aCarrierSenseErrors
aOctetsReceivedOK
This counter is incremented when the transmit is interrupted internally within EMAC.

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IBM Core Databook
3.1.12 aCarrierSenseErrors
Access: Read/Write
IEEE Optional
During the transmission of a frame without collision, this counter gives the number of times that the carri-
erSense variable is not asserted or is deasserted. This counter is incremented when, during the transmission
of a frame, the PHY_CRS input is de-asserted after it previously was asserted, or it was not asserted at all. It
is applicable only in half-duplex mode; it is not incremented in full-duplex mode.

time.

Core Databook IBM
3.1.13 aOctetsReceivedOK
aOctetsReceivedOKLOW
aOctetsReceivedOKHIGH
Address Offset: 34, 38
Width: Minimum 14, maximum width of each is width of OPB (32), overall maximum is 64 bits
Reset Value: 0x0000_0000, 0x0000_0000
Access: Read
IEEE Optional
All Applications
aOctetsReceivedOKLOW is bits (31 down to 0) of aOctetsReceivedOK. aOctetsReceivedOKHIGH is bits (63

down to 32) of aOctetsReceivedOK.
This counter gives the number of data and padding octets in frames that are successfully received. This does
not include octets in frames received with frame-too-long, FCS, length or alignment errors, or frames lost due
to internal MAC sublayer error. This counter is updated when the result of a reception is reported as recei-
veOK status, by adding the value on EMC_RX_Frame_Bytes to the value in this counter.
If a write is done during normal operation, the existing value is overwritten. A write to this counter is only for
bring-up and testing of the counters and interrupt mechanism. Only a Fullword write can be used on the OPB
via the OPB protocol. A write to the HIGH address, offset 0x38, causes the OPB value to be written into the
LOW part of the counter and all 0’s to the HIGH part of the counter. This allows for testing of the carry over
from the LOW part of the counter to the HIGH part of the counter. It also allows for reset of the counter during
testing. A write to the LOW address, offset 0x34, causes the OPB value to be written into the LOW part of the
counter and all 1’s to the HIGH part of the counter. This allows for testing of the overflow from the counter,
and setting of the corresponding interrupt status bit.

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IBM Core Databook
3.1.14 aFramesLostDueToIntMACRcvError
Access: Read/Write
Optional
All applications
This counter gives the number of frames that are not received by the station due to an internal MAC sublayer
receive error. If this counter is incremented, none of the other counters in this section are incremented.
Counters “in this section” refer to the MACEntity Managed Object Class as defined in IEEE 802.3 Clause 30
in both Table 30-1 and Section 30.3.1 MAC entity managed object class:
aFramesTransmittedOK
aSingleCollisionFrames
aMultipleCollisionFrames
aFramesReceivedOK
aFrameCheckSequenceErrors
aAlignmentErrors
aOctetsTransmittedOK
AFramesWithDeferredXmissions
aLateCollisions
aFramesAbortedDueToXSColls
aCarrierSenseErrors
aOctetsReceivedOK
This counter is incremented when frame reception is interrupted internally within EMAC. This counter is not
incremented if aFramesLostDueToIntMACRcvError is to be incremented at the same time.

Core Databook IBM
3.1.15 aMulticastFramesXmittedOK
Access: Read/Write
Optional
All applications
This counter gives the number of frames that are successfully transmitted, to a group destination address
other than broadcast, as indicated by the status value transmitOK. It is incremented when the frame is trans-
mitted to a group destination address other than broadcast. This counter is not incremented if aFramesLost-
DueToIntMACXmitError is to be incremented at the same time.
3.1.16 aBroadcastFramesXmittedOK
Access: Read/Write
Optional
All applications
This counter gives the number of frames that are successfully transmitted to the broadcast address, as indi-
cated by the TransmitStatus transmitOK. Frames transmitted to multicast addresses are not broadcast
frames and are excluded. This counter is incremented when the frame is transmitted to the broadcast desti-
nation address. It is not incremented if aFramesLostDueToIntMACXmitError is to be incremented at the same
time.

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IBM Core Databook
3.1.17 aFramesWithExcessiveDeferral
Access: Read/Write
Optional
This counter gives the number of frames that are deferred for an excessive period of time. It may only be
incremented once per Logical Link Control (LLC) transmission and is incremented when the frame has been
deferred for an excessive period of time. The value of this period in bits is calculated in the following way:
• For 10 and 100 Mbps operation: 2 x (maxFrameSize x 8) bit times
• For 1000 Mbps operation: 2 x (burstLimit + maxFrameSize x 8 + headerSize) bit times
It is applicable only in half-duplex mode.

time.
3.1.18 aMulticastFramesReceivedOK
Access: Read/Write
Optional
All applications
This counter gives the number of frames that are received successfully and sent to an active, nonbroadcast
group address. This does not include frames received with frame-too-long, FCS, length or alignment errors,
or frames lost due to internal MAC sublayer error. This counter is incremented when the frame is received
with a group destination address other than broadcast and at least 6 bytes are received. This counter is not

Core Databook IBM
3.1.19 aBroadcastFramesReceivedOK
Access: Read/Write
IEEE Optional
All applications
This counter gives the number of frames that are received successfully and sent to the broadcast group
address. This does not include frames received with frame-too-long, FCS, length or alignment errors, or
frames lost due to internal MAC sublayer error. This counter is incremented when the frame is received with
the broadcast destination address and at least 6 bytes are received. This counter is not incremented if
aFramesLostDueToIntMACRcvError is to be incremented at the same time.
3.1.20 aInRangeLengthErrors
Access: Read/Write
IEEE Optional
All applications
This counter gives the number of frames with a length/type field value (between the minimum unpadded MAC
client data size and the maximum allowed MAC client data size, inclusive) that does not match the number of
MAC client data octets received. It also includes a count of frames whose length/type field value is less than
the minimum-allowed, unpadded MAC client data size and the number of MAC client data octets received is
greater than the minimum unpadded MAC client data size. The counter is incremented when the content of
the length field in the received frame is less or equal to the maximum allowed MAC client data size (1500
bytes). It is not incremented if FrameTooLong, and AlignmentError, and BadFCSReceivedFrame are
reported at the same time. It is not incremented if aFramesLostDueToIntMACRcvError is to be incremented
at the same time. See Section 3.1 Registers on page 23 for a description of priority.

120
IBM Core Databook
3.1.21 aOutOfRangeLengthField
Access: Read/Write
IEEE Optional
All applications
This counter gives the number of frames with a length field value greater than the maximum allowed LLC data
size. The counter is incremented when the received frame has a length field value greater than the maximum
allowed LLC data size (greater than 1500 and less than 1536). This counter is not incremented if
3.1.22 aFrameTooLongErrors
Access: Read/Write
IEEE Optional
All applications
This counter gives the number of frames received that exceed the maximum permitted frame size. It is incre-
mented when the length of the received frame exceeds the maximum allowed value (maxFrameSize). The
value of maxFrameSize is defined as:
Jumbo Packets Support Enabled VLAN Support Enabled maxFrameSize (bytes)
0 0 1518
0 1 1522
1 0 9018
1 1 9022

Core Databook IBM
3.1.23 aSQETestErrors
Access: Read/Write
IEEE Optional
10 Applications
This counter gives the number of times that the SQE_TEST_ERROR is set in accordance with the rules for
verification of the SQE detection mechanism in the PLS carrier sense function. The SQE test function is not a
part of 100 or 1000 Mbps or 10 Gbps PHY operation, so SQETestErrors will not occur in 100 or 1000 Mbps or
10 Gbps PHYs.
This counter is incremented when the Signal Quality Error test has failed. Following the end of a successful
EMAC transmission (ended with no collision), EMAC expects the PHY to assert the collision signal until the
end of the first part of the inter-frame-gap (IFG1). If collision is not asserted, EMAC indicates a signal quality
error. When the IGNORE_SQE_TEST bit in EMAC mode register 1 is set, SQE test is not performed.

time.
This counter is applicable only for the half-duplex 10 Mbps medium.

120
IBM Core Databook
3.1.24 aSymbolErrorDuringCarrier
Access: Read/Write
IEEE Optional
All applications
For 100 Mbps operation, this counter gives a count of the number of times when a valid carrier is present and
there is at least one occurrence of an invalid data symbol.
For half-duplex operation at 1000 Mbps, this counter gives a count of the number of times the receiving media
is non-idle (a carrier event) for a period of time equal to or greater than slotTime, and during which there was
at least one occurrence of an event that causes the PHY to indicate “data reception error” or “carrier extend
error” on the GMII.
For full-duplex operation at 1000 Mbps, this counter gives a count of the number of times the receiving media
is non-idle (a carrier event) for a period of time equal to or greater than minFrameSize, and during which
there is at least one occurrence of an event that causes the PHY to indicate “data reception error” on the
GMII.
For 10 Gbps operation, this counter gives a count of the number of times the receiving media is non-idle (the
time between the start and end of packet delimiter) for a period of time equal to or greater than minFrame-
Size, and during which there was at least one occurrence of an event that causes the PHY to indicate
‘Receiver Error’ on the XGMII.
At all speeds, this counter is incremented only once per valid CarrierEvent. If a collision is present, this
counter does not increment.
This counter is incremented as follows:
• For 100 Mbps operation, a valid carrier is present and there is at least one occurrence of data reception
error.
• For 1000 Mbps operation, the receiving media is non-idle (a carrier event) for a period of time greater
than or equal to slotTime for half-duplex, or greater than or equal to minFrameSize for full-duplex, and
during which there was at least one occurrence of an event that causes the PHY to indicate data recep-
tion error on the GMII.
• For 10 Gbps operation, the receiving media is non-idle (the time between the start and end of packet
delimiter) for a period of time equal to or greater than minFrameSize, and during which there was at least
one occurrence of an event that causes the PHY to indicate ‘Receiver Error’ on the XGMII.

Core Databook IBM
3.1.25 aMACControlFramesTransmitted
Access: Read/Write
IEEE Optional
All applications
This counter gives the number of MAC control frames passed for transmission to the MAC sublayer. This
counter is incremented when the currently transmitted frame is a control frame, but only if a control packet is
self-assembled by EMAC. This counter is not incremented if aFramesLostDueToIntMACXmitError is to be
incremented at the same time.
3.1.26 aMACControlFramesReceived
Access: Read/Write
IEEE Optional
All applications
This counter gives the number of MAC control frames passed by the MAC sublayer to the MAC control
sublayer. It is incremented when the currently received frame is a control frame. This counter is not incre-
mented if aFramesLostDueToIntMACRcvError is to be incremented at the same time.

120
IBM Core Databook
3.1.27 aUnsupportedOpcodesReceived
Access: Read/Write
IEEE Optional
All applications
This counter gives the number of received MAC control frames that contain an opcode not supported by the
device. It is incremented when the currently received frame was a control frame with unsupported opcode.
(See Ethernet Media Access Controller3 (EMAC), Section 2.6 Flow Control for more details.) This counter is
not incremented if aFramesLostDueToIntMACRcvError is to be incremented at the same time.
3.1.28 aPAUSEMACCtrlFramesTransmitted
Access: Read/Write
IEEE Optional
All applications
This counter gives the number of PAUSE frames passed to the MAC sublayer for transmission. It is incre-
mented when the currently transmitted frame is a pause frame. It activates only if a control packet is self-
assembled by EMAC. Packets are considered “Control” and/or “Pause Control” only according to the
length/type and opcode fields, and not according to the actual packet size (Control Pause packets have a
length of 64 bytes). This counter is not incremented if aFramesLostDueToIntMACXmitError is to be incre-
mented at the same time.

Core Databook IBM
3.1.29 aPAUSEMACCtrlFramesReceived
Access: Read/Write
IEEE Optional
All applications
This counter gives the number of MAC Control frames passed by the MAC sublayer to the MAC control
sublayer. It is incremented when the currently received frame is a control pause frame. This counter is not
3.1.30 aShortEvents
Access: Read/Write
IEEE Optional
This counter gives the number of CarrierEvent with ActivityDuration less than ShortEventMaxTime:
• In the 10 Mbps case, ShortEventMaxTime is greater than 74 bit time (BT) and less than 82 BT. Short-
EventMaxTime has tolerances included to provide for circuit losses between a conformance test point at
the AUI and the measurement point within the state diagram.
• In the 100 Mbps case, ShortEventMaxTime is 84 bits (21 nibbles).
• In the 1000 Mbps case, ShortEventMaxTime is 72 bits (9 octets).
This counter is incremented when the duration of the PHY_RX_DV signal is less than or equal to ShorEvent-
MaxTime. For this indication EMAC always assumes that the preamble and the SFD fields contain 8 bytes
regardless of the number actually received.

120
IBM Core Databook
3.1.31 aRunts
Access: Read/Write
IEEE Optional
All applications
This counter gives the number of CarrierEvent that meets one of the following conditions:
• The activityDuration is greater than ShortEventMaxTime and less than ValidPacketMinTime, and the Col-
lisionEvent signal is deasserted
• The OctetCount is less than 64, the ActivityDuration is greater than ShortEventMaxTime, and the Colli-
sionEvent signal is deasserted.
For 10 and 100 Mbps repeaters, ValidPacketMinTime is greater than or equal to 552 BT and less than 565
BT. A CarrierEvent greater than or equal to 552 BT but less than 565 BT may or may not be counted as a
runt.
At 10 Mbps, an event whose length is greater than 74 BT but less than 82 BT is counted as either aShort-
Events or aRunts, but not both. ValidPacketMinTime has tolerances included to provide for circuit losses
between a conformance test point at the AUI and the measurement point within the state diagram. For 1000
Mbps repeaters, ValidPacketMinTime is 4136 BT.
Runts usually indicate collision fragments, a normal network event. In certain situations associated with large
diameter networks, a percentage of runts may exceed ValidPacketMinTime.
This counter is incremented when the frame length is less than minFrameSize (64 bytes, excluding the
preamble and SFD bytes) and a Short Event is not detected.

Core Databook IBM
3.1.32 aBursts
Access: Read/Write
IEEE Optional
1000 Applications
This counter gives the number of CarrierEvent with ActivityDuration greater than or equal to slotTime during
which the CollisionEvent signal has not been asserted. It is incremented when the CarrierEvent (from the first
byte of DA until the end of transmission) is equal to or greater than slotTime. It is applicable only in half-
duplex mode in 1000 Mbps medium.

120
IBM Core Databook
3.1.33 etherStatsOctets
Address Offset: N/A
Width: 32
Access: Read Only
RFC Mandatory
All applications
This counter is implemented in the EMAC as the Receive Octets register. See the EMAC specification for the
address offset required to read this register.
This counter gives the total number of octets of data (including those in bad packets) received on the network
(excluding framing bits but including FCS octets). This counter can be used as a reasonable estimate of
ethernet utilization. If greater precision is desired, the etherStatsPkts and etherStatsOctets counters should
be sampled before and after a common interval. The differences in the sampled values are Pkts and Octets,
respectively, and the number of seconds in the interval is Interval. These values are used to calculate the
Utilization as follows:
Pkts * (9.6 + 6.4) + (Octets * 0.8)
Utilization = ---------------------------------------
Interval * 10,000
The result of this equation is the value Utilization which is the percent utilization of the ethernet segment on a
scale of 0 to 100 percent.
3.1.34 etherStatsPkts
Access: Read/Write
RFC Mandatory
All applications
This counter gives the total number of packets (including bad packets, broadcast packets, and multicast
packets) received. It is incremented when the EMAC signal EMC_RX_STATUS_VALID is asserted. This
counter is not incremented if aFramesLostDueToIntMACRcvError is to be incremented at the same time.

Core Databook IBM
3.1.35 etherStatsBroadcastPkts
Access: Read/Write
RFC Mandatory
All applications
This counter gives the total number of good packets received that were directed to the broadcast address.
This does not include multicast packets. This counter is incremented when the frame is received with the
broadcast destination address and at least 6 bytes are received. This counter is not incremented if
3.1.36 etherStatsMulticastPkts
Access: Read/Write
RFC Mandatory
All applications
This counter gives the total number of good packets received that were directed to a multicast address. This
number does not include packets directed to the broadcast address. It is incremented when the frame is
received with a group destination address other than broadcast and at least 6 bytes are received. This

120
IBM Core Databook
3.1.37 etherStatsCRCAlignErrors
Access: Read/Write
RFC Mandatory
All applications
This counter gives the total number of packets received that have a length (excluding framing bits, but
including FCS octets) of between 64 and 1518 octets, inclusive, but had either a bad Frame Check Sequence
(FCS) with an integral number of octets (FCS Error), or a bad FCS with a non-integral number of octets
(Alignment Error). It is incremented when Bad FCS in the received frame is detected (Neither Frame is too
long, Short event, nor Runt frame are active from EMAC)). This counter is not incremented if aFramesLost-
DueToIntMACRcvError is to be incremented at the same time.
3.1.38 etherStatsOversizePkts
Access: Read/Write
RFC Mandatory
All applications
This counter gives the total number of well-formed packets received that were longer than 1518 octets
(excluding framing bits, but including FCS octets). It is incremented when frame-too-long is detected and not
Bad FCS in the received frame, not In Range Length Error, not Out of Range Length error, not Received With
Symbol Error, not Alignment error, not Short Event, and not Runt Event are active from EMAC. This counter
is not incremented if aFramesLostDueToIntMACRcvError is to be incremented at the same time.

Core Databook IBM
3.1.39 etherStatsJabbers
Access: Read/Write
RFC Mandatory
All applications
This counter gives the total number of packets received that were longer than 1518 octets (excluding framing
bits, but including FCS octets), and had either a bad Frame Check Sequence (FCS) with an integral number
of octets (FCS Error) or a bad FCS with a non-integral number of octets (Alignment Error). This counter is
incremented when frame-too-long is set and Bad FCS in the received frame are active from EMAC. This
3.1.40 etherStatsCollisions
Address Offset: 0xA0
Access: Read/Write
RFC Mandatory
This counter gives the best estimate of the total number of collisions on this ethernet segment. It is incre-
mented when either Transmit OK, or Single Collision Frame, or Late Collision, or Excess Collisions is active
from EMAC. This counter is not incremented if aFramesLostDueToIntMACRcvError is to be incremented at
the same time.

120
IBM Core Databook
3.1.41 etherStatsPkts64Octets
Access: Read/Write
RFC Mandatory
All applications
This counter gives the total number of packets (including bad packets) received that were 64 octets in length
(excluding framing bits but including FCS octets). It is incremented when the currently received frame
(including bad frames) is 64 bytes in length (excluding framing bits but including FCS bytes). This counter is
not incremented if aFramesLostDueToIntMACRcvError is to be incremented at the same time.
3.1.42 etherStatsPkts65to127Octets
Access: Read/Write
RFC Mandatory
All applications
This counter gives the total number of packets (including bad packets) received that were between 65 and
127 octets in length inclusive (excluding framing bits but including FCS octets). It is incremented when the
currently received frame (including bad frames) was between 65 and 127 bytes in length (excluding framing
bits but including FCS bytes). This counter is not incremented if aFramesLostDueToIntMACRcvError is to be

Core Databook IBM
Address Offset: 0xAC
Access: Read/Write
RFC Mandatory
All applications
This counter gives the total number of packets (including bad packets) received that are between 128 and
currently received frame (including bad frames) is between 128 and 255 bytes in length (excluding framing
Address Offset: 0xB0
Access: Read/Write
RFC Mandatory
All applications

120
IBM Core Databook
Access: Read/Write
RFC Mandatory
All applications

Core Databook IBM
Access: Read/Write
RFC Mandatory
All applications
currently received frame (including bad frames) is between 1024 and maxFrameSize in length (excluding
framing bits but including FCS bytes).
0 0 1518
0 1 1522
1 0 9018
1 1 9022

120
IBM Core Databook
3.1.47 ReceivedInLoopBackMode
Address Offset: 0xBC
Access: Read/Write
Optional
All applications
This counter gives the number of frames received in the Loop Back mode of operation. It is incremented
when the currently received frame is an “echo” of a frame transmitted by EMAC. This counter is not incre-
mented if aFramesLostDueToIntMACRcvError is to be incremented at the same time.
3.1.48 RXVLANTaggedFrame
Address Offset: 0xC0
Access: Read/Write
Optional
All applications
This counter gives the number of VLAN tagged frames. It is incremented when the currently received frame
was a VLAN tagged frame. This counter is not incremented if aFramesLostDueToIntMACRcvError is to be

Core Databook IBM
3.1.49 RXVLANUserPriorityField
Width: 3 bits
Access: Read/Write
Optional
All applications
This is a register, not a counter. It contains the content of the user priority field from the currently received
VLAN tagged frame.
This register is not loaded if aFramesLostDueToIntMACRcvError is to be incremented at the same time.
3.1.50 RXUnicastAddr
Access: Read/Write
Optional
All applications
This counter gives the total number of good packets received that were directed to a unicast address. It is
incremented when the frame is received with a unicast destination address and at least 6 bytes are received.

120
IBM Core Databook
3.1.51 RXFIFOOverrun
Address Offset: 0xCC
Access: Read/Write
Optional
All applications
This counter gives the total number of received packets that created an overrun in the receive FIFO. It is
incremented when the current frame is aborted because an overrun-flow of received data applied to the FIFO
was detected, and the data was invalidated since there was no empty space in the receive FIFO. This counter
is not incremented if aFramesLostDueToIntMACRcvError is to be incremented at the same time.
3.1.52 TXPkts64Octets
Address Offset: 0xD0
Access: Read/Write
Optional
All applications
This counter gives the total number of packets (including bad packets) transmitted that were 64 octets in
length (excluding framing bits but including FCS octets). It is incremented when the currently transmitted
frame (including bad frames) is 64 bytes in length (excluding framing bits but including FCS bytes). This
counter is not incremented if aFramesLostDueToIntMACXmitError is to be incremented at the same time.

Core Databook IBM
3.1.53 TXPkts65to127Octets
Access: Read/Write
Optional
All applications
This counter gives the total number of packets (including bad packets) transmitted that are between 65 and
currently transmitted frame (including bad frames) is between 65 and 127 bytes in length (excluding framing
bits but including FCS bytes). This counter is not incremented if aFramesLostDueToIntMACXmitError is to be
Access: Read/Write
Optional
All applications
currently transmitted frame (including bad frames) is between 128 and 255 bytes in length (excluding framing
bits but including FCS bytes). This counter is not incremented if aFramesLostDueToIntMACXmitError is to be

120
IBM Core Databook
Address Offset: 0xDC
Access: Read/Write
Optional
All applications
511 octets in length inclusive (excluding framing bits but including FCS octets). This counter is incremented
when the currently transmitted frame (including bad frames) is between 256 and 511 bytes in length
(excluding framing bits but including FCS bytes). This counter is not incremented if aFramesLostDueToInt-
3.1.56 TXPkts512to1023
Address Offset: 0xE0
Access: Read/Write
Optional
All applications
currently transmitted frame (including bad frames) is between 512 and 1023 bytes in length (excluding
framing bits but including FCS bytes). This counter is not incremented if aFramesLostDueToIntMACXmitError
is to be incremented at the same time.

Core Databook IBM
3.1.57 TXPkts1024toMaxSizeOctets
Access: Read/Write
Optional
All applications
maxFrameSize in length inclusive (excluding framing bits but including FCS octets). It is incremented when
the currently transmitted frame (including bad frames) is between 1024 and maxFrameSize in length
(excluding framing bits but including FCS bytes). This counter is not incremented if aFramesLostDueToInt-
0 0 1518
0 1 1522
1 0 9018
1 1 9022

120
IBM Core Databook
3.1.58 TXBadFCS
Access: Read/Write
Optional
All applications
This counter gives the number of transmitted frames that are an integral number of octets in length and do not
pass the FCS check. It is incremented when a transmitted frame has an FCS value which does not match the
FCS value calculated by EMAC. This increment occurs only if the frame transmitted ended without interfer-
ence (that is, there was not a collision or a stop request during frame transmission). This counter is not incre-
mented if aFramesLostDueToIntMACXmitError is to be incremented at the same time.
3.1.59 TXFramePausedByControlPacket
Address Offset: 0xEC
Access: Read/Write
Optional
This counter gives the total number of frames paused by reception of a pause packet. It is incremented when
the currently transmitted frame is delayed before its start due to a pause packet received by EMAC. This
counter is not incremented if aFramesLostDueToIntMACXmitError is to be incremented at the same time.

Core Databook IBM
3.1.60 TXUnicastAddr
Address Offset: 0xF0
Access: Read/Write
Optional
All applications
This counter gives the total number of packets transmitted that are directed to a unicast address. It is incre-
mented when the frame is transmitted with a unicast destination address. This counter is not incremented if
aFramesLostDueToIntMACXmitError is to be incremented at the same time.
3.1.61 TXFIFOUnderrun
Access: Read/Write
Optional
All applications
This counter gives the total number of transmitted packets that created an underrun in the transmit FIFO. It is
incremented when the current frame is aborted because an underrun-data indication from the FIFO was not
valid in time to allow continuous data transmission on the MII/GMII interface. This counter is not incremented
if aFramesLostDueToIntMACXmitError is to be incremented at the same time.

120
IBM Core Databook
3.1.62 MIB_INTERRUPT_STATUS_A
Width: 32 bits
Access: Read/Write
Optional
All applications
This register records which counters wrapped within address offsets 00 through 84. See Section 3.1.1
aFramesTransmittedOK on page 29 through Section 3.1.34 etherStatsPkts on page 51.
See Section 3.2 Interrupt Handling on page 74 for the procedure for optional Interrupt on Wrap.
This register is Read Only; it may not be written to, but it is reset on a read.
Bit Register Name Address Offset See
31 aFramesTransmittedOK 00 Section 3.1.1 aFramesTransmittedOK on page 29
30 aSingleCollisionFrames or 04 Section 3.1.2 aSingleCollisionFrames on page 30 or

TXLocalFault Section 3.1.67 TXLocalFault on page 72
29 aMultipleCollisionFrames or 08 Section 3.1.3 aMultipleCollisionFrames on page 30 or

TXRemoteFault Section 3.1.68 TXRemoteFault on page 73
28 aFramesReceivedOK 0C Section 3.1.4 aFramesReceivedOK on page 31
27 aFrameCheckSequenceErrors 10 Section 3.1.5 aFrameCheckSequenceErrors on page 32
26 aAlignmentErrors 14 Section 3.1.6 aAlignmentErrors on page 32
25 aOctetsTransmittedOKLOW 18 Section 3.1.7 aOctetsTransmittedOK on page 33

aOctetsTransmittedOKHIGH 1C
24 aFramesWithDeferredXmissions 20 Section 3.1.8 aFramesWithDeferredXmissions on page 34
23 aLateCollisions 24 Section 3.1.9 aLateCollisions on page 34

22 aFramesAbortedDueToXSColls 28 Section 3.1.10 aFramesAbortedDueToXSColls on page 35
21 aFramesLostDueToIntMACXmitError 2C Section 3.1.11 aFramesLostDueToIntMACXmitError on page 36
20 aCarrierSenseErrors 28 Section 3.1.12 aCarrierSenseErrors on page 37
19 aOctetsReceivedOKLOW 34 Section 3.1.13 aOctetsReceivedOK on page 38

aOctetsReceivedOKHIGH 38
18 aFramesLostDueToIntMACRcvError 3C Section 3.1.14 aFramesLostDueToIntMACRcvError on page 39
17 aMulticastFramesXmittedOK 40 Section 3.1.15 aMulticastFramesXmittedOK on page 40

16 aBroadcastFramesXmittedOK 44 Section 3.1.16 aBroadcastFramesXmittedOK on page 40
15 aFramesWithExcessiveDeferral 48 Section 3.1.17 aFramesWithExcessiveDeferral on page 41
14 aMulticastFramesReceivedOK 4C Section 3.1.18 aMulticastFramesReceivedOK on page 41
13 aBroadcastFramesReceivedOK 50 Section 3.1.19 aBroadcastFramesReceivedOK on page 42
12 aInRangeLengthErrors 54 Section 3.1.20 aInRangeLengthErrors on page 42
11 aOutOfRangeLengthField 58 Section 3.1.21 aOutOfRangeLengthField on page 43

Core Databook IBM
10 aFrameTooLongErrors 5C Section 3.1.22 aFrameTooLongErrors on page 43
9 aSQETestErrors 60 Section 3.1.23 aSQETestErrors on page 44
8 aSymbolErrorDuringCarrier 64 Section 3.1.24 aSymbolErrorDuringCarrier on page 45

7 aMACControlFramesTransmitted 68 Section 3.1.25 aMACControlFramesTransmitted on page 46
6 aMACControlFramesReceived 6C Section 3.1.26 aMACControlFramesReceived on page 46
5 aUnsupportedOpcodesReceived 70 Section 3.1.27 aUnsupportedOpcodesReceived on page 47
4 aPAUSEMACCtrlFramesTransmitted 74 Section 3.1.28 aPAUSEMACCtrlFramesTransmitted on page 47
3 aPAUSEMACCtrlFramesReceived 78 Section 3.1.29 aPAUSEMACCtrlFramesReceived on page 48
2 aShortEvents 7C Section 3.1.30 aShortEvents on page 48
1 aRunts 80 Section 3.1.31 aRunts on page 49
0 aBursts or ReceivedWithCodeError 84 Section 3.1.32 aBursts on page 50 or Section 3.1.66 Received-

WithCodeError on page 72

120
IBM Core Databook
3.1.63 MIB_INTERRUPT_STATUS_B
Address Offset: 0xFC
Width: 32 bits
Access: Read/Write
Optional
All applications
This register records which counters wrapped within address offsets 88 through F4. See Section 3.1.35
etherStatsBroadcastPkts on page 52 through Section 3.1.61 TXFIFOUnderrun on page 66.
This register is Read Only; it may not be written to, but it is reset on a read.
31 etherStatsPkts 88 Section 3.1.34 etherStatsPkts on page 51
30 etherStatsBroadcastPkts 8C Section 3.1.35 etherStatsBroadcastPkts on page 52
29 etherStatsMulticastPkts 90 Section 3.1.36 etherStatsMulticastPkts on page 52
28 etherStatsCRCAlignErrors 94 Section 3.1.37 etherStatsCRCAlignErrors on page 53
27 etherStatsOversizePkts 98 Section 3.1.38 etherStatsOversizePkts on page 53
26 etherStatsJabbers 9C Section 3.1.39 etherStatsJabbers on page 54

25 etherStatsCollisions A0 Section 3.1.40 etherStatsCollisions on page 54
24 etherStatsPkts64Octets A4 Section 3.1.41 etherStatsPkts64Octets on page 55
23 etherStatsPkts65to127Octets A8 Section 3.1.42 etherStatsPkts65to127Octets on page 55

22 etherStatsPkts128to255Octets AC Section 3.1.43 etherStatsPkts128to255Octets on page 56
21 etherStatsPkts256to511Octets B0 Section 3.1.44 etherStatsPkts256to511Octets on page 56
18 ReceivedInLoopBackMode BC Section 3.1.47 ReceivedInLoopBackMode on page 59
17 RXVLANTaggedFrame C0 Section 3.1.48 RXVLANTaggedFrame on page 59

16 RXVLANUserPriorityField C4 Section 3.1.49 RXVLANUserPriorityField on page 60
15 RXUnicastAddr C8 Section 3.1.50 RXUnicastAddr on page 60
14 RXFIFOOverrun CC Section 3.1.51 RXFIFOOverrun on page 61
13 TXPkts64Octets D0 Section 3.1.52 TXPkts64Octets on page 61
12 TXPkts65to127Octets D4 Section 3.1.53 TXPkts65to127Octets on page 62
11 TXPkts128to255Octets D8 Section 3.1.54 TXPkts128to255Octets on page 62

10 TXPkts256to511Octets DC Section 3.1.55 TXPkts256to511Octets on page 63
1. Zeros will be returned on a Read.

Core Databook IBM
9 TXPkts512to1023Octets D0 Section 3.1.56 TXPkts512to1023 on page 63
8 TXPkts1024toMaxSizeOctets E4 Section 3.1.57 TXPkts1024toMaxSizeOctets on page 64
7 TXBadFCS E8 Section 3.1.58 TXBadFCS on page 65

6 TXFramePausedByControlPacket EC Section 3.1.59 TXFramePausedByControlPacket on page 65
5 TXUnicastAddr F0 Section 3.1.60 TXUnicastAddr on page 66
4 TXFIFOUnderrun F4 Section 3.1.61 TXFIFOUnderrun on page 66
3-0 Reserved1
1. Zeros will be returned on a Read.

120
IBM Core Databook
3.1.64 MIB_ENABLE_INTERRUPT_STATUS_A
Width: 32 bits
Access: Read/Write
Optional
All applications
This register indicates which conditions in the MIB_INTERRUPT_STATUS_A register can generate an inter-
rupt. Reference Section 3.1.62 , MIB_INTERRUPT_STATUS_A, on page 67 for bit associations.
3.1.65 MIB_ENABLE_INTERRUPT_STATUS_B
Width: 32 bits
Access: Read/Write
Optional
All applications
This register indicates which conditions in the MIB_INTERRUPT_STATUS_B register can generate an inter-
rupt. Reference Section 3.1.63 , MIB_INTERRUPT_STATUS_B, on page 69 for bit associations.

Core Databook IBM
3.1.66 ReceivedWithCodeError
Access: Read/Write
Optional
10G Applications
This counter gives the total number of frames received which were terminated by a non-EPD (end of packet
delimiter) charter on the XGMII. This may include Local/Remote Link Fault characters or any other control
character except Terminate/Error. This counter is not incremented if aFramesLostDueToIntMACRcvError is
to be incremented at the same time.
To create this counter, select aSingleCollisionFrames for synthesis.
3.1.67 TXLocalFault
Access: Read/Write
Optional
10G Applications
This counter gives the total number of frames transmitted which were interrupted as a result of a detected
local link fault. This counter is not incremented if aFramesLostDueToIntMACXmitError is to be incremented at
the same time.
To create this counter, select aMultipleCollisionFrames for synthesis.

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IBM Core Databook
3.1.68 TXRemoteFault
Access: Read/Write
Optional
10G Applications
This counter gives the total number of frames transmitted which were interrupted as a result of a detected
remote link fault. This counter is not incremented if aFramesLostDueToIntMACXmitError is to be incremented
at the same time.
To create this counter, select aBursts for synthesis.
3.1.69 CoreConnect Revision ID Register
Width: Fixed, width of OPB (32)
Reset Value: 0x00000X_YY
Access: Read-Only
All
All Applications
This read-only register stores the CoreConnect Revision ID Register value. It represents the version of the
this core. It is does not represent the version of the OPB that it adhere’s to.

Core Databook IBM
3.2 Interrupt Handling

Following reset, the MIB begins monitoring the interfaces. There are no configuration registers required to be
set except the optional MIB_ENABLE_INTERRUPT_STATUS_A and
MIB_ENABLE_INTERRUPT_STATUS_B registers. These two registers need to be set to activate the
optional interrupt on counter wrap function discussed in Section 3.1 Registers on page 23.
The procedure for optional Interrupt on Wrap is as follows:

1. Write to the MIB_ENABLE_INTERRUPT_STATUS_A(_B) registers to set up a mask which will enable the
interrupt for the desired corresponding counter. This write can be done by Fullword, Halfword, or Byte via
the appropriate OPB protocol.
2. For Bring-Up Test only, do a Fullword write to the counters with a value near roll-over. this is not to be
used for normal operation.
3. When a counter rolls over, the respective status bit will set in MIB_INTERRUPT_STATUS_A(_B)
4. If the corresponding mask bit in the MIB_ENABLE_INTERRUPT_STATUS_A(_B) is set, the
MIB_INTERRUPT line will go active. The MIB_INTERRUPT is not a latch. The
MIB_INTERRUPT_STATUS_A(_B) bits are logically ANDed with the respective
MIB_ENABLE_INTERRUPT_STATUS_A(_B) bits. The resulting bits are then logically ORed to produce
the MIB_INTERRUPT signal. Thus, if any of the status bits equals ‘1’, an interrupt is generated.
5. Reset the interrupt via a write to the status registers. The MIB_INTERRUPT_STATUS_A(_B) bits are
reset by writing a ‘1’ to the bit; writing a ‘0’ has no effect. The MIB_INTERRUPT is cleared once all of the
non-masked status bits are cleared. This method is comparable to that used in the EMAC. See the
related section in the EMAC databook.
6. The MIB_INTERRUPT_STATUS_A(_B) bits cannot be set via a write to the register. They are read-only.
There is an interrupt generated on wrap for any counter. The interrupt status registers record which counters
wrapped. The interrupt enable status registers indicate for which counters to generate an interrupt on wrap.

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IBM Core Databook
3.3 Software Implementation

A software-based implementation of the mandatory MIB counters as specified in IEEE 802.3 Clause 30 is
based on the usage of the content in transmit/receive status information provided by EMAC to MadMAL at the
end of each packet. For the content of the MadMAL transmit and receive control/status ports as implemented
in EMAC, see Sections 8.4.2 and 9.2.4 of the Ethernet Media Access Controller3 (EMAC) specification.
Note: Bit 11 in MadMAL Rx status port will reflect ‘Alignment Error’ instead of ‘Symbol Error’.
In order to implement all mandatory MIB counters the software should process each status word provided by
EMAC in the following manner:
The status word following a transmit transaction (based on content of MadMAL Tx status port):
• FramesTransmittedOK: This counter is incremented when bits 6, 8, 9, 10, 11, 14, and 15 are not set.
• SingleCollisionFrames: This counter is incremented when Transmitted OK is true and bit 13 is set.
• MultipleCollisionFrames: This counter is incremented when Transmitted OK is true and bit 12 is set
The status word following receive transaction (based on content of MadMAL Rx status port):
• FramesReceivedOK: This counter is incremented when bits 6, 8, 11, 12, 13, and 15 are not set.
• FrameCheckSequenceErrors: This counter is incremented when bit 12 is set and bits 10, 11, and 13 are
reset.
• AlignmentErrors: This counter is incremented when bit 11 is set. (This counter will not increment for 8-bit
wide group encoding schemes.)
An alternative software implementation solution that works for all of the counters is to synthesize a counter
width of 1 bit and to synthesize the hardware interrupt status to provide indications of the events.
The etherStatsOctets counter is implemented in the EMAC as the Receive Octets register.

Core Databook IBM

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IBM Core Databook
4. Hardware Interface
4.1 EMAC Interface

As EMAC processes a frame (during both transmit and receive operations), it prepares a comprehensive set
of status and error indicators that reflect various medium events. These indicators are intended to be
processed by the MIB (external to the EMAC). This mechanism allows the logic, located outside EMAC, a
flexible implementation of the network management counters (see Figure 3).
Figure 3. EMAC - MIB Interface
EMC_RX_STATUS 32
EMC_RX_STATUS_VALID
EMC_RX_FRAMES_BYTES 14
EMC_TX_STATUS 32
EMC_TX_STATUS_VALID
EMAC MIB
EMC_TX_FRAMES_BYTES 14
MIB_RX_RDY
MIB_TX_RDY
It is possible that a single receive frame can result in multiple error indications. EMAC does not prioritize
these errors.
Figure 4 illustrates the transaction timing on the EMAC - MIB interface.
Figure 4. EMAC - MIB Timing Diagram
PHY_TX(RX)_CLK
EMC_TX(RX)_STATUS
EMC_TX(RX)_FRAME_BYTES
EMC_TX(RX)_STATUS_VALID A C
MIB_TX(RX)_RDY B
Note: Actual delays between events may be different from the delays depicted in the figure.
• A: When the valid status for the recently processed packet is prepared and presented on the
EMC_TX(RX)_STATUS and EMC_TX(RX)_FRAME_BYTES, EMAC asserts its related
EMC_TX(RX)_STATUS_VALID output.
• B: When MIB has finished processing this status, it asserts the MIB_TX(RX)_RDY signal.
SA14-2434-11 Hardware Interface

Core Databook IBM
• C: EMAC is allowed to provide a new status for MIB only when assertion of MIB_TX(RX)_RDY for the
previous packet was detected.
Note: Step C is only used in EMAC3. For all other applications, the MIB_TX(RX)_RDY lines should be
terminated. In these applications, an OPB Sequential Address operation might cause a collision in the
MIB with the status vector which would result in the loss of some part of the status vector.
Description of the EMC_RX(TX)_FRAME_BYTES bus(es):
• EMC_RX_FRAME_BYTES
— This 14-bit bus presents the number of bytes that were received on the MII/GMII interface during last
frame reception (it counts all bytes excluding framing and extension bytes). This bus contains the
valid data only when EMC_RX_STATUS_VALID is active. This bus is synchronous with respect to the
PHY_RX_CLK clock. When the EMC_RX_STATUS bit 0, ReceiveOK, is active, the value of this bus
is added to the value in the aOctetsReceivedOK counter.
• EMC_TX_FRAME_BYTES
— This 14-bit bus presents the number of bytes that were transmitted on the MII/GMII interface during
last frame trans-mission (it counts all bytes excluding framing and extension bytes). This bus con-
tains the valid data only when EMC_TX_STATUS_VALID is active. This bus is synchronous with
respect to the PHY_TX_CLK clock. When the EMC_TX_STATUS bit 0, TransmitOK, is active, the
value of this bus is added to the value in the aOctetsTransmittedOK counter.
For detailed descriptions of the related signals, see Section 5.3.2.3 EMAC MIB Interface on page 94.
It takes a minimum of 5 PHY cycles after EMC_TX(RX)_STATUS_VALID for the respective

MIB_TX(RX)_RDY to be raised.
Hardware Interface SA14-2434-11

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IBM Core Databook
4.1.1 Content of Transmit Status Word for 10/100/100 Applications
The content of the transmit status word is described in Table 2.
Table 2. Transmit Status Word for 10/100/1000 Applications (Page 1 of 2)
Bits Bit Name Bit Description
0 Transmit OK Activates if none of the following events was discovered during transmission:
• Collision
• Late collision
• Lost of carrier sense
• Excessive deferral
• Bad FCS
• Internal MAC transmit error
• SQE error (for half-duplex 10 Mbps only)
1 Single collision frame This bit activates if the transmitted frame collided with other data on the bus just once.
2 Multiple collision frame This bit activates if the transmitted frame collided with other data on the bus more than
once, but less than 16 times. This is applicable only in half-duplex mode.
3 Deferred frame Indicates that current frame transmission is deferred due to activity on the medium on
its first transmission attempt. (Note that if EMAC waits to the end of the IFG period with-
out indicating an active medium, the frame is not considered as a deferred frame.) This
is applicable only in half-duplex mode.
4 Late collision This bit activates if the frame collided with other data outside of the collision window.
5 Excessive collisions Indicates that the current frame transmission had ended with a collision at the 16th con-
secutive attempt. This is applicable only in half-duplex mode.
6 Excessive deferral Indicates that the current frame has been deferred for an excessive period of time. This
is applicable only in half-duplex mode. The value of this period in bits is calculated in the
following way:
- For 10 and 100 Mbps operation: 2 x (maxFrameSize x 8) bit times.
- For 1000 Mbps operation: 2 x (burstLimit + maxFrameSize x 8 + headerSize) bit times
7 EMAC internal error When set, indicates that transmit was interrupted internally within EMAC.
8 Reserved Read as zero.
10 Loss of carrier sense Activates if during the transmission of frame, the PHY_CRS input was de-asserted after
it previously was asserted, or it was not asserted at all. Applicable only in half-duplex
mode. Returns zero in full-duplex mode.
11 SQE indication This bit is applicable only for the HDX 10 Mbps medium.
When set, indicates that Signal Quality Error test has failed. Following the end of a suc-
cessful EMAC transmission (ended with no collision), EMAC expects the PHY to assert
the collision signal until the end of the first part of the inter frame-gap (IFG1). If collision
was not asserted, EMAC indicates a signal quality error.
When the IGNORE_SQE_TEST bit in mode register 1 is set, SQE test is not performed.
12 64 bytes transmitted When set, indicates that the currently transmitted frame was 64 bytes in length (exclud-
ing framing bits but including FCS bytes).
Note: If transmit frame was interrupted internally within EMAC, then all bits except bits 4, 5, 6, 7, and 25 will be in an unpredictable
state.

Core Databook IBM
Table 2. Transmit Status Word for 10/100/1000 Applications (Page 2 of 2)
13 65 - 127 bytes transmitted When set, indicates that the currently transmitted frame was between 65 and 127 bytes
in length (excluding framing bits but including FCS bytes).
14 128 - 255 bytes transmitted When set, indicates that the currently transmitted frame was between 128 and 255
bytes length (excluding framing bits but including FCS bytes).
17 1024-MaxSize bytes transmit- When set, indicates that the currently transmitted frame was between 1024 and 1518
ted (1522 in case of VLAN mode) bytes length (excluding framing bits but including FCS
bytes).
18 TX Control Frame When set, indicates that the currently transmitted frame was a control frame. Activates
only if a control packet was self-assembled by EMAC.
19 TX Control Pause Frame When set, indicates that the currently transmitted frame was a pause frame. Activates
only if a control packet was self-assembled by EMAC.
20 Bad FCS Of The Transmitted Indicates that the transmitted frame had an FCS which does not match the FCS calcu-
Frame lated by EMAC. EMAC asserts this indication only if the frame transmitting ended with-
out interference (that is, there was not a collision or stop request during frame
transmission).
21 Frame Paused By Control When set, indicates that the currently transmitted frame was delayed before its start
Packet due to a pause packet received by EMAC.
22 UnicastAddr Activates if the frame was transmitted to a unicast destination address.
23 MulticastAddr Activates if the frame was transmitted to a group destination address other than broad-
cast.
24 BroadcastAddr Activates if the frame was transmitted to the broadcast destination address.
25 TXFIFOUnderrun Indicates that current frame was aborted because an underrun-data indication from the
FIFO was not valid in time to allow continuous data transmission on the MII/GMII inter-
face.
26:31 Reserved Read as zero.
Note: If transmit frame was interrupted internally within EMAC, then all bits except bits 4, 5, 6, 7, and 25 will be in an unpredictable
state.

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IBM Core Databook
4.1.2 Content of Receive Status Word for 10/100/1000 applications
The content of the receive status word is described in Table 3.
Table 3. Receive Status Word for 10/100/1000 Applications (Page 1 of 3)
0 Receive OK Activates if none of the following events were discovered during a receive operation:
Receive FIFO Handler interrupted receive process
FCS error
• Length mismatch error
• Too long frames
• Alignment errors
• Received with symbol error
• Short event
• Internal MAC receive error
• FCS error
1 Bad FCS in the received Activates if frame had an FCS value which does not match the FCS value calculated by
frame EMAC.
2 Frame lost due to internal When set, means that frame reception was interrupted internally within EMAC.
MAC receive error
3 In range length error This test is activated only when the content of the length field in the received frame is
less or equal to the maximum allowed MAC client data size (1500 bytes).
4 Out of range length error Indicates that the received frame has a length field value greater than the maximum
allowed LLC data size (greater than 1500 and less than 1536).
5 Frame is too long Indicates that the length of the received frame exceeded the maximum allowed value:
- 1518 octets for standard frame (checked only when the length/type field of
the transmitted frame contains a length value and it is not a jumbo frame)
- 1522 octets for VLAN tagged frame (checked only when the length/type field
of the transmitted frame contains a length value and is not a jumbo frame)
- 9018 octets for a jumbo frame (with no VLAN support)
- 9022 octets for a VLAN tagged jumbo frame
6 Received burst When active, indicates that carrier event (from the first byte of DA till the end of trans-
mission) was equal or greater then slotTime. Applicable only in HDX mode in 1000
Mbps medium.
8 Received with symbol error For 100 Mbps operation, indicates when a valid carrier was present and there was at
least one occurrence of data reception error.
For 1000 Mbps operation, indicates when the receiving media is non-idle (a carrier
event) for a period of time greater than or equal to slotTime for half-duplex, or greater
than or equal to minFrameSize for full-duplex, and during which there was at least one
occurrence of an event that causes the PHY to indicate Data reception error on the
GMII.
9 Alignment error When active, indicates that received frame does not have an integral number of octets
in length. This is applicable only on 10/100 Mbps medium.
10 Short event When active, indicates that the duration of PHY_RX_DV signal was less than the Short-
EventMaxTime constant. For this indication, EMAC always assumes that the preamble
and SFD fields contain 8 bytes regardless of the number actually received.
Note: If the receive frame was interrupted internally within EMAC, then all bits except bits 2, 5, and 29 can be in an unpredictable
state.

Core Databook IBM
11 Runt frame When active, indicates that the frame length was less than minFrameSize (64 bytes,
excluding the preamble and SFD bytes) and a ShortEvent was not detected.
12 64 bytes received When set, indicates that the currently received frame (including bad frame) was 64
bytes in length (excluding framing bits but including FCS bytes).
13 65-127 bytes received When set, indicates that the currently received frame (including bad frame) was
between 65 and 127 bytes in length (excluding framing bits but including FCS bytes).
between 128 and 255 bytes length (excluding framing bits but including FCS bytes).
17 1024-MaxSize bytes received When set, indicates that the currently received frame (including bad frame) was
between 1024 and maxFrameSize.
Jumbo Packets VLAN Support maxFrameSize

Support Enabled Enabled (bytes)
0 0 1518
0 1 1522
1 0 9018
1 1 9022
18 RX control frame When set, indicates that the currently received frame was a control frame.
19 RX control pause frame When set, indicates that the currently received frame was a control pause frame.
20 Rx unsupported opcode When set, indicates that the currently received frame was a control frame with unsup-
ported opcode.
21 Received in loop-back mode When set, indicates that the currently received frame is an “echo” of frame transmitted
by TXMAC block.
22 RX VLAN tagged frame When set, indicates that the currently received frame was a VLAN tagged frame.
23-25 User priority field Provides the content of user priority field (bits 7 and 5 respectively) from received VLAN
tagged frame.
26 UnicastAddr Activates if the frame was received with a unicast destination address and at least 6
bytes are received.
27 MulticastAddr Activates if the frame was received with a group destination address other than broad-
cast and at least 6 bytes are received.
28 BroadcastAddr Activates if the frame was received with the broadcast destination address and at least
6 bytes are received.
state.

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IBM Core Databook
29 RXFIFOOverrun Indicates that the current frame was aborted because an overrun - flow of received data
applied to the FIFO was detected, and the data was invalidated since there was no
empty space in the Receive FIFO.
state.

Core Databook IBM
4.1.3 Content of Transmit Status Word for 10 G Applications
The content of the transmit status word is described in Table 4.
Table 4. Transmit Status Word for 10 G Applications f (Page 1 of 2)
0 Transmit OK Activates if none of the following events was discovered during transmission:
• Bad FCS
• Link fault (local or remote)
• TX FIFO underrun during transmit session
• Internal MAC transmit error
1 Local fault Frame transmit process is interrupted as a result of detected local link fault.
2 Remote fault Frame transmit process is interrupted as a result of remote link fault.
7 XEMAC internal error When set, indicates that transmit was interrupted internally within XEMAC.
12 64 bytes transmitted When set, indicates that the currently transmitted frame was 64 bytes in length (exclud-
ing framing bits, but including FCS bytes).
13 65 - 127 bytes transmitted When set, indicates that the currently transmitted frame was between 65 and 127 bytes
in length (excluding framing bits, but including FCS bytes).
bytes in length (excluding framing bits, but including FCS bytes).
17 1024-MaxSize bytes transmit- When set, indicates that the currently transmitted frame was between 1024 and 1518
ted (1522 in case of VLAN mode) bytes in length (excluding framing bits, but including FCS
bytes).
18 TX Control Frame When set, indicates that the currently transmitted frame was a control frame. Activates
only if a control packet was self-assembled by XEMAC.
Notes:
1. If the transmit frame was interrupted internally within XEMAC, then all bits (except bits 7 and 25) can be in an unpredictable
state.
2. If a frame is aborted during transmission because of remote or local link fault, then all bits (except bits [2:0]) can be in an unpre-
dictable state.
3. Reserved bits are read as zeros.

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IBM Core Databook
Table 4. Transmit Status Word for 10 G Applications f (Page 2 of 2)
19 TX Control Pause Frame When set, indicates that the currently transmitted frame was a pause frame. Activates
only if a control packet was self-assembled by XEMAC.
20 Bad FCS Of The Transmitted Indicates that the transmitted frame had an FCS which does not match the FCS calcu-
Frame lated by XEMAC. XEMAC asserts this indication only if the frame transmitting ended
without interference.
22 UnicastAddr Activates if the frame was transmitted to a unicast destination address.
23 MulticastAddr Activates if the frame was transmitted to a group destination address other than broad-
cast.
24 BroadcastAddr Activates if the frame was transmitted to the broadcast destination address.
25 TXFIFOUnderrun Indicates that current frame was aborted because an underrun-data indication from the
FIFO was not valid in time to allow continuous data transmission on the MII/GMII inter-
face.
Notes:
1. If the transmit frame was interrupted internally within XEMAC, then all bits (except bits 7 and 25) can be in an unpredictable
state.
2. If a frame is aborted during transmission because of remote or local link fault, then all bits (except bits [2:0]) can be in an unpre-
dictable state.
3. Reserved bits are read as zeros.

Core Databook IBM
4.1.4 Content of Receive Status Word for 10 G Applications
The content of the receive status word is described in Table 5.
Table 5. Receive Status Word for 10 G Applications (Page 1 of 2)
0 Receive OK Activates if none of the following events were discovered during a receive operation:
• Receive FIFO Handler interrupted receive process
• FCS error
• Length mismatch error
• Frames too long
• Link fault sequence set terminated reception
1 Bad FCS in the received Activates if frame had an FCS value which does not match the FCS value calculated by
frame XEMAC. XEMAC asserts this indication only if the received frame was ended without
interference.
2 XEMAC internal error When set, means that frame reception was interrupted internally within XEMAC.
3 In range length error This test is activated only when the content of the length field in the received frame is
less or equal to the maximum allowed MAC client data size (1500 bytes).
4 Out of range length error Indicates that the received frame has a length field value greater than the maximum
allowed LLC data size (greater than 1500 and less than 1536).
5 Frame is too long Indicates that the length of the received frame exceeded the maximum allowed value:
- 1518 octets for standard frame (checked only when the length/type field of
the transmitted frame contains a length value and it is not a jumbo frame)
- 1522 octets for VLAN tagged frame (checked only when the length/type field
of the transmitted frame contains a length value and is not a jumbo frame)
- 9018 octets for a jumbo frame (with no VLAN support)
- 9022 octets for a VLAN tagged jumbo frame
6 Received with Code Error Frame reception was terminated by a non-EPD (end of packet delimiter) character on
the XGMII. This may include Local/Remote Link Fault characters or any other control
character except Terminate/Error.
8 Received with symbol error Indicates when the receiving media is non-idle (a carrier event) for a period of time
greater than or equal to minFrameSize, and during which there was at least one occur-
rence of an event that causes the PHY to indicate a ‘data reception error’ on the XGMII.
11 Runt frame When active, indicates that the frame length was less than minFrameSize (64 bytes,
excluding the preamble and SFD bytes) and a ShortEvent was not detected.
12 64 bytes received When set, indicates that the currently received frame (including bad frame) was 64
bytes in length (excluding framing bits but including FCS bytes).
between 65 and 127 bytes in length (excluding framing bits but including FCS bytes).
Notes:
1. If the receive frame was interrupted internally within XEMAC, then all bits (except bits 2, 5, and 29) can be in an unpredictable
state.
2. Packets which contain less than 8 bytes (total, not including framing bytes) may be discarded by XEMAC without any indication.

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IBM Core Databook
Table 5. Receive Status Word for 10 G Applications (Page 2 of 2)
between 128 and 255 bytes in length (excluding framing bits, but including FCS bytes).
between 256 and 511 bytes in length (excluding framing bits, but including FCS bytes).
between 512 and 1023 bytes in length (excluding framing bits, but including FCS
bytes).
17 1024-MaxSize bytes received When set, indicates that the currently received frame (including bad frame) has a byte
length between 1024 and maxFrameSize. This is defined by the jumbo packets support
enabled bit and VLAN support enabled bit as follows:
Jumbo Packets VLAN Support maxFrameSize

Support Enabled Enabled (bytes)
0 0 1518
0 1 1522
1 0 9018
1 1 9022
18 RX control frame When set, indicates that the currently received frame was a control frame.
19 RX control pause frame When set, indicates that the currently received frame was a control pause frame.
20 Rx unsupported opcode When set, indicates that the currently received frame was a control frame with unsup-
ported opcode.
21 Received in loop-back mode When set, indicates that the currently received frame is an ‘echo’ of the frame transmit-
ted by TXMAC block.
22 RX VLAN tagged frame When set, indicates that the currently received frame was a VLAN tagged frame.
23-25 User priority field Provides the content of user priority field (bits 5-7 respectively) from received VLAN
tagged frame.
26 UnicastAddr Activates if the frame was received with a unicast destination address and at least 6
bytes are received.
27 MulticastAddr Activates if the frame was received with a group destination address other than broad-
cast and at least 6 bytes are received.
28 BroadcastAddr Activates if the frame was received with the broadcast destination address and at least
6 bytes are received.
29 RXFIFOOverrun Indicates that the current frame was aborted because an overrun - flow of received data
applied to the FIFO was detected, and the data was invalidated since there was no
empty space in the Receive FIFO.
30-31 Reserved Read as zero.
Notes:
1. If the receive frame was interrupted internally within XEMAC, then all bits (except bits 2, 5, and 29) can be in an unpredictable
state.
2. Packets which contain less than 8 bytes (total, not including framing bytes) may be discarded by XEMAC without any indication.

Core Databook IBM
4.2 OPB Interface

The MIB is a 32-bit OPB slave and is accessed from the OPB for read transactions. It behaves as a standard
OPB slave in compliance with the On-Chip Peripheral Bus Architecture Specifications with the proviso that all
reads and writes be fullword transactions.
Notes:
1. The MIB does not implement the slave retry operation.
2. The MIB utilizes the time-out suppression (TOUTSUP) mechanism to hold off the OPB operation if a
counter update is in progress.
3. Supports OPB Sequential Address mechanism.
Note: For all applications other than EMAC3, an OPB Sequential Address operation might cause a colli-
sion in the MIB with the status vector, which would result in the loss of some part of the status vector.
4. Provides 2-cycle latency OPB slave for single data transfer (without sequential address, and first data
transfer in sequential address burst mode.
5. Supports 1-cycle latency OPB slave for all data cycles using sequential address, except for the first trans-
action.
6. If OPB clock is < 33 MHz: Do not do a sequential read when EMAC is in HDX 10 Mbps mode.
The 23 most significant bits of the OPB address are compared with the content of the OPB_HRDW_ADDR
bus to distinguish between transactions targeted for the MIB and those intended for other OPB slave devices.
The 9 least significant bits of the OPB address define the specific counter within the MIB. The MIB supports
the sequential address mechanism for more efficient utilization of the OPB interface.
Figure 5. MIB - OPB Interface
OPB_ABUS[0:31] MIB_DBUS[0:31]
OPB_DBUS[0:31] MIB_DBUSEN
OPB_HRDW_ABUS[0:31] MIB_XFERACK
OPB_SELECT
MIB_ERRACK
OPB_RNW
OPB_HWXFER MIB_FWACK
OPB_FWXFER MIB_HWACK
OPB_SEQADDR MIB_TOUTSUP
MIB
OPB_RESET
MIB_INTERRUPT

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IBM Core Databook
Table 6. MIB - OPB Interface Signals (Page 1 of 2)
Pin Name Pins I/O Ext/Int Required/ Connection Description

Optional
Inputs
OPB_ABUS 32 I Int Required OPB OPB address bus. Used by host processor
to address the MIB’s internal counter.
OPB_DBUS 32 I Int Required OPB OPB Data Bus. Used by Host processor to
provide data to MIB’s internal registers.
OPB_HRDW_ABUS 23 I Int Required OPB Hard Wired Address Bus. Unique MIB
address in the host processor configuration
space.
OPB_SELECT 1 I Int Required OPB Driven by Host processor to assume control

of the bus and to indicate that a valid data
transfer cycle is in progress.
OPB_RNW 1 I Int Required OPB Indicates the direction of a data transfer.

(Read Not Write)
OPB_HWXFER 1 I Int Required OPB Half Word Transfer. In the OPB master
device communication with MIB, this signal,
in conjunction with OPB_FWXFER, indi-
cates the size of the requested transfer.
OPB_FWXFER 1 I Int Required OPB Full Word Transfer. In the OPB master
device communication with MIB, this signal,
in conjunction with OPB_HWXFER, indi-
cates the size of the requested transfer.
OPB_SEQADDR 1 I Int Required OPB Sequential Address. When set, indicates

that transfer being performed can be fol-
lowed with a transfer to the next sequential
address.
OPB_RESET 1 I Int Required OPB OPB reset signal. This signal is synchro-
nous with respect to the OPB_CLK clock.
Outputs
MIB_DBUS 32 O Int Required OPB OPB data bus
MIB_DBUSEN 1 O Int Required OPB OPB data bus enable signal
MIB_XFERACK 1 O Int Required OPB Transfer Acknowledge. Indicates that MIB

has completed the transfer on the bus.
MIB_ERRACK 1 O Int Required OPB Error Acknowledge. When asserted, indi-

cates the MIB has encountered an error in
performing the requested transfer.
MIB_FWACK 1 O Int Required OPB Full Word Acknowledge. In the OPB master
device communication with MIB this signal
always indicates a fullword transaction.
The appropriate value is MIB_FWACK= ‘1’.
MIB_HWACK 1 O Int Required OPB Half Word Acknowledge. In the OPB MIB
slave communication with the master, this
signal in conjunction with MIB_FWACK, indi-
cates the size of the MIB, and always indi-
cates a fullword transaction. This signal is
tied MIB_HWACK = ‘0’.

Core Databook IBM
Table 6. MIB - OPB Interface Signals (Page 2 of 2)
Pin Name Pins I/O Ext/Int Required/ Connection Description

Optional
MIB_TOUTSUP 1 O Int Required OPB Time Out Suppress. Indicates to the OPB
Arbiter that the bus operation can be
delayed for an extended period of time.
MIB_INTERRUPT 1 O Int Optional Processor Processor interrupt due to wrap detection on

a counter
Sub-Total 132
4.3 Power Management Interface

The MIB does not have embedded clock trees and corresponding power management inputs. Therefore, the
chip clock tree designer is responsible for the correct power management implementation on the clock inputs
to the core.

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IBM Core Databook
5. Core Integration
The MIB core is designed for use in a CoreConnect chip design. It is specifically designed to interface with
the EMAC core and the OPB.
During synthesis with Synopsys Design Compiler, the following register bits are removed, which are indicated
by messages displayed in the log. These bits are Reserved on the interface with the EMAC, so they have no
fanout. The names might be slightly different in the resulting netlist due to variations in user naming conven-
tions.
• /EMACMIB/EMAC_PHYCLK_RX/STATUS_HOLD_REG_reg[7]
• /EMACMIB/EMAC_PHYCLK_TX/STATUS_HOLD_REG_reg[8]
• Warning: In design ‘MIB’, port ‘EMC_RX_STATUS[31]’ is not connected to any nets. (LINT-28)
• Warning: In design ‘MIB’, port ‘EMC_TX_STATUS[31]’ is not connected to any nets. (LINT-28)
• Warning: In design ‘MIB’, output port ‘MIB_FWACK’ is connected directly to output port ‘MIB_XFERACK’.
(LINT-31)
5.1 Configurability
Each counter in the MIB register file can be individually selected for simulation/synthesis, and each counter
width can be individually determined during simulation/synthesis to a maximum value of the OPB (32 bits).
In the MIB.defines.v file, there is a list of Verilog ‘define(s) used to configure the MIB RTL. These follow the
naming convention of CONFIG_countername_WIDTH. They are only defined here. They control the width of
the counters. A width of 0 removes the counter and its associated interrupt status bit. A read of a nonexistent
counter or interrupt status bit returns a “0” value. A width of 32 is the maximum allowed value, except for
aOctetsTransmittedOK and aOctetsReceivedOK which have a maximum value of 64, and
RXVLANPriority_Field which has valid values of 0 or 3.
SA14-2434-11 Core Integration

Core Databook IBM
To configure the core:

1. Verilog ‘define statements have been put into the RTL. All declarations are located in the MIB.defines.v
file and can be modified. Change the value of the width of define to the desired width of the respective
counter.
Notes:
• If there are to be multiple instantiations with different counter configurations of the MIB, rename the
modules using the module name defines in the defines file.
• If an IEEE specified counter (‘aXXX’ type) is to be 32 bits in hardware, it cannot be reset when read,
according to the referenced specification. In this case, the MIB must be configured with the reset on
read function disabled (define MIB_RESET_ON_READ 0).
• To create TXLocalFault, select aSingleCollisionFrames.
• To create TXRemoteFault, select aMultipleCollisionFrames.
• To create ReceivedWithCodeError, select aBursts.
2. Simulate and synthesize with the configured RTL defines file.
3. To change the configuration, modify the defines file.
5.1.1 Interconnect
The EMAC - MIB interface names are the same on the MIB and the EMAC cores so that chip interconnect is
easier. The MIB - OPB interface names are similar to the names in the OPB specification so that chip inter-
connect is easier.
All pins except MIB_INTERRUPT and MIB_HWACK must be connected. These can be terminated to prevent
an antennae effect. The synthesis scripts do not add clock trees or LSSD logic. The post-synthesis netlist has
pseudo-latches and idealized clocks. LSSD logic and the associated interface pins and clock tree must be
added by the user. If the non-core chip logic has pseudo-latches and idealized clocks, then the post-synthesis
netlist can be merged with it, and then the LSSD logic and clock trees can be inserted at the chip level.
The PHY_RX_CLK and PHY_TX_CLK are multi-dropped to both the EMAC and MIB cores. Both cores get
the same PHY clocks.
5.2 Initialization Sequence

When the reset signal, OPB_RESET, is activated, all internal counters and registers are reset to
0x0000_0000. The OPB_RESET signal is synchronous to the OPB_CLK clock and is latched before use.
This ensures that OPB_RESET is deactivated to all counters and registers at the same time. The
OPB_RESET must be active for a minimum of three PHY clock periods plus three OPB clock periods.
Conversely, the OPB_RESET must then be inactive for a minimum of three PHY clock periods plus three
OPB clock periods, before communication with the MIB can begin. This takes into account the latch of the
OPB_RESET signal, and the propagation of the signal across the internal asynchronous interface to reset the
registers and synchronizers in the PHY clock domains and the corresponding synchronizers in the OPB clock
domain.
Note: PHY clocks must be running for the reset to occur.
Following reset, the MIB begins monitoring the interfaces. There are no configuration registers required to be
set except the optional MIB_ENABLE_INTERRUPT_STATUS_A and
MIB_ENABLE_INTERRUPT_STATUS_B registers. These two registers need to be set to activate the
optional interrupt on counter wrap function discussed in Section 3.1 Registers on page 23. See Section 3.2
Interrupt Handling on page 74 for the procedure for optional Interrupt on Wrap.
Core Integration SA14-2434-11

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IBM Core Databook
5.3 Synthesis Guidelines and Requirements
5.3.1 User-Defined Synthesis Options
There are no user-defined synthesis options for this core.
5.3.2 Timing Information
5.3.2.1 Clocking
• OPB interface (OPBCLK) operates from 33 MHz (10 MHz in 1 Gbps mode) to 133 MHz.
• EMAC interface (PHY_RX_CLK, PHY_TX_CLK) operates at the PHY clock rate:

— For 100 Mbps medium - 25 MHz
— For 10 Mbps medium - 2.5 MHz
5.3.2.2 Timing Definitions for Interfacing Pins
The timing parameters are defined according to the MII/GMII and OPB specifications. The values in the
Timing column in the following Interface Signal tables represent the time in which the signal is valid. The
signal is valid within a certain percentage of the respective clock cycle, from the rise of the clock, at the
latches input.
The OPB specification defines the timing (see Figure 6 on page 94) using the terms Begin, Early, Middle, and
Late. These timing definitions are used for all pins, OPB and PHY, and are as follows.
Begin: Signal is driven off a latch and should not have any combinatorial logic with the exception of any
necessary buffering logic. Signal is valid within 8% of the cycle from the rise of clock signal.
• Early: Signal is valid within 18% of the cycle from the rise of clock signal.
• Early+: Signal is valid within 28% of the cycle from the rise of clock signal.
• Middle-: Signal is valid within 33% of the cycle from the rise of clock signal.
• Middle: Signal is valid within 43% of the cycle from the rise of clock signal.
• Middle+: Signal is valid within 53% of the cycle from the rise of clock signal.
• Late-: Signal is valid within 58% of the cycle from the rise of clock signal.
• Late: Signal is valid within 68% of the cycle from the rise of clock signal.
• End: Signal is valid within 78% of the cycle from the rise of clock signal.

Core Databook IBM
Figure 6. Signal Timing Definitions
OPB clock
Begin
Early valid valid
Middle valid valid
Late valid valid
5.3.2.3 EMAC MIB Interface
Table 7. EMAC MIB Interface Signals (Page 1 of 2)
Pin Name Pins I/O Ext/Int Timing Required/ Connec- Description

Optional tion
Inputs
EMC_RX_STATUS 32 I Int Middle Required EMAC Contains status information about recently
43% received frame.
This bus is synchronous with respect to
the PHY_RX_CLK clock.
EMC_RX_STATUS 1 I Int Early Required EMAC When active (single cycle pulse), the
_VALID 18% information presented on the
EMC_RX_STATUS bus is valid.
This signal is synchronous with respect to
EMC_RX_FRAME_ 14 I Int Early Required EMAC This 14-bit bus presents the number of
BYTES 18% bytes that were received on the MII/GMII
interface during last frame reception (it
counts all bytes excluding framing and
extension bytes).
This bus contains the valid data only
when EMC_RX_STATUS_VALID is
active.
EMC_TX_STATUS 32 I Int End Required EMAC Contains status information about recently
78% transmitted frame.
the PHY_TX_CLK clock.

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IBM Core Databook
Table 7. EMAC MIB Interface Signals (Page 2 of 2)
Pin Name Pins I/O Ext/Int Timing Required/ Connec- Description

Optional tion
EMC_TX_STATUS 1 I Int Early Required EMAC When active (single cycle pulse), the
_VALID 18% information presented on the
EMCTX_STATUS bus is valid.
EMC_TX_FRAME_ 14 I Int Early Required EMAC This 14-bit bus presents the number of
BYTES 18% bytes that were transmitted on the
MII/GMII interface during last frame trans-
mission (it counts all bytes excluding
framing and extension bytes).
This bus contains the valid data only
when EMC_TX_STATUS_VALID is
active.
Outputs
MIB_TX_RDY 1 O Int Late Required EMAC When active, the MIB has finished pro-
68% cessing the status of the previous transmit
packet. EMAC monitors the active level of
this signal to issue
EMC_TX_STATUS_VALID signal when
status is ready.
Note: MIB can de-activate this signal
immediately after the falling edge of
EMC_TX_STATUS_VALID. MIB can hold
MIB_TX_RDY inactive for an arbitrary
period of time with one exception:
In HDX 10 Mbps medium, EMAC expects
that MIB_TX_RDY can be re-asserted
within 16 cycles of PHY_TX_CLK.
MIB_RX_RDY 1 O Int Late Required EMAC When active, the MIB has finished pro-
68% cessing the status of the previous receive
packet.
Note: The MIB can de-activate this signal
immediately after the falling edge of
EMC_RX_STATUS_VALID. The MIB can
hold MIB_RX_RDY inactive for an arbi-
trary period of time, but it should be noted
that EMAC monitors the active level of
this signal before activation of its
EMC_RX_STATUS_VALID signal. If, at
the beginning of a new incoming packet,
EMAC is still waiting for the
MIB_RX_RDY assertion for accomplish-
ment of the previous packet, EMAC
misses this new packet.
Sub-Total 96

Core Databook IBM
5.3.2.4 MIB OPB Interface
Table 8. MIB OPB Interface Signals with Timing (Page 1 of 2)
Pin Name Pins I/O Ext/Int Timing Required Connec- Description

/Optional tion
Inputs
OPB_ABUS 32 I Int Early Required OPB OPB address bus. Used by host proces-
18% sor to address the MIB’s internal
counters.
OPB_DBUS 32 I Int Late Required OPB OPB Data Bus. Used by Host processor
68% to provide data to MIB’s internal
counters.
OPB_HRDW_ABUS 23 I Int - Required OPB Hard Wired Address Bus. Unique MIB
address in the host processor configura-
tion space.
OPB_SELECT 1 I Int Early Required OPB Driven by Host processor to assume

18% control of the bus and to indicate that a
valid data transfer cycle is in progress.
OPB_RNW 1 I Int Early Required OPB Indicates the direction of a data transfer.
18% (Read Not Write)
OPB_HWXFER 1 I Int Early Required OPB Half Word Transfer. In the OPB master
18% device communication with MIB, this
signal, in conjunction with
OPB_FWXFER, indicates the size of the
requested transfer.
OPB_FWXFER 1 I Int Early Required OPB Full Word Transfer. In the OPB master
18% device communication with MIB, this
signal, in conjunction with
OPB_HWXFER, indicates the size of
the requested transfer.
OPB_SEQADDR 1 I Int Early Required OPB Sequential Address. When set, indi-
18% cates that transfer being performed can
be followed with a transfer to the next
sequential address.
OPB_RESET 1 I Int N/A Required OPB OPB reset signal. This signal is syn-
chronous with respect to the OPB_CLK
clock.
Outputs
MIB_DBUS 32 O Int Middle Required OPB OPB data bus

43%
MIB_DBUSEN 1 O Int Middle Required OPB OPB data bus enable signal
43%
MIB_XFERACK 1 O Int Middle Required OPB Transfer Acknowledge. Indicates that

33% MIB has completed the transfer on the
bus.
MIB_ERRACK 1 O Int Middle Required OPB Error Acknowledge. When asserted,

33% indicates the MIB has encountered an
error in performing the requested trans-
fer.

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IBM Core Databook
Table 8. MIB OPB Interface Signals with Timing (Page 2 of 2)
Pin Name Pins I/O Ext/Int Timing Required Connec- Description

/Optional tion
MIB_FWACK 1 O Int Middle Required OPB Full Word Acknowledge. In the OPB
33% master device communication with MIB
this signal always indicates a fullword
transaction.
The appropriate value is MIB_FWACK=
‘1’.
MIB_HWACK 1 O Int Middle Required OPB Half Word Acknowledge. In the OPB
33% MIB slave communication with the mas-
ter, this signal in conjunction with
MIB_FWACK, indicates the size of the
MIB, and always indicates a fullword
transaction. This signal is tied
MIB_HWACK = ‘0’.
MIB_TOUTSUP 1 O Int Early Required OPB Time Out Suppress. Indicates to the
18% OPB Arbiter that the bus operation can
be delayed for an extended period of
time.
MIB_INTERRUPT 1 O Int Middle Optional Processor Processor interrupt due to wrap detec-
43% tion on a counter
Sub-Total 132
5.3.2.5 MIB Clocks
The MIB does not contain any DFT structures, either MUX-SCAN or LSSD. That is expected to be inserted by
the user, into the netlist after synthesis. The table below provides some assistance for identifying core ports
relevant to test.
Table 9. MIB Clocks
Name I/O Ext/Int Required/ Con- Nominal LSSD Flag Signal Description
Optional nection Mode Value
Inputs
OPB_CLK I Int Required OPB clock +SG OPB clock
PHY_RX_CLK I Ext/Int Required PHY clock +SG Receive Medium

clock
PHY_TX_CLK I Ext/Int Required PHY clock +SG Transmit Medium

clock
Outputs
Sub-Total 3
Total 231

Core Databook IBM
5.3.2.6 Supplied Timing Constraints
The PHY_RX_CLK and PHY_TX_CLK are multi-dropped to both the MIB and the EMAC cores. Both cores
get the same PHY clocks.
The Synopsys SDC timing constraints file is used for synthesis and timing analysis. In this file, the clock
periods for the clocks must be set by modifying the default. The file also contains a clock jitter variable that
can be set to the desired amount of clock uncertainty.
In the chip EinsTimer™ assertions (PHASE file), it is imperative to have phase pair exclusions between each
PHY clock and the OPB clock. In the case of the MIB, it needs a phase pair exclusion between the
PHY_RX_CLK and the OPB_CLK, and between the PHY_TX_CLK and the OPB_CLK. The phase pair exclu-
sions, therefore, are essential to have.
The required phase pair exclusions exist in the SDC (Synopsys Delay Constraint) timing assertion file which
is used in the MIB synthesis scripts.
For asynchronous clock domain crossing assertions, See Appendix A, Asynchronous Interface, on page 104,
which contains a list of crossing that can be used to create a file of UDT assertions that can be used for chip
EinsTimer timing analysis. The actual names of the flip-flops involved can vary in the netlist depending on the
naming convention selected during synthesis.
5.3.2.7 User-Defined Timing Constraints for Asynchronous Clock Domain Crossings
There are several structures used in this core to implement its asynchronous behavior. They consist of:
• Flip-flop pairs for dual-rank synchronization
• Mux for data synchronization (status busses) using an AND gate enabled with synchronized valid signal.
Caution: Users are responsible for creating timing constraints in their design system in order to ensure the
correct operation of these structures. See Appendix A, Asynchronous Interface, on page 104 for more infor-
mation.
Figure 7. Asynchronous Crossing and Synchronizer Flops
Asynchronous Synchronizer
Delay Path Delay Path
SOURCE_REG DESTINATION1_REG DESTINATION2_REG
D L2 D L2 D L2
Source Clock Destination Clock

Capture Flop

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IBM Core Databook
Figure 8. Asynchronous Crossing With Gating
Delay Path
SOURCE_REG DESTINATION_REG
AND
D L2
D L2
Gating Signal
Synchronous to
Source Clock Destination Clock Destination Clock
Capture Flop
5.4 Test Interface Requirements

This core contains no test signals or test logic.
The MIB adheres to Level 0 Test Support. It has no special core requirements for test. The synthesis scripts
do not add clock trees or scan logic. The post-synthesis netlist has pseudo-latches and idealized clocks. Test
logic and the associated interface pins and clock tree must be added by the user. The post-synthesis netlist
can be merged with the remaining chip logic, and then the test logic and clock trees can be inserted at the
chip level.

Core Databook IBM
5.5 Physical Design Requirements

The MIB is a synthesizable core. There is no physical design released. It meets all requirements to assure
inclusion of the core when the chip physical design is done.
The hierarchy of the MIB is represented in Figure 9 Module Instance Names and Hierarchy on page 100.
Figure 9. Module Instance Names and Hierarchy
MIB (MIB)
MIB_REGFILE (REGFILE)
MIB_READ_64BIT_COUNTERS_FSM (inst_READ_aOctetsTransmittedOK_FSM)
MIB_READ_64BIT_COUNTERS_FSM (inst_READ_aOctetsReceivedOK_FSM)
MIB_MIBOPB (MIBOPB)
MIB_OPB_LINK (OPB_LINK)
MIB_OPB_FSM (OPB_FSM)
MIB_EMACMIB (EMACMIB)
MIB_EMAC_PHYCLK (EMAC_PHYCLK_TX)
MIB_SYNC_CONTROLS (SYNC_TX_CONTROLS)
MIB_DUAL_RANK_SYNC (reset_sync)
MIB_PULSE_RISING_EDGE_DETECT (status_valid_detect)
MIB_DUAL_RANK_SYNC (status_valid_sync)
MIB_PULSE_GEN (status_valid_pulse_gen)
MIB_DUAL_RANK_SYNC (inc_complete_sync)
MIB_SYNC_VECTORS (sync_vectors)
MIB_SPECIAL_AND2 (and2_1xx)
MIB_SYNC_CONTROLS (SYNC_RX_CONTROLS)
MIB_DUAL_RANK_SYNC (reset_sync)
MIB_PULSE_RISING_EDGE_DETECT (status_valid_detect)
MIB_DUAL_RANK_SYNC (status_valid_sync)
MIB_PULSE_GEN (status_valid_pulse_gen)
MIB_DUAL_RANK_SYNC (inc_complete_sync)
MIB_SYNC_VECTORS (sync_vectors)
MIB_SPECIAL_AND2 (and2_1xx)
Format: A (B)
A = Module Name
(B) = Instance Name

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IBM Core Databook
5.5.1 Size
Since the core is synthesizable, any number of counters can be synthesized from 1 to the maximum, and they
can be of any width from 0 bits to the maximum, which is the width of the OPB (32 bits - exception: see
Section 3.1.7 aOctetsTransmittedOK on page 33, Section 3.1.13 aOctetsReceivedOK on page 38, and
Section 3.1.49 RXVLANUserPriorityField on page 60.) Therefore, the size of the core can vary based on the
configuration chosen at synthesis time.
The maximum configuration was test synthesized. This included all counters listed in Chapter 3 for a total of
64 counters. The counters were synthesized at the maximum of the OPB width (32 bits), except for RXVLA-
NUserPriorityField which is a fixed 3 bits wide, and aOctetsTransmittedOK and aOctetsReceivedOK, which
were synthesized at their maximum of 64 bits. This results in a total of 2,196 latches, including control logic.
To calculate the number of latches, add:
• For each counter selected, width + 1
• 60 interrupt status bits
• 64 interrupt enable status bits
• 117 control logic latches
The size might also vary based on the target OPB operating frequency and PHY clock frequency (based on
Ethernet mode), and the target voltage and temperature.
5.5.2 Technology
The Ethernet MIB synthesis constraints have been validated with the IBM ASIC SA-27E, Cu-11 and Cu-08
technologies.
5.6 Cell Names and Associated Library Elements

The MIB can use standard ASIC library elements, and does not require any arrays.
The MIB instantiates a 2-way AND gate. The instance is located in the MIB_SPECIAL_AND2 module. A
substitute needs to be found in the target library, and this MIB_SPECIAL_AND2 module needs to be changed
to instance that gate.
5.7 Performance and Operating Environment
5.7.1 Clock Frequencies
The clock frequencies for the MIB were validated in IBM ASIC SA-27E to 125×C at 1.65 V, Cu-11 high perfor-
mance to 125×C at 1.60 V and Cu-08 to 125×C at 0.70 V.
Table 10. Clock Frequencies

Mode MII Frequency Minimum OPB Frequency Maximum OPB Frequency
10 Mbps 2.5 MHz 33 MHz 133 MHz
100 Mbps 25 MHz 33 MHz 133 MHz
1000 Mbps 125 MHz 33 MHz 133 MHz
10 Gbps 156.25 MHz 10 MHz 133 MHz

Core Databook IBM
5.7.2 Voltages and Temperature Ranges
Supports extended voltages and extended temperature ranges, validated using the following parameters
during static timing analysis (see Table 11) with maximum configuration and maximum frequencies.
Table 11. Extended Voltages and Extended Temperature Ranges

Wireload
Technology Worst Case/Best Case Vdd Temperature Wireload Model Wireload Mode
Package
IBM ASIC SA-27E Worst case 1.65 V 125°C 5mzc4p 5.3mm_chip Top
Best case 1.95 V - 40°C
IBM ASIC Cu-11 Worst case 1.40 V 125°C 6lmc4a 1M_cells Top
IBM ASIC Cu-08 Worst case 0.8 V 125°C 7lbc4a 1M_cells Top
5.7.3 Nominal Power Dissipation
Nominal power dissipation depends on the clock frequencies chosen and the configuration implemented.
5.7.4 CoreConnect™ Device Compliance
The MIB has one CoreConnect OPB slave interface.
Table 12. OPB Device Compliance List (Page 1 of 2)

Item Protocol Description Supported?
OPB Slave Compliance

S1 Addressing Can coexist with other OPB slaves? Yes
OPB address decode size 32 Bits
Programmable address location Yes
Address decoding Internal
Supports 32-bit addressing Yes
Supports 64-bit addressing NoNotes:
S2 Read Operations Single byte No*
Halfword transfers No*
Fullword transfers Yes*

Doubleword transfers No*
S3 Write Operations Single byte Yes*
Halfword transfers Yes*
Fullword transfers Yes*
Doubleword transfers No*
S4 Aborts Support for master transaction aborts Yes

S5 Bus Locking Support locked_bus transfers Yes

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IBM Core Databook
Table 12. OPB Device Compliance List (Page 2 of 2)

Item Protocol Description Supported?
S6 Sequential Addressing Support sequential addressing (OPB_seqAddr signal) Yes
S7 Data Steering Support for writes from 8-bit masters No*
Support for writes from 16-bit masters No*

Support for writes from 32-bit masters Yes*
Support for writes from 64-bit masters No*
Support for reads from 8-bit masters No*
Support for reads from 32-bit masters Yes*
S8 Retry Without bus locked No
With bus locked No
S9 Wait/Timeout Slave provides for “timeout suppression (Sln_toutSup signal) Yes

S10 Transfer Errors Slave provides error acknowledgment when transfer errors Yes
occur? (Sln_errAck signal)
S11 Byte Enable Support for transactions with byte enables? No
Provide acknowledgements for byte-enabled transfers (use of the No

Sln_beAck signal)
Notes: S2, S3, S7 - The counters in the register file only support 32-bit write and 32-bit read. the Inter-
rupt Status registers and Enable Interrupt Status registers support 8-bit, 16-bit and 32-bit writes and 32-
bit reads.

Core Databook IBM
Appendix A. Asynchronous Interface

This is the comprehensive list of asynchronous crossings and synchronizing paths that must be timing
constrained in the chip for physical synthesis or physical design (place/route). In every case, the tests are
being done to ensure that the path between the output of one flip-flop to the input of the next flip-flop is
constrained to a maximum delay that is less than a full destination clock cycle. The implementation of these
tests is left to the user’s chip-level timing engineer, since signal names can vary and it is impossible to give
tests that will work for all users.
A.1 Assertion for Synopsys Tools

Example assertions for Synopsys tools could contain the following values:
set OPB_PERIOD 7.50

set OPB_SHORT_DELAY [expr 0.20 * ${OPB_PERIOD}]
set OPB_LONG_DELAY [expr 1.0* ${OPB_PERIOD}]
set_max_delay ${OPB_PERIOD} \
-from [get_pins -hier {*EMACMIB. EMAC_PHYCLK_RX.FRAME_BYTES_HOLD_REG_reg*/*}] \
-to [get_pins -hier {*REGFILE. aOctetsReceivedOK_reg*/*}]
Note: Due to variations and changes in the tool, the above are for example only. Implementation is left to the
user’s chip-level timing engineer.
A.2 EinsTimer Assertions

Example EinsTimer assertions could take the form:
set OPB_PERIOD 7.50

set OPB_SHORT_DELAY [expr 0.20 * ${OPB_PERIOD}]
set OPB_SHORT_DELAY [expr 1.0* ${OPB_PERIOD}]
et::set_user_defined_test -same_mode -early \

-pin1${instance}EMACMIB. EMAC_PHYCLK_RX.FRAME_BYTES_HOLD_REG_reg_0/L2 \
-pin2 ${instance}REGFILE. aOctetsReceivedOK_reg_0/D \
-wc_guard [expr -1.0 * ${OPB_LONG_DELAY}] \
-nominal_guard [expr -1.0 * ${OPB_LONG_DELAY}] \
-bc_guard [expr -1.0 * ${OPB_LONG_DELAY}] ;
Alternatively, creating a new phase for the asynchronous crossing, and basing asserted arrival times and
required arrival times, could take the form:
et::create_clock -name ASYNCOPBCLK+ -waveform [list 0 5] -period 10 ;

et::clone_phase -phase OPBCLK+ \
-pin ${instance}EMACMIB. EMAC_PHYCLK_RX.FRAME_BYTES_HOLD_REG_reg_0/E \
-new_phase ASYNCOPBCLK+ ;
et:: set_arrival -phase ASYNCOPBCLK@L \
-pins ${instance}EMACMIB. EMAC_PHYCLK_RX.FRAME_BYTES_HOLD_REG_reg_0/L2 -time 0.0 ;
et::set_required -phase ASYNCOPBCLK@L \
-pins ${instance}REGFILE. aOctetsReceivedOK_reg_0/D -time ${OPB_LONG_DELAY} ;

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IBM Core Databook
Note: Due to variations and changes in the tool, the previous assertions are for example only. Implementa-
tion is left to the user’s chip-level timing engineer.
Note: The EinsTimer assertion does not use wildcards and should be more directly specified, which requires
more assertions when multi-bit busses are involved.
• The Synopsys assertion would constrain the fourteen bits of the frame bytes hold register of the EMAC-
MIB unit to1 OPB clock period from output pin of the source flops (formed in the unit “EMACMIB” by the
RTL flop inferred by the reg named “FRAME_BYTES_HOLD_REG[3:0]” to the input pins of the destina-
tion flops (formed in the unit “REGFILE” by the RTL flops inferred by the reg named “aOctetsReceive-
dOK[63:0]”).
• The EinsTimer assertion would make the same constraint for just bit 0. Additional, similar assertions
would be required for the other paths. Users can be more specific about the hierarchy of the MIB instanti-
ation and might need to change the hierarchy divider character (a period [.] in this example) or pin delim-
iter (a front-slash [/] in this example).
A.3 User-Defined Timing Constraints for Asynchronous Clock Domain Crossings

There are several structures used in this core to implement its asynchronous behavior. They consist of:
• Flip-flop pairs for dual-rank synchronization
• Mux for data using AND gate enabled with synchronized valid signal.
Caution: Users are responsible for creating timing constraints in their design system in order to ensure the
correct operation of these structures.
Figure 10. Asynchronous Crossing and Synchronizer Flops
Asynchronous Synchronizer
Delay Path Delay Path
SOURCE_REG DESTINATION1_REG DESTINATION2_REG
D L2 D L2 D L2
Source Clock Destination Clock

Capture Flop

Core Databook IBM
Figure 11. Asynchronous Crossing With Gating
Delay Path
SOURCE_REG DESTINATION_REG
AND
D L2 D L2
Gating Signal
Synchronous to
Source Clock Destination Clock Destination Clock
Capture Flop
A.3.1 Synchronizer Flip-Flop Pairs
Reference Figure 10 Asynchronous Crossing and Synchronizer Flops on page 105. Flip-flop pairs are used to
synchronize signals to individual clock domains. Table 13 Table of Flip-Flops in Dual Rank Synchronization
Path lists the captured signal, the standard synthesized instance names of the capture flip-flops, and the
capture clock’s name: For example, correct operation of these flip-flop pairs can be ensured in one of the
following ways:
1. Ensure that the delay from the output of the first flip-flop to the input of the second flip-flop is, at most,
20% of the capture clock’s period.
2. Ensure that the flip-flops are placed next to each other, their clock inputs are connected to the same net
with minimum wiring length between them, and there is minimum wiring length between the output of the
first and the input of the second. The dual rank synchronizer only protects the second latch from metasta-
bility if the delay between the two flip-flops is kept to a minimum.
3. Change the following synchronizer file to instance a synchronizer library element equivalent to the recom-
mended function:
• MIB_DUAL_RANK_SYNC.v
The ‘LEVEL1’ to ‘LEVEL2’ paths are the metastability-hardening flip-flops that are used to ensure solid
synchronous signals after an asynchronous crossing. The flip-flops used in these instantiations should be
selected based on their electrical characteristics for stabilizing these signals. If the MIB is used in a tech-
nology where two back-to-back flip-flops are insufficient for metastability hardening, then the
MIB_DUAL_RANK_SYNC.v file can be altered to add a third flop, ‘LEVEL3’, and additional timing assertions
between ‘LEVEL2’ and ‘LEVEL3’ (similar to the ones between ‘LEVEL1’ and ‘LEVEL2’) can be used to
ensure metastability hardening of the asynchronous signals.
Table 13. Table of Flip-Flops in Dual Rank Synchronization Path (Page 1 of 2)

Signal to be Captured Instance Name of Flop 1 Instance Name of Flop 2 Capture Clock
RX_STATUS_VALID_EDGE_ EMACMIB. EMACMIB. OPB_CLK

PHY SYNC_RX_CONTROLS. SYNC_RX_CONTROLS.
status_valid_sync.LEVEL1 status_valid_sync.LEVEL2
RX_INC_COMPLETE_SYS EMACMIB. EMACMIB. PHY_RX_CLK

SYNC_RX_CONTROLS. SYNC_RX_CONTROLS.
inc_complete_sync.LEVEL1 inc_complete_sync.LEVEL2

120
IBM Core Databook
Table 13. Table of Flip-Flops in Dual Rank Synchronization Path (Page 2 of 2)

Signal to be Captured Instance Name of Flop 1 Instance Name of Flop 2 Capture Clock
RX_STATUS_VALID_EDGE_ EMACMIB. EMACMIB. OPB_CLK

PHY SYNC_RX_CONTROLS. SYNC_RX_CONTROLS.
SYS_RESET_SYS EMACMIB. EMACMIB. PHY_RX_CLK

SYNC_RX_CONTROLS. SYNC_RX_CONTROLS.
reset_sync.LEVEL1 reset_sync.LEVEL2
TX_STATUS_VALID_EDGE_ EMACMIB. EMACMIB. OPB_CLK

PHY SYNC_TX_CONTROLS. SYNC_TX_CONTROLS.
TX_INC_COMPLETE_SYS EMACMIB. EMACMIB. PHY_TX_CLK

SYNC_TX_CONTROLS. SYNC_TX_CONTROLS.
inc_complete_sync.LEVEL1 inc_complete_sync.LEVEL2
SYS_RESET_SYS EMACMIB. EMACMIB. PHY_TX_CLK

SYNC_TX_CONTROLS. SYNC_TX_CONTROLS.
reset_sync.LEVEL1 reset_sync.LEVEL2
A.3.2 Asynchronous Clock Domain Crossings (of Control and Status Signals)
Reference Figure 11 Asynchronous Crossing With Gating on page 106. Users must create constraints for
correct operation of the clock domain crossing signals, even though the signals are considered asynchro-
nous. Table 14 Table of Flip-Flops in Control Asynchronous Paths lists the signals which require use
constraints, the source(s) in the source clock domain and their sink(s) in the capture clock domain, and the
maximum delay between the points.
Ensure the delay from source point (input or flop) to the destination point (output or flop) is, at most, the value
specified in the Maximum Delay column.
Table 14. Table of Flip-Flops in Control Asynchronous Paths (Page 1 of 2)

Instance Name of Source Flip-Flop(s) Instance Name of Destination Flip-Flop(s) Maximum Delay from Source(s) to Des-
tination(s)
RX_STATUS_VALID_EDGE_PHY - RX_STATUS_VALID_EDGE_SYS - internal signal 1 OPB clock period
internal signal The standard synthesized instance name of the
The standard synthesized instance name flip-flip which sinks the asynchronous signal is:
of the flip-flop which sources this signal EMACMIB.SYNC_RX_CONTROLS.
is: status_valid_sync.LEVEL1
EMACMIB. SYNC_RX_CONTROLS.
status_valid_detect.TOGGLE
RX_STATUS_VALID_SYS - internal sig- RX_INC_COMPLETE_EDGE_PHY - internal sig- 1 PHY clock period (use clock period for
nal nal fastest mode to be used)
The standard synthesized instance name The standard synthesized instance name of the
of the flip-flop which sources this signal flip-flop which sources this signal is:
is: EMACMIB.SYNC_RX_CONTROLS.
EMACMIB.SYNC_RX_CONTROLS. inc_complete_sync.LEVEL1
status_valid_pulse_gen.TOGGLE
OPB_RESET - internal signal SYS_RESET_PHY - internal signal. 1 PHY clock period (use clock period for
The standard synthesized instance name The standard synthesized instance name of the fastest mode to be used)
is: EMACMIB.SYNC_RX_CONTROLS.
MIBOPB.OPB_LINK.H2O_MIB_xxx_yy reset_sync.LEVEL1
(Substitute core version number for
xxx_yy)

Core Databook IBM
Table 14. Table of Flip-Flops in Control Asynchronous Paths (Page 2 of 2)

Instance Name of Source Flip-Flop(s) Instance Name of Destination Flip-Flop(s) Maximum Delay from Source(s) to Des-
tination(s)
TX_STATUS_VALID_EDGE_PHY - TX_STATUS_VALID_EDGE_SYS - internal signal 1 OPB clock period

internal signal The standard synthesized instance name of the
The standard synthesized instance name flip-flip which sinks the asynchronous signal is:
of the flip-flop which sources this signal EMACMIB.SYNC_TX_CONTROLS.
is: status_valid_sync.LEVEL1
EMACMIB.SYNC_TX_CONTROLS.
status_valid_detect.TOGGLE
TX_STATUS_VALID_SYS - internal sig- TX_INC_COMPLETE_EDGE_PHY - internal sig- 1 PHY clock period (use clock period for
nal nal fastest mode to be used)
The standard synthesized instance name The standard synthesized instance name of the
is: EMACMIB.SYNC_TX_CONTROLS.
EMACMIB.SYNC_TX_CONTROLS. inc_complete_sync.LEVEL1
status_valid_pulse_gen.TOGGLE
OPB_RESET - internal signal SYS_RESET_PHY - internal signal. 1 PHY clock period (use clock period for
The standard synthesized instance name The standard synthesized instance name of the fastest mode to be used)
is: EMACMIB.SYNC_TX_CONTROLS.
MIBOPB.OPB_LINK.H2O_MIB_xxx_yy reset_sync.LEVEL1
(Substitute core version number for
xxx_yy)
Table 15. Table of Flip-Flops in MUX Asynchronous Paths (Page 1 of 13)

Instance Name of Source Flip-Flop(s) Instance Name of Destination Flip-Flop(s) Maximum Delay from Source(s) to Destination(s)
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aOctetsTransmittedOK* 1 OPB clock period

FRAME_BYTES_HOLD_REG*
EMACMIB.EMAC_PHYCLK_TX. REGFILE.ISA_6 1 OPB clock period

EMACMIB.EMAC_PHYCLK_RX. REGFILE.aOctetsReceivedOK* 1 OPB clock period

EMACMIB.EMAC_PHYCLK_RX. REGFILE.ISA_12 1 OPB clock period


EMACMIB.EMAC_PHYCLK_TX. REGFILE.aOctetsTransmittedOK* 1 OPB clock period

STATUS_HOLD_REG*0

STATUS_HOLD_REG*0
EMACMIB.EMAC_PHYCLK_TX. REGFILE.etherStatsCollisions* 1 OPB clock period

STATUS_HOLD_REG*1
EMACMIB.EMAC_PHYCLK_TX. REGFILE.ISB_6 1 OPB clock period

STATUS_HOLD_REG*1
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aSingleCollisions* 1 OPB clock period

STATUS_HOLD_REG*1

STATUS_HOLD_REG*1

120
IBM Core Databook

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aMultipleCollisionFrames* 1 OPB clock period

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aFramesWithDeferredXmis- 1 OPB clock period

STATUS_HOLD_REG*3 sions*

STATUS_HOLD_REG*3
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aLateCollisions* 1 OPB clock period

STATUS_HOLD_REG*4

STATUS_HOLD_REG*4

STATUS_HOLD_REG*4

STATUS_HOLD_REG*4
STATUS_HOLD_REG*5

STATUS_HOLD_REG*5
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aFramesAbortedDueToXSColls* 1 OPB clock period

STATUS_HOLD_REG*5
STATUS_HOLD_REG*5
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aFramesWithExcessiveDeferral* 1 OPB clock period

STATUS_HOLD_REG*6

STATUS_HOLD_REG*6
EMACMIB.EMAC_PHYCLK_TX. REGFILE.OctetsTransmittedOK* 1 OPB clock period
STATUS_HOLD_REG*7

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aFramesTransmittedOK* 1 OPB clock period

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aLateCollisions* 1 OPB clock period

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7

Core Databook IBM

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aMultipleCollisionFramesK* 1 OPB clock period

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aSingleCollisionFrames* 1 OPB clock period

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aBroadcastFramesXmittedOK* 1 OPB clock period

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aFramesAbortedDueToXSColls* 1 OPB clock period

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.TXFIFOUnderrun* 1 OPB clock period

STATUS_HOLD_REG*7
STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.TXBadFCS* 1 OPB clock period

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.TXPkts256to511Octets* 1 OPB clock period
STATUS_HOLD_REG*7

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.TXPkts64Octets* 1 OPB clock period

STATUS_HOLD_REG*7
STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aSQETestErrors* 1 OPB clock period

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aMulticastFramesXmittedOK* 1 OPB clock period

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.TXFramePausedByControl- 1 OPB clock period

STATUS_HOLD_REG*7 Packet*

STATUS_HOLD_REG*7

120
IBM Core Databook

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aMACControlFramesTransmit- 1 OPB clock period

STATUS_HOLD_REG*7 ted*

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.TXUnicastAddr* 1 OPB clock period

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.TXPkts1024toMaxSizeOctets* 1 OPB clock period

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.TXPkts128to255OctetsK* 1 OPB clock period
STATUS_HOLD_REG*7

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aPAUSEMACCtrol- 1 OPB clock period

STATUS_HOLD_REG*7 FramesTransmitted*
STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aCarrierSenseErrors* 1 OPB clock period

STATUS_HOLD_REG*7

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aFramesWithDeferredXmis- 1 OPB clock period
STATUS_HOLD_REG*7 sions*

STATUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aFramesLostDueToIntMACXmi- 1 OPB clock period

STATUS_HOLD_REG*7 tError*
EMACMIB_EMAC_PHYCLK_TX_STA REGFILE.ISA_10 1 OPB clock period

TUS_HOLD_REG*7
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aCarrierSenseErrors* 1 OPB clock period

STATUS_HOLD_REG*10

STATUS_HOLD_REG*10
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aSQETestErrors* 1 OPB clock period

STATUS_HOLD_REG*11

Core Databook IBM

STATUS_HOLD_REG*11
EMACMIB.EMAC_PHYCLK_TX. REGFILE.TXPkts64Octets* 1 OPB clock period

STATUS_HOLD_REG*12

STATUS_HOLD_REG*12

STATUS_HOLD_REG*13

STATUS_HOLD_REG*13

STATUS_HOLD_REG*14

STATUS_HOLD_REG*14

STATUS_HOLD_REG*15

STATUS_HOLD_REG*15

STATUS_HOLD_REG*16
STATUS_HOLD_REG*16
EMACMIB.EMAC_PHYCLK_TX. REGFILE.TXPkts1024toMaxSizeOctets* 1 OPB clock period

STATUS_HOLD_REG*17

STATUS_HOLD_REG*17
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aMACControlFramesTransmit- 1 OPB clock period
STATUS_HOLD_REG*18 ted*

STATUS_HOLD_REG*18
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aPauseMACCtrlFramesTrans- 1 OPB clock period

STATUS_HOLD_REG*19 mitted*
STATUS_HOLD_REG*19
EMACMIB.EMAC_PHYCLK_TX. REGFILE.TXBadFCS* 1 OPB clock period

STATUS_HOLD_REG*20

STATUS_HOLD_REG*20
EMACMIB.EMAC_PHYCLK_TX. REGFILE.TXFramePausedByControl- 1 OPB clock period

STATUS_HOLD_REG*21 Packet*

STATUS_HOLD_REG*21
EMACMIB.EMAC_PHYCLK_TX. REGFILE.TXUnicastAddr* 1 OPB clock period

STATUS_HOLD_REG*22

STATUS_HOLD_REG*22

120
IBM Core Databook

EMACMIB.EMAC_PHYCLK_TX. REGFILE.aMulticastFramesXmittedOK* 1 OPB clock period
STATUS_HOLD_REG*23

STATUS_HOLD_REG*23
EMACMIB.EMAC_PHYCLK_TX. REGFILE.aBraodcastFramesXmittedOK* 1 OPB clock period

STATUS_HOLD_REG*24

STATUS_HOLD_REG*24
EMACMIB.EMAC_PHYCLK_TX. REGFILE.TXFIFOUnderrun* 1 OPB clock period

STATUS_HOLD_REG*25

STATUS_HOLD_REG*25

STATUS_HOLD_REG*0
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aFramesReceivedOK* 1 OPB clock period

STATUS_HOLD_REG*0

STATUS_HOLD_REG*0
STATUS_HOLD_REG*0
EMACMIB.EMAC_PHYCLK_RX. REGFILE.etherStatsOversizePkts* 1 OPB clock period

STATUS_HOLD_REG*1
EMACMIB.EMAC_PHYCLK_RX. REGFILE.ISB_4 1 OPB clock period

STATUS_HOLD_REG*1
EMACMIB.EMAC_PHYCLK_RX. REGFILE.etherStatsJabbers* 1 OPB clock period
STATUS_HOLD_REG*1

STATUS_HOLD_REG*1
EMACMIB.EMAC_PHYCLK_RX. REGFILE.etherStatsCRCAlignErrors* 1 OPB clock period

STATUS_HOLD_REG*1

STATUS_HOLD_REG*1
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aFrameCheckSequenceErrors* 1 OPB clock period

STATUS_HOLD_REG*1

STATUS_HOLD_REG*1
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aInRangeLengthErrors* 1 OPB clock period
STATUS_HOLD_REG*1

STATUS_HOLD_REG*1
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aAlignmentErrors* 1 OPB clock period

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aBursts* 1 OPB clock period

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aBroadcastFramesReceivedOK* 1 OPB clock period

STATUS_HOLD_REG*2

Core Databook IBM

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aFramesLostDueToInt- 1 OPB clock period

STATUS_HOLD_REG*2 MACRcvError*
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aFramesReceivedOK* 1 OPB clock period

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aFrameTooLongErrors* 1 OPB clock period

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aMACControlFramesReceived* 1 OPB clock period

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aMulticastFramesReceivedOK* 1 OPB clock period

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aOutOfRangeLengthField* 1 OPB clock period

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aPAUSEMACCtrlFramesRe- 1 OPB clock period

STATUS_HOLD_REG*2 ceived*
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aRunts* 1 OPB clock period
STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aShortEvents* 1 OPB clock period

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aSymbolErrorDuringCarrier* 1 OPB clock period

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aUnsupportedOpcodesRe- 1 OPB clock period
EMACMIB.EMAC_PHYCLK_RX. REGFILE.etherStatsBroadcastPkts* 1 OPB clock period

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.* 1 OPB clock period
STATUS_HOLD_REG*2

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.etherStatsMulticastPkts* 1 OPB clock period

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.etherStatsPkts* 1 OPB clock period

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.etherStatsPkts64Octets* 1 OPB clock period

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.etherStatsPkts65to127Octets* 1 OPB clock period

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

120
IBM Core Databook

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REG- 1 OPB clock period

STATUS_HOLD_REG*2 FILE.etherStatsPkts1024to1518Octets*
EMACMIB.EMAC_PHYCLK_RX. REGFILE.ReceivedInLoopBackMode* 1 OPB clock period

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.RXFIFOOverrun* 1 OPB clock period

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.RXUnicastAddr* 1 OPB clock period

STATUS_HOLD_REG*2
EMACMIB.EMAC_PHYCLK_RX. REGFILE.RXVLANTaggedFrame* 1 OPB clock period

STATUS_HOLD_REG*2


STATUS_HOLD_REG*2
STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2
STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2
STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

Core Databook IBM

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2
STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2
STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2
STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*2

STATUS_HOLD_REG*3

STATUS_HOLD_REG*3

STATUS_HOLD_REG*3

STATUS_HOLD_REG*3

120
IBM Core Databook

EMACMIB.EMAC_PHYCLK_RX. REGFILE.etherStatsoversizePkts* 1 OPB clock period
STATUS_HOLD_REG*4
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aOutOfRangeLengthField* 1 OPB clock period

STATUS_HOLD_REG*4

STATUS_HOLD_REG*4

STATUS_HOLD_REG*4

STATUS_HOLD_REG*5

STATUS_HOLD_REG*5
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aFrameTooLongErrors* 1 OPB clock period

STATUS_HOLD_REG*5

STATUS_HOLD_REG*5

STATUS_HOLD_REG*5

STATUS_HOLD_REG*5
STATUS_HOLD_REG*5

STATUS_HOLD_REG*5

STATUS_HOLD_REG*5
STATUS_HOLD_REG*5

STATUS_HOLD_REG*5

STATUS_HOLD_REG*5
STATUS_HOLD_REG*5
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aBursts* 1 OPB clock period

STATUS_HOLD_REG*5

STATUS_HOLD_REG*5
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aSymbolErrorDuringCarrier* 1 OPB clock period

STATUS_HOLD_REG*8

STATUS_HOLD_REG*8

STATUS_HOLD_REG*8

STATUS_HOLD_REG*8

Core Databook IBM

STATUS_HOLD_REG*9

STATUS_HOLD_REG*9
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aInRangelengthErrors* 1 OPB clock period

STATUS_HOLD_REG*9

STATUS_HOLD_REG*9

STATUS_HOLD_REG*9

STATUS_HOLD_REG*9

STATUS_HOLD_REG*9

STATUS_HOLD_REG*9

STATUS_HOLD_REG*10

STATUS_HOLD_REG*10
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aShortEvents* 1 OPB clock period
STATUS_HOLD_REG*10

STATUS_HOLD_REG*10

STATUS_HOLD_REG*10
STATUS_HOLD_REG*10
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aRunts* 1 OPB clock period

STATUS_HOLD_REG*11

STATUS_HOLD_REG*11
STATUS_HOLD_REG*11

STATUS_HOLD_REG*11

STATUS_HOLD_REG*11

STATUS_HOLD_REG*11
EMACMIB.EMAC_PHYCLK_RX. REGFILE.etherStatsPkts64Octets* 1 OPB clock period

STATUS_HOLD_REG*12

STATUS_HOLD_REG*12

STATUS_HOLD_REG*13

120
IBM Core Databook

STATUS_HOLD_REG*13

STATUS_HOLD_REG*14

STATUS_HOLD_REG*14

STATUS_HOLD_REG*15

STATUS_HOLD_REG*15

STATUS_HOLD_REG*16

STATUS_HOLD_REG*16
EMACMIB.EMAC_PHYCLK_RX. REG- 1 OPB clock period

STATUS_HOLD_REG*17 FILE.etherStatsPkts1024to1518Octets*

STATUS_HOLD_REG*17
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aMACControlFramesReceived* 1 OPB clock period

STATUS_HOLD_REG*18
STATUS_HOLD_REG*18
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aPAUSEMACCtrolFramesRe- 1 OPB clock period


STATUS_HOLD_REG*19

STATUS_HOLD_REG*20
EMACMIB.EMAC_PHYCLK_RX. REGFILE.ReceivedInLoopBackMode* 1 OPB clock period

STATUS_HOLD_REG*21
STATUS_HOLD_REG*21
EMACMIB.EMAC_PHYCLK_RX. REGFILE.RXVLANTaggedFrame* 1 OPB clock period

STATUS_HOLD_REG*22
EMACMIB.EMAC_PHYCLK_RX. REGFILE.RXVLANUserPriorityField* 1 OPB clock period

STATUS_HOLD_REG*22

STATUS_HOLD_REG*22

STATUS_HOLD_REG*22
EMACMIB.EMAC_PHYCLK_RX. REGFILE.RXVLANUserPriorityField*0 1 OPB clock period

STATUS_HOLD_REG*23

STATUS_HOLD_REG*24

Core Databook IBM

STATUS_HOLD_REG*25
EMACMIB.EMAC_PHYCLK_RX. REGFILE.RXUnicastAddr* 1 OPB clock period

STATUS_HOLD_REG*26

STATUS_HOLD_REG*26
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aMulticastFramesReceivedOK* 1 OPB clock period

STATUS_HOLD_REG*27
EMACMIB.EMAC_PHYCLK_RX. REGFILE.etherStatsMulticastPkts* 1 OPB clock period

STATUS_HOLD_REG*27

STATUS_HOLD_REG*27

STATUS_HOLD_REG*27
EMACMIB.EMAC_PHYCLK_RX. REGFILE.aBroadcastFramesReceivedOK* 1 OPB clock period

STATUS_HOLD_REG*28

STATUS_HOLD_REG*28

STATUS_HOLD_REG*28
STATUS_HOLD_REG*28
EMACMIB.EMAC_PHYCLK_RX. REGFILE.RXFIFOOverrun* 1 OPB clock period

STATUS_HOLD_REG*29

STATUS_HOLD_REG*29

120

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Revision 11 Ethernet Management Information Base (MIB)

2. Functional Description ............................................................................................. 21

3. Software Interface ..................................................................................................... 23

3.1.28 aPAUSEMACCtrlFramesTransmitted .................................................................................. 47

4. Hardware Interface .................................................................................................... 77

Revision 11 Ethernet Management Information Base (MIB)

4.1.3 Content of Transmit Status Word for 10 G Applications ........................................................ 84

5. Core Integration ........................................................................................................ 91

Appendix A. Asynchronous Interface ....................................................................... 104

Revision 11 Ethernet Management Information Base (MIB)

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Version Date Description of Revision Page

Added additional instruction to chip-level timing engineer in Section Appendix A. , 104

Fixed typos in first bullet in Section A.2 , EinsTimer Assertions. 104

Version Date Description of Revision Page

Changed paragraph to Note, to emphasis need for RESET_ON_READ must be 24, 92

AddedCoreConnect Revision ID Register table. and Section 3.1.69, CoreConnect 28, 73

Changed RESET_ON_READ to 0 for default configuration. 92

Added to description for Section 5.3.2.5 , MIB Clocks 97

Changed description of minimum reset requirement in Section 5.2, Initialization 92

Changed paragraph to Note to emphasize requirement for PHY clocks to be running 92

Clarified description for Section 5.7.3, Nominal Power Dissipation 102

Added reference to need to substitute instance of 2-way and in module 101

Added description of User-Defined Timing Constraints (UDT) for asynchronous 105

Updated Section 5.7.3 Nominal Power Dissipation. 102

Added qualification to aPAUSEMACCTrlFramesTransmitted in Section 3.1.28 47

Changed the word ‘incremented’ to ‘loaded’ on RXVLANUserPriorityField in 60

Added cc -E -C alternative to cpp for invoking C preprocessor in Section 5.1 Config- 91

Revision 11 Ethernet Management Information Base (MIB)

Version Date Description of Revision Page

Updated references in Section 1.4 References to support 10G. 19

Updated Section 1.5 Additional Required Elements to support 10G. 20

Added indication of application to Table 1 MIB Counters and Registers Summary. 25

Added 10G information to Section 3.1.24 aSymbolErrorDuringCarrier. 45

Commented use of MIB_TX(RX)_RDY and OPB Sequential Address operations in 77, 88

Updated text in Section 5 Core Integration. 91

Added Section 3.1.33 etherStatsOctets. 51

Revision 5 March, 2001 Revised Section 5.3.2.6 Supplied Timing Constraints. 98

Revision 5 February, 2001 Updated bullet #5 in Section 3.2 Interrupt Handling. 74

Removed all references to Class 1 Power Management. —

Added Notation Conventions to the Preface. 14

Removed Transfer Size table from Section 4.2 OPB Interface. 88

Added Table 10 Clock Frequencies to Section 5.7.1 Clock Frequencies. 101

Updated information in Table 11 Extended Voltages and Extended Temperature 102

Version Date Description of Revision Page

Added paragraph to Section 3.1.7 aOctetsTransmittedOK. 33

Added paragraph to Section 3.1.13 aOctetsReceivedOK. 38

Removed sentence from Section 3.1.35 etherStatsBroadcastPkts. 52

Removed sentence from Section 3.1.36 etherStatsMulticastPkts. 52

From Section 3.1.1 aFramesTransmittedOK through Section 3.1.46 29 - 58

In Section 5.1 Configurability: 91

In Section 5.5.1 Size: 101

Revision 11 Ethernet Management Information Base (MIB)

Version Date Description of Revision Page

Added incrementation information to each register’s description in Section 3 Soft- 23