PLB4XAHB CoreDataBook

DesignWare® IBM
PLB4 Peripherals:
PLB4XAHB Bi-directional Bridge
Core Databook
Document Version 1.1.3
March 15, 2007

PLB4 Peripherals: PLB4XAHB Bi-directional Bridge
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PLB4 Peripherals: PLB4XAHB Bi-directional Bridge Revision History
Revision History
Date Doc Version Description

20 July, 2007 1.1.2 Updated with SNPS application note template
16 March, 2007 1.1.3 Updated for release as part of DesignWare Star-IP
PLB4 Peripherals.
March 15, 2007 Synopsys, Inc. 3

Revision History PLB4 Peripherals: PLB4XAHB Bi-directional Bridge

PLB4 Peripherals: PLB4XAHB Bi-directional Bridge Contents
Contents
1. Introduction ....................................................................................................................... 9
1.1. About this Document .................................................................................... 9
1.2. Overview of the Core.................................................................................... 9
2. Features and Functions .................................................................................................... 11
2.1. AMBA Advanced High Performance Bus Interface ............................................ 11
2.1.1. AHB Slave Interface ............................................................................. 11
2.1.2. AHB Master Interface ........................................................................... 12
2.2. Processor Local Bus Interface ...................................................................... 13
2.2.1. PLB Master Interface ............................................................................ 13
2.2.2. PLB Slave Interface .............................................................................. 14
2.3. Device Control Register Interface ................................................................. 15
2.3.1. DCR Master Interface ........................................................................... 15
2.3.2. DCR Slave Interface ............................................................................. 16
3. Hardware Interface Signals ............................................................................................. 17
3.1. I/O Description Tables ................................................................................ 17
3.2. I/O Symbol Diagram .................................................................................. 25
4. Functional Description ..................................................................................................... 27
4.1. Architectural Overview................................................................................ 27
4.2. PLB to AHB Bridge...................................................................................... 29
4.2.1. Description ......................................................................................... 29
4.2.2. PLB Slave Interface .............................................................................. 31
4.2.3. AHB Master Interface ........................................................................... 33
4.3. AHB to PLB Bridge...................................................................................... 42
4.3.1. AHB to PLB Bridge Overview.................................................................. 42
4.3.2. AHB Slave Interface ............................................................................. 43

Contents PLB4 Peripherals: PLB4XAHB Bi-directional Bridge
4.3.3. PLB Master Interface ............................................................................ 45

4.3.4. Transfer Mapping Tables ....................................................................... 46
4.3.5. Latency Table ...................................................................................... 82
4.3.6. Timing Diagrams ................................................................................. 84
4.4. Device Control Register Interface ................................................................. 92
4.4.1. Device Control Register Master Interface ................................................. 92
4.4.2. Device Control Register Slave Interface................................................... 93
4.5. Control and Status Registers ....................................................................... 93
4.5.1. CSR Mapping in AHB Address Space ....................................................... 93
4.6. System Integration Considerations ............................................................... 94
4.6.1. AMBA AHB Subsystem .......................................................................... 94
4.6.2. Endian Bit Order .................................................................................. 94
4.6.3. LOCK Transfers.................................................................................... 95
4.6.4. Deadlock Conditions ............................................................................. 95
4.6.5. Error Handling ..................................................................................... 96
4.6.6. 64-bit PLB Slave Accesses ..................................................................... 97
4.6.7. Retry Limit.......................................................................................... 97
4.6.8. Delayed Reads and Sideband aborts ....................................................... 97
4.6.9. Bidirectional Bridge ordering.................................................................. 98
4.7. Power Management .................................................................................... 99
4.8. Clocks .....................................................................................................100
4.9. Reset ......................................................................................................100
5. Register Descriptions ..................................................................................................... 101
5.1. PLB4XAHB Register Overview .....................................................................101
5.2. Register Memory Map ................................................................................102
5.3. Register Descriptions.................................................................................103
5.3.1. PLB to AHB Registers...........................................................................103
5.3.2. AHB to PLB Registers...........................................................................106
6. Configuration ................................................................................................................. 109
6.1. PLB4XAHB.defines.v ..................................................................................109
6.2. Configuration Parameters Table ..................................................................109
7. Synthesizing the PLB4XAHB Core .................................................................................. 113
7.1. Synthesis Constraints ................................................................................113
7.1.1. Considerations for Constraints ..............................................................113
7.1.2. Constraint Tables ................................................................................114
8. Reference Documentation ............................................................................................. 119

PLB4 Peripherals: PLB4XAHB Bi-directional Bridge List of Figures
List of Figures
Figure 1: The PLB4XAHB bridge in a SOC Environment ........................................... 10

Figure 2: I/O Symbol Diagram ............................................................................ 25
Figure 3: PLB4XAHB top level Architecture ............................................................ 28
Figure 4: PLB to AHB Top level Block Diagram ....................................................... 30
Figure 5: AHB Master Interface Block Diagram....................................................... 34
Figure 6: Decision Tree for HBURST[2:0] for 32-bit AHB ......................................... 36
Figure 8: Decision Tree for HBURST[2:0] for 128-bit AHB........................................ 38
Figure 9: Decision Tree for HSIZE[2:0] for 32-bit AHB ............................................ 39
Figure 11: Decision Tree for HSIZE[2:0] for 128-bit AHB .......................................... 41
Figure 12: AHB to PLB Top-level Block Diagram....................................................... 42
Figure 13: AHB Slave Interface Diagram................................................................. 43
Figure 14: PLB Master Interface Diagram................................................................ 45
Figure 15: Non-bufferable Write (HBURST=SINGLE, HSIZE=128) .............................. 85
Figure 16: Bufferable Write (HBURST=INCR4, HSIZE=128)....................................... 87
Figure 17: Non-bufferable Read (HBURST=SINGLE, HSIZE=128) ............................... 89
Figure 18: Bufferable Read (HBURST=INCR4, HSIZE=128) ....................................... 91

List of Tables PLB4 Peripherals: PLB4XAHB Bi-directional Bridge
List of Tables
Figure 1: The PLB4XAHB bridge in a SOC Environment ........................................... 10

Figure 2: I/O Symbol Diagram ............................................................................ 25
Figure 3: PLB4XAHB top level Architecture ............................................................ 28
Figure 4: PLB to AHB Top level Block Diagram ....................................................... 30
Figure 5: AHB Master Interface Block Diagram....................................................... 34
Figure 8: Decision Tree for HBURST[2:0] for 128-bit AHB........................................ 38
Figure 11: Decision Tree for HSIZE[2:0] for 128-bit AHB .......................................... 41
Figure 12: AHB to PLB Top-level Block Diagram....................................................... 42
Figure 13: AHB Slave Interface Diagram................................................................. 43
Figure 14: PLB Master Interface Diagram................................................................ 45
Figure 15: Non-bufferable Write (HBURST=SINGLE, HSIZE=128) .............................. 85
Figure 16: Bufferable Write (HBURST=INCR4, HSIZE=128)....................................... 87
Figure 17: Non-bufferable Read (HBURST=SINGLE, HSIZE=128) ............................... 89
Figure 18: Bufferable Read (HBURST=INCR4, HSIZE=128) ....................................... 91

PLB4 Peripherals: PLB4XAHB Bi-directional Bridge 1. Introduction
1. Introduction
1.1. About this Document

The application note details the design overview and configuration for the
DesignWare PLB4XAHB, a PLB4 to AHB bi-directional bridge. This document
also includes details on how to simulate and synthesize the core.
1.2. Overview of the Core

The Synopsys DesignWare® Cores PLB4XAHB Bi-directional bridge is a fully
synthesizable core that allows transactions from AMBA Advanced High
Performance Bus (AHB) to CoreConnect Processor Local Bus (PLB4) and vice
versa.
This bi-directional bridge is a configurable high performance bridge that
allows the integration of PowerPC-440FS CPU and PLB4 peripherals into an
AMBA AHB on-chip bus sub-system.
The bridge consists of two components
¾ AHB to PLB The bridge—the bridge is a slave on the AHB interface and
master on the PLB interface
¾ PLB to AHB bridge —the bridge is a slave on the PLB interface and
master on the AHB interface
The bridge can be configured to be unidirectional (either AHB2PLB
direction or PLB2AHB direction bridge) or bi-directional.
The bridge includes both master and slave interfaces on the Device
Control Register (DCR) bus Interface allowing Control and Status Register
(CSR) access.
Figure 1 displays how the PLB4XAHB bridge fits into a System on a Chip
(SOC) environment.

1. Introduction PLB4 Peripherals: PLB4XAHB Bi-directional Bridge
PLB Master 1 Power PC PLB Arbiter PLB Save
PLB4 Bus
P2A direction
A2P direction
PLB4XAHB
AHB Bus
AHB Fabric
(Decoder,
AHB Slave ARM Processor AHB Master
Arbiter, control/
data muxes)
Figure 1: The PLB4XAHB bridge in a SOC Environment

PLB4 Peripherals: PLB4XAHB Bi-directional Bridge 2. Features and Functions
2. Features and Functions
2.1. AMBA Advanced High Performance Bus

Interface
PLB4XAHB bridge is compliant to the transaction protocols in the AMBA
Advanced High-performance Bus (AHB) Specification 2.0, Ref. [2] for AHB
interface. Refer to this specification for detail transaction waveforms and
protocols.
Listed below are the AHB features that the bridge supports as a slave and
master in the AHB interface.
2.1.1. AHB Slave Interface

Supported features include the following items:
Slave on AHB interface for AHB to PLB transactions
Supports 32/64/128 bit AHB data bus width (static configurable option)
Operates at clock speeds up to 166 MHz
Supports all transfer types (HTRANS) - IDLE, BUSY, SEQ and NONSEQ
Supports all burst types (HBURST) for both read and write transactions
¾ Single Transfer
¾ Incrementing burst transfers (INCR4, INCR8 and INCR16)
¾ Wrapping Burst transfers (WRAP4, WRAP8 and WRAP16)
¾ Variable length Burst transfers (INCR)
Supports all transfer sizes (HSIZE) – Byte, half word, word, hsize64 and
hsize128
Issues all transfer responses (HRESP) - SPLIT, RETRY, OKAY, and ERROR
Operates in both multi-master and single-master AHB systems
Supports early burst termination
Supports Locked transactions
Supports non-buffer

2. Features and Functions PLB4 Peripherals: PLB4XAHB Bi-directional Bridge
able transactions from AHB to PLB based on HPROT[2]

The bridge Control and Status Registers (CSR) are also mapped to AHB
address space in addition to the DCR slave access. Note that these CSRs
do not have a separate HSEL. The AHB slave interface is shared between
data and CSR.
Note: The AHB slave interface ignores HPROT[3], which indicates cacheable
accesses. Both cacheable/non-cacheable INCR* and WRAP* transactions
are handled the same way and are converted to normal bursts on the PLB
interface. Refer to the Transfer table for details.
2.1.2. AHB Master Interface

Master on AHB interface for PLB to AHB transactions
Supports 32/64/128 bit AHB data bus width. This is a static configurable
option
Operates up to 166 MHz
Issues all transfer types (HTRANS) - IDLE, BUSY, SEQ and NONSEQ
Supports all burst types (HBURST) for both read and write transactions
¾ Single Transfer
¾ Incrementing burst transfers (INCR4, INCR8 and INCR16)
¾ Wrapping Burst transfers (WRAP4, WRAP8 and WRAP16)
¾ Variable length Burst transfers (INCR)
Supports all transfer sizes (HSIZE) – Byte, half word, word, hsize64 and
hsize128
¾ Supports all transfer responses (HRESP) issued by AHB slave - SPLIT,
RETRY, OKAY & ERROR . AHB slave’s transaction error response is
reported back to the PLB master by SL_MRdErr and SL_MIRQ signals
for read and write error, respectively. SEAR and SESR are used for
reporting the error address and status. (SL_MWrErr is not supported.)
Operates in both multi master and single master AHB system. The bridge
is the only AHB master in a single master AHB system.
Endianess - Support for both little and big Endian AHB. It is a static
configuration option. The data bytes and byte enables are swapped
accordingly if AHB is Little Endian.
HPROT[3], the protection control signal to indicate cacheable/non-
cacheable memory access, is supported.
The PLB’s ordered-transfer attribute (PLB_TAttribute[8]), is directly
translated into HPROT[2] - the AHB’s bufferable attribute bit. When
ordered-transfer is set on the PLB bus cycle, the HPROT[2] bit is set to
0x0 (i.e., non-bufferable), and vice-versa.
This attribute is intended to be conveyed only to AHB slaves. The bridge
always executes its transactions in the order initiated. In addition, the bridge
has a bit in the CSR, called Force Non-buffered, which force the AHB logic to
always set the HPROT[2] to 0x0 for all transactions, regardless of the
PLB_TAttribute[8] bit.

The following feature is not supported by the interface:

The bridge does not implement BUSY transfers on the AHB.
2.2. Processor Local Bus Interface

PLB4XAHB bridge is compliant to the transaction protocols in the 128-bit
Processor Local Bus Architecture (PLB) Specifications, version 4.6, Ref. [1] for
the PLB interface. Refer to this specification for detail transaction waveforms
and protocols
2.2.1. PLB Master Interface

Master on PLB interface for AHB to PLB transactions
Supports 128 data bus width slaves.
Supports only SINGLE transfers to 64-bit slaves.
Operates up to 166 MHz PLB bus operation. The bridge implements single
or dual clock FIFOs selected as a configurable option.
Generates Single and Fixed-length burst transfers for both read and write
transactions.
Address pipelining is supported for read followed by write or write followed
by read bufferable transfers
Supports Early Burst Termination from PLB slave.
Capable of generating Early Burst Termination as a PLB Master
The bridge records the transaction details in the status register for the
following error scenarios. The details stored in the CSR are the 32-bit PLB
address that encountered the error.
PLB timeout error
¾ PLBMWrErr
¾ PLBMRdErr
The bridge generates a non-maskable interrupt in response to the
Sl_MIRQ received from the PLB Slave device.
The following PLB features are not supported by the PLB master interface
Mn_TAttribute signals are not supported
Does not support Parity generation or checking
Does not support variable length burst transfers
Does not support any type of Line transfers
Burst transfers to 64-bit PLB slave are not supported. AHB master
initiating a burst transfer to 64-bit slave is considered a system error and
the bridge does not take any actions to correct or report this error
Address pipelining is not supported for write followed by write or read
followed by read
Dynamic data bus width sizing of 32/64-bit bus width

2.2.2. PLB Slave Interface

Slave on PLB interface for PLB to AHB transactions
Supports both 64-bit and 128-bit PLB masters. Both the read and write
data buses are 128-bit wide but PLB_MSize [1:0] is used to determine the
master’s data bus width. 32-bit and 256-bit data bus widths are not
supported.
Byte enables to indicate valid, contiguous byte lanes during write data
transfer
Separate read/write data buses. Capable of overlapped transfers of read
and write data on the PLB.
Supports all PLB transfers other than address-pipelined for both read and
write transactions
¾ Single transfer
¾ Variable-length burst transfer of one or more beats
¾ Fixed-length burst transfer of one or more beats
¾ 4, 8 or 16 word line data transfer. Always target word first in line read
response
¾ Write operations are posted by the PLB master. The bridge uses a FIFO
to queue the write data for transfer to the AHB slave
Supports transfer abort by the PLB master either in the same clock cycle
the request was being acknowledged or before the acknowledgement by
the bridge.
Supports slave requested re-arbitration. The bridge will assert
SL_rearbitrate signal when it is unable to perform the currently requested
transfer and requires the PLB arbiter to re-arbitrate the PLB bus. SL_wait
is not supported.
Supports 36-bit PLB addressing
¾ Use PLB_ABus[0:31] and PLB_UABus[28:31]. The minimum AHB
address space is 256MB. The maximum AHB address space is 64GB, in
increments of 256 MB.
Supports transaction error handling via SL_MRdErr and SL_MIRQ signaling
for read and write transactions, respectively, and SEAR and SESR
registers access with DCR. The bridge generates an interrupt to AHB host
coincident with the Sl_MIRQ generation. SL_MWrErr is not supported
High and low AHB bootstrap-address inputs. These inputs are used to
facilitate PLB address decoding in the bridge immediately after a system-
reset event and before the bridge’s internal TopAddr and BotAddr
registers are programmed with the AHB address range along with their
corresponding valid bits. This allows a PLB master, such as the PPC440
CPU, to fetch code from the AHB side of the bridge immediately after a
system-reset event. After the TopAddr and BotAddr registers are
programmed and their valid bits are set, these bootstrap addresses are
ignored, and addresses in TopAddr and BotAddr registers are used for PLB
address decoding.

The following PLB features are not supported by the PLB-to-AHB direction
of the bridge
¾ Address pipelining
¾ Dynamic data bus width sizing of 32- and 256-bit data bus widths
¾ Data compression and decompression
¾ Any PLB transfer type that is not memory transfer, which is
PLB_type[0:2] = 0x0. (That is, only memory transfer type is
supported.)
¾ The bridge asserts SL_rearbitrate signal when address pipelining is
detected. When the PLB transfer type is not memory transfer or when
a 32- or 256-bit PLB master initiates a PLB transfer, the bridge does
not acknowledge the transaction and lets the PLB timeout.
¾ The bridge does not implement bus snooping logic, and it does not
have the ability to invalidate the caches in the PLB masters, so if a PLB
master uses a memory on the AHB that can potentially be cached,
restrictions must be imposed on the AHB masters not to write to that
memory and it can only be a read-only memory to them, or the
memory cannot be cacheable for the PLB master.
¾ For a PLB fixed-length transfer, if the total bytes to be transferred are
64 bytes or more, only 64 bytes is transferred. The bridge uses
Sl_rdBTerm and Sl_wrBTerm to terminate the read burst and write
burst, respectively, in the data beat before the last beat of the
transaction.
2.3. Device Control Register Interface

PLB4XAHB bridge is compliant to the transaction protocols in the 32-bit
Device Control Register (DCR) Interface, version 2.9, Ref. [3] for the DCR
interface. Refer to this specification for detail transaction waveforms and
protocols.
2.3.1. DCR Master Interface

Interfaces to 10-bit DCR interface as a DCR master. DCR master is
memory mapped into 1K Word of AHB address space. AHB hosts can
access the PLB peripheral’s CSRs in the DCR interface using this DCR
master interface. This is a configuration option
Shares the AHB address space with the other PLB slaves. i.e. single HSEL
for both the data transactions to the PLB interface as well as to the DCR
interface
All AHB transactions towards DCR master interface should be SINGLE
transfer of WORD size. The bridge will issue an ERROR response for the
AHB DCR accesses that do not meet this condition.

2.3.2. DCR Slave Interface

Interfaces to 10-bit DCR interface as a DCR slave. The bridge’s CSRs are
mapped into a contiguous DCR address space. They are also accessible
from AHB interface. DCR slave interface is a configuration option.
The bridge CSRs in DCR slave interface are always accessed by an
external DCR master. i.e. In the configuration when the bridge has both
DCR master and DCR slave interface, bridge’s DCR master is meant only
to access the external DCR slaves.

PLB4 Peripherals: PLB4XAHB Bi-directional Bridge 3. Hardware Interface Signals
3. Hardware Interface Signals
3.1. I/O Description Tables

Below table gives details of all the I/O pins of PLB4XAHB in the maximum
configuration. Once configured for the end system, some of these I/O will not
be used in the implementation. For example, if the bridge is configured only
for AHB to PLB direction, all I/Os listed in the AHB master interface signals
and PLB slave interface signals is optimized away. Refer to section on
Configuring the PLB4XAHB bridge for the details on the configuration
parameters
Table 1: AHB Master Interface Signals

AHB Master Interface Signals
Port Name Direction Source Functional Description

M_HRDATA[127/63/31:0] Input AHB Bus Read Data Bus from the Slave. Data
width depends on the configuration
parameter AHB_MASTER_DATAWIDTH
M_HREADY Input AHB Bus Indicates the transfer has finished on
the bus
M_HRESP[1:0] Input AHB Bus Transfer response from AHB slave.
Decodes to OKAY, ERROR, RETRY and
SPLIT
M_HGRANT Input AHB Bus Signal from Arbiter indicating
PLB4XAHB AHB master has the access
to the bus.
M_HADDR[31:0] Output AHB Bus 32-bit System Address bus
M_HTRANS[1:0] Output AHB Bus Indicates the current type of transfer.
NONSEQUENTIAL, SEQUENTIAL, BUSY
or IDLE. BUSY is not supported by the
AHB Master of the bridge
M_HWRITE Output AHB Bus Indicates current transfer is a write
transfer
M_HSIZE[2:0] Output AHB Bus Indicates the size of transfer, which
can be byte, half word or word
transfers
M_HBURST[2:0] Output AHB Bus Indicates if the current transfer is a
burst transfer. Incrementing and
wrapping bursts are supported
M_HPROT[3] Output AHB Bus Indicates if the current transfer is
cacheable or non-cacheable. Other
bits of HPROT are not supported by
PLB4XAHB bridge master

3. Hardware Interface Signals PLB4 Peripherals: PLB4XAHB Bi-directional Bridge
AHB Master Interface Signals

M_HWDATA[127/63/31:0] Output AHB bus Write Data Bus from the Master. Data
width depends on the configuration
parameter AHB_MASTER_DATAWIDTH
M_HBUSREQ Output AHB arbiter PLB4XAHB bridge indicates to the AHB
arbiter that it needs the ownership of
the bus for data transfer.
M_HLOCK Output AHB Bus This signal indicates that the master
wants to do a Locked transfer.
Table 2: AHB Slave Interface Signals

AHB Slave Interface Signals

S_HSPLIT[15:0] Output AHB arbiter 16 bit bus to arbiter, used by
PLB4XAHB to indicate that it has data
ready for a master, and the arbiter
should allow the pending split
transaction of that master to complete
S_HRDATA[127/63/31:0] Output AHB Bus Read Data Bus. Data width depends
on the configuration parameter
AHB_SLAVE_DATAWIDTH
S_HREADY_RESP Output AHB Bus Indicates that the transfer has
finished in the bridge. PLB4XAHB
bridge uses this to insert wait states
during data transfer
S_HRESP[1:0] Output AHB Bus Transfer response from PLB4XAHB.
Decodes to OKAY, ERROR, RETRY and
SPLIT
S_HADDR[31:0] Input AHB Bus Address of the current transaction on
the bus
S_HTRANS[1:0] Input AHB Bus Transfer type of transfer on the bus
S_HWRITE Input AHB Bus Indicates current transfer is a write
transfer
S_HSIZE[2:0] Input AHB Bus Indicates the size of the transfer
S_HBURST[2:0] Input AHB Bus Indicates if the current transfer is a
burst transfer. Incrementing and
wrapping bursts are supported
S_HPROT2 Input AHB Bus Indicates if the current transfer is
bufferable or non-bufferable. Other
bits of HPROT are not supported by
PLB4XAHB bridge as an AHB slave
S_HWDATA[127/63/31:0] Input AHB Bus Write Data Bus. Data width depends
on the configuration parameter
AHB_SLAVE_DATAWIDTH
S_HSEL Input AHB Bus Input from the arbiter indicating
Decoder PLB4XAHB bridge is the selected slave
for the current transaction on the bus
S_HLOCK Input AHB Arbiter Indicates the current transaction is a
LOCK transfer from the current
master.

AHB Slave Interface Signals

S_HMASTER[3:0] Input AHB Arbiter Indicates the master number of the
current transfer. The bridge stores it
and uses it when the data for already
SPLIT master is ready. Also used to
see if the data swapping needs to be
performed for this address region
S_HREADY Input AHB Bus Used to indicate the completion of the
current data transfer on the bus.
Slave state machine qualifies the
HSEL with this HREADY to determine
that the current address on the bus is
meant for it
Table 3: AHB Interface Global Control Signals

AHB Interface Global Control Signals

HCLK Input Clock AHB system clock
Source
HRESETN Input Reset Active low, AHB system reset. This is
Controller used in conjunction with the
SYS_PLB_RESET. All sequential
elements in the bridge are cleared
and the outputs driven to the default
inactive state.
Table 4: PLB Slave Interface Signals

PLB Slave Interface Signals

PLB_PAVALID Input PLB Arbiter PLB Primary address valid indicator
from PLB arbiter
PLB_BUSLOCK Input PLB Arbiter Indicates that the current PLB transfer
is a Locked transfer
PLB_RNW Input PLB Arbiter Type of current transfer. A low
indicates a read transfer and high
indicates a write transfer
PLB_BE[0:15] Input PLB Arbiter Byte enables indicating which byte
lanes on the 128 bus are valid
PLB_LOCKERR Input PLB Arbiter This indicates whether the SEAR and
SESR registers are to be locked or
not.
PLB_SIZE[0:3] Input PLB Arbiter PLB Transfer size
PLB_ABUS[0:31] Input PLB Arbiter 32-bit Address bus
PLB_UABUS[28:31] Input PLB Arbiter 4 bits of the upper address bus, to
expand the memory mapping beyond
4GB


PLB_TATTRIBUTE_1 Input PLB Arbiter Indicates whether the access is
cacheable or not. This is transferred
to HPROT[3] on the AHB interface,
which indicates if the access is
cacheable or not.
PLB_TATTRIBUTE_3 Input PLB Arbiter Indicates whether the access is
guarded access or not. This is
transferred to HPROT[1] on the AHB
interface, which indicates if the access
is privileged or not.
PLB_TATTRIBUTE_8 Input PLB Arbiter Indicates if the write access is ordered
or not. This signal is ignored during
read transfer. PLB2AHB bridge
translates this bit to HPROT[2] on the
AHB interface, which indicates if the
access is bufferable or not.
PLB_SAVALID Input PLB Arbiter PLB secondary address valid indicator.
PLB2AHB direction does not support
address pipelining, so it asserts
SL_REARBITRATE in response to
PLB_SAVALID
PLB_MSIZE[0:1] Input PLB Arbiter PLB master data bus size of the
current master
PLB_MASTERID[0:3] Input PLB Arbiter PLB Master ID of the current
transaction. PLB2AHB bridge uses this
to determine which master’s error
signal are to be asserted, in case of
an error transaction
PLB_TYPE[0:2] Input PLB Arbiter PLB Transfer type. PLB2AHB bridge
supports only memory type of
transfers.
PLB_ABORT Input PLB Arbiter PLB abort. Indicates if the requested
transfer was aborted by the initiating
PLB master for the current primary
access on the PLB bus
PLB_WRBURST Input PLB Arbiter Indicates master has initiated an early
burst termination for the write burst
transaction.
PLB_RDBURST Input PLB Arbiter Indicates master has initiated an early
burst termination for the read burst
transaction.
PLB_WRDBUS[0:127] Input PLB Arbiter 128-bit PLB write data bus
M_ABORT_IN[0:15] Input PLB Masters This indicates if a requested access
from a master is aborted by that
master. Support for 16 such masters
is given to flush the already queued
read request in the bridge if the
master aborts it.
Note that Mn_Abort output from each
master should be routed to this input
since the bridge does a delayed read
from PLB to AHB direction. Refer to
section “Delayed Reads and Sideband
aborts” for the details.


SL_ADDRACK Output PLB slave Address Acknowledge from slave
SL_REARBITRATE Output PLB slave Indicates that the slave can not
acknowledge to the requested transfer
and needs the arbiter to re-arbitrate
the bus
SL_SSIZE[0:1] Output PLB slave Slave Data bus size. The bridge is
always 128-bit on the PLB bus
SL_MBUSY[0:15] Output PLB slave Slave Busy Indicator. Indicates the
bridge has a transaction ongoing or
pending on the PLB interface
SL_MRDERR[0:15] Output PLB slave Read Error Indicator. Indicates that a
read transaction from a specific
master encountered an error
SL_MIRQ Output PLB slave Slave Interrupt Indicator. The bridge
asserts MIRQ for write transactions
encountering an error condition
SL_WRDACK Output PLB slave Write Data Acknowledge
SL_RDDACK Output PLB slave Read Data Acknowledge
SL_RDCOMP Output PLB slave Slave Read Transfer Complete
Indicator
SL_WRCOMP Output PLB slave Slave Write Transfer Complete
Indicator
SL_WRBTERM Output PLB slave Slave Early Burst Termination signal,
for a write burst
SL_RDBTERM Output PLB slave Slave Early Burst Termination signal,
for a read burst
SL_RDWDADDR[0:3] Output PLB slave Slave read word address. This is the
word address within the line of data
requested by the master
SL_RDDBUS[0:127] Output PLB slave Read Data bus.
Table 5: PLB Master Interface Signals

PLB Master Interface Signals

M_REQUEST Output PLB Master PLB bus request to the Arbiter, from
PLB master interface
M_PRIORITY[0:1] Output PLB master Priority of the master’s request. This
is the output from the CSR bits,
except when there is AHB LOCK
transaction, bridge forces these
signals to correspond to highest
priority irrespective of the content of
the priority bits in the CSR
M_RNW Output PLB master Type of Transfer
M_BE[0:15] Output PLB master Byte Enable indicator. Indicates the
valid bytes in the 128-bit data bus
M_SIZE[0:3] Output PLB master Master Transfer Size

PLB Master Interface Signals

M_TYPE[0:2] Output PLB master Master Transfer Type
M_LOCKERR Output PLB master SEAR, SESR lock indicator. Master
indicates if the slaves SEAR and SEST
should be locked or not. The bridge
drives the value of the Bridge Control
Register LockErr bit on this signal
M_ABUS[0:31] Output PLB master 32-bit address bus
M_UABUS[28:31] Output PLB master Lower order 4 bits of the upper order
address bus M_UABUS. This is the
output of the Bridge Control Register.
M_WRBURST Output PLB master Master Burst write transfer indicator
M_RDBURST Output PLB master Master Burst read transfer indicator
M_WRDBUS[0:127] Output PLB master 128-bit write data bus
PLB_MADDRACK Input PLB arbiter Address Acknowledge from the arbiter
PLB_MTIMEOUT Input PLB arbiter PLB Master Bus Timeout. The bridge
gives an interrupt in response to the
M_TIMEOUT if the interrupt mask bit
is not set
PLB_MSSIZE[0:1] Input PLB arbiter PLB slave data bus size. Slave
indicates the size of its data bus when
PLB_PAVALID or PLB_SAVALID is
asserted.
PLB_MRDERR Input PLB arbiter PLB slave read error, indication the
slave encountered an error for the
read transaction
PLB_MWRERR Input PLB arbiter PLB slave write error, indication the
slave encountered an error for the
write transaction
PLB_MIRQ Input PLB arbiter PLB master, slave interrupt indicator.
The bridge stores this value in the
status register, and also generates an
PLB4XAHB_INTR in response to this
PLB_MWRDACK Input PLB Arbiter PLB master slave write data
acknowledge
PLB_MRDDACK Input PLB Arbiter PLB master slave read data
acknowledge
PLB_MRDBTERM Input PLB Arbiter PLB master terminate read burst
indicator. The bridge re-requests the
bus to complete the incomplete read
burst transaction.
PLB_WRBTERM Input PLB Arbiter PLB master terminate write burst
indicator. The bridge re-requests the
bus to complete the incomplete write
burst transaction
PLB_RDWDADDR[0:3] Input PLB Arbiter PLB master read word address.
Indicates the address of the word in
the requested line transfer.
PLB_MRDDBUS[0:127] Input PLB Arbiter PLB master read data bus

Table 6: PLB Interface Global Control Signals

PLB Interface Global Control Signals

SYS_PLBCLK Input Clock PLB system clock input
Source
SYS_PLBRESET Input Reset PLB system global reset. All the
controller sequential elements in the bridge are
cleared, and outputs driven to their
default inactive state
Table 7: DCR Slave Interface Signals

DCR Slave Interface Signals

CPU_DCRABUS[0:9] Input DCR master 10 bit CPU DCR address bus
CPU_DCRDBUSOUT[0:31] Input DCR master CPU DCR Data Bus Out
CPU_DCRREAD Input DCR master CPU DCR read control
CPU_DCRWRITE Input DCR master CPU DCR write control
DCR_CPUACK Output The bridge DCR Acknowledge from bridge,
DCR slave indicating the current transfer is to
bridge’s CSR
DCR_CPUDBUSIN[0:31] Output The bridge DCR CPU Data Bus in
DCR slave

Table 8: DCR Master Signals

DCR Master Interface Signals

CPU_DCRM_ABUS[0:9] Output The bridge 10-bit DCR address bus driven by the
DCR master bridge
CPU_DCRM_DBUSOUT[0:31] Output The bridge Data Bus Out for write transfer
DCR master
CPU_DCRM_WRITE Output The bridge Write control signal, from DCR master
DCR master
CPU_DCRM_READ Output The bridge Read control signal from DCR master
DCR master
DCRM_CPUACK Input DCR slave Acknowledge from DCR slaves
connected in DCR daisy chain
DCRM_CPUDBUSIN[0:31] Input DCR slave Read Data returned from the DCR
slave
DCR_CLK Inputs Clock DCR clock input for the DCR slave
source interface. This input should be edge
synchronous to SYS_PLBCLK input as
per DCR Specification 2.9
Table 9: Miscellaneous Signals

Miscellaneous signals

BOOTSTRAP_ADDR_HI[0:7] Input Tie HI/LO Bootstrap higher order address bits.
pins Refer to the description below
BOOTSTRAP_ADDR_LO[0:7] Input Tie HI/LO Bootstrap lower order address bits.
pins Refer to the description below
PLB4XAHB_INTR Output System The bridge interrupt in AHB clock
Interrupt domain.
Controller

3.2. I/O Symbol Diagram
Figure 2: I/O Symbol Diagram


PLB4 Peripherals: PLB4XAHB Bi-directional Bridge 4. Functional Description
4. Functional Description
4.1. Architectural Overview

AHB2PLB direction bridge converts the transactions from 32/64/128 bit wide
AHB masters to 64/128 bit wide PLB transfers on the PLB bus, DCR transfers
on 32-bit wide DCR bus, or to the bridge’s internal Control and Status
registers. The PLB2AHB direction of the bridge converts the transactions from
64/128 bit wide PLB masters to 32/64/128 bit wide AHB transactions on the
AHB bus.
Figure 3 is the top level block diagram of the PLB4XAHB bi-directional bridge.
The dotted blocks are optional and can be selected using the configuration
options PLB4XAHB_DCRM_SEL and PLB4XAHB_DCRS_SEL

4. Functional Description PLB4 Peripherals: PLB4XAHB Bi-directional Bridge
DCR BUS
PLB4XAHB_TOP
DCR AHB2PLB OR
MASTER BIDIRECTIONAL
INTERFACE
WDFIFO
AHB SLAVE PLB MASTER

INTERFACE TQFIFO INTERFACE
LOGIC LOGIC
RDFIFO
AHB BUS
DCR BUS
A
PLB BUS
PLB2AHB OR DCR
H
AHB2PLB OR CONTROL AND STATUS REGISTERS SLAVE
B
BIDIRECTIONAL IF
IF
RDFIFO
AHB MASTER PLB SLAVE

INTERFACE AFIFO INTERFACE
LOGIC LOGIC
WRFIFO
PLB2AHB OR
BIDIRECTIONAL
Figure 3: PLB4XAHB top level Architecture

The bi-directional bridge also includes an optional DCR master interface in
order for the AHB master to be able to access the PLB peripherals that have
their CSRs in the DCR address map. The bridge’s CSRs are mapped to AHB
address space and an optional DCR address space for bi-directional
configuration of the bridge or AHB2PLB unidirectional bridge. The CSRs of the
unidirectional PLB2AHB bridge always reside in the DCR memory region.

4.2. PLB to AHB Bridge

4.2.1. Description
The PLB-to-AHB bridge is a high-performance interface for PLB masters to the
AMBA AHB on-chip bus. The bridge logic is a slave on the PLB interface and a
master on the AHB interface. This allows a PLB master to use a 32-, 64-, or
128-bit AHB on-chip bus without any glue logic. The bridge is designed for
SOC designers and ASIC developers who want to use one or more PLB
masters, such as the PPC440-S core, with AHB peripherals
The PLB write and read data buses (PLB_wrDBus and SL_rdDBus,
respectively) are 128 bits, but the bridge supports both 64- and 128-bit PLB
masters based on the signal PLB_MSize[1:0], which may change with each
master’s request. However, the bridge’s AHB interface is statically configured
for a 32-, 64-, or 128-bit interface. The bridge can be used in either a single
master AHB system or a multi-master AHB system. It supports AHB slaves
that use SPLIT/RETRY responses.
The direction of the PLB4XAHB bridge is a configurable option, selected when
the PLB4XAHB_P2A_CFG parameter is defined.
Figure 4 displays a diagram of the PLB to AHB bridge.

PLB_wrDBus[0:127]
(32/64/128-bits)
(32/64/128-bits)
PLB transfer qualifiers
Figure 4: PLB to AHB Top level Block Diagram

4.2.2. PLB Slave Interface

4.2.2.1. FIFOs
The bridge uses WRFIFO, which is a 128-bit wide by 4 deep synchronous
dual-clock FIFO, for queuing the write data and byte enables from PLB. A
DesignWare FIFO, DW_fifo_s2_sf, is used in this design. The FIFO depth is set
to 4 in this design. Before the write data is pushed into WRFIFO, a buffer
register is used to collect the write data from PLB first as shown in Figure 5.
In a burst transaction, if the PLB master’s interface is 128-bit, the burst data
is pushed into WRFIFO in the next cycle from the buffer. However, if the PLB
master’s interface is 64-bit, then the write data [0:63] is steered to the upper
or lower 64-bit of the buffer based on Byte Enable values. Furthermore, the
write data is collected in the buffer based on the PLB address and burst
transaction type until the address advances to the next 16-byte boundary;
then, the data is pushed into WRFIFO. The byte enables are treated in the
same way as the write data.
Byte Swapping
The static configuration parameter PLB4XAHB_AHB_ENDIANESS is used to
indicate if AHB bus is little endian or big endian. If this parameter is set to 1,
byte swapping for the write data and byte enables are performed before they
are pushed into WRFIFO from the write buffer. Byte swapping for read
response data from the output of RDFIFO is carried out the same way before
the data is put on the SL_rdDBus.
AFIFO
Another 4-deep synchronous dual-clock FIFO, AFIFO, is used to store the
information such as the start address, read/write, transaction type, and the
byte count for the transaction. AFIFO is implemented with the DesignWare
FIFO DW_fifo_s2_sf. PLB address and transfer qualifiers are latched into a
buffer register first when PLB_PAValid is detected. The 8 address bits
{PLB_UABus[28:31], PLB_ABUS[0:3]} are compared with the upper and
lower address ranges in the min_ahb_addr_reg and max_ahb_addr_reg
registers to determine if the transaction is for AHB. If it is, then based on the
conditions such as space availability in WRFIFO and AFIFO, the transaction
type, and PLB_abort signal, a decision is made to either accept the current
transaction by asserting SL_addrACK or ask the PLB to rearbitrate the
transaction by asserting SL_rearbitrate. If the transaction is aborted with
PLB_abort in the same cycle that the transaction is being acknowledged, then
nothing is pushed into AFIFO. The AHB address range registers,
min_ahb_addr_reg and max_ahb_addr_reg, are programmable via the DCR
interface
RDFIFO
RDFIFO is also a four-deep synchronous dual-clock FIFO for queuing read
data from AHB. In the AHB logic, there exists a read buffer that buffer collects
the read data from AHB, and appropriately address aligns it. When the
address advances to the next 16-byte boundary, the read buffer’s data is
pushed into RDFIFO. If the amount of data to be read does not warrant
crossing a 16-byte boundary, the data is pushed anyway into the RDFIFO,

when the required amount of data is collected. When a read transfer is

complete on the AHB side, AHB interface block sends the ahb_done_n signal
to PLB interface block, which uses this signal to start the PLB read data
transfer to complete the PLB read transaction. RDFIFO is implemented with
the DesignWare FIFO DW_fifo_s2_sf. It is to be emphasized that the RDFIFO
is not used as a buffer. It is used solely as a method of synchronizing
between the AHB and PLB clock domains. This is the reason we use the
DesignWare dual-clock symmetric FIFO (DW_fifo_s2_sf) for the RDFIFO.
Since the AFIFO is 4 deep, PLB transactions can be queued, especially write
transactions since writes are always posted. The following set of rules is used
in deciding when to queue a PLB transaction in AFIFO:
Queue single writes as long as WRFIFO and AFIFO have space (not full).
Queue a read transaction if AFIFO has space. Note that at a time only one
read transaction is queued in the AFIFO.
If WRFIFO is not empty, no burst (variable- or fixed-length) or 8/16 word
line write transaction is queued. A 4-word line write is queued if WRFIFO
is not full.
SL_rearbitrate is asserted when a valid transaction cannot be accepted by the
bridge due to unavailable resources.
In a bi-directional bridge configuration, during primary read transfers, when
the bridge’s read resources are free, the bridge responds with SL_rearbitrate
when there are posted writes in the other direction of the bridge. Refer to the
Bidirectional Bridge Ordering section for more details.
When PLB_SAValid is asserted, the bridge waits for the transfer to become
primary transfer and then asserts SL_rearbitrate based on the availability of
bridge resources. SL_wait is tied to logic 0, and the bridge does not use it.
Each DesignWare FIFO is instantiated in a FIFO wrapper. In this design flip-
flops are used as storage elements instead of a generated RAM from a RAM
compiler.
4.2.2.2. Burst Length

A variable-length burst write transaction is terminated by the bridge when
WRFIFO is full. The bridge asserts SL_wrBTerm to end the write burst. When
the transaction is ended, the byte count of the burst is computed and pushed
into the AFIFO for AHB interface logic. Similarly, for a variable-length read
burst, the bridge supplies as much data as can be queued into RDFIFO, and
terminates the burst transaction using SL_rdBTerm.
A fixed-length burst write is accepted up to 64-bytes or until the burst is
terminated by the PLB master. The bridge inserts wait states whenever
WRFIFO is full by not asserting SL_wrDAck. Similarly, the bridge returns
fixed-length burst read data to the PLB master whenever there is data in
RDFIFO. A fixed-length burst read is terminated when the RDFIFO becomes
empty or when the PLB master terminates it.
Whenever either a variable- or fixed-length burst read transaction error
occurred on AHB side, the AHB interface logic stops AHB read transactions
immediately. The bridge terminates the PLB burst transactions when the
remaining data in RDFIFO is empty. The appropriate SL_MRdErr and

SL_rdDAck are asserted for the last PLB read transfer. Both SEAR and SESR
are updated if they were not locked. SEAR is updated with the address of the
transaction for which the error occurs. SESR is updated with the error status.
Whenever either a variable- or fixed-length burst write transaction error
occurred on AHB side, the bridge terminates the AHB burst transaction
immediately. If there are data remaining in WRFIFO, WRFIFO is flushed by
the AHB interface control logic. SEAR and SESR are updated in the same
manner as before. For all write errors, the bridge asserts the appropriate
SL_MIRQ signal to the PLB master since write transactions is posted.
4.2.2.3. Memory Access

The bridge handles guarded memory access as follows. If the
PLB_TAttribute[3] (G - Guarded Storage Attribute) is not asserted, the 1K
page of memory corresponding to the requested address is well behaved, and
the bridge may cross the 1K page boundary to complete the burst normally. If
this bit is asserted, then the bridge restricts itself to exactly what is
requested, and it does not cross the 1K page boundary. The bridge
terminates the AHB transactions at 1K page boundary for either read or
writes in a variable- or fixed-length burst. Therefore, the read data supplied
from AHB to PLB is only up to the 1K page boundary; the write data is written
from PLB to AHB is only up to the 1K page boundary. The PLB interface logic
asserts the SL_wrBTerm to terminate the burst transaction at the 1K page
boundary for write; SL_rdBTerm is asserted to terminate the burst
transaction at the 1K page boundary for read.
The bridge does not do data prefetching on AHB side; it always fetches the
exact number of bytes required. For 4/8-word line transaction, the G bit is
ignored.
4.2.3. AHB Master Interface

This section discusses the structure, address paths and decision trees of the
AHB interface
4.2.3.1. Interface Structure

The AHB master interface consists of 3 sub-blocks: Address path, Read data
path, and Write data path. The internal structure of the AHB interface block is
shown in Figure 5.

Figure 5: AHB Master Interface Block Diagram

4.2.3.2. Address Path

The AHB interface is commanded via the Address and Data FIFOs. A non-
empty condition on the AFIFO causes the AHB interface to un-enqueue the
head end once, and initialize its start_address, byte_count, read/write
command and other transfer qualifiers. This sets the address-path finite state
machine in motion. The address-path FSM initiates the AHB bus cycle, by
driving the haddr, htrans, hwrite, hburst, and hsize signals.
4.2.3.3. Write Address Path

For write operations, the contents of the WRFIFO are used to drive the AHB’s
hwdata bus. If the width of the AHB data bus is 128 bits, then the non-empty
WRFIFO is un-enqueued on each clock that the hready signal is sensed active.
If the AHB data bus width is less than 128 bits (i.e., 32 bits or 64 bits), then
individual 32-bit word-lanes of the head-end word of the WRFIFO is
multiplexed out on to the hwdata bus, depending on the bus-width, and
address alignment. When all the required words of the head-end word of the
WRFIFO have been multiplexed out, the WRFIFO is popped once. This process
continues until the byte count for the transfer is exhausted.
Write-errors on the AHB interface cause the SEAR and SESR registers to be
updated (if they’re not locked), the current AHB operation is terminated and
the WRFIFO is flushed. The PLB interface will then assert SL_MIRQ. Read-
errors on the AHB interface cause the information to be propagated to the
PLB logic. The PLB interface will then assert SL_MRdErr on the PLB. As
described in the previous section, the AHB interface checks for 1K page
boundary when the G bit is set, so the read and write bursts do not cross the
1K page boundary.
If a write request comes in first and then a read request comes in, the AHB
interface ensures that the write operation completes first before a read
operation. If the write operation ends with an ERROR response, then the read
to the same address gets the old data.
4.2.3.4. Read Address Path

For read operations, data read from the hrdata bus is un-enqueued into the
RDFIFO. If the AHB data bus width is 128 bits, then data read from the hrdata
bus is enqueued every time the hready input from the AHB is asserted. If the
AHB data bus width is less than 128 bits (i.e., 32 bits or 64 bits), then the
data read from the hrdata bus is collected in a 128-bit wide buffer,
appropriately address-aligned, until either the top of the buffer fills up, or the
byte-count is exhausted. When either of these events happens, the buffer is
enqueued into the RDFIFO.

4.2.3.5. AHB Interface Decision Trees

The following figures illustrate the mapping between the PLB transactions’
characteristics and the AHB’s HBURST[2:0] and HSIZE[2:0] signals. Note that
in these figures, the values of HBURST and HSIZE are derived for the first
(i.e., NON-SEQ) cycle of the AHB transaction. The values driven at this point
are sustained until the current AHB transaction completes either successfully,
or with errors. Note that a given PLB transaction may require the bridge to
execute more than one AHB transaction. In this case, the HBURST and HSIZE
are derived afresh for each AHB transaction that needs to be run.
Figure 6: Decision Tree for HBURST[2:0] for 32-bit AHB

ahb_data_width
64-bits
PLB Burst FIXED_LENGTH/

SINGLE
Type VARIABLE_LENGTH
read Yes INCR8

4/8 WORD LINE OPERATION
count == 16
&& 16-byte
Yes INCR No
aligned
haddr yes count == 16
count >= 64 Yes INCR8
NO No
No
INCR No count == 32
SINGLE Yes
count >=32 Yes INCR4
Addr aligned No
Count == 64 32bytes?
Yes
count >= 16 Yes INCR
No
Addr aligned No
64bytes?
Yes WRAP4 INCR4
No SINGLE
INCR8 WRAP8


ahb_data_width
32-bits
2'b00 haddr[1:0]
HSIZE_32 Yes count >= 4
No
2'b10
No others
HSIZE_8
Figure 9: Decision Tree for HSIZE[2:0] for 32-bit AHB

ahb_data_width
64-bits
3'b000 haddr[2:0]
No
3'b100
3'b010,
No
3'b110

others
No
HSIZE_8

ahb_data_width
128 bits
4'b0000 haddr[3:0]
count >= 64 |
HSIZE_128 Yes
count == 16,32,48
No
count >=
HSIZE_64 Yes 4'b1000
8,24,40,56
No
4'b0100,
4'b1100
4'b0010,
4'b0110,
No 4'b1010,
4'b1110

others
No
HSIZE_8

4.3. AHB to PLB Bridge

4.3.1. AHB to PLB Bridge Overview
The AHB to PLB bridge logic is the slave on the AHB interface and master on
the PLB interface. It allows a AHB masters to use the PLB bus peripherals
without any glue logic.
The bridge PLB interface is 128 bits, but the bridge supports both 64- and
128-bit PLB slaves. The bridge’s AHB interface can be configured statically for
a 32-, 64-, or 128-bit interface.
The PLB4XAHB bridge direction can be configured by defining the
PLB4XAHB_A2P_CFG parameter.
The major blocks of the AHB2PLB bridge are described in the following
sections.
Figure 12: AHB to PLB Top-level Block Diagram

4.3.2. AHB Slave Interface

This chapter gives an overview of the AHB slave interface logic. The AHB
slave interface block includes an address decoder and the AHB slave state
machine. It interfaces to the other data FIFOs and the transaction Queue
FIFOs to pass the data and control to the PLB master interface from the AHB
clock domain.
Figure 13 displays an overview of the AHB interface logic.
s_hsel
s_hsize
s_write
s_htrans
s_hready s_hready_resp
s_hprot s_hresp s_haddr s_hwrite s_hrdata
CONTROL LOGIC + STATE MACHINE
DCR Master CONTROL

Bridge CSR TO TO FROM
Interface SIGNALS
Access TQFIFO WDFIFO RDFIFO
Access FROM CSR
Figure 13: AHB Slave Interface Diagram

The Address decoder determines whether the intended transfer on the AHB is
for
DCR Master Interface (optional block – as shown in the dotted lines)
The bridge CSR accesses
Data Path between AHB and FIFO (PLB Bus)
AHB slave state machine handles the following transfers.
The bridge CSR access
DCR bus access as Master, if enabled through configuration
Bufferable write transfers
Prefetchable read transfers
Non bufferable write transfers
Non bufferable read transfers
Locked write transfers
Locked read transfers
The AHB slave state machine is capable of generating all kinds of responses
as detailed in the feature list and makes use of the SPLIT response to improve
the AHB bus utilization.
In case of a write transfer, all the transaction details including control
information are transferred into the Transaction Queue FIFO (TQFIFO) and
the data associated with write transfer are loaded into the write data FIFO
(WDFIFO). The data from the AHB data bus is collected to 128-bit wide and
then pushed into WDFIFO. AHB slave interface logic used the
PLB4XAHB_AHB_ENDIANESS and PLB4XAHB_AHB_DATAWIDTH* parameters
as input for the data collection logic, to appropriately steer the correct byte
lanes into WDFIFO.
Similarly for the read transfers, the state machine first loads all the
transaction details including control information into the Transaction Queue
FIFO (TQFIFO). Whenever the data is available on the Read data FIFO
(RDFIFO), the state machine completes the transfer. The data from the
RDFIFO are disassembled before getting steered on the AHB data bus. AHB
slave interface logic used the PLB4XAHB_AHB_ENDIANESS and
PLB4XAHB_AHB_DATAWIDTH* parameters as input for the data
disassembling logic, to appropriately steer the correct byte lanes onto AHB
bus.
The transaction details such as HADDR, HBURST, HSIZE, HPROT, HLOCK are
stored in the TQFIFO. Based on the entries in TQFIFO, PLB master interface
initiates the transactions on the PLB bus. The transfer mapping table section
details how each transaction on AHB slave interface is converted to
corresponding PLB transfers.

4.3.3. PLB Master Interface

The PLB Master interface logic interfaces with the PLB bus on one side and
with the FIFO interfaces and CSR logic on the other side. It includes write,
read and request state machines as its main internal blocks.
The state machines handle the following transfers.
Single transfers
Line transfers
Burst transfers of Fixed Length
Dynamically change priority for Lock transfers on AHB Bus
Supports slave bus sizes of 64 and 128 bit
Address Pipelining. This feature can be disabled using a programmable bit
in the Bridge Control Register.
Error status reporting to CSRs
Support for bufferable and non bufferable transfers on AHB Bus
The following figure displays an overview of the PLB master interface logic.
Mn_abort
Mn_request
Mn_ABus
MnAbusPar
Mn_ABusParEn
Mn_UABus
Mn_UABusPar
Mn_UABusParEn
Mn_BE PLB_MnAddrAck
Mn_BEPar PLB_MnTimeout
MN_BEParEn PLB_MnRearbitrate PLB_MnRdDAck
Mn_Msize PLB_MnSSize PLB_MnRdBTerm
Mn_size PLB_Mbusy PLB_MnRdWdAddr Mn_wrBurst
Mn_priority PLB_MRdErr PLB_MnRdDBus Mn_wrDBus
Mn_type PLB_MWrErr Mn_rdBurst PLB_MnRdDBusPar Mn_wrDBusPar PLB_MnWrDAck SYS_plbClk
Mn_RNW PLB_MIRQ Mn_rdDBusParErr PLB_MnRdDBusParEn Mn_wrDBusParEn PLB_MnWrBTerm SYS_plbReset
PLB MASTER INTERFACE BLOCK
FROM FROM TO
BRIDGE CSR TQFIFO WDFIFO RDFIFO
WRITE
Figure 14: PLB Master Interface Diagram

The PLB State machine initiates transactions on PLB Bus based on the
contents of the Transaction Queue FIFO, Write Data FIFO and returns
response and/or data through Read Data FIFO.
The PLB Master module generates transactions as a master on the PLB Bus.
This block gets the new transaction information from TQFIFO and WDFIFO
and sends the data and status to AHB interface through RDFIFO. It also gets
control information from CSR block and reports error status information to
CSR. The PLB Master interface contains 3 state machines Request State
Machine, Write State Machine(WSM) and Read State Machine(RSM). For every
new entry in the TQFIFO the request state machine and control logic will issue
request to PLB Arbiter and will also trigger read state machine or write state
machine.
The read state machine or write state machine will either finish the transfer
with OK or ERROR response or trigger request state machine if a new
transaction need to be started to complete the transfer. Once a transaction is
started on the PLB master bus, the transactions can get terminated by the
PLB slave, or due to the unavailability of FIFO resources. The PLB master
state machine handle this efficiently by reinitiating the pending transfers by
from the stored pending transaction buffers.
4.3.4. Transfer Mapping Tables

4.3.4.1. About the Tables
This section describes how AHB transactions initiated by the AHB master are
converted into PLB transfers by the AHB to PLB direction of the bridge. Given
below are detailed tables for bufferable writes and prefetchable reads. All the
non-bufferable write and non-bufferable read transactions are always started
as single transfers on PLB Bus. Locked transactions on AHB Bus, are started
as regular PLB transfers with highest Master priority.
Note: In all the following transfer mapping tables for Hsize 128, 64 and 32,
the complete address range is not specified. The table can be extrapolated
for similar type of transfers with appropriate bit count and PLB address
Note: Following transfer tables are meant for PLB slave size of 128 bit. In
case of 64-bit PLB slave size, it is the responsibility of the application to
ensure that it does not initiate an AHB transfer of more than 64 bits
(targeted to 64 bit PLB Slave Device). If the application starts such a burst
transfer targeted to a 64-bit PLB slave device, it is considered a system
error and bridge does not take any corrective action nor does it follow any
error reporting mechanism
Note: Below is the example of how the transfer table should be interpreted
for the cases where a single transaction from AHB is converted to multiple
transactions on the PLB bus. The example is for AHB transaction with
HSIZE = 128 and HADDR = 2010
For INCR4: Burst of length 4 at Starting PLB Address 2010, Address

incremented internally for each data transfer (2020, 2030 and 2040
respectively). There are a total four data phases

For WRAP4: Broken into two PLB transactions

Burst of length 3, Starting PLB Address 2010, Address incremented
internally for each data transfer (2020 and 2030 respectively). There are a
total three data phases (first three data from WDFIFO).
Single transfer, starting at PLB Address 2000 (Last Data from the
WDFIFO)
Note: PLB master interface logic has an ability to rebuild the remaining
transaction when an early termination is encountered after a burst
transaction has started on the PLB bus. This rebuilding of transaction
happens in the following conditions.
If any burst transaction receives a Wr/RdBTerm from a PLB Slave then

only that transaction is rebuilt by PLB master until the beat count for that
burst transfer is exhausted. This rebuilt transaction is not combined with
the subsequent transaction to optimize the performance.
When any burst write transaction sees a EOT bit in WDFIFO, it is
terminated by PLB Master. Remaining transactions (for that table entry)
are discarded.
When any transaction is terminated because of a FIFO full (reads) or
empty (writes) condition, then only the current transaction is rebuilt when
the FIFO resources become available again.
Note: If the address is aligned to WRAP# boundary (for any HSIZE) then it is
implemented as corresponding INCR# e.g. WRAP4 is implemented as
INCR4
Note: All SINGLE read transactions are started with all byte enables
asserted. The PLB master Interface logic will push only proper bytes in the
RDFIFO based on address.
Note: One AHB INCR Read transaction may result into multiple Fixed Length
Burst Reads of quadwords on the PLB Bus. Consider the scenario where
there is an INCR Read (on AHB Bus for any HSIZE) and it continues the
transaction beyond 8 beats, then AHB Slave first introduce wait states for
14 clcock and at the same time makes new entry in TQFIFO for another
Read and PLB Master would start another Fixed length burst Read of
Quadword with 8 beat. If the Read is available in RDFIFO before 14 clock
wait limit is exhausted then AHB Slave will continue returning the read
data to AHB Master. If the 14 clock wait limit is exhausted and there is no
data available in RDFIFO then AHB Slave will issue split to the AHB Master
and will issue split completion request whenever the first data is available
in RDFIFO.

4.3.4.2. AHB to PLB Transfer Mapping Tables

Table 10: Bufferable Write Transfer: Hsize 128
Bufferable Write Transfer: Hsize 128
HADDR SINGLE INCR4 INCR8 INCR16 INCR WRAP4 WRAP8 WRAP16 PLB_ADDR
2000 Single Fixed Fixed Fixed Fixed Fixed burst of Fixed Fixed 2000
with All burst burst burst burst quad word, burst burst of
Byte of of of of beat 4 of quad quad
enables quad quad quad quad word, word,
word, word, word, word, beat 8 beat 16
beat beat beat beat
4 8 16 64
2010 Single Fixed Fixed Fixed Fixed Fixed length Fixed Fixed 2010
with All burst burst burst burst burst of quad length length
Byte of of of of word 3 beats burst burst of
enables quad quad quad quad of quad quad
word, word, word, word, word 7 word 15
beat beat beat beat beats beats
4 8 16 64
Single with All Single Single 2000
Byte enables with All with All
Byte Byte
enables enables
4 8 16 64
Fixed length Fixed Fixed 2000
burst of quad length length
word 2 beats burst burst of
of quad quad
word 2 word 2
beats beats
2030 Single Fixed Fixed Fixed Fixed Single with All Fixed Fixed 2030
with All burst burst burst burst Byte enables length length
Byte of of of of burst burst of
4 8 16 64
of quad quad
word 3 word 3
beats beats
with All burst burst burst burst quad word, length length
Byte of of of of beat 4 burst burst of
4 8 16 64
Fixed Fixed 2000
length length
burst burst of
of quad quad
word 4 word 4
beats beats


4 8 16 64
Single with All Fixed Fixed 2000
Byte enables length length
@2040 burst burst of
of quad quad
word 5 word 5
beats beats
4 8 16 64
@2040 of quad quad
word 6 word 6
beats beats
2070 Single Fixed Fixed Fixed Fixed Single with All Single Fixed 2070
with All burst burst burst burst Byte enables with All length
Byte of of of of Byte burst of
enables quad quad quad quad enables quad
word, word, word, word, word 9
beat beat beat beat beats
4 8 16 64
@2040 of quad quad
word 7 word 7
beats beats
with All burst burst burst burst quad word, burst length
Byte of of of of beat 4 of quad burst of
enables quad quad quad quad word, quad
word, word, word, word, beat 8 word 8
beat beat beat beat beats
4 8 16 64
Fixed 2000
length
burst of
quad
word 8
beats


4 8 16 64 Single with All Single Fixed 2000
Byte enables with All length
@2080 Byte burst of
enables quad
@2080 word 9
beats
20a0 Single Fixed Fixed Fixed Fixed Fixed length Fixed Fixed 20a0
4 8 16 64
@2080 of quad quad
word 2 word 10
beats beats
@2080
20b0 Single Fixed Fixed Fixed Fixed Single with All Fixed Fixed 20b0
4 8 16 64
@2080 of quad quad
word 3 word 11
beats beats
@2080
20c0 Single Fixed Fixed Fixed Fixed Single with All Fixed Fixed 20c0
4 8 16 64
Fixed Fixed 2000
length length
burst burst of
of quad quad
word 4 word 12
beats beats
@2080
20d0 Single Fixed Fixed Fixed Fixed Fixed length Fixed Fixed 20d0
4 8 16 64
Single with All Fixed Fixed 2000
Byte length length
enables@20c0 burst burst of
of quad quad
word 5 word 13
beats beats
@2080


20e0 Single Fixed Fixed Fixed Fixed Fixed length Fixed Fixed 20e0
4 8 16 64
@20c0 of quad quad
word 6 word 14
beats beats
@2080
20f0 Single Fixed Fixed Fixed Fixed Single with All Single Single 20f0
with All burst burst burst burst Byte enables with All with All
Byte of of of of Byte Byte
enables quad quad quad quad enables enables
word, word, word, word,
beat beat beat beat
4 8 16 64
@20c0 of quad quad
word 7 word 15
beats beats
@2080


2000 Single Fixed Fixed Fixed Fixed Fixed Fixed Fixed 2000
with Burst burst of burst of burst Burst burst burst of
Byte of Quad Quad of of of Quad
enables Quad word, word, Quad Quad Quad word,
word beat 4 beat 8 word, word word, beat 8
beat 2 beat 64 beat 2 beat 4
2008 Single Single Single Single Single Single Single Single 2008
with @2008 @2008 @2008 @2008 @2008 @2008 @2008
Byte with with with with with with with
enables Byte Byte Byte Byte Byte Byte Byte
enables enables enables enables enables enables enables
Single Fixed Fixed Fixed Single Fixed Fixed 2010
@2010 length length length @2010 length length
with All burst of burst of burst with All burst burst of
Byte quad quad of quad Byte of quad quad
enables words 4 words 8 words enables words words
beat beat 64 beat 3 beat 5 beat
@2010 @2010 @2010 @2010 @2010
(Though (Though
will will
finish finish
with 3 with 7
beats beats
Single Single Single Single Single Single

@2020 @2040 @2080 @2000 @2000 @2000
with with with with with with
Byte Byte Byte Byte Byte Byte
enables enables enables enables enables enables
2010 Single Fixed Fixed Fixed Fixed Single Fixed Fixed 2010
with Burst burst of burst of burst @2010 Burst Burst
Byte of Quad Quad of with All of of
enables Quad word, word, Quad Byte Quad Quad
word beat 4 beat 8 word, enables word word
@2010 @2010
Single Single Single 2000
@2000 @2000 @2000
with All with All with All
Byte Byte Byte
enables enables enables
with @2018 @2008 @2008 @2008 @2018 @2018 @2018


beat beat 64 beat 2 beat 6 beat
@2020 @2020 @2020 @2020 @2020
(Though (Though
will will
finish finish
with 3 with 7
beats beats
@2030 @2050 @2090 @2010 @2000 @2000
with with with with with All with All
Single Single
@2010 @2010
with with
Byte Byte
enables enables
with Burst burst of burst of burst Burst burst Burst
Byte of Quad Quad of of of of
enables Quad word, word, Quad Quad Quad Quad
word beat 4 beat 8 word, word word 2 word
beat 2 beat 64 beat 2 beat beat 6
@2020 @2020
Fixed Fixed
burst Burst
of of
Quad Quad
word 2 word
beat beat 2
@2000 @2000
with @2028 @2028 @2028 @2028 @2028 @2028 @2028
Single Fixed Fixed Fixed Single single Fixed 2030
@2030 length length length @2030 @2030 length
with All burst of burst of burst with All with All burst of
Byte quad quad of quad Byte Byte quad
enables words 4 words 8 words enables enables words
beat beat 64 beat 5 beat
@2030 @2030 @2030 @2030
(Though (Though
will will
finish finish
with 3 with 7
beats beats


Single Single Single Single Fixed Fixed
@2040 @2060 @20a0 @2020 burst burst of
with with with with of Quad
Byte Byte Byte Byte Quad word 2
enables enables enables enables word 2 beat
beat @2000
@2000
Single Single
@2020 @2020
with with
Byte Byte
enables enables
2030 Single Fixed Fixed Fixed Fixed Single Single Fixed 2030
with Burst burst of burst of burst @2030 @2030 Burst
Byte of Quad Quad of with All with All of
enables Quad word, word, Quad Byte Byte Quad
word beat 4 beat 8 word, enables enables word
beat 2 beat 64 beat 5
@2030
Single Fixed Fixed 2020
@2020 Burst Burst
with All of of
Byte Quad Quad
enables word word
beat 3 beat 3
@2000 @2000
with @2038 @2038 @2038 @2038 @2038 @2038 @2038
beat beat 64 beat 3 beat beat 4
@2040 @2040 @2040 @2000 @2040
(Though (Though
will will
finish finish
with 3 with 7
beats beats
Single Single Single Single Single Fixed
@2030 @2070 @20b0 @2030 @2030 length
with with with with with burst of
Byte Byte Byte Byte Byte quad
enables enables enables enables enables words
beat 3
@2000
Single
@2030
with
Byte
enables


with Burst burst of burst of burst Burst burst Burst
Byte of Quad Quad of of of of
enables Quad word, word, Quad Quad Quad Quad
word beat 4 beat 8 word, word word, word
beat 2 beat 64 beat 2 beat 4 beat 4
@2040
Fixed
Burst
of
Quad
word
beat 4
@2000
with @2048 @2048 @2048 @2048 @2048 @2048 @2048
@2050 burst of burst of burst @2050 burst burst of
with All quad quad of quad with All of quad quad
Byte words 4 words 8 words Byte words words
enables beat beat 64 beat enables 3 beat 3 beat
@2050 @2050 @2050 @2050 @2050
(Though (Though
will will
finish finish
with 3 with 7
beats beats
@2060 @2080 @20c0 @2040 @2040 burst of
with with with with with quad
Byte Byte Byte Byte Byte words
enables enables enables enables enables beat 3
@2000
Single
@2040
with
Byte
enables
with Burst burst of burst of burst @2050 Burst Burst
Byte of Quad Quad of with All of of
enables Quad word, word, Quad Byte Quad Quad
word beat 4 beat 8 word, enables word word
@2050 @2050
Single Single Fixed 2000

@2040 @2040 Burst
with All with All of
Byte Byte Quad
enables enables word
beat 5
@2000


with @2058 @2058 @2058 @2058 @2058 @2058 @2058
quad quad of quad with All of quad quad
words 4 words 8 words Byte words words
beat beat 64 beat enables 2 beat 2 beat
@2060 @2060 @2060 @2060 @2060
(Though (Though
will will
finish finish
with 3 with 7
beats beats
@2070 @2090 @20d0 @2050 @2040 burst of
with with with with with All quad
Byte Byte Byte Byte Byte words
enables enables enables enables enables 5 beat
@2000
Single Single
@2050 @2050
with with
Byte Byte
enables enables
with Burst burst of burst of burst Burst burst burst of
Byte of Quad Quad of of of Quad
enables Quad word, word, Quad Quad Quad word 6
word beat 4 beat 8 word, word word 6 beat
beat 2 beat 64 beat 2 beat @2060
@2060
Fixed Fixed
burst burst of
of Quad
Quad word 6
word 6 beat
beat @2000
@2040
with @2068 @2068 @2068 @2068 @2068 @2068 @2068
Single Fixed Fixed Fixed Single single single 2070
@2070 burst of burst of burst @2070 @2070 @2070
with All quad quad of quad with All with All with All
Byte words 4 words 8 words Byte Byte Byte
enables beat beat 64 beat enables enables enables
@2070 @2070 @2070
(Though (Though
will will
finish finish
with 3 with 7
beats beats


Single Single Single Single Fixed Fixed
@2080 @20a0 @20e0 @2060 burst burst of
with with with with of Quad
Byte Byte Byte Byte Quad word 6
enables enables enables enables word 2 beat
beat @2040
@2040
Single Single
@2060 @2060
with with
Byte Byte
enables enables
2070 Single Fixed Fixed Fixed Fixed Single Single single 2070
with Burst burst of burst of burst @2070 @2070 @2070
Byte of Quad Quad of with All with All with All
enables Quad word, word, Quad Byte Byte Byte
word beat 4 beat 8 word, enables enables enables
beat 2 beat 64
Single Fixed Fixed
@2060 Burst Burst
with All of of
Byte Quad Quad
enables word word
beat 3 beat 7
@2040 @2000
with @2078 @2078 @2078 @2078 @2078 @2078 @2078
Single Fixed Fixed Fixed single Fixed Fixed
with All quad quad of quad with All of quad quad
Byte words 4 words 8 words Byte words words
enables beat beat 64 beat enables 3 beat beat 7
@2080 @2080 @2080 @2040 @2000
(Though (Though
will will
finish finish
with 3 with 7
beats beats
@2090 @20b0 @20f0 @2070 @2070 @2070
with with with with with with


2000 Single Single Single 4 Fixed Single Single 4 2000
with of quad of quad singles burst of of quad of quad singles
Byte word word at of quad word word at of
enables address quad words address quad
2000 word 64 beat 2000 word
with @2000 with
address address
Single Single
2000, 2000,
of quad of quad
word at 2010, word at 2010,
address 2020, address 2020,
2010 2030 2010 2030
2004 Single Single Single 5 Single Single 3 5 2004
with with with singles with of quad singles singles
Byte valid valid of valid word at of of
enables 4 -15 4 -15 quad 4 -15 address quad quad
bytes bytes word bytes 2000 word word
@2004 @2004 with @2004 with with
valid valid valid
byte byte byte
Single @2010 enables Fixed enables enables
with Single at burst of at at
Valid 0- address quad address address
3 bytes Single 2000, words 2004, 2004,
@2010 @2020 64 beat
2010, 2010, 2010,
@2010
2020, 2000, 2020,
2030, 2030,
2040 2000
at at with at with with
address address valid address valid valid
2008 2008 byte 2008 byte byte
at at at
Single Single address Fixed address address
with @ 2010 2000, burst of 2008, 2008,
Valid 0 quad
2010, 2010, 2010,
- 7 words
bytes Single 2020, 64 beat 2000, 2020,
at with 2030, @2010 2030,
address Valid 0
2040 2000
2010 - 7
bytes
at
address
2020


200C Single Single Single 5 Single Single 3 5 200C
200C 200C byte 200C byte byte
at at at
with @ 2010 2000, burst of 200C, 200C,
Valid 0 quad
2010, 2010, 2010,
- 11 words
at with 2030, @2010 2030,
address Valid 0
2040 2000
2010 - 11
bytes
at
address
2020
Byte word word at of quad word word at of
enables address quad words address quad
2010 word 64 beat 2010 word
with @2010 with
address address
Single Single
2010, 2010,
of quad of quad
word at 2020, word at 2020,
address 2030, address 2030,
2020 2040 2000 2000
@2014 @2014 with @2004 with with
valid valid valid
byte byte byte
Single @2020 enables Fixed enables enables
with Single at burst of at at
Valid 0- address quad address address
3 bytes Single 2014, words 2014, 2014,
@2020 @2030 64 beat
2020, 2000, 2020,
@2010
2030, 2010, 2030,
2040, 2000,
2050 2010
2018 2018 byte 2018 byte byte


Single Single at Fixed at at
with @ 2020 address burst of address address
Valid 0 2018, quad 2018, 2018,
- 7 2020, words 2000, 2020,
bytes Single 64 beat
with 2030, 2010, 2030,
at @2020
address Valid 0 2040, 2000,
2020 - 7 2050 2010
bytes
at
address
2030
201C Single Single Single 5 Single Single 3 5 201C
201C 201C byte 201C byte byte
at at at
with @ 2020 200c, burst of 201C, 201C,
Valid 0 quad
2010, 2000, 2020,
- 11 words
at with 2030, @2020 2000,
address Valid 0
2040 2010
2020 - 11
bytes
at
address
2030


Byte word word of quad word word of
enables quad words quad
of quad word 64 beat word
word with @2000 with
valid valid
byte byte
enables enables
at at
address address
2000, 2000,
2010 2010
2002 Single Single 2 2 Single Single Single 3 2002
with with singles singles with with with singles
Byte Byte of of valid Byte Byte of
enables enables quad quad Byte enables enables quad
of quad of quad word word enables of quad of quad word
word word with with at word word with
valid valid address valid
byte byte 2002 byte
at at at
address address Fixed address
2000, 2000, burst of 2002,
quad
2010 2010 2010,
words
64 beat 2000
@2010
byte byte 2004 byte
at at at
2004, 2000, burst of 2004,
quad
2010 2010 2010,
words
64 beat 2000
@2010
byte byte 2006 byte


at at Fixed at
address address burst of address
2000, 2000, quad 2006,
2010 2010 words 2010,
64 beat
2000
@2010
byte byte 2008 byte
at at at
2000, 2000, burst of 2008,
quad
2010 2010 2010,
words
64 beat 2000
@2010
200A Single 2 2 2 Single Single Single 3 200A
with singles singles singles with with with singles
Byte of of of valid Byte Byte of
enables quad quad quad Byte enables enables quad
of quad word word word enables of quad of quad word
word with with with at word word with
valid valid valid address valid
byte byte byte 200A byte
enables enables enables enables
at at at at
address address address Fixed address
2000, 2000, 2000, burst of 200A,
quad
2010 2010 2010 2010,
words
64 beat 2000
@2010
200C Single 2 2 2 Single Single Single 3 200C
byte byte byte 200C byte
at at at at
2000, 2000, 2000, burst of 200C,
quad
2010 2010 2010 2010,
words
64 beat 2000
@2010


200E Single 2 2 2 Single Single Single 3 200E
byte byte byte 200E byte
at at at at
2000, 2000, 2000, burst of 200E,
quad
2010 2010 2010 2010,
words
64 beat 2000
@2010


2000 Single Single Single Single Fixed Single Single Single 2000
with of quad of quad of quad burst of of quad of quad of quad
Byte word word word quad word word word
enables words
of quad 64 beat
word @2000
2001 Single Single Single 2 Single Single Single Single 2001

2002 with of quad of quad singles with with with with 2002
2003 Byte word word of valid Byte Byte Byte 2003
enables quad Byte enables enables enables
2004 of quad word of quad of quad of quad 2004
enables
2005 word with at word word word 2005
2006 valid address 2006
2007 byte 2001 2007
enables or
2008 2008
2002
or … or
2008
Fixed
burst of
quad
words
64 beat
@2010
2009 Single Single 2 2 Single Single Single Single 2009
200A with of quad Singles singles with with with with 200A
Byte word of of valid Byte Byte Byte
200B 200B
enables quad quad Byte enables enables enables
200C of quad word word of quad of quad of quad 200C
enables
word with with at word word word
valid valid address
byte byte 2009
enables enables or
200A
or … or
200C
Fixed
burst of
quad
words
64 beat
@2010


200D Single 2 2 2 Single Single Single Single 200D
200E with singles singles singles with with with with 200E
Byte of of of valid Byte Byte Byte
200F 200F
enables quad quad quad Byte enables enables enables
of quad word word word enables of quad of quad of quad
word with with with at word word word
valid valid valid address
byte byte byte 200D,
enables enables enables or
at at at 200E,
address address address or 200F
2000, 2000, 2000,
2010 2010 2010
Fixed
burst of
quad
words
64 beat
@2010

Table 15: Prefetchable Read Transfer: Hsize 128

Prefetchable Read Transfer: Hsize 128
burst burst burst burst burst burst burst of
of of of of of of quad
quad quad quad quad quad quad word,
word, word, word, word, word, word, beat 16
beat 4 beat 8 beat beat 8 beat 4 beat 8
16
burst burst burst burst length length length
of of of of burst burst burst of
quad quad quad quad of of quad
word, word, word, word, quad quad word
beat 4 beat 8 beat beat 8 word word 15
16 3 7 beats
beats beats
1 1 1 single
single single
burst burst burst burst length length length
of of of of burst burst burst of
quad quad quad quad of of quad
word, word, word, word, quad quad word
beat 4 beat 8 beat beat 8 word word 14
16 2 6 beats
beats beats
Fixed Fixed Fixed
length length length
burst burst burst of
of of quad
quad quad word 2
word word beats
2 2
beats beats
2030 Single Fixed Fixed Fixed Fixed 1 Fixed Fixed 2030
burst burst burst burst single length length
of of of of burst burst of
quad quad quad quad of quad
word, word, word, word, quad word
beat 4 beat 8 beat beat 8 word 13
16 5 beats
beats
Fixed Fixed Fixed
of of quad
quad quad word 3
word word beats
3 3
beats beats


Prefetchable Read transfer: Hsize 64
of burst of burst burst of burst of burst burst burst of
double quad of quad quad quad of of quad
word word, word, word, word, quad quad word,
beat 2 beat 4 beat 8 beat 8 word, word, beat 8
beat 2 beat 4
of burst of burst burst of burst of length length length
double quad of quad quad quad burst burst burst of
word word, word, word, word, of 2 of 4 8
beat 3 beat 5 beat 9 beat 9 beats beats beats
at at @2000
address address @2000 @2000
2000 2000
of 128 of 128 of 128
@2000 @2000 @2000
of burst of burst burst of burst of of 128 length length
double quad of quad quad quad @2010 burst burst of
word word, word, word, word, of 3 7
beat 2 beat 4 beat 8 beat 8 beats beats
@2010
@2010

of 128 of 128 of 128
@2000 @2000 @2000
of burst of burst burst of burst of of 128 length length
double quad of quad quad quad @2010 burst burst of
at at @2010
address address @2010
2010 2010
Fixed Fixed Fixed 2000

of 2 of 2 2
beats beats beats
@2000
@2000 @2000
of burst of burst of burst of burst of burst length length
double quad quad quad quad of burst burst of
word word, word, word, word, quad of 2 6
beat 2 beat 4 beat 8 beat 8 word, beats beats
beat 2 @2020
at @2020


address Fixed Fixed
2000 length length
burst burst of
of 2 2
beats beats
@2000
@2000
of burst of burst of burst of burst of length length length
double quad quad quad quad burst burst burst of
at at at at @2020
address address address address @2020 @2020
2020 2020 2020 2020
of 128 length length
of 3 3
beats beats
@2000
@2000
of burst of burst of burst of burst of of 128 of 128 length
double quad quad quad quad @2030 @2030 burst of
word word, word, word, word, 5
beat 2 beat 4 beat 8 beat 8 beats
@2030

of 3 3
beats beats
@2000
@2000
of burst of burst of burst of burst of of 128 of 128 length
double quad quad quad quad @2030 @2030 burst of
word word, word, word, word, 5
beat 3 beat 5 beat 9 beat 9 beats
at at at at @2030
address address address address
2030 2030 2030 2030

of 2 of 4 4
beats beats beats
@2000
@2020 @2020


of burst of burst of burst of burst of burst burst length
double quad quad quad quad of of burst of
word word, word, word, word, quad quad 4
beat 2 beat 4 beat 8 beat 8 word, word, beats
beat 2 beat 4 @2040
Fixed
length
burst of
4
beats
@2000
at at at at @2040
2040 2040 2040 2040
of 128 of 128 length
@2040 @2040 burst of
5
beats
@2000
of burst of burst of burst of burst of of 128 length length
double quad quad quad quad @2050 burst burst of
@2050
@2050

of 128 of 128 length
@2040 @2040 burst of
5
beats
@2000
of burst of burst of burst of burst of of 128 length length
double quad quad quad quad @2050 burst burst of
at at at at @2050
address address address address @2050
2050 2050 2050 2050

of 2 of 2 6
beats beats beats
@2000
@2040 @2040


of burst of burst of burst of burst of burst length length
double quad quad quad quad of burst burst of
word word, word, word, word, quad of 2 2
beat 2 beat 4 beat 8 beat 8 word, beats beats
beat 2 @2060
@2060
Fixed Fixed
length length
burst burst of
of 2 6
beats beats
@2000
@2040
at at at at @2060
2060 2060 2060 2060
Single Fixed Fixed
of 2 7
beats beats
@2000
@2040
2070 Single Fixed Fixed Fixed Fixed Single Single Single 2070
of burst of burst of burst of burst of of 128 of 128 of 128
double quad quad quad quad @2070 @2070 @2070
word word, word, word, word,
Single Fixed Fixed

of 3 7
beats beats
@2000
@2040
of burst of burst of burst of burst of of 128 of 128 of 128
double quad quad quad quad @2070 @2070 @2070
word word, word, word, word,
at at at at
2070 2070 2070 2070


Fixed Fixed Fixed
of 2 of 4 8
beats beats beats
@2000
@2060 @2040


2000 Single Single Fixed Fixed Fixed Single Fixed Fixed 2000
with of quad burst of burst of burst of of quad burst of burst of
Byte word quad quad quad word quad quad
enables word, word, word, word, word,
at at at at at
address address address address address
2000 2000 2000 2000 2000
with burst of burst of burst of burst of of quad burst of burst of
Byte quad quad quad quad word at quad quad
enables word, word, word, word, address word, word,
beat 2 beat 3 beat 5 beat 9 2000 beat 2 beat 4
at at at at at at
address address address address address address
2000 2000 2000 2000 2000 2000
Single Single
of 128 of 128
@2000 @2000
at at at at at at
2000 2000 2000 2000 2000 2000
Single Single
of 128 of 128
@2000 @2000
200C Single Fixed Fixed Fixed Fixed Single Fixed Fixed 200C
at at at at at at
2000 2000 2000 2000 2000 2000
Single Single
of 128 of 128
@2000 @2000
2010 Single Single Fixed Fixed Fixed Single Single Fixed 2010
with of quad burst of burst of burst of of quad of 128 burst of
Byte word quad quad quad word @2010 quad
enables word, word, word, word,
at at at at
2010 2010 2010 2010


Single Single
of 128 of 128
@2000 @2000
with burst of burst of burst of burst of of quad of 128 burst of
Byte quad quad quad quad word at @2010 quad
enables word, word, word, word, address word,
beat 2 beat 3 beat 5 beat 9 2010 beat 3
at at at at at
2010 2010 2010 2010 2010
Fixed Fixed
burst of burst of
quad quad
word, word,
beat 2 beat 2
at at
address address
2000 2000
at at at at at
2010 2010 2010 2010 2010
Fixed Fixed
burst of burst of
quad quad
word, word,
beat 2 beat 2
at at
address address
2000 2000
201C Single Fixed Fixed Fixed Fixed Single Single Fixed 2010
at at at at at
2010 2010 2010 2000 2010
Fixed Fixed
burst of burst of
quad quad
word, word,
beat 2 beat 2
at at
address address
2000 2000


2020 Single Single Fixed Fixed Fixed Single Fixed Fixed 2020
with of quad burst of burst of burst of of quad burst of burst of
Byte word quad quad quad word quad quad
enables word, word, word, word, word,
at at at at at
2020 2020 2020 2020 2020
Fixed
burst of
quad
word,
beat 2
at
address
2000
at at at at at at
2020 2020 2020 2020 2020 2020
Single Fixed
of 128 burst of
@2020 quad
word,
beat 3
at
address
2000
at at at at at at
2020 2020 2020 2020 2020 2020
Single Fixed
of 128 burst of
@2020 quad
word,
beat 3
at
address
2000
202C Single Fixed Fixed Fixed Fixed Single Fixed Fixed 2020
at at at at at at
2020 2020 2020 2020 2020 2000


Single Fixed
of 128 burst of
@2020 quad
word,
beat 3
at
address
2000
2030 Single Single Fixed Fixed Fixed Single Single Single 2030
with of quad burst of burst of burst of of quad of 128 of 128
Byte word quad quad quad word @2030 @2030
enables word, word, word,
beat 2 beat 4 beat 8
at at at Single Fixed
address address address of 128 burst of
2030 2030 2030 @2020 quad
word,
beat 3
at
address
2000
with burst of burst of burst of burst of of quad of 128 of 128
Byte quad quad quad quad word at @2030 @2030
enables word, word, word, word, address
Fixed Fixed
beat 2 beat 3 beat 5 beat 9 2030
burst of burst of
at at at at
quad quad
word, word,
2030 2030 2030 2030
beat 2 beat 4
at at
address address
2020 2000
Fixed Fixed
burst of burst of
at at at at
quad quad
word, word,
2030 2030 2030 2030
beat 2 beat 4
at at
address address
2020 2000
203C Single Fixed Fixed Fixed Fixed Single Single Single 2030
Fixed Fixed
burst of burst of
at at at at
quad quad
word, word,
2030 2030 2030 2030
beat 2 beat 4
at at
address address
2020 2000


2000 Single Single Single Fixed Fixed Single Single Fixed 2000
with with of quad length burst of with of quad length
Byte Byte word burst of quad Byte word burst of
enables enables quad word, enables quad
word beat 8 word
length at length
2 address 2
2000
with with length length burst of with with length
Byte Byte burst burst of quad Byte Byte burst of
enables enables of quad quad word, enables enables quad
word word beat 9 of quad of quad word
length length at word word length
2 2000 3 2000 address 2
2000 starting
at
address
2000
Single
of 128
@2000
with with length length burst of with with length
Byte Byte burst burst of quad Byte Byte burst of
enables enables of quad quad word, enables enables quad
word word beat 9 of quad of quad word
length length at word word length
2 2000 3 2000 address 2
2000 starting
at
address
2000
Single
of 128
@2000
2006 Single Single Fixed Fixed Single Single Single Fixed 2006
with with length length of quad with with length
Byte Byte burst burst of word Byte Byte burst of
enables enables of quad quad Fixed enables enables quad
word word burst of of quad of quad word
length length quad word word length
2 2000 3 2000 word, 2
beat 9 starting
at at
address address
2000 2000
Single
of 128
@2000


2008 Single Single Fixed Fixed Single Single Single Fixed 2008
with with length length of quad with with length
Byte Byte burst burst of word Byte Byte burst of
enables enables of quad quad Fixed enables enables quad
word word burst of of quad of quad word
length length quad word word length
2 2000 3 2000 word, 2
beat 9 starting
at at
address address
2000 2000
Single
of 128
@2000
200A Single Fixed Fixed Fixed Single Single Single Fixed 200A
with burst of length length of quad with with length
Byte quad burst burst of word Byte Byte burst of
enables word, of quad quad Fixed enables enables quad
beat 2 word word burst of of quad of quad word
at length length quad word word length
address 2 2000 3 2000 word, 2
2000 beat 9 starting
at at
address address
2000 2000
Single
of 128
@2000
200C Single Fixed Fixed Fixed Single Single Single Fixed 200C
address 2 2000 3 2000 word, 2
at at
address address
2000 2000
Single
of 128
@2000
200E Single Fixed Fixed Fixed Single Single Single Fixed 200E
address 2 2000 3 2000 word, 2
at at
address address
2000


2000 Single
of 128
@2000
2010 Single Single Single Fixed Fixed Single Single Single 2010
with with of quad length burst of with of quad of quad
Byte Byte word burst of quad Byte word word
enables enables quad word, enables @2010
word beat 8
length at
2 at address Single
address 2010 of quad
2010 word
@2000
with with length length burst of with with of quad
Byte Byte burst of burst of quad Byte Byte word
enables enables quad quad word, enables enables @2010
word word beat 9 of quad of quad
length length at word word
2 at 3 at address Fixed
address address 2010 length
2010 2010 burst of
quad
word
length
2
starting
at
address
2000
with with length length burst of with with of quad
Byte Byte burst of burst of quad Byte Byte word
enables enables quad quad word, enables enables @2010
word word beat 9 of quad of quad
length length at word word
2 at 3 at address Fixed
address address 2010 length
2010 2010 burst of
quad
word
length
2
starting
at
address
2000
2016 Single Single Fixed Fixed Single Single Single Single 2016
with with length length of quad with with of quad
Byte Byte burst of burst of word Byte Byte word
enables enables quad quad Fixed enables enables @2010
word word burst of of quad of quad


length length quad word word Fixed
2 at 3 at word, length
address address beat 9 burst of
2010 2010 at quad
address word
2010 length
2
starting
at
address
2000
with with length length of quad with with of quad
Byte Byte burst of burst of word Byte Byte word
enables enables quad quad Fixed enables enables @2010
word word burst of of quad of quad
length length quad word word
2 at 3 at Fixed
word,
address address length
beat 9
2010 2010 burst of
at
quad
address
word
2010
length
2
starting
at
address
2000
201A Single Fixed Fixed Fixed Single Single Single Single 201A
with burst of length length of quad with with of quad
Byte quad burst of burst of word Byte Byte word
enables word, quad quad Fixed enables enables @2010
beat 2 word word burst of of quad of quad
at length length quad word word
address 2 at 3 at Fixed
word,
2000 address address length
beat 9
2010 2010 burst of
at
quad
address
word
2010
length
2
starting
at
address
2000
201C Single Fixed Fixed Fixed Single Single Single Single 201C
address 2 at 3 at Fixed
word,
beat 9
2010 2010 burst of
at
quad
address
word
2010
length
2
starting
at
address
2000


201E Single Fixed Fixed Fixed Single Single Single Single 201E
address at 3 at Fixed
word,
beat 9
2010h 2010 burst of
at
2 quad
address
word
2010
length
2
starting
at
address
2000


HADDR SINGLE INCR4 INCR8 INCR16 INCR/ WRAP4 WRAP8 WRAP16 PLB_ADDR
with with with of of quad of quad of quad of quad
Byte Byte Byte quad word word word word
enables enables enables word Fixed
of quad of quad of quad burst of
word word word quad
word,
beat 8
at
address
2000
2001 Single Single Single Fixed Single Single Single Single 2001
2002 with with with length of quad with with with 2002
Byte Byte Byte burst word Byte Byte Byte
2003 2003
enables enables enables of Fixed enables enables enables
2004 of quad of quad of quad quad of quad of quad of quad 2004
burst of
2005 word word word word quad word word word 2005
2006 length word, 2006
2007 2 beat 9 2007
2008 at 2008
address
2000
200A with with length length of quad with with with 200A
Byte Byte burst burst word Byte Byte Byte
200B 200B
enables enables of quad of Fixed enables enables enables
200C of quad of quad word quad of quad of quad of quad 200C
burst of
word word length word quad word word word
2 length word,
2 beat 9
at
address
2000
200D Single Fixed Fixed Fixed Single Single Single Single 200D
200E with length length length of quad with with with 200E
200F Byte burst burst burst word Byte Byte Byte 200F
enables of quad of quad of Fixed enables enables enables
of quad word word quad burst of of quad of quad of quad
word length length word quad word word word
2 2 length word,
2 beat 9
at
address
2000

4.3.5. Latency Table

Following is the latency table for read and write transactions initiated from
AHB master towards the slaves in the PLB interface. The table is based on the
architecture of the AHB2PLB direction of the bridge proposed in this
document. Following are the points to be noted regarding various
assumptions made in this table.
The estimated latency assumes synchronous clocking of the PLB and AHB
interface. This is for planning purposes only and does not represent a
requirement by IBM or a guarantee by Synopsys to achieve the stated
performance latency estimate.
The PLB Data Bus Size is 128 bits and the AHB Data Bus Size is 128 bits.
The write latency is from data available at the AHB interface to first data
available on the PLB interface. The read latency is from read request on
AHB interface to read data available on AHB interface.
The latency table assumes single cycle acknowledge timing behavior of
the PLB slaves. The latency numbers should be adjusted appropriately
depending on the timing behavior of the slaves. For example if the PLB
slaves follow a 3-cycle timing behavior, a value of 2 should be added to
the table entries
Table 20: Latency table for AHB to PLB transactions

PLB Transfer Estimated Latency
AHB Transfer AHB Size Write Read Write Read
Single byte Single Single 4 8
half Single Single 4 8
word Single Single 4 8
hsize64 Single Single 4 8
hsize128 Single Single 4 8
INCR byte Fixed length Fixed length 35 8
Burst of 64 burst of 8
beats beats
half Fixed length Fixed length 19 8
beats beats
word Fixed length Fixed length 11 8
beats beats
hsize64 Fixed length Fixed length 7 8
burst of 64 burst of 8
beats beats
burst of 64 burst of 8
beats beats
INCR4 byte 1- 2 Singles 1-2 Singles 7 8
half 1-2 Singles 1-2 Singles 7 8
word 1-2 Singles 1-2 Singles 7 8


hsize64 3 singles or Fixed length 5 8
Fixed Length burst
Burst of beat 2
hsize128 Fixed Length Fixed length 4 8
Burst of beat 4 burst
WRAP4 byte Single Single 7 8
word Single Single 7 8
hsize64 3 singles 8 word line 5 8
hsize128 2 fixed length Fixed 4 8
bursts or 1 Length
single and 1 Burst
fixed length
burst
INCR8 byte Singles 1-2 Singles 11 8
half Singles 1-2 Singles 11 8
word Singles Fixed length 7 8
burst
hsize64 2 singles and Fixed length 5 8
1 Fixed length burst
Burst or 1
fixed length
Burst
burst burst
word 3 Singles 3 Singles 7 8
hsize64 2/1 singles 8 word line 5 8
and 1 Fixed
length Burst
hsize128 2 fixed length 2 fixed 4 8
bursts or 1 length burst
single and 1
fixed length
burst
INCR16 byte Single Singles 19 8
half 2 Singles Fixed length 11 8
burst
word Multiple Fixed length 7 8
Singles burst
hsize64 2 singles and Fixed length 5 8
1 Fixed length burst
Burst or 1
fixed length
Burst
burst burst
half 3 singles Fixed length 11 8
Burst


word Multiple Multiple 7 8
singles Singles
hsize64 2/1 singles 2 fixed 5 8
and 1 Fixed length burst
length Burst
hsize128 2 fixed length 2 fixed 4 8
bursts or 1 length burst
single and 1
fixed length
burst
4.3.6. Timing Diagrams

The Following timing diagrams represent the actual behavior of the PLB4XAHB
bridge with The bridge acting as a slave on AHB side and master on the PLB
side. The conditions assumed are ideal viz. no transaction happening on AHB
Bus and PLB Bus, The bridge FIFOs are empty and no pending transactions in
the bridge.
4.3.6.1. Non-bufferable Write

This timing diagrams show a non-bufferable write from an AHB Master to the
PLB4XAHB bridge. The PLB Master interface of the bridge starts a single write
transfer and writes the status back into RDFIFO.
The markers in the waveform can be explained as:
AHB_nonbufwrite_SPLIT—The AHB master generates a non bufferable
write transfer to the bridge. The PLB4XAHB bridge as an AHB slave issues
SPLIT response to this transfer.
PLB_write_start—The PLB4XAHB bridge as a master on the PLB bus
initiates this write transfer by asserting the m_request
AHB_splitclear—The AHB slave interface on the PLB4XAHB bridge issues
split clear to the AHB master for which it has split before.
AHB_nonbufwrite_complete—The AHB master comes back with the
non buf transfer and this time the AHB slave interface on the PLB4XAHB
bridge issues the OKAY response.

Figure 15: Non-bufferable Write (HBURST=SINGLE, HSIZE=128)

4.3.6.2. Bufferable Write

This timing diagrams show a bufferable write from an AHB Master to the
PLB4XAHB bridge. The PLB Master interface of the bridge starts a Fixed
Length Quad word Burst write of length 4.
AHBxfer_start—The AHB master generates a bufferable write transfer to
the bridge. The PLB4XAHB bridge as an AHB slave issues OKAY response
to this transfer.
PLBxfer_start—The PLB4XAHB bridge as a master on the PLB bus
initiates this write transfer by asserting the m_request

Figure 16: Bufferable Write (HBURST=INCR4, HSIZE=128)

4.3.6.3. Non-bufferable Read

This timing diagrams show a non-bufferable read from an AHB Master to the
PLB4XAHB bridge. The PLB Master interface of the bridge starts a single read
transfer and writes the data and status back into RDFIFO.
AHB_nonbufread_SPLIT—The AHB master generates a non bufferable
read transfer to the bridge. The PLB4XAHB bridge as an AHB slave issues
SPLIT response to this transfer.
PLB_read_start—The PLB4XAHB bridge as a master on the PLB bus
initiates this read transfer by asserting the m_request
AHB_nonbufread_complete—The AHB master comes back with the non
buf read transfer and this time the AHB slave interface on the PLB4XAHB
bridge issues the OKAY response along with the read data on S_HRDATA.

Figure 17: Non-bufferable Read (HBURST=SINGLE, HSIZE=128)

4.3.6.4. Prefetchable Read

This timing diagrams show a bufferable read from an AHB Master to the
PLB4XAHB bridge. The PLB Master interface of the bridge starts a Fixed
Length Quad word Burst write of length 4.
AHB_read_SPLIT—The AHB master generates a bufferable read transfer
to the bridge. The PLB4XAHB bridge as an AHB slave issues SPLIT
response to this transfer.
PLB_read_start—The PLB4XAHB bridge as a master on the PLB bus
initiates this read transfer by asserting the m_request
AHB_read_complete—The AHB master comes back with the read
transfer and this time the AHB slave interface on the PLB4XAHB bridge
issues the OKAY response along with the read data on S_HRDATA.

Figure 18: Bufferable Read (HBURST=INCR4, HSIZE=128)

4.4. Device Control Register Interface

The PLB4XAHB bridge interfaces with a Device Control Register (DCR)
interface as a 32-bit master or 32-bit slave—or both. This is selected during
configuration using the parameters PLB4XAHB_DCRM_SEL and
PLB4XAHB_DCRS_SEL.
4.4.1. Device Control Register Master Interface

DCR master configuration is selected using the PLB4XAHB_DCRM_SEL
parameter. This configuration is useful in the following system configuration
scenarios:
Scenario 1—The host resides on AHB interface, the PLB peripherals
connected to the bridge have their control and status registers in DCR
slave interface, and there is no other DCR master capable host/peripheral
in the system
In Scenario 1, the bridge Configuration and Status Registers (CSR) and
the DCR master are mapped into AHB memory space. This scenario does
not require a DCR slave interface in the bridge. PLB4XAHB_DCRS_SEL can
be set to 0.
Scenario 2—A host appears on either side of the bridge, and the PLB
peripherals are allocated among both the hosts.
In Scenario 2, the bridge CSR are also mapped to DCR slave address
space accessed by a separate DCR master in the system, such as a
PowerPC or other DCR master-capable device. In this case, the DCR
master interface in the bridge can be used to access a separate set of PLB
peripherals having their CSRs in the DCR slave interface, and need to
accessed by the AHB master such as an ARM processor. This system
scenario requires both DCR master and DCR slave interfaces in the bridge
4.4.1.1. Device Control Register Master Accesses from AHB

In the AHB memory map, 4 KB of address space is allocated to the DCR
master interface. The base address for this memory map is fixed during
configuration using the PLB4XAHB_DCRM_BASE_ADDRESS configuration
parameter. PLB4XAHB bridge has a single HSEL shared between the DCR
master interface and AHB to PLB data transaction logic.
All AHB transactions towards DCR master interface should be SINGLE
transfers of WORD size. The bridge issues an ERROR response for the AHB
DCR accesses that do not meet this condition.
Note: The DCR master interface signals are synchronous to PLB interface
clock. So the DCR slaves in the DCR daisy chain controlled by this DCR
master interface should be connected to a clock that is edge synchronous
to the PLB clock as per the DCR specification 2.9

4.4.2. Device Control Register Slave Interface

PLB4XAHB bridge has a DCR slave interface when the PLB4XAHB_DCRS_SEL
configuration parameter is set to 1. In this configuration, both of the AHB2PLB
and PLB2AHB direction CSRs are mapped into contiguous address range in
the DCR address space. The DCR base address is fixed using the
PLB4XAHB_DCRS_BASE_ADDRESS parameter.
The bridge CSRs are also mapped in the AHB address space, from the base
address fixed using the PLB4XAHB_CSR_BASE_ADDRESS parameter.
4.5. Control and Status Registers

The Control and Status Registers (CSRs) of the bridge are mapped in the DCR
address region (if the PLB4XAHB_DCRS_SEL configuration parameter is set to
1) as well as in the AHB address region.
The AHB master interface block is responsible for updating SEAR and SESR
registers whenever a read or write transaction error response occurs from an
AHB slave. Similarly, the PLB master interface logic is responsible for
updating the AHB2PLB Error Status register and AHB2PLB Error Address
Register when there is a transaction error from a PLB slave. The host is
responsible for clearing these status bits by writing a 1 to these status bits.
Therefore, the status register update involves three different clock domains:
DCR_CLK
SYS PLBCLK
HCLK
Since SYS_PLBCLK and HCLK can be completely asynchronous to each other,
the CSR access control logic includes asynchronous handshaking logic
between SYS_PLBCLK and HCLK, as appropriate.
Note: It is the system designer’s responsibility to make sure that there are
no simultaneous accesses to the same CSRs from the DCR as well as the
AHB interface
4.5.1. CSR Mapping in AHB Address Space

In the A2P unidirectional bridge or bidirectional bridge configuration, the
bridge CSRs are always mapped in the AHB address space, in 16 consecutive
word addresses from the base address fixed using the
PLB4XAHB_CSR_BASE_ADDRESS parameter.
Note: Since the bridge uses the same HSEL for both CSR address maps and
PLB address maps, PLB4XAHB_CSR_BASE_ADDRESS should be set to an
address that lies within the address range programmed in the AHB arbiter
for HSEL generation for the PLB4XAHB bridge

Note: There is no provision in the bridge to disable this CSR address

mapping in AHB space.
While there is no provision to disable the CSR address mapping in the AHB
space, the system integrator can avoid the CSR access by the below method:
Program the PLB4XAHB_CSR_BASE_ADDRESS to an address outside the
range of addresses programmed in the AHB arbiter for the HSEL generation
for the Bridge. Since the Bridge’s address decoding logic always qualifies the
CSR accesses with HSEL, the accesses to CSR will not be done if the HSEL is
not generated along with the address.
4.6. System Integration Considerations

This section contains implementation-specific considerations for the system
integrator.
4.6.1. AMBA AHB Subsystem

Since the AHB to PLB direction always issues SPLIT for a fresh incoming read,
only an AMBA AHB full subsystem must be used. Since the AMBA AHB Lite
subsystem has no SPLIT or RETRY response support, the lite subsystem
cannot be used with the PLB4XAHB bridge.
4.6.2. Endian Bit Order

The AHB subsystem can be programmed to be little endian or big endian.
Little endian—the low-order byte is stored at the lowest address (the
little end comes first).
Big endian—the high-order byte is stored at the lowest address (the big
end comes first).
The bridge provides PLB4XAHB_AHB_ENDIANESS as a configuration
parameter to select endian mode. This parameter allow you to statically
configure the endianess appropriate to the AHB system it is integrated into.
The bridge AHB master interface logic and AHB slave interface logic
PLB4XAHB_AHB_ENDIANESS to steer and collect the data to and from the
appropriate byte lanes of the AHB bus.
Note: The PLB4XAHB bridge assumes a big endian PLB bus. There is no
special swapping mechanism in the bridge for the endianess conversion
from AHB bus to PLB bus or vice versa. When an AHB master needs to
interface with a little endian PLB slave, the SOC design or the little endian
PLB slave device connecting to the bridge should have this glue logic built
in.

4.6.3. LOCK Transfers

The bridge supports LOCK transactions from initiating masters in both
directions.
PLB to AHB—locked transactions from the PLB master are converted to
LOCK transfers on the AHB bus.
AHB to PLB—the bridge’s PLB master interface does not initiate LOCK
transfers on PLB bus. However, when transferring the LOCK transaction
from AHB bus, the bridge forces the priority bits M_PRIORITY to the
highest priority, value 2'b11.
In general, the bridge executes read and write transactions in the order
received. However, when there is a LOCK transfer from an AHB master, any
pending read transfers are aborted from other AHB masters that were
previously given SPLIT, and any data in the RDFIFO is flushed and HSPLIT is
given to the original AHB master. Subsequently, the LOCK transfer is allowed
to complete.
When the master that received the HSPLIT comes back to complete the read
(after the AHB bus is free), the read is treated as a fresh read, and the
master is SPLIT once again to complete the read. At the time of receiving the
locked transaction, all posted writes in the bridge are completed on the
destination bus.
If ORDERING has been enabled in the bi-directional bridge and the fresh
incoming transfer to AHB slave interface of the bridge is a LOCK transfer,
then ordering is ignored by the bridge until the lock transfer completes on the
AHB bus. This avoids deadlock conditions that can occur with ordering
enabled, and also avoids fresh lock transfers initiated on the AHB bus.
4.6.4. Deadlock Conditions

The SPLIT response mechanism on the AHB bus gives adequate protection
against the dead lock scenario in the bi-directional bridge. However, deadlock
can occur when locked transfer types are used simultaneously by both the
AHB master and PLB master. Therefore you should avoid configurations in
which of both AHB master and PLB master can start LOCKed transaction at
exactly the same time to prevent an irrecoverable deadlock condition.

4.6.5. Error Handling

This section describes how the PLB4XAHB bridge handles an ERROR response.
4.6.5.1. Error Handling: PLB to AHB

If a write ERROR response occurs on the AHB side,
The bridge terminates the AHB burst transaction immediately.
If there are data remaining in WRFIFO, WRFIFO is flushed by the AHB
interface control logic.
SEAR and SESR registers are updated.
The bridge asserts the appropriate SL_MIRQ signal to the PLB master.
If a read ERROR response is received on the AHB bus,
The bridge terminates the AHB burst transaction immediately.
The bridge terminates the PLB burst transactions when the remaining data
in RDFIFO is empty.
The appropriate SL_MRdErr and SL_rdDAck are asserted for the last PLB
read transfer.
SEAR and SESR registers are updated.
4.6.5.2. Error Handling: AHB to PLB

During a write, when PLB timeout error or PLBMWrErr occurs on the PLB side:
Since writes are posted in the bridge, the bridge continues to finish the
intended bufferable write on the PLB bus.
The Error status registers and error address registers are updated.
If interrupts are enabled, the bridge generates a non-maskable interrupt
in response to the error received from a PLB slave device.
During a prefetchable read, or non-bufferable read and write:
The bridge asserts an ERROR response on the AHB bus for the particular
address for which PLB slave gave a PLBMWrErr or SL_MRdErr or timeout
error.
The bridge updates the error address and error status registers.
If there is a continuation of the same transfer by AHB master after ERROR
response, the bridge issues a RETRY for the subsequent transfer.
Thus the slave interface responds with RETRY when an ERROR is encountered
on the PLB bus on a prefetchable read or on a non-bufferable read/write, and
the transfer is continued by the AHB master.
This RETRY allows the master to initiate the transfer with newly formed
HBURST for the remaining transfer, or for a fresh new transfer. During this
RETRY response, the AHB slave interface does not record any transaction
information in its internal logic and treats the next incoming transfer as a
fresh transfer.

Note: The PLB bus is aligned to 128-bit address boundary. Therefore the
AHB master must specifically accommodate an error response when a
prefetchable read and hsize is 64-, 32-, 16-, or 8-bits, because a
subsequent attempt to try the remaining bits in the same 128 bit address
boundary always ends in the error response.
4.6.6. 64-bit PLB Slave Accesses

The PLB4XAHB bridge supports only SINGLE AHB transfers to 64-bit PLB
slaves. Burst transfers to 64-bit PLB slaves are not supported.
Note: Any AHB burst transfer targeting 64-bit PLB slave is considered a
system error and the bridge does not take any actions to correct or report
this error
4.6.7. Retry Limit

Since the AHB to PLB direction of the PLB4XAHB is capable of generating
RETRY response for some specific conditions like wdfifo being full for
bufferable write transfers, the system integrator has to program the retry
limit on the AHB master to a reasonable value.
4.6.7.1. INCR Bursts

Write Transfers—On the AHB to PLB direction of the PLB4XAHB bridge,
when the ahb_slave receives INCR write transfers, the bridge collects the
data up to the 128-bit address boundary and pushes in the wdfifo. When
the wdfifo becomes full, the ahb_slave interface inserts wait states.
¾ When the wdfifo becomes available within 14 clocks, the bridge
continues to load the wdfifo.
¾ When the wdfifo is not available even after 14 clock wait states, the
AHB slave interface of the bridge issues a RETRY response.
Read Transfers—Similar to write transfers. When the rdfifo becomes
empty for read transfers, then the AHB slave interface of the PLB4XAHB
bridge issues SPLIT on the AHB bus and internally loads the TQFIFO.
For example, the rdfifo becomes empty for read transfers because the PLB
master interface completed a prefetchable transfer on the PLB bus and
there is a continuation of the INCR read on the AHB bus. This marks a
fresh prefetchable read transfer with corresponding address.
4.6.8. Delayed Reads and Sideband aborts

PLB4XAHB does a delayed read in the PLB2AHB direction of the bridge,
storing all the transaction qualifiers for the delayed read including the master
ID. While the brige is perfoming the delayed reads on the AHB bus, no new
reads from any other masters are accepted, until the original master is able
to complete the delayed read. However it is possible for the original master to
never complete the delayed read by issuing Mn_Abort.
In cases where the arbiter is granted to another master in the system, while
the Mn_Abort is issued by the master that requested read through PLB4XAHB
bridge, the abort does not get reflected as PLB_Abort on the PLB bus. This

can result in a condition whereby PLB4XAHB can never accept any additional
reads because the original master never completed the delayed reads. To
handle this situation, PLB4XAHB bridge also samples the Mn_Abort from all
other masters (M_ABORT_IN[0:15]) in the system and compares it with the
stored Master_ID of the pending read request. If a PLB master aborts a read
cycle while the bridge has a pending read for that master, the bridge flushes
this read request and resets its internal buffers to accept the other read
requests.
M_ABORT_IN[0:15] corresponds to each masters with masterID 0 to 15
respectively. If the system does not have all the masters the corresponding
M_ABORT_IN signals should be tied off at the Bridge input.
4.6.9. Bidirectional Bridge ordering
As per the Producer-Consumer Ordering outlined in PLB5 specification,

bidirectional bridges that support posted writes should adhere to the following
rule in order to operate correctly. ”A read response cannot pass an ordered
write request when both are traveling in the same direction through the
bridge”. Below is the description of this scenario for the both direction of the
bridge
4.6.9.1. PLB2AHB ordering:
When a PLB read request is initiated by a PLB master when the WDFIFO in the
AHB2PLB direction of the bridge is not empty, the bridge makes sure that all
the posted data in the WDFIFO is flushed to the targeted slave, before the
current read request from the PLB master is initiated on the AHB bus. Below
is the detailed description how this is implemented
1. PLB4XAHB does a delayed read in the PLB2AHB direction of the bridge. All
newly requested reads are rearbitrated by the PLB slave interface of the
bridge and the address and transfer qualifiers are latched along with the
master ID.
2. The read is performed on AHB as a delayed read. When the AHB master
of the bridge gets the grant for the AHB bus for this read transaction, the
level of the WDFIFO in AHB2PLB direction is loaded in a 2-bit counter on
the PLB clock domain (Using Grant on AHB is to make sure that all the
write data posted in the WDFIFO before this read is flushed onto PLB
bus). This counter will be decremented on each POP of the WDFIFO
3. If the bridge has this pending read being fetched from AHB, and if it
receives another read request from PLB master, the address and transfer
qualifiers for the newly initiated read is compared with the already
latched read transaction information in the bridge.
4. If the comparison results in a match, and if the data is already fetched
from AHB and all the posted writes in AHB2PLB direction have been
completed on PLB (as indicated by the zero value of counter in step 2),

the read will be AddrAcked and data transfer is completed. If not, the
slave will be rearbitrated again.
5. If the comparison results in a match, and if the PLB_abort is sampled, the
pending transaction is flushed.
6. Mn_aborts from 12 other masters are also sampled continuously. If at
any time, any of the Mn_aborts are active, it is compared with the master
ID stored in the bridge. If this master ID comparison results in a match,
the pending request in the queue is flushed.
7. If the transfer qualifier comparison for the new read results in a
mismatch, the new read transfer will be rearbitrated, without storing the
new transaction details. So essentially there can be only one read
transaction in the transaction queue at any time
4.6.9.2. AHB2PLB ordering
When an AHB read request is initiated by an AHB master when the WRFIFO in
the PLB2AHB direction of the bridge is not empty, the bridge makes sure that
all the posted data in the WRFIFO is flushed to the targeted AHB slave, before
the current read request from the AHB master is initiated on the PLB bus.
Below is the detailed description how this is achieved
1. PLB4XAHB gives a SPLIT to any new read transactions and does a
delayed read on the PLB bus, in the AHB2PLB direction of the bridge. The
AHB slave interface logic stores the address and master ID of this read
transaction in the TQFIFO
2. When the PLB master interface initiates the request for this read transfer
and gets the PAValid, the level of the WRFIFO in the PLB2AHB direction of
the bridge is loaded in a 2-bit counter on the AHB clock domain. This
counter will be decremented on each POP of the WRFIFO
3. The AHB slave interface logic will not assert the HSPLITx signal (to
indicate that the requested read data is ready) until the 2-bit counter in
step 2 decrements to a value of 0, that indicates all the posted writes in
WRFIFO has been emptied on to the AHB slave
4.7. Power Management

Automatic clock gating is done using the synthesis tools for power saving. No
module level- or software-controlled power management is supported.

4.8. Clocks
There are three different clock inputs to the bridge:
HCLK on the AHB interface
SYS_PLBCLK on the PLB interface
DCR_CLK on the DCR interface
Bridge supports any frequency ratios between HCLK and SYS_PLBCLK.

SYS_PLBCLK and HCLK can be totally asynchronous to each other. Note that
the configuration parameters USE_SINGLE_CLOCK_FIFO and
FIFO_SYNC_STAGES should be setup appropriately in order to use the correct
configuration of FIFOs based on the nature of SYS_PLBCLK and HCLK
relationship
As per the DCR specification DCR_CLK and SYS_PLBCLK should be edge
synchronous
4.9. Reset
The PLB4XAHB has two reset signals:
HRESETN on the AHB side
SYS_PLB_RESET on the PLB side
On the assertion of either of these signals, the bridge resets all sequential
logic and brings all the outputs to their default inactive condition.
HRESETN should be coincidental with the SYS_PLB_RESET signal, and should
be asserted for a minimum of three AHB clock cycles.
Note: There are no reset synchronizers within the core. The bridge assumes
a asynchronous assertion and synchronous de-assertion of the reset from
the system reset controller, so that all registers are in a known state when
the bridge comes out of reset.

PLB4 Peripherals: PLB4XAHB Bi-directional Bridge 5. Register Descriptions
5. Register Descriptions
5.1. PLB4XAHB Register Overview

PLB4XAHB Control and Status Registers (CSRs) are mapped in the DCR
address space as well as the AHB address space.
AHB Address Space—CSRs are mapped to the first 15 word-aligned
addresses, starting from the base address configured using the parameter
PLB4XAHB_CSR_BASE_ADDRESS.
DCR Address Apace—CSRs are mapped to the first 15 word-aligned
addresses, starting from the base address configured using the parameter
PLB4XAHB_DCRS_BASE_ADDRESS.
The following sections describe the memory map of the PLB4XAHB CSRs in
both the DCR and AHB memory space.

5. Register Descriptions PLB4 Peripherals: PLB4XAHB Bi-directional Bridge
5.2. Register Memory Map

If the bridge is configured to be a unidirectional bridge, the registers that
correspond to the other side of the bridge do not exist. For example, if the
BRIDGE_DIRECTION configuration is set to 1 (AHB2PLB unidirectional bridge)
PLB2AHB direction Command and Status Registers (CSRs) are unavailable. So
the AHB2PLB direction CSRs start from the address offset of 0 from the base
addresses and occupy the first 8-word aligned address.
If the BRIDGE_DIRECTION configuration is set to 0 (PLB2AHB unidirectional
bridge), AHB2PLB direction CSRs are unavailable. Also PLB2AHB direction
CSRs will only be mapped in the DCR address space.
Table 21: Command and Status Register Memory Map

DCR address offset AHB address offset
Uni- Bi- Uni - Bi -
Directional Directional Directional Directional
Register Name Bridge Bridge Bridge Bridge Reset value
Revision ID register 0 0 0x00/NA* 0x00 DCR_REVI
SON_ID
PLB2AHB System Error 1 1 NA 0x04 0x000000
Upper Address Register 00
PLB2AHB System Error 2 2 NA 0x08 0x000000
Lower Address Register 00
PLB2AHB System Error 3 3 NA 0x0C 0x000000
Status Register 00
PLB2AHB TopAddr Register 4 4 NA 0x10 0x000000
00
PLB2AHB BotAddr Register 5 5 NA 0x14 0x000000
00
PLB2AHB Attributes Register 6 6 NA 0x18 0x000000
00
AHB2PLB Control Register 1 7 0x04 0x1C 0x000000
04
AHB2PLB Error Status 2 8 0x08 0x20 0x000000
Register 00
AHB2PLB Error Address 3 9 0x0C 0x24 0x000000
Register 00
AHB2PLB Interrupt Mask 4 A 0x10 0x28 0x000000
Register 00

5.3. Register Descriptions

This section contains bit level descriptions for the PLB4XAHB registers:
Note: Bit numbering in this chapter uses the AHB system, in which 0=LSB
and 31=MSB. Thus bit numbering of [31:0] in the AHB corresponds to
[0:31] in the DCR bus. Take this into consideration when you program
Command and Status Registers from the DCR address space.
5.3.1. PLB to AHB Registers

5.3.1.1. PLB2AHB System Error Upper Address Register
(SEAR_AddrUpper)
This register contains the upper 4-bits of the address that encounters a
transaction error on the AHB bus. Writes to this register will clear the
contents of this register.
Table 22: PLB2AHB System Error Upper Address Bit Descriptions

Bits Name Direction Reset Description
3:0 AddrUpper RW 0x0 Least significant 4-bits of the
offending PLB_UABus upon the first
error; no more capture until SEAR is
reset
31:4 - R 0x0 Reserved. Reads return a zero value.
5.3.1.2. PLB2AHB System Error Lower Address Register

(SEAR_AddrLower)
This register contains the lower 32-bits of the address that encounters a
transaction error on the AHB bus. Writes to this register will clear the
contents of this register.
Table 23: PLB2AHB System Error Lower Address Bit Descriptions

31:0 AddrLower RW 0x00000000 32-bit of the offending address upon
the first error; no more capture until
SEAR is reset

5.3.1.3. PLB2AHB System Error Status Register (SESR)

The AHB interface logic records the status of the transactions from PLB to
AHB in this register. These status bits are cleared by a write transaction to
this register.
Table 24: PLB2AHB System Error Status Bit Descriptions

3:0 Master RW 0x0 Indicates which master reported the
number first error; These bits get locked until
RdErr and WrErr are both cleared
29:14 MIRQ RW 0x000 Indicates which master received an
MIRQ. This register is sticky and
accumulates all of the MIRQs since it
was last reset. This field is never locked
30 WrErr RW 0 Indicates that the first reported error
was due to a write. Locked upon first
error (either read or write)
31 RdErr RW 0 Indicates that the first reported error
was due to a read. Locked upon first
error (either read or write)
5.3.1.4. PLB2AHB TopAddr and BotAddr Registers

The AHB address range is defined by two registers: TopAddr and BotAddr.
Together, they define a minimum of 256 MB memory space for AHB. The
maximum address space is up to 64 GB.
Table 25: PLB2AHB TopAddr Bit Descriptions

7:0 Top Address RW 0x00 8-bits of PLB address bits. Bits 7-4
forms the PLB_UABus[28:31] and bits
3:0 forms the PLB_Abus [0:3] , thus
forming a minimum address map of
256MB
31 Valid Bit RW 0 When set, indicates that the 8-bit
TopAddr value field in this register is
valid
Table 26: PLB2AHB BotAddr Register

7:0 Bottom RW 0x00 8-bits of PLB address bits. Bits 7-4
Address forms the PLB_UABus[28:31] and bits
3:0 forms the PLB_Abus [0:3] , thus
forming a minimum address map of
256MB
31 Valid Bit RW 0 When set, indicates that 8-bit Bottom
Address field in this register is valid

For example:
When TopAddr is 0x00 and BotAddr is 0x00, then the bridge address
space is 256 MB because the 36-bit PLB address is from 0x0_0000_0000
to 0x0_0FFF_FFFF. If TopAddr is 0x00 and the BotAddr is 0xFF, then the
36-bit bridge address is 0x0_0000_0000 to 0xF_FFFF_FFFF, which gives
an address space of 64 GB.
When BotAddr is 0x10 and TopAddr is 0x20, the 36-bit PLB address for
the bridge is from 0x1_0000_0000 to 0x2_0FFF_FFFF. Thus, the bridge’s
address space is in increments of 256MB.
TopAddr[31] and BotAddr[31] are address valid bits that indicate if the
address ranges in these TopAddr and BotAddr registers are valid.
These bits must be set for the bridge to use the addresses in TopAddr and
BotAddr registers to perform address comparison to respond to PLB
transactions.
When these bits are not set, the bridge uses the bootstrap_addr_hi[0:7]
and bootstrap_addr_lo[0:7] inputs for PLB address decoding.
When BOTH of these bits are set, the bridge ignores the bootstrap address
inputs, and the values programmed in the TopAddr and BotAddr registers
are used.
TopAddr[31] and BotAddr[31] bits are automatically reset to 0x0 when a
system-reset event occurs.
5.3.1.5. PLB2AHB Attributes Register

This register specifies AHB transaction attributes
Table 27: PLB2AHB Attributes Bit Descriptions

0 FNBUF RW 0 Force Non-buffered (FNBUF) transfer on
AHB. When this bit is set, HPROT[2] is
forced to 0x0, and PLB_TAttribute[8] is
ignored.
When this bit is not set,
PLB_TAttribute[8] is propagated to
HPROT[2]
0

5.3.1.6. PLB4XAHB Revision ID Register

This register contains the version identification of the bridge.
Table 28: PLB4XAHB Revision ID Bit Descriptions

31:0 Revision ID R DCR_REVISI 32-bit Revision ID. For example, use
ON_ID bits [0:15] is for major revision ID, bits
[16:23] reserved, and bits [24:31] for a
minor revision ID.
This is a read-only register. Writes have
no effect.
The format is user defined. Reads
return the value of the
DCR_REVISION_ID parameter that you
set during bridge configuration.
5.3.2. AHB to PLB Registers

5.3.2.1. AHB2PLB Bridge Control Register
Table 29: AHB2PLB Bridge Control Bit Descriptions
0 PLB Lock RW 1’b0 Represents the value to be driven on
Error M_lockErr on the PLB interface.
Indicates whether or not the slave
should lock its Slave Error Address
Register (SEAR) and Slave Error Status
Register (SESR) register, when an error
is detected during the transfer
2:1 PLB Request RW 0x2 These bits drive the request priority
Priority signals M_PRIORITY[0:1] on the PLB
interface. PLB4XAHB bridge indicates
the priority of its requests to the PLB
Arbiter.
• 2'b11 – Highest
• 2'b10 – Next highest
• 2'b01 – Next highest
• 2'b00 – Lowest
6:3 PLB Upper RW 0x0 These bits corresponds to the upper
Order order address bits M_UABUS[28:31] on
Address the PLB interface. This allows the
expansion of address space beyond 4
GB
7 PLB Address R/W 0x0 When set, address pipelining on PLB
Pipelining interface is disabled
Disable

5.3.2.2. AHB2PLB Error Status Register

The AHB2PLB status registers have the records of different types of error
occurring on the PLB & DCR master interface. These registers are written by
the PLB and DCR interface logic block.
They are combined to form a single interrupt to the host through the
PLB4XAHB_INTR pin when enabled in the PLB4XAHB interrupt mask register.
These bits are cleared when the host writes a value of 1'b1 to the individual
bits.
Table 30: AHB2PLB Error Status Bit Descriptions

0 PLB Master RW 1’b0 This bit is set when the PLB interface
Timeout logic encounter a timeout for its
Error transfer request on the PLB bus
indicated by PLB_MTimeout
1 PLB Write RW 1’b0 This bit is set by the PLB interface logic,
Transfer when the bridge encounters an error
Error (PLB_MWrErr) for a PLB write
transaction
2 PLB Read RW 1’b0 This bit is set by the PLB interface logic,
Transfer when the bridge encounters an error for
Error a PLB read PLB_MRdErr) transaction
3 PLB MIRQ RW 1’b0 This bit is a registered version of the
PLB_MIRQ signal.
5.3.2.3. AHB2PLB Error Address Register

This register has the 32-bit PLB address of one of the five different type of
errors that the bridge encounters on the PLB Master interface.
This is set when The AHB2PLB Error Status register bits are set. Once set, this
register remains locked until the error status is cleared by the host.
Table 31: AHB2PLB Error Address Bit Descriptions

31:0 PLB Address RW 1’b0 32-bit PLB address

5.3.2.4. AHB2PLB Interrupt Mask Register

The Interrupt Mask register is written by the host to mask or unmask the
individual errors going as an interrupt.
Table 32: AHB2PLB Interrupt Mask Bit Descriptions

0 PLB Master RW 1’b0 When set, disables the PLB Master
Timeout Timeout Error from generating an
error Mask interrupt
1 PLB Write RW 1’b0 When set, disables the Write Errors on
Error Mask the PLB interface from generating an
interrupt
2 PLB Read RW 1’b0 When set, disables the Read Errors on
Error Mask the PLB interface from generating an
interrupt
3 PLB MIRQ RW 1’b0 When set masks the MIRQ input from
Mask generating the system interrupt

PLB4 Peripherals: PLB4XAHB Bi-directional Bridge 6. Configuration
6. Configuration
6.1. PLB4XAHB.defines.v
PLB4XAHB is a highly configurable core. The system integrator needs to
configure the core as per the requirement using Synopsys coreConsultant
during “SpecifyConfiguration” activity. Please refer to the PLB4 Peripherals
Implementation View User guide for details on how to configure the core
using coreConsultant.
Once configured, coreConsultant creates a parameter file called
“PLB4XAHB.defines.v” in the user’s workspace. This file includes verilog
`define statements for the parameters of the selected configuration.
6.2. Configuration Parameters Table

The following table displays parameters with their default values and
descriptions. Default values correspond to maximum configuration of the
bridge:
Bi-directional bridge
Little endian bit order
AHB data bus width of 128 bits
AHB and PLB clocks are same
Note that the parameter names in the below table are the define names in the
coreConsultant created PLB4XAHB.defines.v file. The symbolic names in the
coreConsultant GUI are different with the relevant details to help the user
configure the core correctly.

6. Configuration PLB4 Peripherals: PLB4XAHB Bi-directional Bridge
Table 33: PLB4XAHB Configuration Parameters
Parameter Name Default Values Description

PLB4XAHB_A2P_CFG Defined This parameter selects the AHB to
PLB direction of the bridge.
Needs to be defined for AHB to PLB
unidirectional bridge or bidirectional
bridge.
PLB4XAHB_P2A_CFG Defined This parameter selects the PLB to
AHB direction of the bridge.
Needs to be defined for PLB to AHB
bridge.
PLB4XAHB_AHB_ENDIANESS 1’b1 AHB bus Endianess. This parameter
indicates the AHB bus endianess. If
set to big endian, the data bytes are
taken from the appropriate lanes on
the AHB bus based on HADDR and
HSIZE
• 0x0: big endian
• 0x1: little endian
PLB4XAHB_AHB_DATA_WIDTH_128 Defined AHB Data bus is 128-bit wide
PLB4XAHB_AHB_DATA_WIDTH_64 Undefined AHB Data bus is 64-bit wide
PLB4XAHB_AHB_DATA_WIDTH_32 Undefined AHB Data bus is 32-bit wide
USE_SINGLE_CLOCK_FIFO 1’b1 FIFO clock type select

• 0 = Use Dual Clock FIFO—Do not
define Use Single Clock FIFO if
AHB and PLB clocks are not the
same frequency. The number of
synchronization stages are
selected by FIFO_SYNC_STAGES
define settings.
• 1 = Use single Clock FIFO—Define
this if AHB and PLB are on the
same clock frequency.
FIFO_SYNC_STAGES 2 Number of synchronization stage in
FIFO. This is meaningful only when
USE_SINGLE_CLOCK_FIFO is
undefined
• 1 = Single synchronization stage.
Select this value if AHB and PLB
clocks are edge synchronous
• 2 = Two synchronization stages.
Select this if AHB and PLB clock
are not edge/phase synchronous.
Note that even if the
USE_SINGLE_CLOCK_FIFO is defined,
FIFO_SYNC_STAGES should be
defined. But the value is ignored
during compilation for synthesis or
simulation

PLB4 Peripherals: PLB4XAHB Bi-directional Bridge 6. Configuration
Parameter Name Default Values Description

PLB4XAHB_DCRS_SEL Defined DCR slave interface selection
• 0 = CSR are mapped only in AHB
address space. This option is valid
only if bridge is configured as AHB
to PLB unidirectional bridge or
bidirectional bridge
• 1 = CSRs mapped in DCR address
space. Default value if The bridge
is configured as unidirectional PLB
to AHB bridge
PLB4XAHB_DCRM_SEL Defined DCR master interface selection
This option is valid only if bridge is
configured as AHB to PLB
bridge
PLB4XAHB_DCRS_BASE_ADDRESS 0x000 10-bit base address for DCR slave.
Used only if DCR slave is selected
PLB4XAHB_DCRM_BASE_ADDRESS 0x00000000 DCR master base address in AHB
address space (DCR master is
mapped to 1 KWord or 4 KB of the
AHB memory map).
Only upper order 20-bit is used
Used only if DCR master interface is
selected
PLB4XAHB_CSR_BASE_ADDRESS 0x00000000 CSR base address in the AHB address
space, reserved for the bridge CSR.
The lower order 6-bits is ignored
This option is valid only when the
bridge is configured bi-directional or
AHB to PLB uni-directional.
PLB4XAHB_DCR_REVID 0x00000101 32-bit DCR Revision ID allotted to
PLB4XAHB. Valid only if DCR slave
interface is selected
PLB4XAHB_ORDERING Undefined Ordering feature enable.

Valid only in bidirectional
configuration

6. Configuration PLB4 Peripherals: PLB4XAHB Bi-directional Bridge

PLB4 Peripherals: PLB4XAHB Bi-directional Bridge 7. Synthesizing the PLB4XAHB Core
7. Synthesizing the PLB4XAHB Core
7.1. Synthesis Constraints

7.1.1. Considerations for Constraints
For synthesis, PLB signals use the PLB Three Cycle Timing Guidelines
given in Section 4.3 of the PLB Specification, except PLB_abort. PLB_abort
uses the Two Cycle Timing Guidelines.
The signals PLB_rdPrim and PLB_wrPrim are not used by the bridge.
All input constraints are input delays as percentage of the clock.
All output constraints are output delays as percentage of the clock.
The target PLB and AHB maximum clock frequency is 200 MHz at worst
case conditions (slow, 0.9 V, 125 C) for Artisan 13LVFSG technology.

7. Synthesizing the PLB4XAHB Core PLB4 Peripherals: PLB4XAHB Bi-directional Bridge
7.1.2. Constraint Tables

Constraint tables are grouped by interfaces: PLB master/slave; DCR
master/slave; and AHB master/slave. Each interface has constraints for
clocks, inputs, and outputs.
Note: All DCR signals use the DCR Timing Guidelines given in Section 4.1 of
the DCR Specification.
7.1.2.1. Synthesis Constraints of PLB MASTER Signals

Table 34: PLB MASTER Clocks
Signal Name Constraint
SYS_PLBCLK Period = 6 ns
Uncertainty = 0.3 ns
Table 35: PLB MASTER Inputs

PLB_MADDRACK 50%
PLB_MTIMEOUT 15%
PLB_MSSIZE 50%
PLB_MRDERR 30%
PLB_MIRQ 30%
PLB_MWRDACK 30%
PLB_MRDDACK 50%
PLB_MRDBTERM 50%
PLB_MWRBTERM 50%
PLB_MRDDBUS 50%
Table 36: PLB MASTER Outputs

M_REQUEST 85%
M_PRIORITY 85%
M_RNW 85%
M_BE 85%
M_SIZE 85%
M_TYPE 85%
M_LOCKERR 85%
M_ABUS 85%
M_UABUS 85%
M_WRBURST 85%
M_RDBURST 85%
M_WRDBUS 85%

7.1.2.2. Synthesis Constraints of PLB SLAVE Signals

Table 37: PLB SLAVE Clock
SYS_PLBCLK Period = 6ns
Table 38: PLB SLAVE Inputs

PLB_BUSLOCK 5%
PLB_MASTERID 5%
PLB_RNW 5%
PLB_BE 5%
PLB_SIZe 5%
PLB_TATTRIBUTE 5%
PLB_TYPE 5%
PLB_MSIZE 5%
PLB_LOCKERR 5%
PLB_ABUs 5%
PLB_UABUS 5%
PLB_PAVALID 15%
PLB_SAVALID 15%
PLB_RDBURST 50%
PLB_WRDBUD 50%
PLB_WRBURST 50%
PLB_ABORT 75%
Table 39: PLB SLAVE Outputs

SL_MBUSY 85%
SL_MRDERR 85%
SL_MIRQ 85%
SL_RDDADDR 85%
SL_RDACK 85%
SL_RDCOMP 85%
SL_RDDBUS 85%
SL_RDBTERM 85%
SL_WRBTERM 85%
SL_WRDACK 85%
SL_WRCOMP 85%
SL_ADDRACK 85%
SL_SSIZE 85%
SL_REARBITRATE 85%

7.1.2.3. Synthesis Constraints of DCR MASTER Signals
Note: DCR master signals use the DCR timing guidelines given in Section 4.1
of the DCR Specification.
Table 40: DCR MASTER Clocks

DDR_CLK Period = 6 ns
Table 41: DCR MASTER Inputs

DCRM_CPUACK 2ns
DCRM_CPUDBUSIN 2ns
Table 42: DCR MASTER Outputs

CPU_DCRM_ABUS 2ns
CPU_DCRM_DBUSOUT 2ns
CPU_DCRM_READ 2ns
CPU_DCRM_WRITE 2ns
7.1.2.4. Synthesis Constraints of DCR SLAVE Signals
Note: DCR slave signals use the DCR timing guidelines given in Section 4.1
of the DCR Specification.
Table 43: DCR SLAVE Clocks

DDR_CLK Period = 6 ns
Table 44: DCR SLAVE Inputs

CPU_DCRREAD 2ns
CPU_DCRWRITE 2ns
CPU_DCRABUS 2ns
CPU_DCRBUSOUT 2ns

Table 45: DCR SLAVE Outputs

DCR_CPUACK 2ns
DCR_CPUDBUSIN 2ns
7.1.2.5. Synthesis Constraints of AHB MASTER Signals

Table 46: AHB MASTER Clocks
HLCK Period = 6 ns
Table 47: AHB MASTER Inputs

M_HRDATA 50%
M_HREADY 50%
M_HGRANT 50%
M_HRESP 50%
Table 48: AHB MASTER Outputs

M_HADDR 50%
M_HWRITE 50%
M_HTRANS 50%
M_HSIZE 50%
M_HBURST 50%
M_HPROT 50%
M_HWDATA 50%
M_HBUSREQ 50%
M_HLOCK 50%

7.1.2.6. Synthesis Constraints of AHB SLAVE Signals

Table 49: AHB SLAVE Clocks
HLCK Period = 6 ns
Table 50: AHB SLAVE Inputs

S_HADDR 50%
S_HTRANS 45%
S_HWRITE 50%
S_HSIZE 50%
S_HBURST 50%
S_HPROT2 50%
S_HWDATA 50%
S_HLOCK 50%
S_HSEL 50%
S_HMASTER 50%
S_HREADY 50%
Table 51: AHB SLAVE Outputs

S_HRDATA 50%
S_HREADY_RESP 45%
S_HRESP 50%
S_HSPLIT 50%
PLB4XAHB_INTR 50%

PLB4 Peripherals: PLB4XAHB Bi-directional Bridge
8. Reference Documentation
128-bit Processor Local Bus, Architecture Specifications, Version 4.6, SA-

14-2538-04 (Source: IBM)
AMBA Specification, Rev 2.0, ARM IHI 0011A, May 13, 1999 (Source:
ARM)
32-bit Device Control Register Bus Architecture Specification, Version 2.9,
June 2000 (First Edition), SA-14-2525-00 (Source: IBM)
DesignWare AHB Verification IP Databook (Source: Synopsys)
Synopsys, Inc.
700 East Middlefield Road
Mountain View, California 94043
www.synopsys.com

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DesignWare® IBM

Document Version 1.1.3

March 15, 2007

Copyright Notice and Proprietary Information

Destination Control Statement

Registered Trademarks (®)

Service Marks (SM)

2 Synopsys, Inc. March 15, 2007

Date Doc Version Description

March 15, 2007 Synopsys, Inc. 3

4 Synopsys, Inc. March 15, 2007

March 15, 2007 Synopsys, Inc. 5

4.3.3. PLB Master Interface ............................................................................ 45

6 Synopsys, Inc. March 15, 2007

Figure 1: The PLB4XAHB bridge in a SOC Environment ........................................... 10

March 15, 2007 Synopsys, Inc. 7

Figure 1: The PLB4XAHB bridge in a SOC Environment ........................................... 10

8 Synopsys, Inc. March 15, 2007

1.1. About this Document

1.2. Overview of the Core

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PLB Master 1 Power PC PLB Arbiter PLB Save

Figure 1: The PLB4XAHB bridge in a SOC Environment

10 Synopsys, Inc. March 15, 2007

2. Features and Functions

2.1. AMBA Advanced High Performance Bus

2.1.1. AHB Slave Interface

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 able transactions from AHB to PLB based on HPROT[2]

2.1.2. AHB Master Interface

12 Synopsys, Inc. March 15, 2007

The following feature is not supported by the interface:

2.2. Processor Local Bus Interface

2.2.1. PLB Master Interface

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2.2.2. PLB Slave Interface

14 Synopsys, Inc. March 15, 2007

2.3. Device Control Register Interface

2.3.1. DCR Master Interface

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2.3.2. DCR Slave Interface

16 Synopsys, Inc. March 15, 2007

3. Hardware Interface Signals

3.1. I/O Description Tables

Table 1: AHB Master Interface Signals

Port Name Direction Source Functional Description

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AHB Master Interface Signals

Port Name Direction Source Functional Description

Table 2: AHB Slave Interface Signals

Port Name Direction Source Functional Description

18 Synopsys, Inc. March 15, 2007

AHB Slave Interface Signals

Port Name Direction Source Functional Description

Table 3: AHB Interface Global Control Signals

Port Name Direction Source Functional Description

Table 4: PLB Slave Interface Signals

Port Name Direction Source Functional Description

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PLB Slave Interface Signals

Port Name Direction Source Functional Description

20 Synopsys, Inc. March 15, 2007

PLB Slave Interface Signals

able transactions from AHB to PLB based on HPROT[2]