A Survey of RF DACs
M. Reza Sadeghifar and J Jacob Wikner
Division of Electronics Systems, Department of Electrical Engineering, Linköping University, Sweden.
mreza@isy.liu.se, Jacob.Wikner@LiU.se
Abstract—A brief overview of different approaches to implement high-
frequency, digital-to-analog converters (DACs), sometimes also referred
to as radio-frequency DACs (RF DACs) or mixer DACs is given.
Recently, there has been a fairly increased activity within this research
field. RF CMOS processes have matured and enables a higher degree
of integration with high-speed digital circuits at a more reasonable cost.
Also, lately, some new advances have been reported which addresses the
architectural-level design issues. These new advances include, for exam-
ple, the implementation of high-speed, digital sigma-delta modulators
to be used with RF DACs to further enable an increase of the output
frequency of the DACs.
This work presents a small survey on how RF DACs operate and in
some sense how they can be implemented. We outline some different
architectures and discuss the pros and cons of those.
Index Terms—Digital-to-analog converters, high-frequency data con-
verters, mixer DACs, RF DACs, Sigma-Delta.
I. I NTRODUCTION
High-speed (and high-resolution) data converters are vital com-
ponents in all telecommunication systems. Normally, the higher
speed we can use for sampling, the lower requirements are put on
analog components, such as analog filters. Of course, a larger digital
complexity is then required, but that is mostly scaled with process
dimensions and becomes less of a concern for us.
In this work, we present a discussion on some different design
methodologies for high-speed, digital-to-analog converters (DACs)
suitable for wideband applications with demanding requirements on
linearity. The first, and perhaps obvious, approach to convert from a
digital to an analog representation at high speed is to increase the
clock frequency of the DAC. This approach is however tied with an
important question: do we need to also increase the signal bandwidth?
For example, there is a substantial difference in design strategy if we
want to obtain a 10-MHz signal bandwidth centered at some 500 MHz
or if we want to obtain a 500-MHz signal bandwidth at a sample
frequency of some 1 GHz, thus converting the entire Nyquist band.
This is of course a system-dependent issue, which could be related
to for example software-defined radio or flexible front-ends.
With a radio-frequency DAC, an RF DAC, we understand a DAC
that operates at a high speed; higher than or equal to the radio bands,
and that it converts a fairly narrow banded signal. The requirements
on linearity are high to meet several standards from e.g. telecommuni-
cations applications, such as GSM, to the next-generation radar. The
next-generation radar puts very high requirements on the linearity,
much higher than for example GSM.
To reach highest possible performance, one might have to apply
some kind of optimization of the signal chain. For direct digital
synthesis (DDS), for example, our group has previously shown that
a more efficient solution is obtained by using nonlinear DACs which
are co-optimized together with the signal generation from a hardware
point of view [1]. This approach enables high-speed digital and high-
speed analog implementations. In this work, we focus however on
slightly more generalized cases.
There are plenty of academic publications demonstrating high-
speed DACs, often in the sub-GHz region though, and still somewhat
“modest” linearity. Publications demonstrating results in the high
Fig. 1. Block representation of an ideal K-bit DAC
GHz region use more exotic processes, such as e.g. SiGe [2] or
SOI principles [3]. Typically, you find from all reported results (and
conveniently from theory too) that there is a relationship between
resolution (i.e. linearity) and frequency: with higher frequency or
bandwidth, the linearity decreases [4].
First, we discuss properties of the ideal DAC and then some typical
errors in high-speed DACs. We then elaborate on some traditional
ways to increase speed. We present a short survey of some existing
designs claiming to be RF DACs together with conclusions.
II. DAC S IN G ENERAL
Assume that we have an K-bit digital word, X(n), as input to a
DAC where n is the sequence index, as shown in Fig. 1. The digital
word input can also be written as
K−1
X
X(n) = xk (n) · 2k , (1)
k=0
where x0 is the least significant bit (LSB) and xK−1 is the most
significant bit (MSB). The output analog signal is denoted with Y (t).
In fact, the ideal DAC is nothing else but a pulse-amplitude modulator
(PAM), i.e., the output, Y (t), can be written as:
X
Y (t) = X(n) · p(t − nT ) (2)
∀n
where p(t) is the pulse waveform and T is the sampling interval. It is
in theory possible to perfectly reconstruct Y (t) from X(n) (for now
ignoring the effect of truncation error due to limited word length)
by properly selecting p(t) as a so called sinc function [5]. However,
in practice this is not possible as the sinc function is double sided
and thus cannot be realized by causal systems. Normally we select
a rectangular pulse, p(t) = u(t) − u(t − τ ), with a duration of τ .
This forms a zero-order hold function, and typically, the duration, τ ,
equals the sampling period, but could be a fraction of that time if
so-called return-to-zero schemes are applied.
In Fig. 2 we have plotted the amplitude characteristics for some
different return-to-zero schemes. (We have normalized such that the
frequency is T = 1/f = 1). The O factor describes the width of the
active-high part of the PAM pulse compared to the sample period,
i.e., we have (
1 0 ≤ t ≤ T /O,
p(t) =
0 otherwise
From the equation above and the figure, we can see that the gain also
decreases with the O factor, and normally if we apply a return-to-zero
scheme, we also need to amplify the output of the DAC accordingly
to restore the amplitude level. The advantage however – in our case
– is that we get a widening of the spectrum and we will pass through
 Simulated return−to−zero transfer functions
1 O=1
Normalized amplitude gain [−]
0.8
0.6
0.4
0.2
0 1 2 3 4 5
Frequency normalized w.r.t. sample frequency [−]
Fig. 2. Frequency characteristics for different return-to-zero schemes
high-frequency components (i.e. images of baseband spectrum), such
that we can use other Nyquist ranges than that at frequencies below
half the sample frequency.
A. Frequency-domain aspects
In terms of how the DACs behave in the frequency domain, we
refer to Nyquist-rate, interpolating, and oversampling converters.
The Nyquist-rate converter is designed to use the entire available
signal band from ωT = 0 to ωT = π, (i.e., up to the Nyquist
frequency). Quite often this is an over-design in many applications,
since the signal actually can be quite narrow banded.
There are two flavors of interpolating DACs: analog [6] and digital
interpolation. Both share the property of not being able to reproduce
the entire Nyquist band.
Even higher linearity can be reached by further employing the
interpolation technique and also introducing the sigma-delta mod-
ulator. For DACs, sigma-delta it is somewhat more attractive than
for ADCs, since the modulators in the DAC can be implemented in
digital domain.
B. A comment on high-speed DAC architectures
The most suitable architecture for high-speed DACs is the current-
steering architecture as it has the benefits of not (necessarily) requir-
ing an output buffer for high performance. It directs almost all of its
current to the output, which means high efficiency. The current can
also be terminated off-chip to minimize on-chip heat dissipation. The
weighting elements of the DAC are implemented as current source
and switches and we can typically write the (static) output current
as:
iout (X(n)) = iunit · X(n) (3)
for the code X(n) and iunit is the output current of a unit current
source. However, there are several significant limitations on achiev-
able speed and performance in current-steering DACs too.
III. N ON - IDEAL DAC S
As illustrated in Fig. 3: there is normally a relationship between
resolution and frequency in digital-to-analog converters [4], [7], [8]:
with higher frequencies, the linearity decreases. There is not that
much you can do about the overall tendency, but there are, of
course, different sources for limited performance, and they might
have different slopes and one could design the DAC to track the
best of these slopes over the frequency domain. What one generally
O=2
O=3
O=4
Fig. 3. Trade-off between frequency and resolution
does, to improve linearity, is to move the upper frequency break-
6 7 8 point by advances in technology (and clever design tricks). This upper
frequency break-point is partly given by the transition-frequency, fT ,
of the transistor. There are however other parameters that play a role
too, and one needs to find the optimum values for the application. By
knowing these limits we also know what barriers we cannot breach.
In the favorable current-steering DAC, the current sources will
have a limited output impedance. For a linear system, this would
not cause us any major issues, it would just result in a gain error
in the output. There would “only” be a loss of signal power due to
the unmatched impedance levels. However, as the output impedance
varies with signal level, it affects the linearity significantly. The output
voltage is dependent on the code as
ZL
Vout (X) = iout (X) · (4)
1 + ZL /ZS (X)
where ZL is the load impedance and ZS is the output impedance
of the DAC which is in the unbuffered current-steering DAC also
a function of input code, X. Each current source will have a unit
output impedance, Z0 , and if the corresponding weight is 2n , the
effective output impedance will be Zunit /2n . We can generalize this
and say that if the code X is applied to the DAC there will be
X current sources connected to the output and hence the effective
output impedance will be Zs = Zunit /X. This means that the output
voltage can be written as:
iunit · X · ZL ∆V · X
Vout = = (5)
1 + ZZ L
unit
· X 1 + X/ρ
where we have set ∆V = iunit ·ZL as our least significant bit (LSB)
voltage step at the output of the DAC and ρ = Zunit /ZL is the ratio
between output and input impedance of a unit source. The equation
above is nonlinear with respect to the input code X and distortion
will be introduced: the harmonic distortion (HD) will depend on the
impedance ratio and the amplitude. The peak amplitude, X0 , is given
by the number of bits in the DAC as X0 ≈ 2N . The full-scale output
current is iunit · X0 , and quite often we have levels around iunit ·
X0 · ZL ≈ 1 V. The ρ value is quite likely large, but for a higher
number of bits, the X0 grows larger too. The problem is also that the
ρ decreases steadily with higher frequency. It can be shown [4] that
the third order distortion for a differential DAC can be approximated
as
HD3 = 40 · log10 ρ − 12 · (N − 2). (6)
So, for an output impedance of 100 MΩ, the harmonic distortion
becomes some 45 dB for a 14-bit DAC. For a 12-bit DAC it becomes
57 dB. If the output impedance is some 100 MΩ at 10 kHz and the
load is 50 Ω, we get HD3 ≈ 110 dB. Assuming a slope of 20 dB per
decade, we will at 1 MHz have 1 MΩ output impedance, resulting in
HD3 ≈ 70 dB, etc. Major challenges are therefore to increase output
impedance of the converter and/or to lower its load impedance.

Fig. 4. Illustrating the boundaries of the RF DAC
Fig. 5. Two examples of unit DAC element integrated with mixers, one with
passive mixer on output (left) and one with active mixer on input (right).
IV. E XAMPLES ON H IGH -S PEED DAC S
In this section we outline some different architectures from a
system-level point of view. The top of Fig. 4 outlines a traditional
IQ transmitter with the DC/low-IF baseband digital processing, the
digital-to-analog converter (DAC) that generates the analog waveform
which is then bandpass or low-pass filtered (BPF/LPF), then mixed,
summed, filtered again (BPF) and brought to the antenna by the power
amplifier (PA). This is of course a simplified picture, but illustrative
for our purpose here.
The idea with the RF DAC or mixer DAC is to combine the mixer
with the DAC in a clever way i.e. by reducing the number of analog
components. We illustrate this in Fig. 4 where parts of the baseband,
the DAC, filters, mixers and optionally the final bandpass filter can be
merged. One result of this operation is that the digital sampling speed,
as well as the requirements on linearity and frequency selectivity
increase quite dramatically.
A. DAC and mixer
The most intuitive approach is to combine the DAC directly with
a mixer. This will constitute a traditional way of modulating and
transmitting. The ambition should be to push the DAC closer to the
antenna by preferably increasing its sampling frequency as much as
possible. We also want to push the mixer closer to the DAC and
such that we can remove the resistive load at the output of the DAC.
The left-most part of Fig. 5 shows an example of a DAC element
merged with a passive mixer (passive in the sense that there is no
gain associated with it). For this purpose we integrate the mixer close
to the DAC and without the resistive load. The current-to-voltage-to-
current conversion – which introduces distortion – is avoided. The
load impedance is also reduced by sinking the DAC output currents
in the low-impedance drains of the mixer transistors.
In the right-most part of Fig. 5 we find an active implementation
of the mixer DAC. In this case we have actually illustrated this with a
single unit element of the DAC. Then, several of these units must be
connected in parallel to achieve the overall functionality of the DAC.
We know since previously that the static output current is given by
iout (t) = X(n) · iunit , (7)
and to be more accurate we need to include the PAM waveform in
the expression and we get
X X
iout (t) = iout (n)·p(t−nT ) = iunit ·X(n)·p(t−nT ), (8)
∀n ∀n
where, for example, X(n) = X0 ·sin(ω1 T n), could contain the signal
information and p(t) could be the brickwall function or a return-to-
zero. Now, assume that iunit instead is a time-dependent oscillating
signal as
iunit (t) = iunit,0 · q(t) (9)
where q(t) is an additional pulse-amplitude modulation signal at a
frequency which is a multiple of the sample period, T , i.e., q(t) =
q(t + kT ). (Selecting a multiple of the sample period, minimizes the
glitches.) We can now write the output current as
X
iout (t) = iunit,0 · X(n) · q(t) · p(t − nT ) (10)
∀n
or
X
iout (t) = iunit,0 · q(t) · X(n) · p(t − nT ). (11)
∀n
If q(t) now is given by the local oscillator (LO) signal, sin(ω0 T n),
we see that the mixed products at ω0 ± ω1 are produced such that
we can center the signal information at higher frequencies. One
problematic design issue is to distribute the mixing signal to multiple
unit source and maintaining matching and skew.
B. Interpolating DAC
In literature you sometimes find the interpolating DAC as a high-
speed converter. The digital interpolating DAC is however nothing
else but a normal, Nyquist-rate DAC combined with a digital interpo-
lator: we apply digital multi-rate interpolators at the input of the DAC
such that the update frequency is increased and signal can be located
at higher frequencies by applying digital filtering. The advantage is
that we can feed the DAC with a lower frequency input thus relaxing
the interface to the circuit. In the case of analog interpolation we try
instead to mimic the desired analog output waveforms by for example
microstepping methods as in e.g. [6] or by using return-to-zero
schemes which effectively introduce similar kind of zero-padding as
the digital interpolation does, but with maintained requirements on
the analog filters.
The return-to-zero scheme, i.e., using a PAM waveform which is
unity for 0 < t < T /2 rather than 0 < t < T , as effectively gives
you zero padding and a form of interpolation. The inverse clock
signal can be used to “easily” create the zero padding. Notice, that
the PAM waveform is still defined such that it has the same sample
frequency as the brickwall one. Advantages with the return-to-zero
scheme is that we reduce both analog settling memory effects, as well
as memory effects inside the digital logic, thus improving linearity
and noise.

Fig. 6. Example of three time-interleaved DACs
C. Time-Interleaved DACs
Another way to increase the overall frequency is to use time-
interleaved converters as outlined in Fig. 6. The overall functionality,
in this example, is given by the three DACs connected in parallel
and by summing their outputs. Notice that the DACs operate at
time-shifted clocks, but at the same update frequency. By carefully
generating the time shifts with high accuracy delay-locked loops
(DLL) or similar, we could for example let all the DACs operate
at 1 GHz, but with a 120-degree phase shift between each other,
thus outputting data at 3 GHz in total. An obvious challenge during
the design phase is to align the clocks well enough to eliminate any
skew between the DACs. So, to this overall DAC system, there will
be a data stream which is split into three streams. We feed samples
1, 4, 7, 10, ... to DAC1 and 2, 5, 8, 11, ... to DAC2 and 3, 6,
9, 12, ... to DAC3 , etc. This means that we are effectively sending
the signal decimated-by-three, but with an internal time shift to each
DAC. The time shift relates to the original input update period, T , and
the DACs operate at T /3. Assume that the input amplitude spectrum
(in the digital domain) is given by X(ejωT ), the decimated spectrum
will be
M −1
1 X
Xd (ejωT M ) = · X(ejωT −j2πm/M ). (12)
M m=0
This implies a potential overlap of spectrum if the input is not
bandwidth limited. This suits us however quite well, since mostly
we use a relatively narrow banded signal in RF DACs. The total
output amplitude spectrum now becomes
Y (jω) =
X
Xd (ejωT M ) · P (jω) · (1 + e−jωT + e−j2ωT ). (13)
∀m
So, we see two things: the input signal must be bandwidth limited as
BW < 1/3T and there is an amplitude attenuation due to the time
shifts. Using the z-domain notation instead, we see that the spectrum
will be weighted according to a form of FIR filtering:
z2 + z + 1
H(z) = 1 + z −1 + z −2 = . (14)
z2
A pair of complex zeros are introduced in the frequency domain.
Thereby the spectrum will be attenuated accordingly and certain fre-
quency bands become distorted. However, the bandwidth is limited,
and we are mostly able to also cater for the positions of these zeros,
and/or keep our signal out of those bands, we still quite likely have
a competitive solution to reach high speed conversion.
Actually, the FIR filtering distortion can be avoided by using
return-to-zero scheme. This means that each DAC is more or less
an interpolating DAC, if we use a return-to-zero scheme such that
the outputs of the DACs never overlap, i.e., the p(t) is chosen such
that p(t) = 1 for 0 < t ≤ T /3 and 0 otherwise.
Fig. 7. Simplistic view of a sigma-delta modulator
Optionally, one could have mixers at the outputs of the time-
interleaved DACs and then sum the outputs - this would avoid the
zeros in the combined transfer characteristics [9]. But, then we are in
some sense also back at an IQ concept shown in Fig. 4. The mixers
could be integrated with the DACs on the same chip using special
quadrature switching schemes as suggested in for example [10] and
[11], bridging some of the gaps in terms of reducing the number of
discrete components.
D. Sigma-Delta DACs
Quite likely the RF DACs will contain some kind of interpolation,
and then the step is not far to also apply sigma-delta modulators.
Some different results have been presented in this field [12], [13].
Even Though the measured and simulated results are somewhat
moderate, the results show some promising ideas within the field.
From these references, we can see that a large effort is put on the
digital domain rather than the analog which is what the future is
offering us.
The physical number of bits in the DAC can be reduced by using
a sigma-delta modulator. A lot of the design challenges are shifted
into the digital and system domains instead of the analog domain.
The modulators are attractive in many ways: they truncate the word
length of the digital input word to the DAC and the error introduced
by this operation is spectrally shaped to out-of-band frequencies. A
simplified picture of a sigma-delta modulator is found in Fig. 7 where
the word length is reduced from N bits down to M . By filtering
out this quantization noise (designed to be outside the signal band)
we land at the original resolution within the band. They are also
attractive since all operations are (unlike for ADCs) done in the
digital domain. However, it is also highly nonlinear and has high-
gain in the feedback loop making it hard to analyze and stabilize.
Sigma-delta DACs require a fairly high oversampling ratio between
the sample frequency and signal bandwidth such that the added
quantization noise can be moved far enough out-of-band and then
filtered out with low complexity filters. If we for a moment neglect
the complexity of the analog filter, the reduction in number of analog
components using a sigma delta modulator is enormous. For example,
if we have a 16-bit converter, we need 216 ∼ 65000 components in
a Nyquist-rate converter. By allowing ourselves a certain amount of
oversampling we can now trade frequency against analog complexity.
For example by allowing an oversampling of 16 times and apply a
modulator with a third-order transfer function, we can reduce the
number of components to approximately 26 ∼ 64, i.e. 1000 times
less components. With less analog complexity the design becomes
simpler, more regular and accurate, even though the analog accuracy
requirements are the same in terms of linearity and in-band noise.
Researchers at MIT have developed wideband digital sigma-delta
modulators for high-speed applications with global feedback paths
and still reached for example 200 MHz bandwidth at 5.25 GHz [14].
This would correspond quite well to e.g. multi-carrier WCDMA,
including additional bandwidth for pre-distortion.
 Sample Signal Signal
Reference Tech Supply NOB freq freq BW SFDR SNR IMD3 Comments, type of DAC
(nm) (V) (MHz) (GHz) (MHz) (dBc) (dB) (dBc)
Luschas [11] 180 1.8 3 514 0.9425 17.5 75 53 71 Σ∆
Taleie [16] 250 2.5 1 250 1.062 15 75 72 65 Σ∆, semidigital FIR filter
Eloranta [17] 130 1.2 8 150 1.9 – – – ACPR: 57 Nyquist-rate
Jerng [14] 130 1.2 3 1000 5.25 200 44 47 – SiGe BiCMOS, Σ∆
Pham [13] 90 1.0 4 2660 – 155 55 – – Time-interleaved Σ∆
Schafferer [18] 180 1.8 14 1400 – 50 67 – – Nyquist-rate
Bosch [8] 350 3.0 10 1000 – 490 61 – – Nyquist-rate
AD9739 180 1.8 14 2400 0.95 – 60 – 68 RF
MAX5881 – – 12 4300 1 – – – 68 RF
AD9122 180 1.8 14 1200 0.55 – 55 – 65 Nyquist-rate
TABLE I
R EPORTED PERFORMANCE OF DIFFERENT DAC ARCHITECTURES

Fig. 8. DAC signal chain used by Luschas, et al. [11]
With a lower number of analog components we can design for
high-speed and apply dynamic element matching (DEM) techniques.
These techniques use randomization to cancel out signal-dependent
components and transforming this energy into noise. We have pre-
viously shown methods that can be applied to spectrally shape the
error energy such that it falls out of band and does not degrade the
effective signal-to-noise ratio (SNR) [15].
V. C OMPARISON AND C ONCLUSIONS
Some interesting results on RF DACs were presented in [11] and
Fig. 8 outlines the basics of that architecture. In fact, it is rather
straight-forward approach: a sigma-delta modulator used to reduce
the number of analog components in the RF DAC. Dynamic element
matching (DEM) is used to scramble data and decorrelate static
errors from the signal to further reduce nonlinearity. The sigma-
delta modulator is an effective way to spectrally shape quantization
errors such that a DAC with less analog contents can be used.
The results they present are elegant in the way that they have
successfully implemented the mixing switching scheme to the DAC
together with sigma-delta converters. They have also demonstrated
that the oscillator signal connected to the internal elements of the
unit DAC elements does not have to be that accurate to achieve
promising results. They have chosen waveforms such that the spectral
attenuation of the DAC output is not that high at certain frequency
bands above the sample frequency. (See Fig. 2 for comparison).
Instead, the lobes at higher frequency are amplified compared to the
traditional sinc waveform, such that a local maximum is achieved
at approximately twice the sample frequency, equal to the oscillating
frequency. They report 75 dBc linearity in a 17.5-MHz band centered
at 942 MHz. The technique is promising, but it is not wide-band
enough. It must also be mentioned that for example digital pre-
distortion (DPD) required to linearize e.g. the power amplifier will
need a bandwidth a couple of times wider than the signal band for
proper cancellation of harmonics. To not destroy the properties of the
DPD we cannot narrow down our bandwidth through the DAC too
much. Table I summarizes the performance of different architectures
of high speed DAC, reported in the recent publications. Also included
in the table are some commercial products from Maxim and Analog
Devices.
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