R423 Stingray: Gddr3 8M X 32 (Bga) Gddr3 8M X 32 (Bga)

5 4 3 2 1
MEMORY CHANNEL A B MEMORY CHANNEL C D

D D
GDDR3 8M X 32 (BGA) GDDR3 8M X 32 (BGA)

SHT 13
SHT 12
From +12V DIRECT:

Channel A-B memory Address, Data nad Control signals
FAN Channel C-D memory Address, Data nad Control signals
Slim_VGA
MEM A B MEM C D CRT1 slim
DAC1 R G B HSY VSY DDC1DATA DDC1CLK FILTERS
STRAPS GPIO CONN
SHT 7 SHT 20
C SHT 20, 22 C
POWER
REGULATION BIOS
SHT 14,15,16,17 ROMCS# ROM
SHT 4
From +12V_Bus VIP
SWITCHING R423
+MVDDQ, +MVDDC, +VTT, Speed control SHEET 3, 4, 5, 6, 8, 9
+VDDC, +PCIE_VDDRC & temperature
FAN TVout
SHT 19
From +12V_Bus sense SHT 19 CONN
Linear TVOUT
+5V FILTERS
TVO
SHT 23
From +3.3V_Bus SHT 24
Linear
+VDD_1.8V, +VDDC_CT
DAC2
+VPCIE_VDDR, +A2VDD,
+PVDD, +TPVDD, +MPVDD
PCIE_PVDD_18, VDDCI CRT CRT2 FILTERS
POWER DELIVERY SHT 21 DVI-I
From +3.3V DIRECT: CONN
VDDR3
From +3.3V direct Or drivitive
VDDR4,5
TMDS TMDS_TX[C,2..0]N TMDS_TX[C,2..0]P HPD, DDC2CLK DDC2DATA
IMPEDANCE
From on board +5V MATCHING SHT 21
B B
+RTAVDD
From +12V DIRECT:

FAN
PCIE
+3.3V +12V
Receiver and Transmitter differential lanes (x16),
PERST# and JTAG signals
R423 Stingray
BLOCK DIAGRAM REFLECTING DELL UHMGA11
CONFIGURATION.
PCIE_Bus x16 12V_Bus COMPONENTS THAT ARE NOT POPULATED FOR DELL
3.3V_Bus
SHT 2 UHMGA11 SKU ARE MARKED AS "DNI"
A A
ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCIe R480 GDDR3 256MB 8MX32 DVI-I DVI-I
Size Document Number Rev
C 105-A474XX-10 2
Date: Thursday, November 11, 2004 Sheet 1 of 23
5 4 3 2 1
8 7 6 5 4 3 2 1
PCI-EXPRESS EDGE CONNECTOR

+12V_BUS +3.3V_BUS +12V_BUS +3.3V_BUS +3.3V_BUS SYMBOL LEGEND
USE 47uF TANTALUM DNI DO NOT

C1616 C1617 100nF C1619 CAPACITOR OR HIGHER INSTALL
100uF_16V 100uF_16V 120nF C18 47uF_16V
C11 >=6.3V # ACTIVE
LOW
DIGITAL
GROUND
D D
(7) VDDC_PGOOD R1833 0R
ANALOG
GROUND DNI
+12V_BUS +12V_BUS
+3.3V_BUS +3.3V_BUS
+5V
x16 PCIe
B1 A1 PRESENCE
+12V#B1 PRSNT1#A1 R1835
B2 A2
+12V#B2 +12V#A2 0R R1834
B3 A3
RSVD#B3 +12V#A3
B4 A4 10K
GND#B4 GND#A4
B5
SMCLK JTAG2
A5 JTAG_TCK RP216D 4 5 0R DNI VSYNC_DAC1 (4,14,16)
C972
B6
SMDAT JTAG3
A6 JTAG_TDI RP216C 3 6 0R DNI CRT1DDCDATA (4,16)
100nF
JTAG_TDO RP216B 0R DNI
14
B7 A7 2 7
GND#B7 JTAG4 SCL (4,15,19)
B8
+3.3V#B8 JTAG5
A8 JTAG_TMS RP216A 1 8 0R DNI CRT1DDCCLK (4,16)
+ U2A
(4,14,16) HSYNC_DAC1 R1008 0R DNI JTAG_TRST# B9
JTAG1 +3.3V#A9
A9 1
B10 A10 3 R1837 100R
3.3Vaux +3.3V#A10 PERST# PERST#_buf (3,19,20)
B11 A11 2
WAKE# PERST#
Mechanical Key
B12 A12 -
7
RSVD#B12 GND#A12 74ACT08MTC
B13 A13
GND#B13 REFCLK+ PCIE_REFCLKP (3) R1838
B14 A14
(3) PETp0_GFXRp0 PETp0 REFCLK- PCIE_REFCLKN (3) 180R
B15 A15
(3) PETn0_GFXRn0 PETn0 GND#A15 PERp0 C1620
B16 A16
GND#B16 PERp0 PERn0 100nF C1621 GFXTp0_PERp0 (3)
B17 A17
PRSNT2#B17 PERn0 100nF GFXTn0_PERn0 (3)
B18 A18
GND#B18 GND#A18
B19 A19
(3) PETp1_GFXRp1 PETp1 RSVD#A19
B20 A20
B21 A21
B22 A22
GND#B22 PERn1 100nF GFXTn1_PERn1 (3)
B23 A23
(3) PETp2_GFXRp2 PETp2 GND#A23
B24 A24
B25 A25
B26 A26
B27 A27
C B28 A28 C
B29 A29
B30 A30
RSVD#B30 PERn3 100nF GFXTn3_PERn3 (3)
B31 A31
PRSNT2#B31 GND#A31
B32 A32
GND#B32 RSVD#A32
B33 A33
B34 A34
B35 A35
B36 A36
B37 A37
B38 A38
B39 A39
B40 A40
B41 A41
B42 A42
B43 A43
B44 A44
B45 A45
B46 A46
B47 A47
B48 A48
B49 A49
GND#B49 GND#A49
B50 A50
B51 A51
B52 A52
B53 A53
B54 A54
B55 A55
B56 A56
B57 A57
B58 A58
B59 A59
B60 A60
B61 A61
B62 A62
B63 A63
B64 A64
B65 A65
B GND#B65 PERn11 100nF GFXTn11_PERn11 (3) B
B66 A66
B67 A67
B68 A68
B69 A69
B70 A70
B71 A71
B72 A72
B73 A73
B74 A74
B75 A75
B76 A76
B77 A77
B78 A78
B79 A79
B80 A80
PRESENCE GND#B80 PERp15 PERn15 100nF C1651 GFXTp15_PERp15 (3)
B81 A81
B82 A82
RSVD#B82 GND#A82
MPCIE1
A A
<Core Design>
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title PCIe R480 GDDR3 256MB 8MX32 DVI-I DVI-I
Size Document Number 105-A474XX-10 Rev
C 2
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
ATI PN# 215RBKAGA11F
U1A
TP28 PART 1 OF 10
AU38 AN36
(2) PETp0_GFXRp0 PCIE_RX0P PCIE_TX0P GFXTp0_PERp0 (2)
AU39 AM36
(2) PETn0_GFXRn0 TP30 PCIE_RX0N PCIE_TX0N GFXTn0_PERn0 (2)
TP29 AT38 PCI AK34
(2) PETp1_GFXRp1 PCIE_RX1P Express PCIE_TX1P GFXTp1_PERp1 (2)
AR38 AJ34
Interface
TP31 AR39 AK36
AP39 AJ36
TP33 AP38 AK35
AN38 AJ35
TP35 AM38 AH33
AM39 AG33
TP37 AL39 AE32
AL38 AE33
TP39 AK38 AG34
AJ38 AF34
TP41 AJ39 AG35
AH39 AF35
TP43 AH38 AD34
AG38 AC34
TP45 AG37 AD36
AF37 AC36
TP47 AF38 AD35
AF39 AC35
(2) PETn10_GFXRn10 TP50 PCIE_RX10N
215RBKAGA11F PCIE_TX10N GFXTn10_PERn10 (2)
C TP49 AE39 AE31 C
AE38 AD31
TP51 AD38 AB32
AC38 AA32
TP53 AC39 AB33
AB39 AA33
TP55 AB38 AA36
AA38 Y36
TP57 Y38 AA35
Y39 AA34
(2) PETn15_GFXRn15 PCIE_RX15N PCIE_TX15N GFXTn15_PERn15 (2)
TP59
AH31 AL34
(2) PCIE_REFCLKP PCIE_REFCLKP PERSTb_MASK
AG31
(2) PCIE_REFCLKN PCIE_REFCLKN
AM34 AV38 10K R1011

(2,19,20) PERST#_buf PERSTB CALI
AN35 150R R1009
CALRP PCIE_VDDR
AM35 100R R1010
CALRN
B B
A A
<Variant Name>

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
C 105-A474XX-10 2
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
INSTALL TERMINATION RESISTORS

CLOSE TO ASIC
TXCM (18)
TXCP (18)
R797 330R
VID[7..0]
(20) VID[7..0]
U1B
PART 2 OF 10 TX0M (18)
+3.3V_BUS +3.3V_BUS +3.3V_BUS TX0P (18)
VID0 AK26 R796 330R
VID1 VID_0
AJ26 AW23
VID2 VID_1 TXCM
AL24 AW24 TX1M (18)
VID3 VID_2 TXCP
AN25 TX1P (18)
R51 R58 R60 VID4 VID_3 R795 330R
AM23
D
VID5 VID_4 D
4.7K 4.7K 4.7K AL23 AV24
VID6 VID_5 TX0M
AK23 AV25 TX2M (18)
VID7 VID_6 Video Capture/ TX0P
AJ23 TX2P (18)
VID_7 VIP R794 330R
AW26
TX1M
(20) CLK_VIDCLK AM27 AW27
VPCLK0 TX1P
TMDS
(14) DVALID AL26 AV27 +TPVDD
DVALID TX2M
AV28
TX2P
(14) PSYNC AK28
PSYNC
(20) VHAD1 AJ20 AW21 C16

VHAD_1 TPVDD 1.0uF C17 C13 22uF_16V R44
(20) VHAD0 AK20
VHAD_0 Rk
AV22 C15 82pF 100nF 0R
TPVSS DNI +VDD_1.8V
(20) VPHCTL AK19
VPHCTL Ba2
AW29 TXVDDR GND_TPVSS +3.3V_BUS
TXVDDR_1 B4
(20) CLK_VIPCLK AK18 AV30
VIPCLK TXVDDR_2 C8
AL20 AV29 C9 82pF C21 Bead
TP12 SDA I2C TXVSSR_1 22uF_16V 100nF R50
AV26
TXVSSR_2
AK22 AV23 4.7K
TP13 SCL TXVSSR_3 GND_TXVSSR
DVOMODE_0 AW20 AV33
(14) DVOMODE_0 DVOVMODE_0 R R_DAC1 (16)
DVOMODE_1 AP23 AW33
(14) DVOMODE_1 DVOVMODE_1 DVO G G_DAC1 (16)
AW32 B_DAC1 (16)
B
(19) DVO_VSYNC AU13
ZV_LCDCNTL_0
(19) DVO_HSYNC AV14 AU36 VSYNC_DAC1 (2,14,16)
DVO[11..0] ZV_LCDCNTL_1 VSYNC
(19) DVO[11..0] (19) DVO_DE AW14 AU35 HSYNC_DAC1 (2,14,16)
ZV_LCDCNTL_2 HSYNC
(19) CLK_DVOCLK0 AU14 215RBKAGA11F AR36 STEREOSYNC (21)
DVO0 ZV_LCDCNTL_3 STEREOSYNC
AW15
DVO1 ZV_LCDDATA_0
AV15 AR35
DVO2 ZV_LCDDATA_1 AUXWIN
AU15
DVO3 ZV_LCDDATA_2 R52 499R
AV16 AW35
DVO4 ZV_LCDDATA_3 DAC1 RSET
Install close to ASIC to provide DVO5
AU16
AV17
ZV_LCDDATA_4
AV34 GND_RSET Ba3 +VDD_1.8V +VDD_1.8V
ZV_LCDDATA_5 AVDD_1 B5 B7
return path for EMI DVO6
DVO7
AW17
AU17
ZV_LCDDATA_6 AVDD_2
AV35
AVDD
+AVDD +VDDDI
DVO8 ZV_LCDDATA_7 C7 C40 Bead

AW18 AT34
82pF C525 DVO9 ZV_LCDDATA_8 AVSSQ 1.0uF 100nF C23 1.0uF C28 Bead
C AV18 AU34 C
DVO10 ZV_LCDDATA_9 AVSSN_1 GND_AVSSQ DNI 22uF_16V C30 22uF_16V
AV19 AU33
DVO11 ZV_LCDDATA_10 AVSSN_2 C29 100nF
AV20
ZV_LCDDATA_11 GND_AVSSN
AP17 AP35
ZV_LCDDATA_12 VDD1DI
(14) DC_Strap2 AR17
ZV_LCDDATA_13
(14,21) DC_Strap3 AT17 AP36
ZV_LCDDATA_14 VSS1DI
(14) DC_Strap4 AM18
ZV_LCDDATA_15
AP19 AV31 R_DAC2 (17)
ZV_LCDDATA_16 R2
AN19 AU31 G_DAC2 (17)
ZV_LCDDATA_17 G2
(14) PAL/NTSC AM19 AW30 B_DAC2 (17)
ZV_LCDDATA_18 B2
AM21
(14) DEMUX_SEL ZV_LCDDATA_19
AP20 AN31 HSYNC_DAC2 (14,17)
ZV_LCDDATA_20 H2SYNC
AM22 AP31 VSYNC_DAC2 (14,17)
ZV_LCDDATA_21 V2SYNC
AP22
ZV_LCDDATA_22
(14) GPIO[6..0] AN22 AR32 C_DAC2 (21)
ZV_LCDDATA_23 C
(8,14) GPIO[13..8] AT32 Y_DAC2 (21)
GPIO0 Y
AV13 AT31 COMP_DAC2 (21)
GPIO1 GPIO_0 COMP
(8) GPIO15 AU12
GPIO2 GPIO_1 R55 715R +A2VDD
AV12 AV32
GPIO3 GPIO_2 R2SET
(15) ThermINT AW12
GPIO4 GPIO_3 GND_R2SET 1.0uF
AU11 AP28
+3.3V_BUS GPIO5 GPIO_4 DAC2 A2VDD_1 C32
AW11 AN28
GPIO6 GPIO_5 A2VDD_2 DNI C33
AV11
GPIO_6 C31 100nF 22uF_16V
AU10 AP29
499R R586 499R R587 GPIO8 GPIO_7 A2VSSN_1 +A2VDDQ +VDD_1.8V
AV10 AN29
GPIO9 GPIO_8 A2VSSN_2 GND_A2VSSN B9
AV9
GPIO_9
Ba5
GPIO10 AT13 GPIO AM28
GPIO11 GPIO_10 A2VDDQ 1.0uF
AR14
GPIO12 GPIO_11 C38 C39 Bead
(15) GPU_DPLUS AT14 AM29
GPIO13 GPIO_12 A2VSSQ +VDD2DI +VDD_1.8V C37 100nF +3.3V_BUS +3.3V_BUS
(15) GPU_DMINUS AN15
GPIO_13 B8 Bead 22uF_16V
(19) HPD2_INT AT15 AL29
GPIO_14 VDD2DI
AT16
GPIO_15 1.0uF C34
AN16 AK29
+PVDD GPIO_16 VSS2DI C36 22uF_16V GND_A2VSSQ R53 R54
AP16
GPIO_17 C35 100nF 4.7K 4.7K
C41 AK15 Hot Plug AL16
C27 C26 1.0uF VREFG HPD1
HPD1 (18)
22uF_16V 100nF AJ16 AT36 SDA (15,19)
B DPLUS Thermal DDC1DATA B
AT35 SCL (2,15,19)
Diode DDC1CLK
AJ17
DMINUS
AL17 CRT1DDCDATA (2,16)
GND_PVSS PVDD DDC DDC2DATA
AW36 AM16 CRT1DDCCLK (2,16)
PVDD PLL DDC2CLK
PVSS AV36 AN32
PVSS DDC3DATA CRT2DDCDATA (17)
+MPVDD AP32
DDC3CLK CRT2DDCCLK (17)
MPVDD A10
1.0uF 1.0uF 1.0uF MPVSS MPVDD Mem PLL TESTEN 1K R43
A11 AN33
C46 C45 C42 MPVSS TEST TESTEN
100nF C44 C43 XTALIN AV37 AK13 ROMCS#
22uF_16V XTALOUT XTALIN XTAL ROM ROMCSb
AW37
XTALOUT
GND_MPVSS
+3.3V_BUS
R1836
10R
JU_LED
JU2
1
SDA R25 33R 2
+3.3V_BUS SCL R26 33R 3
+3.3V_BUS MU11 4
4x2mm
BIOS
Test
B3
220R Oscillator Circuit R91 JU_LED connector in
10K
To Rage Theater 113-A47401-001
the vicinity of Top Left
corner
Y3 GPIO8 33R 1 8 RP193A ROM_SO
4 3 R1623 22R U11
VCC OUT CLK_RT_XTALIN (20)
R1625 C1522 C1523 GPIO9 33R 4 5 RP193D SI/A16 5 2
1K XTALIN D Q
2 1
1.0uF 100nF GND E/D GPIO10 33R 3
A 6 RP193C SCK/WEb 6 A
R65 C
27.000MHz
DNI 0R ROMCS# 33R 2 7 RP193B CSb 1
R57 S
221R HOLD1 7
+3.3V_BUS HOLD
221R 3
R63 XTALOUT W
8 4 <Variant Name> ATI Technologies Inc.
VCC VSS
SERIAL EEPROM 512K/1M C80 M25P05-AVMN6T
Markham, Ontario
100nF
Canada, L3T 7X6
R66 (905) 882-2600
150R ALTERNATIVE PART :M25P05(512Kbit)
C 105-A474XX-10 2
8 7 6 5 4 3 2 1
5 4 3 2 1
U1G
+3.3V_BUS
A7
VDDR1_1
E1
VDDR1_2
T36
VDDR1_3 C66 C624 C625 C626 C627 C1952 C1953 C1954 C1955
A17
VDDR1_4 PART 7 OF 10 VDDR3_1
AH16
C67 1.0uF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF
A19 AH28
VDDR1_5 VDDR3_2 22uF_16V
A22 AH27
VDDR1_6 VDDR3_3
A26 AG16
D VDDR1_7 VDDR3_4 D
A29 POWER AJ28
VDDR1_8 VDDR3_5
A32 AJ29
VDDR1_9 VDDR3_6
AM15 AH15
VDDR1_10 VDDR3_7
N14 AJ27
VDDR1_11 I/O VDDR3_8 +VDDR4 +3.3V_BUS
AW9
VDDR1_12 B12 220R R69 DNI 0R
K39 AH21
+MVDDQ VDDR1_13 VDDR4_1
F8 AJ22
VDDR1_14 VDDR4_2 C74 +VDD_1.8V
J11 AH22
VDDR1_15 VDDR4_3 1.0uF C709 R70 0R
M14 AK21
VDDR1_16 VDDR4_4 100nF
AW6 AL21
C600 C601 C602 C603 C604 C605 C606 C607 VDDR1_17 VDDR4_5
AR1 AL22
10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF VDDR1_18 VDDR4_6 +VDDR5 +3.3V_BUS
AK1
VDDR1_19 B14 220R R67 DNI 0R
AM7 AH18
VDDR1_20 VDDR5_1
AL8 AH19
VDDR1_21 VDDR5_2 +VDD_1.8V
G8 AL18
VDDR1_22 VDDR5_3 C75 C710 R68 0R
L14 AL19
VDDR1_23 VDDR5_4 1.0uF
U1 100nF
C608 C609 C610 C611 C69 VDDR1_24
U11
C70 C71 10nF 10nF 10nF 10nF 1uF VDDR1_25
AL7 AE28
10uf 10uf VDDR1_26 PCIE_VDDR_12_10 PCIE_VDDR
H9 AF28
VDDR1_27 PCIE_VDDR_12_9 change to 4210010600
AL15 AG29
VDDR1_28 PCIE_VDDR_12_1 L82
AM14 AG28
VDDR1_29 PCIE_VDDR_12_2 42r@100MHz
AL10 AK31
VDDR1_30 PCIE_VDDR_12_3
AH10 AK30
C612 C613 C614 C615 C707 C708 VDDR1_31 PCIE_VDDR_12_4 C1668 C1702 C1669 C1670
AK9 AJ30
C72 C73 10nF 10nF 10nF 10nF VDDR1_32 PCIE_VDDR_12_5
100nF AH12 215RBKAGA11F AJ31 10uF_6.3V 10uF_6.3V 100nF 1nF
10uf 10uf 100nF VDDR1_33 PCIE_VDDR_12_6
AG14 AF30
VDDR1_34 PCIE_VDDR_12_7
AG13 AF29
VDDR1_35 PCIE PCIE_VDDR_12_8
AG7
VDDR1_36 PCIE_PVDD_12 L81
AK4 AD28
VDDR1_37 PCIE_PVDD_12_1 60R
N13 AC27
VDDR1_38 PCIE_PVDD_12_2
C616 C617 C618 C619 C620 C621 C622 C623 C676
AF8
VDDR1_39 Memory I/O PCIE_PVDD_12_3
AC29
C1703 C1673 C1674
N27 AD27
10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF VDDR1_40 PCIE_PVDD_12_4 10uF_6.3V 1nF 100nF
AF13 AC28
100nF VDDR1_41 PCIE_PVDD_12_5 PCIE_PVDD_18
W7
VDDR1_42
L10 AB30
H8 AA30
G9 AA29
C VDDR1_45 PCIE_PVDD_18_3 C
AF7 AB29
VDDR1_46 PCIE_PVDD_18_4 C1675 C1704 C1676 C1677
V13 AB28
VDDR1_47 PCIE_PVDD_18_5 10uF_6.3V 10uF_6.3V 1nF 100nF
W13 AA28
AA1 AB27
VDDR1_49 PCIE_PVDD_18_7 +VDDC
AD1
VDDR1_50
AE13
VDDR1_51
AF1 AC21
VDDR1_52 VDDC_1
Y8 U19
VDDR1_53 VDDC_2
K11 U21
VDDR1_54 VDDC_3 C632 C633 C634 C635 C636 C56 C57 C673
V11 AC19
VDDR1_55 VDDC_4 10nF 10nF 10nF 10nF 1.0uF 1.0uF 1.0uF 1.0uF
U6 V18
VDDR1_56 VDDC_5
T33 V19
VDDR1_57 VDDC_6
U33 V20
VDDR1_58 VDDC_7
U34 V21
VDDR1_59 VDDC_8
M13 V22
VDDR1_60 VDDC_9
L13 W18
VDDR1_61 VDDC_10 C637 C638 C639 C640 C641 C642 C643 C644
G20 W19
VDDR1_62 VDDC_11 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF
G19 W20
VDDR1_63 VDDC_12
L22 W21
VDDR1_64 VDDC_13
L23 W22
VDDR1_65 VDDC_14
N29 Y19
VDDR1_66 VDDC_15
P29 Y20
VDDR1_67 VDDC_16
L31 Y21
VDDR1_68 VDDC_17 C61 C62 C59 C63
M1 AA18
VDDR1_69 VDDC_18 10uf 10uf 10uF_10V 10uF_10V
M12 AA19
VDDR1_70 VDDC_19
H20 AA20
VDDR1_71 VDDC_20
M23 AA21
VDDR1_72 VDDC_21
N25
VDDR1_73 CORE VDDC_22
AA22
N26 AB18
VDDR1_74 VDDC_23
M30 AB19
VDDR1_75 VDDC_24
M31 AB20
VDDR1_76 VDDC_25
N16 AB21
VDDR1_77 VDDC_26
N17 AB22
VDDR1_78 VDDC_27
N18 W17
VDDR1_79 VDDC_28
N21 Y18
VDDR1_80 VDDC_29
N22 AA17
VDDR1_81 VDDC_30
N23 AA23
VDDR1_82 VDDC_31
N39 Y22
B VDDR1_83 VDDC_32 B
R1 W23
VDDR1_84 VDDC_33
Y7 U18
VDDR1_85 VDDC_34
U27 U22
VDDR1_86 VDDC_35
T27 AC18
VDDR1_87 VDDC_36
N28 AC22
VDDR1_88 VDDC_37
U13
VDDR1_89
U12 Y27
+MVDDQ VDDR1_90 VDDCI_8
Y13
VDDCI_7 +VDDC
N20
VDDCI_6
AG20
B32 220R VDDCI_5
C38 AC20
B31 220R VDDRH_0 VDDCI_4
A13 Y23
B30 220R VDDRH_1 VDDCI_3 C646 C648 C60
H1 Y17
B29 220R VDDRH_2 VDDCI_2 10nF 10nF 10uf
AM1 U20
VDDRH_3 VDDCI_1 +VDDC_CT
C668 C667 C666 C665 AG22

1.0uF C669 1.0uF C670 1.0uF C671 1.0uF C672 VDD15_6
Memory I/O VDD15_5
AG21
100nF 100nF 100nF 100nF Clock Generator I/O (INTERNAL) VDD15_4
AG18
AG17 C48 C49 C50 C53
VDD15_3
100nF 100nF 100nF 22uF_16V
D36
VSSRH_0
A14
VSSRH_1
J1
VSSRH_2
AN1
VSSRH_3
GND_VSSRH3 GND_VSSRH2 GND_VSSRH1 GND_VSSRH0
A A

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
C 105-A474XX-10 2
5 4 3 2 1
5 4 3 2 1
U1H U1I U1J

J16 AA27
VSS_71
J24 PART
VSS_72 9 OF 10VSS_363
VSS_362
W36 AM32
SSIN PART 10 OF 10 NC_4
AR29
PCIE_VSS_1 PART 8 OF 10
AB31 J25 W37 AR30
GND VSS_73 VSS_361 NC_5
AD33 AL27 L29 W39 AL30
PCIE_VSS_2 VSS_280 VSS_74 VSS_360 NC_1
AD32 AH20 AU27 R32 AU28
AD37 AK25 N36 D12 AL13 AU29
PCIE_VSS_4 VSS_278 VSS_76 VSS_358 NC_2 NC_7
AG36 R35 N35 E36
PCIE_VSS_5 VSS_277 VSS_77 VSS_357
AE35 T34 J35 AK24 AL14 AT28
PCIE_VSS_6 VSS_276 VSS_78 VSS_356 NC_3 NC_8
AE36 AK16 F7 AW8 AT29
AH35 L20 K16 AW5
PCIE_VSS_8 VSS_274 VSS_80 VSS_354 +VDD_1.8V
AG30 AL5 K25 AT6 AU25
AF32 AV21 AH23 AT1 AU26
Y34 AN7 K33 R28
AH37 AL6 K34 AT27 AP25 AT25
D PCIE_VSS_12 VSS_270 VSS_84 VSS_350 LPVDD NC_12 D
AH36 AH5 K35 AT24 AT26
AE29 AK27 K36 D26
PCIE_VSS_14 VSS_268 VSS_86 VSS_348 +A2VDD
AN37 AH26 L1 AT21 AP26
PCIE_VSS_15 VSS_267 VSS_87 VSS_347 LPVSS
AH30 AK6 L7 F17 AR23
AC32 AN26 L9 M20 AR24
AK37 AK17 L11 AT11
AD29 AL12 E16 AT7 AH24 AU22
PCIE_VSS_19 VSS_263 VSS_91 VSS_343 R71 LVDDR_18/VDDL0_1 NC_16
AF33 U30 L16 AR8 AG24 AU23
PCIE_VSS_20 VSS_262 VSS_92 VSS_342 4.7K LVDDR_18/VDDL0_2 NC_17
AL35 AM6 L17 AN5
AM37 AK8 L25 AL4 AG27 AT22
PCIE_VSS_22 VSS_260 VSS_94 VSS_340 LVDDR_25/VDDL1_1 NC_18
AJ33 AG6 L26 AR31 AG26 AT23
PCIE_VSS_23 VSS_259 VSS_95 VSS_339 LVDDR_25/VDDL1_2 NC_19
AL37 AG5 J34 AM26
AL32 AG4 L33 AR28 AU19
AE34 AR34 L39 AU24 AR27 AU20
PCIE_VSS_26 VSS_256 VSS_98 VSS_336 LVSSR_1 NC_21
AF36 AJ18 P4 AR25 AR26
PCIE_VSS_27 VSS_255 VSS_99 VSS_335 LVSSR_2
AC30 AL25 N5 AU21 AR21 AT19
AF27 AJ14 M8 AR22 AR20 AT20
Y37 AK14 M7 AJ24
AG32 AP8 M9 AR18
PCIE_VSS_31 VSS_251 VSS_103 VSS_331 215RBKAGA11F
AJ37 AJ8 M10 AR16
AC33 AJ7 M11 AR15
AH32 AJ1 E15 AP14
AH34 AH17 M17 AR12
AF31 AH14 M26 AR9
AD30 AG19 M35 AT8
AB34 AG23 P5 AR7
AC31 AG15 N9 AP10
AB37 AG1 L12 AP30
AC37 AR33 J4 AP27
AL33 AT33 D16 AN24
AB35 AP33 N15 AP21
PCIE_VSS_43 VSS_239 VSS_115 VSS_319 GND_MPVSS GND_TPVSS GND_A2VSSN GND_AVSSQ GND_RSET GND_VSSRH0 GND_VSSRH2 GND_P GND_RT
AB36 J6 N19 AP18
AE37 AU18 J30 AP15
AA37 AP34 N24 AN11
PCIE_VSS_46 VSS_236 VSS_118 VSS_316 GND_AVSSN GND_PVSS GND_TXVSSR GND_R2SET GND_TVVSSN GND_VSSRH1 GND_VSSRH3 GND_A GND_VIN
AE30 AE9 H23 AP9 GND_A2VSSQ
AA31 AE5 G22 AR5
T35 U28 AR13
VSS_233 VSS_121 VSS_313
C AE27
PCIE_VSS_50 VSS_232
F30 U29
VSS_122 VSS_312
AN30 NOTE: THIS IS A DRAWING. THESE GROUNDS MUST C
Y35 E30 N30 AH25
PCIE_VSS_51 VSS_231 VSS_123 VSS_311 BE MANUALLY CONNECTED TO THE GROUND PLANE
AR37 K31 N31 AN27
AT37 H31 N33 AN23
AP37 F31 N34 AM24
AN34 H32 AJ25 AU30
AL36 AD13 AM33 AN21
AK33 AD11 P1 AN20
AK32 AD10 P8 AN18
AJ32 AD9 P7 AN17
Y33 AD7 P11 AJ21
AC6 P12 AN14
VSS_221 VSS_133 VSS_301
AD5 P13 AN10
VSS_220 VSS_134 VSS_300
A8 AD6 P27 AM10
VSS_1 VSS_219 VSS_135 VSS_299
J10 E21 P28 AM8
R33 D22 T29 AT3
A16 G32 L30 AN8
A20 G36 M33 AT30
A23 AC13 P39 AH29
A25 AC12 R4 AM31
A28 AC11 R5 AT18
A31 AC8 R6 AM30
B3 AC7 R7 AM25
G37 AC1 R9 AP24
Y6 E22 R10 AM20
AL11 F22 R11 AM17
D10 M25 R13 L19
D13 J7 R27 AM11
D19 AU37 T5 AN9
D28 AT12 T9 AP7
D34 H4 T13 AL31
D35 V23 U17 AL28
AJ15 AB23 AC17 AK5
F1 AB13 AC23 AK11
E4 AB9 Y31 AJ12
E9 AB5 U23 AJ11
E10 AU32 K30 AH9
E12 W11 H29 AG11
B VSS_25 VSS_195 VSS_372 VSS_406 B
E13 AF4 J29 AG10
E18 AA13 K29 AG9
E19 AA11 G28 AF11
E27 AA10 H28 AF12
E28 AA9 J28 W9
E33 U7 G26 V10
E34 W6 H26 V9
E38 Y5 D25 V5
F4 AA5 E25 V4
F5 AJ9 G25
VSS_35 VSS_185 VSS_382
G6 AR19 E24
H10 Y28 J22
F13 AG25 K22
F19 AU9 J21
F28 Y12 J19
H34 Y11 K19
C34 U8 J18
G5 V7 J14
G7 Y1 J13
H11 AJ19 K13
G11 Y32 D7
G13 Y30 E7
G14 Y29 E6
G16 W35 U5
G17 W30
VSS_50 VSS_170 215RBKAGA11F
G23 W34
VSS_51 VSS_169
G33 W27
VSS_52 VSS_168
G34 V35
VSS_53 VSS_167
G35 W32
VSS_54 VSS_166
V31 V27
VSS_55 VSS_165
F25 AB17
VSS_56 VSS_164
G10 V17
VSS_57 VSS_163
H7 V1
VSS_58 VSS_162
F11
VSS_59
H14
VSS_60
H17
VSS_61
M29
VSS_62
A H33 A
VSS_63
H39
VSS_64
J5
VSS_65
K5
VSS_66
F9
VSS_67
F10 <Variant Name>
VSS_68
F16
VSS_69
J15
VSS_70 ATI Technologies Inc.
215RBKAGA11F Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
C 105-A474XX-10 2
5 4 3 2 1
8 7 6 5 4 3 2 1
D D
+12V_BUS +12VEXT
60R B78
B72 60R
DNI
OPTIONAL
VIN1
C1692
CORE REGULATOR VDDC C1688 C1689
FDS7096N3 100nF 10uF 10uF
Trace as short as possible for 2A current +5V Q27
*
BAT54SLT1
1
Thermal Thermal
C1151 100nF Pad 9 Pad 9
3
4 5 4 5
D28 3 6 3 6
2 7 2 7
2
1 8 1 8
*
FDS7096N3 Q231
L63 1.71uH
1 2
R1589
C Q28 Q29 C
R1851 CHANGE TO 1.5uH 23A
2.2R
0R Thermal Thermal VISHAY IHLP5050EZRZ1R5M01
Pad 9 Pad 9 +VDDC
4 5 4 5 C1706
3 6 3 6 1nF
2 7 2 7 R1617
1 8 1 8 0R
R1632 DNI C1532 C1152 C1153 C1154 C1155 C1951 C1948 C1949 C1950
DNI 432R FDS7064N FDS7064N *** PADS SHORTED IN 33uF_16V 1500uF 1500uF 1500uF 1500uF 1500uF 330uF_2.5V 330uF_2.5V 330uF_2.5V
LAYOUT
R1618
0R
C1173 R1597 DNI
1uF PADS SHORTED IN
LAYOUT
R1593 432R
+12V_BUS 1.50K
432R R1592 OPTIONAL
DNI
R873 0R VDDC_PGOOD (2) DNI
C1156 R1594
Do not install 220nF C1157
1.00K
R1591
This resistor will R1619 22nf 10K +5V

be shorted in layout. 0R
C1158 C1159
15
16
17
18
19
20
21
22
23
24
25
26
27
28
10uf 0.22uF
U43
ISNS1
SW1
AGND
PGOOD
HDRV1
BOOT1
PGND1
LDRV1
VCORE+
VIN
VCC
VCORE-
DELAY
SS
+3.3V_BUS +12V_BUS +5V
FAN5240MTCX
PGND2
BOOT2
HDRV2
LDRV2
FPWM
ISNS2
R1595 R1840
VID0
VID1
VID2
VID3
VID4
SW2
ILIM
B B
243R 2K
EN
14
13
12
11
10
R1860
15K
R1603
1.00K
3
Q225 Q37 R1596

CMPT3904 1 CMPT3904 41.2K
3
R1602
1 4.7K C1160
2
R1861
2K 1nf *
2
R1598
R1852
R1853
R1854
R1855
R1856
R1857
R1858
221R FDS7064N FDS7064N

1K
1K
1K
1K
1K
1K
1K
1 8 1 8
2 7 2 7
DNI
DNI
DNI
3 6 3 6
R1590 4 5 4 5
+5V
Pad 9 Pad 9
0R Thermal Thermal
*
L64
Q210 Q224 1.71uH
VID
1 2
4 3 2 1 0 +VDDC
FDS7096N3
--------------------------------- R1859
1 8 1 8
1 0 0 1 1 1.200 2 7 2 7 2.2R CHANGE TO 1.5uH 23A +12V_BUS +12VEXT
1 0 0 1 0 1.225 * 3 6 3 6
4 5 4 5 VISHAY IHLP5050EZRZ1R5M01
1 0 0 0 1 1.250
9 9 C1707
1 0 0 0 0 1.275 Pad Pad
1nF 60R B80
Thermal Thermal
0 1 1 1 0 1.300 B79 60R
A DNI A
0 1 1 0 1 1.350
2
Q31
0 1 1 0 0 1.400
Q232 FDS7096N3
3
D29 OPTIONAL
C1161 100nF
1
<Variant Name>
BAT54SLT1 1 Commerce Valley Drive East
C1690 C1691 Markham, Ontario
VIN2 10uF 10uF Canada, L3T 7X6
+5V (905) 882-2600
C 105-A474XX-10 2
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+12V_BUS +5V +12V_BUS +12VEXT
MVDDQ Switching Regulator for

DNI
R372 R373 Memory Core for 256M POWER SEQUENCING CIRCUIT: DESIGN NOTES:
0R 2R2 B21 B76
configuration 60R 60R
1 DNI Add this Capacitor for SP6132
D4
BAT54SLT1 +12V_BUS COMP_VDDC1
3 BST1 C122 100nF SWN1 Q21 R377 DNI +MVDDC C140 DNI
+PW_VDDC1 UVIN1 SS_VDDC1 2.2nF
R376 4 5 R248
3
DNI 0R 3 6 C1680 63.4K 20K
2
D D
2 7 C1678 C1679 R378 R250 1 Compensation Circuit
3
R251 0R BOOT_VDDC1 1 8 10uF 10uF 100K 2K
100nF DNI 1 COMP_VDDC1
2
IRF7413A Q10
DNI R249 Q9 CMPT3904
2
C136 U31 DNI 2.4K CMPT3904 C111 Cc3
0.22uF SS_VDDC1 7 10 BST1 L65 Cc2 33pF
SS BST 1.5uH +MVDDQ C112
9 MVDDQ_UGATE 10nF
Fb_VDDC1 GH
4
C141 COMP_VDDC1 5 Vfb Q22 Fb_VDDC1
COMP GND
3 *** ***
22nf C110 C106 R264
UVIN1 6 2 M<VDDQ_LGATE 4 5 1nf Rc1 330uF_2.5V C105 C104 Rc5 15K
UVIN GL 330uF_2.5V 330uF_2.5V
SWN1 MVDDQ_VCC
3 6 Cc1 R253
Cout1
8
SWN Vcc
1 2 7 ***
1 8 2K ***
SP6132
IRF7413A
R254
1.5K
1% FOR ALTERNATE #2
Rc4 Change C142 for 10uF
+MVDDQ = REF * (1+Rc1/Rc2)
C142 Alternative 2 Fb_VDDC1
1uF SIPEX SP6132 Change C122 for 1uF
Rc2
IRF7413ATR (2020005600) R256 Replace R251 with a bead
1.24K
R257 10K +12V_BUS 1%
Alternative 1 Swap Rc4 with Cc1
MU31
R258 51K 1 14
+PW_VDDC1 R259 3K RT VCC C113
2 13
SS_VDDC1 OCSET PVCC 1uF
3 12
COMP_VDDC1 SS LGATE
4 11
Fb_VDDC1 COMP PGND BOOT_VDDC1 R255 C116
5 10
FB BOOT 2.2R 1nF
6 9
EN UGATE
7 8
GND PHASE
C C
ISL6522CB
ISL6522CB : SOIC
ISL6522CV : TSSOP
+12V_BUS +5V
+12V_BUS +12VEXT
DNI MVDDC Switching Regulator for

R370 R371
0R 2R2 Memory Core for 256M
configuration B28 B77 C163
60R 60R 180uF_16V
DNI DNI
1
D5
BAT54SLT1
3 BST2 C121 100nF SWN2 Q23 R374 DNI
+PW_VDDC2 UVIN2
DNI R112 4 5
0R 3 6 C1683 220K
2
2 7 C1681 C1682 R375

R314 0R BOOT_VDDC2 1 8 10uF 10uF 100K
100nF DNI
IRF7413A
C158 POWER SEQUENCING CIRCUIT: DESIGN NOTES:
0.22uF U32 DNI
DNI SS_VDDC2 7 10 BST2 L66 Add this Capacitor for SP6132
SS BST 1.5uH +MVDDC
9 MVDDC_UGATE 330uF_2.5V COMP_VDDC2
Fb_VDDC2 GH +12V_BUS C168 DNI
4
C169 COMP_VDDC2 5 Vfb Q24 +VDDC 100pF
B COMP GND
3 *** *** B
22nf C161 C164 C165 C166 SS_VDDC2 Cc4
UVIN2 6 2 MVDDC_LGATE 4 5 1nf Rc1 R1848
UVIN GL
3
3 6 Cc1 Cout1 330uF_2.5V 330uF_2.5V 20K
SWN2 8 1 MVDDC_VCC 2 7 R310 *** R1849 1 Compensation Circuit
SWN Vcc
3
1 8 1.87K *** 1K
SP6132 R309 1% 1 COMP_VDDC2
2
IRF7413A 1.5K Q227
Rc4 R1850 Q228 CMPT3904
2
+MVDDC = REF * (1+Rc1/Rc2) 2.4K CMPT3904 C170 Cc3
C157 Alternative 2 Cc2 33pF
1uF SIPEX SP6132 Fb_VDDC2 C171
10nF
Rc2 Fb_VDDC2
IRF7413ATR (2020005600) R311 R313
1.24K Rc5 15K
R307 10K +12V_BUS 1%
Alternative 1
MU32
R305
+PW_VDDC2 R306
51K
3K
1
RT VCC
14
C159
FOR ALTERNATE #2
2 13
SS_VDDC2 OCSET PVCC 1uF
3 12
COMP_VDDC2 SS LGATE
4 11
Fb_VDDC2 5
COMP
FB
PGND
BOOT
10 BOOT_VDDC2 R308 C160 Change C157 for 10 uF
6 9 2.2R 1nF
EN UGATE +12VEXT +12V_BUS
7 8
GND PHASE
J1 Change C121 for 1 uF
***
D36 D37 D38
ISL6522CB 6P_HDER
1 R1868 0R 1 2 1 2 1 2
ISL6522CB : SOIC
+12V_1
+12V_2
2 DNI Replace C764 by 0 Ohm resistor
ISL6522CV : TSSOP 3 L84
+12V_3 61R S3AB S3AB S3AB
1 4 C1956 C1165 C1166 Remove R954
C1957 1nF
1nF 2 3 10uF_25V 10uF_25V
+3.3V_BUS +5V +3.3V_BUS
GND_1
4 Replace R314 with a bead
6 R1869 0R
GND_2 DNI
A
Swap Rc4 with Cc1 A
R1841 R1867 5 B81 220R Sense

10K 10K Sense
DNI
3
Q226
1R1556 10K Sense
<Variant Name>
CMPT3904 ATI Technologies Inc.
2
R874 0R EXT_PWR# 1 Commerce Valley Drive East

(4,14) GPIO8 DNI Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
R1842
R909 0R EXT_PWR# EXTERNAL POWER DETECT 10K Title PCIe R480 GDDR3 256MB 8MX32 DVI-I DVI-I
(4) GPIO15
C 2
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+1.8V Regulator for analog power supplies +1.5V Regulator for VDDC_CT (VDD15)
+3.3V_BUS +3.3V_BUS
D D
B23 B22
60R REG2 +VDD_1.8V 60R REG7 +VDDC_CT
LT1117CST LT1117CST
3 2 3 2
IN ADJ OUT IN OUT
ADJ
C134 C135 4 C131 C132 C129 C128 4 C127 C126
22uF_16V 100nF CASE 100nF 22uF_16V 22uF_16V 100nF CASE 100nF 22uF_16V
R129 R128
1
1
1.50K 1.0K
1% 1%
R126 R125
681R 200R
1% 1%
Max 400 mA if all 1.8 V analog power supplies are connected
REGULATOR REGULATOR REGULATOR REGULATOR

+3.3V_BUS
FOR +3.3V_BUS
FOR PVDD +3.3V_BUS
FOR TPVDD +3.3V_BUS
FOR
A2VDD(+2.5V) (+1.8V) (+1.8V) MPVDD(+1.8V)
B25 200R B27 200R B26 200R
B24
200R
C +A2VDD R139 R143 R142 C
REG3 75R
1 5 33R +PVDD 33R +TPVDD +MPVDD
VIN VOUT
1uF
GND
3
3 4 1uF R140 R145 R144
C145 SHDN BYPASS C146 AS432S 681R REG4 AS432S 681R REG6 AS432S 681R REG5
2.5V 1 1% 4 1 1% 4 1 1% 4
2
C147 NC SC431LC5SK-1 NC SC431LC5SK-1 NC SC431LC5SK-1

1 1 1
470pF MREG4 R141 2 NC MREG6 R147 2 NC MREG5 R146 2 NC
DNI DNI 1.50K DNI 1.50K DNI 1.50K

3
5
1% 1% 1%
GND_A2VSSN GND_A2VSSN
GND_PVSS GND_TPVSS GND_MPVSS
+1.8V Regulator for PCIE_PVDD_18

Regulator for PCIE_VDDR
+VDD_1.8V
Vout = 1.2V +3.3V_BUS
+PVDD
+3.3V_BUS L83
REG11 PCIE_PVDD_18 60R C1618
LT1117CST DNI
B70 50R 3 2 B66
IN OUT BLM21A121SPT 22uF_16V PCIE_VDDR
ADJ
C1666 4 C1664
CASE
3
6
C1665 100nF C1667 22uF_16V REG12
22uF_16V R1792 100nF R1781 1 5
VCNTL
TAB
1
1.50K 1.0K IN VOUT

1%
4 2 ***
REFEN GND R1843 C1705 C1655 C1700
B 22uF_16V B
RT9173ACL5 1K 22uF_6.3V 22uF_6.3V
R1793 R1783 402
681R PCIE_PVDD_18 +3.3V_BUS 2K C975 ***
1% 1.0uF
R1797
3
R1795 Q215
1.5K 20K
CMPT3904 1
3
Q216 R1798 100R 2N7002LT1

1
2
+12V_BUS
2
R1799
2.4K
R1789 R1845 R1846 R1847

110R 110R 110R 110R REG10 +5V
LT1117CST
3 2
IN OUT
ADJ
4
C1663 CASE R1790 C1662
1uF 1.00K 22uF_16V
1
1%
R1791
3.01K
1%
+5V regulator
Vin = 12v
Vout = 5V
Iout =
A A
<Variant Name>
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600

C 2
8 7 6 5 4 3 2 1
5 4 3 2 1
R423 MEMORY CHANNELS A and B
D D
MAA[13..0] MAB[13..0]
(12) MAA[13..0] (12) MAB[13..0]
MDA[63..0]
(12) MDA[63..0] (12) MDB[63..0]
U1C U1D
MDA0 W38 Part 3 of 10 B34 MAA0 MDB0 C33 Part 4 of 10 B12 MAB0
MDA1 DQA_0 MAA_0 MAA1 MDB1 DQB_0 MAB_0 MAB1
V37 B35 B32 B13
V38 A34 C32 C13
U37 B33 B31 C12
MDA4 DQA_3 MAA_3 MAA4 MDB4 DQB_3 Memory MAB_3 MAB4
T39 Memory J38 B29 C22
T38 Channel A H38 C29 Channel B C21
R37 G39 B28 B20
R38 H37 C28 B21
W33 F38 G30 B19
V34 G38 H30 C20
V36 A35 G29 C14
V32 B36 F29 B14
U36 A37 F27 B15
T32 E39 E26 B18
MDA14 DQA_13 MAA_13 MDB14 DQB_13 MAB_13
R36 D38 D27 C17
MDA15 DQA_14 MAA_14 MDB15 DQB_14 MAB_14
R34 DQMA#[7..0] (12) F26 DQMB#[7..0] (12)
MDA16 DQA_15 MDB16 DQB_15
P37 B27
MDA17 DQA_16 DQMA#0 MDB17 DQB_16 DQMB#0
P38 T37 C27 C30
MDA18 DQA_17 DQMAb_0 DQMA#1 MDB18 DQB_17 DQMBb_0 DQMB#1
N37 U35 B26 G27
N38 M37 C26 B25
L38 L34 C24 K21
K37 N32 B23 E23
K38 V30 C23 D20
J37 F32 B22 K15
P34 H27 M24 D9
MDA25 DQA_24 DQMAb_7 QSA#[7..0] (12) MDB25 DQB_24 DQMBb_7 QSB#[7..0] (12)
C P35 L24 C
MDA26 DQA_25 QSA#0 MDB26 DQB_25 QSB#0
P36 U39 K24 C31
MDA27 DQA_26 QSA_0B QSA#1 MDB27 DQB_26 QSB_0B QSB#1
M34 U32 M22 D29
L35 M38 L21 B24
J36 L36 M21 K23
H35 M32 J20 D21
H36 U31 K20 F18
MDA32 DQA_31
215RBKAGA11F QSA_5B QSA#6 MDB32 DQB_31
215RBKAGA11F QSB_5B QSB#6
P30 F33 H24 J17
P31 L27 F24 D11
MDA34 DQA_33 QSA_7B MDB34 DQB_33 QSB_7B
P32 D24
MDA35 DQA_34 QSA[7..0] (12) MDB35 DQB_34 QSB[7..0] (12)
P33 G24
MDA36 DQA_35 QSA0 MDB36 DQB_35 QSB0
J33 U38 F21 B30
MDA37 DQA_36 QSA_0 QSA1 MDB37 DQB_36 QSB_0 QSB1
K32 V33 F23 E29
J32 L37 G21 C25
J31 M36 H22 J23
V28 L32 H21 D23
V29 T31 H19 D18
W31 F34 F20 K17
T30 K27 E20 E11
MDA44 DQA_43 QSA_7 MDB44 DQB_43 QSB_7
R31 G18
R30 H18
MDA46 DQA_45 RASA# MDB46 DQB_45 RASB#
R29 B37 RASA# (12) E17 C15 RASB# (12)
MDA47 DQA_46 RASAb MDB47 DQB_46 RASBb
T28 D17
MDA48 DQA_47 CASA# MDB48 DQB_47 CASB#
F36 C37 CASA# (12) M19 C16 CASB# (12)
MDA49 DQA_48 CASAb MDB49 DQB_48 CASBb
F35 K18
MDA50 DQA_49 WEA# MDB50 DQB_49 WEB#
E35 C39 WEA# (12) L18 B17 WEB# (12)
MDA51 DQA_50 WEAb MDB51 DQB_50 WEBb
D33 M18
MDA52 DQA_51 CSA#0 MDB52 DQB_51 CSB#0
E32 D39 CSA#0 (12) L15 C18 CSB#0 (12)
MDA53 DQA_52 CSAb_0 MDB53 DQB_52 CSBb_0
D32 F37 M16 C19
MDA54 DQA_53 CSAb_1 MDB54 DQB_53 CSBb_1
G31 M15
MDA55 DQA_54 CKEA MDB55 DQB_54 CKEB
D31 B38 CKEA (12) K14 B16 CKEB (12)
MDA56 DQA_55 CKEA MDB56 DQB_55 CKEB
M28 F15
L28 G15
K28 D37 CLKA0 (12) H16 D15 CLKB0 (12)
+MVDDQ MDA59 DQA_58 CLKA0 +MVDDQ MDB59 DQB_58 CLKB0
M27 E37 CLKA#0 (12) H15 D14 CLKB#0 (12)
MDA60 DQA_59 CLKA0b MDB60 DQB_59 CLKB0b
J27 F12
J26 C35 CLKA1 (12) G12 F14 CLKB1 (12)
R137 MDA62 DQA_61 CLKA1 R158 MDB62 DQB_61 CLKB1
K26 C36 CLKA#1 (12) H13 E14 CLKB#1 (12)
B
40.2R MDA63 DQA_62 CLKA1b 40.2R MDB63 DQB_62 CLKB1b B
H25 H12
DQA_63 DQB_63
W29 D30
MVREFD_0 MVREFD_1
W28 E31
MVREFS_0 MVREFS_1
R138 C149 R159 C151
100R 100nF 100R 100nF
+MVDDQ
+MVDDQ
R148
40.2R
R150
40.2R
R149 C148
100R 100nF
R151 C150
100R 100nF
A A

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
C 105-A474XX-10 2
5 4 3 2 1
5 4 3 2 1
R-420 MEMORY CHANNELS C and D
D D
MAD[13..0]
(13) MAD[13..0]
MAC[13..0]
(13) MAC[13..0] (13) MDD[63..0]
U1F
(13) MDC[63..0]
U1E MDD0 AA2 Part 6 of 10 AU8 MAD0
MDD1 DQD_0 MAD_0 MAD1
AA3 AV6
MDC0 Part 5 of 10 MAC0 MDD2 DQD_1 MAD_1 MAD2
B10 P3 AB2 AV7
MDC1 DQC_0 MAC_0 MAC1 MDD3 DQD_2 MAD_2 MAD3
C10 N3 AB3 AV8
MDC2 DQC_1 MAC_1 MAC2 MDD4 DQD_3 Memory MAD_3 MAD4
B9 P2 AD3 AM2
C9 R2 AE2 Channel D AN2
MDC4 DQC_3 Memory MAC_3 MAC4 MDD6 DQD_5 MAD_5 MAD6
C7 E2 AE3 AN3
B6 Channel C F2 AF2 AM3
C6 F3 AB8 AP3
B5 E3 AB6 AP2
D8 G3 AB7 AV5
E8 G2 AD8 AV4
D6 N2 AE6 AV3
F6 M3 AE7 AR3
MDC12 DQC_11 MAC_11 MAC12 MDD14 DQD_13 MAD_13
E5 L3 AE4 AU2
MDC13 DQC_12 MAC_12 MAC13 MDD15 DQD_14 MAD_14
D4 H3 AE8 DQMD#[7..0] (13)
MDC14 DQC_13 MAC_13 MDD16 DQD_15
C4 K2 AF3
MDC15 DQC_14 MAC_14 MDD17 DQD_16 DQMD#0
G4 DQMC#[7..0] (13) AG2 AD2
MDC16 DQC_15 MDD18 DQD_17 DQMDb_0 DQMD#1
A5 AG3 AD4
MDC17 DQC_16 DQMC#0 MDD19 DQD_18 DQMDb_1 DQMD#2
C5 B7 AH2 AH3
MDC18 DQC_17 DQMCb_0 DQMC#1 MDD20 DQD_19 DQMDb_2 DQMD#3
A4 D5 AK2 AH4
B4 A3 AK3 AB12
C2 L8 AL2 AH13
C3 P6 AL3 AT5
D2 T12 AG8 AP13 QSD#[7..0] (13)
MDC23 DQC_22 DQMCb_5 DQMC#6 MDD25 DQD_24 DQMDb_7
D3 V3 AF6
MDC24 DQC_23 DQMCb_6 DQMC#7 MDD26 DQD_25 QSD#0
K10 AA6 QSC#[7..0] (13) AF5 AC2
MDC25 DQC_24 DQMCb_7 MDD27 DQD_26 QSD_0B QSD#1
J9 AH8 AC5
MDC26 DQC_25 QSC#0 MDD28 DQD_27 QSD_1B QSD#2
C J8 B8 AJ6 AJ3 C
MDC27 DQC_26 QSC_0B QSC#1 MDD29 DQD_28 QSD_2B QSD#3
K9 H5 AJ5 AH7
K6 C1 AJ4 AC10
L6 K7 AK7 AL9
M6 R8 AA12 215RBKAGA11F AT4
L5 T11 Y9 AP12
MDC32 DQC_31 QSC_5B QSC#6 MDD34 DQD_33 QSD_7B
N8 215RBKAGA11F V2 AB10 QSD[7..0] (13)
MDC33 DQC_32 QSC_6B QSC#7 MDD35 DQD_34
N7 Y4 AB11
MDC34 DQC_33 QSC_7B MDD36 DQD_35 QSD0
M5 QSC[7..0] (13) AD12 AC3
MDC35 DQC_34 MDD37 DQD_36 QSD_0 QSD1
N6 AE12 AC4
MDC36 DQC_35 QSC0 MDD38 DQD_37 QSD_1 QSD2
T4 C8 AE11 AJ2
MDC37 DQC_36 QSC_0 QSC1 MDD39 DQD_38 QSD_2 QSD3
T8 H6 AE10 AH6
T6 B2 AF9 AC9
U4 K8 AF10 AM9
N10 T7 AG12 AR4
P10 T10 AH11 AR11
MDC42 DQC_41 QSC_5 QSC6 MDD44 DQD_43 QSD_7
P9 U3 AK10
MDC43 DQC_42 QSC_6 QSC7 MDD45 DQD_44
R12 W5 AJ10
MDC44 DQC_43 QSC_7 MDD46 DQD_45 RASD#
U10 AK12 AW3 RASD# (13)
MDC45 DQC_44 MDD47 DQD_46 RASDb
U9 AJ13
MDC46 DQC_45 RASC# MDD48 DQD_47 CASD#
V12 M2 RASC# (13) AN6 AV2 CASD# (13)
MDC47 DQC_46 RASCb MDD49 DQD_48 CASDb
W12 AP6
MDC48 DQC_47 CASC# MDD50 DQD_49 WED#
R3 L2 CASC# (13) AP5 AU1 WED# (13)
MDC49 DQC_48 CASCb MDD51 DQD_50 WEDb
T2 AR6
MDC50 DQC_49 WEC# MDD52 DQD_51 CSD#0
T3 J3 WEC# (13) AU4 AT2 CSD#0 (13)
MDC51 DQC_50 WECb MDD53 DQD_52 CSDb_0
U2 AU5 AR2
MDC52 DQC_51 CSC#0 MDD54 DQD_53 CSDb_1
W2 J2 CSC#0 (13) AU6
MDC53 DQC_52 CSCb_0 MDD55 DQD_54 CKED
W3 H2 AU7 AU3 CKED (13)
MDC54 DQC_53 CSCb_1 MDD56 DQD_55 CKED
Y2 AM12
MDC55 DQC_54 CKEC MDD57 DQD_56
Y3 K3 CKEC (13) AM13
MDC56 DQC_55 CKEC MDD58 DQD_57
V6 AN13 AM4 CLKD0 (13)
MDC57 DQC_56 MDD59 DQD_58 CLKD0
V8 AN12 AM5 CLKD#0 (13)
MDC58 DQC_57 +MVDDQ MDD60 DQD_59 CLKD0b
W8 L4 CLKC0 (13) AP11
+MVDDQ MDC59 DQC_58 CLKC0 MDD61 DQD_60
W4 K4 CLKC#0 (13) AT10 AP4 CLKD1 (13)
MDC60 DQC_59 CLKC0b MDD62 DQD_61 CLKD1
AA4 AR10 AN4 CLKD#1 (13)
MDC61 DQC_60 R161 MDD63 DQD_62 CLKD1b
AB4 N4 CLKC1 (13) AT9
R160 MDC62 DQC_61 CLKC1 40.2R DQD_63
AA7 M4 CLKC#1 (13)
40.2R MDC63 DQC_62 CLKC1b RESET
AA8 B11 RESET (12,13)
B DQC_63 DRAM_RST TEST_MCLK B
Y10 J12
MVREFD_3 TEST_MCLK TEST_YCLK
W10 K12
MVREFS_3 TEST_YCLK
N11 C11
MVREFD_2 R162 MEMTEST
N12
MVREFS_2 100R C156
R133 C154 100nF
100R 100nF
R166 R156 R157 R163
243R 4.7K 4.7K 4.7K
DNI
+MVDDQ
+MVDDQ R154
40.2R
R153
40.2R
R155 C155
100R 100nF
R152 C153
100R 100nF
A A

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
C 105-A474XX-10 2
5 4 3 2 1
5 4 3 2 1
256 Mbit GDDRIII Channels A and B

(10) MDA[63..0]
MDA[63..0] Channel A (10) MDB[63..0]
MDB[63..0] Channel B
(10) MAA[13..0] (10) MAB[13..0]
U52 U53 U54 U55
MAA0 MAA13 M9 A7 MDA0 MAA13 M9 A7 MDA39 MAB0 MAB13 M9 A7 MDB0 MAB13 M9 A7 MDB45
MAA1 MAA12 BA1 DQ31 MDA1 MAA12 BA1 DQ31 MDA38 MAB1 MAB12 BA1 DQ31 MDB1 MAB12 BA1 DQ31 MDB46
M4 B8 M4 B8 M4 B8 M4 B8
MAA2 BA0 DQ30 MDA2 BA0 DQ30 MDA37 MAB2 BA0 DQ30 MDB2 BA0 DQ30 MDB44
A8 A8 A8 A8
MAA3 MAA11 DQ29 MDA3 MAA11 DQ29 MDA36 MAB3 MAB11 DQ29 MDB3 MAB11 DQ29 MDB47
M3 A9 M3 A9 M3 A9 M3 A9
MAA4 MAA10 A11 DQ28 MDA4 MAA10 A11 DQ28 MDA35 MAB4 MAB10 A11 DQ28 MDB4 MAB10 A11 DQ28 MDB42
L3 B12 L3 B12 L3 B12 L3 B12
L10 C11 L10 C11 L10 C11 L10 C11
M10 C12 M10 C12 M10 C12 M10 C12
MAA7 MAA7 A8/AP DQ25 MDA7 MAA7 A8/AP DQ25 MDA32 MAB7 MAB7 A8/AP DQ25 MDB7 MAB7 A8/AP DQ25 MDB43
M12 D12 M12 D12 M12 D12 M12 D12
M11 K1 M11 K1 M11 K1 M11 K1
L11 J2 L11 J2 L11 J2 L11 J2
K11 J1 K11 J1 K11 J1 K11 J1
D
MAA11 MAA3 A4 DQ21 MDA20 MAA3 A4 DQ21 MDA51 MAB11 MAB3 A4 DQ21 MDB22 MAB3 A4 DQ21 MDB34 D
K2 H1 K2 H1 K2 H1 K2 H1
L2 F1 L2 F1 L2 F1 L2 F1
M2 F2 M2 F2 M2 F2 M2 F2
MAA0 A1 DQ18 MDA16 MAA0 A1 DQ18 MDA54 MAB0 A1 DQ18 MDB16 MAB0 A1 DQ18 MDB39
M1 E1 M1 E1 M1 E1 M1 E1
A0 DQ17 MDA18 A0 DQ17 MDA55 A0 DQ17 MDB17 A0 DQ17 MDB38
E2 E2 E2 E2
WEA# RESET DQ16 MDA24 RESET DQ16 MDA47 WEB# RESET DQ16 MDB24 RESET DQ16 MDB61
(10) WEA# L5 E11 L5 E11 (10) WEB# L5 E11 L5 E11
CASA# RESET DQ15 MDA25 RESET DQ15 MDA46 CASB# RESET DQ15 MDB25 RESET DQ15 MDB63
(10) CASA# E12 E12 (10) CASB# E12 E12
RASA# DQ14 MDA26 DQ14 MDA45 RASB# DQ14 MDB26 DQ14 MDB62
(10) RASA# F11 F11 (10) RASB# F11 F11
RESET CLKA#0 DQ13 MDA27 CLKA#1 DQ13 MDA44 CSB#0 CLKB#0 DQ13 MDB27 CLKB#1 DQ13 MDB60
(11,13) RESET M7 F12 M7 F12 (10) CSB#0 M7 F12 M7 F12
CSA#0 CLKA0 CK DQ12 MDA28 CLKA1 CK DQ12 MDA43 CLKB0 CK DQ12 MDB28 CLKB1 CK DQ12 MDB59
(10) CSA#0 M6 H12 M6 H12 M6 H12 M6 H12
CK DQ11 MDA29 CK DQ11 MDA42 CK DQ11 MDB29 CK DQ11 MDB56
J12 J12 J12 J12
CKEA DQ10 MDA30 CKEA DQ10 MDA41 CKEB CKEB DQ10 MDB31 CKEB DQ10 MDB57
L6 J11 L6 J11 (10) CKEB L6 J11 L6 J11
CKEA CKE DQ9 MDA31 CKE DQ9 MDA40 CLKB0 CKE DQ9 MDB30 CKE DQ9 MDB58
(10) CKEA K12 K12 (10) CLKB0 K12 K12
CLKA0 DQ8 MDA15 DQ8 MDA56 CLKB1 DQ8 MDB15 DQ8 MDB55
(10) CLKA0 D1 D1 (10) CLKB1 D1 D1
CLKA1 CSA#0 DQ7 MDA14 CSA#0 DQ7 MDA57 CLKB#0 CSB#0 DQ7 MDB13 CSB#0 DQ7 MDB54
(10) CLKA1 L9 C1 L9 C1 (10) CLKB#0 L9 C1 L9 C1
CLKA#0 CS DQ6 MDA13 CS DQ6 MDA58 CLKB#1 CS DQ6 MDB14 CS DQ6 MDB53
(10) CLKA#0 C2 C2 (10) CLKB#1 C2 C2
CLKA#1 WEA# DQ5 MDA12 WEA# DQ5 MDA59 WEB# DQ5 MDB12 WEB# DQ5 MDB52
(10) CLKA#1 M8 B1 M8 B1 M8 B1 M8 B1
WE DQ4 MDA11 WE DQ4 MDA61 WE DQ4 MDB11 WE DQ4 MDB51
A4 A4 (10) DQMB#[7..0] A4 A4
RASA# DQ3 MDA10 RASA# DQ3 MDA60 RASB# DQ3 MDB10 RASB# DQ3 MDB50
(10) DQMA#[7..0] L4 A5 L4 A5 L4 A5 L4 A5
RAS DQ2 MDA9 RAS DQ2 MDA63 RAS DQ2 MDB8 RAS DQ2 MDB49
B5 B5 B5 B5
CASA# DQ1 MDA8 CASA# DQ1 MDA62 DQMB#0 CASB# DQ1 MDB9 CASB# DQ1 MDB48
M5 A6 M5 A6 M5 A6 M5 A6
DQMA#0 CAS DQ0 CAS DQ0 DQMB#1 CAS DQ0 CAS DQ0
DQMA#1 B3 B3 DQMB#2 B3 B3
DQMA#2 DQMA#0 VDDQ DQMA#4 VDDQ DQMB#3 DQMB#0 VDDQ DQMB#5 VDDQ
B11 B4 B11 B4 B11 B4 B11 B4
DQMA#3 DQMA#2 DM3 VDDQ#B4 DQMA#6 DM3 VDDQ#B4 DQMB#4 DQMB#2 DM3 VDDQ#B4 DQMB#4 DM3 VDDQ#B4
H2 B6 H2 B6 H2 B6 H2 B6
H11 B7 H11 B7 H11 B7 H11 B7
B2 B9 B2 B9 B2 B9 B2 B9
DQMA#6 DM0 VDDQ#B9 +MVDDQ DM0 VDDQ#B9 +MVDDQ DQMB#7 DM0 VDDQ#B9 +MVDDQ DM0 VDDQ#B9 +MVDDQ
B10 B10 B10 B10
DQMA#7 VDDQ#B10 VDDQ#B10 VDDQ#B10 VDDQ#B10
(10) QSA#[7..0] G3 G3 (10) QSB#[7..0] G3 G3
QSA#0 VDDQ#G3 QSA#4 VDDQ#G3 QSB#0 VDDQ#G3 QSB#5 VDDQ#G3
A12 G10 A12 G10 A12 G10 A12 G10
QSA#2 WDQS3 VDDQ#G10 QSA#6 WDQS3 VDDQ#G10 QSB#2 WDQS3 VDDQ#G10 QSB#4 WDQS3 VDDQ#G10
G1 E3 G1 E3 G1 E3 G1 E3
QSA#0 QSA#3 WDQS2 VDDQ#E3 QSA#5 WDQS2 VDDQ#E3 QSB#0 QSB#3 WDQS2 VDDQ#E3 QSB#7 WDQS2 VDDQ#E3
G12 E10 G12 E10 G12 E10 G12 E10
QSA#1 QSA#1 WDQS1 VDDQ#E10 QSA#7 WDQS1 VDDQ#E10 QSB#1 QSB#1 WDQS1 VDDQ#E10 QSB#6 WDQS1 VDDQ#E10
A1 F3 A1 F3 A1 F3 A1 F3
QSA#2 WDQS0 VDDQ#F3 WDQS0 VDDQ#F3 QSB#2 WDQS0 VDDQ#F3 WDQS0 VDDQ#F3
F10 F10 F10 F10
QSA#3 VDDQ#F10 VDDQ#F10 QSB#3 VDDQ#F10 VDDQ#F10
H3 H3 H3 H3
QSA#4 QSA0 VDDQ#H3 QSA4 VDDQ#H3 QSB#4 QSB0 VDDQ#H3 QSB5 VDDQ#H3
A11 H10 A11 H10 A11 H10 A11 H10
QSA#5 QSA2 RDQS3 VDDQ#H10 QSA6 RDQS3 VDDQ#H10 QSB#5 QSB2 RDQS3 VDDQ#H10 QSB4 RDQS3 VDDQ#H10
G2 J3 G2 J3 G2 J3 G2 J3
QSA#6 QSA3 RDQS2 VDDQ#J3 QSA5 RDQS2 VDDQ#J3 QSB#6 QSB3 RDQS2 VDDQ#J3 QSB7 RDQS2 VDDQ#J3
C G11 J10 G11 J10 G11 J10 G11 J10 C
QSA#7 QSA1 RDQS1 VDDQ#J10 QSA7 RDQS1 VDDQ#J10 QSB#7 QSB1 RDQS1 VDDQ#J10 QSB6 RDQS1 VDDQ#J10
(10) QSA[7..0] A2 C6 A2 C6 A2 C6 A2 C6
RDQS0 VDD +MVDDC RDQS0 VDD +MVDDC RDQS0 VDD +MVDDC RDQS0 VDD +MVDDC
C7 C7 (10) QSB[7..0] C7 C7
VDD#C7 VDD#C7 VDD#C7 VDD#C7
D3 D3 D3 D3
QSA0 VDD#D3 VDD#D3 VDD#D3 VDD#D3
D10 D10 D10 D10
QSA1 VDD#D10 VDD#D10 QSB0 VDD#D10 VDD#D10
E5 K3 E5 K3 E5 K3 E5 K3
QSA2 NC/VSS VDD#K3 NC/VSS VDD#K3 QSB1 NC/VSS VDD#K3 NC/VSS VDD#K3
E6 K6 E6 K6 E6 K6 E6 K6
QSA3 NC/VSS#E6 VDD#K6 NC/VSS#E6 VDD#K6 QSB2 NC/VSS#E6 VDD#K6 NC/VSS#E6 VDD#K6
E7 K7 E7 K7 E7 K7 E7 K7
E8 K10 E8 K10 E8 K10 E8 K10
F5 F5 F5 F5
QSA6 NC/VSS#F5 NC/VSS#F5 QSB5 NC/VSS#F5 NC/VSS#F5
F6 E4 F6 E4 F6 E4 F6 E4
QSA7 NC/VSS#F6 VSSQ NC/VSS#F6 VSSQ QSB6 NC/VSS#F6 VSSQ NC/VSS#F6 VSSQ
F7 C3 F7 C3 F7 C3 F7 C3
NC/VSS#F7 VSSQ#C3 NC/VSS#F7 VSSQ#C3 QSB7 NC/VSS#F7 VSSQ#C3 NC/VSS#F7 VSSQ#C3
F8 C4 F8 C4 F8 C4 F8 C4
NC/VSS#F8 VSSQ#C4 NC/VSS#F8 VSSQ#C4 NC/VSS#F8 VSSQ#C4 NC/VSS#F8 VSSQ#C4
G5 C5 G5 C5 G5 C5 G5 C5
+MVDDQ NC/VSS#G5 VSSQ#C5 NC/VSS#G5 VSSQ#C5 NC/VSS#G5 VSSQ#C5 NC/VSS#G5 VSSQ#C5
G6 C8 G6 C8 G6 C8 G6 C8
NC/VSS#G6 VSSQ#C8 NC/VSS#G6 VSSQ#C8 NC/VSS#G6 VSSQ#C8 NC/VSS#G6 VSSQ#C8
G7 C9 G7 C9 G7 C9 G7 C9
60.4R R274 NC/VSS#G7 VSSQ#C9 NC/VSS#G7 VSSQ#C9 +MVDDQ NC/VSS#G7 VSSQ#C9 NC/VSS#G7 VSSQ#C9
(10) CLKA0 G8 C10 G8 C10 G8 C10 G8 C10
H5 D5 H5 D5 H5 D5 H5 D5
NC/VSS#H5 VSSQ#D5 NC/VSS#H5 VSSQ#D5 60.4R R260 NC/VSS#H5 VSSQ#D5 NC/VSS#H5 VSSQ#D5
H6 D8 H6 D8 (10) CLKB0 H6 D8 H6 D8
NC/VSS#H6 VSSQ#D8 NC/VSS#H6 VSSQ#D8 NC/VSS#H6 VSSQ#D8 NC/VSS#H6 VSSQ#D8
H7 E9 H7 E9 H7 E9 H7 E9
60.4R R275 NC/VSS#H7 VSSQ#E9 NC/VSS#H7 VSSQ#E9 NC/VSS#H7 VSSQ#E9 NC/VSS#H7 VSSQ#E9
(10) CLKA#0 H8 F4 H8 F4 H8 F4 H8 F4
NC/VSS#H8 VSSQ#F4 NC/VSS#H8 VSSQ#F4 NC/VSS#H8 VSSQ#F4 NC/VSS#H8 VSSQ#F4
F9 F9 F9 F9
VSSQ#F9 VSSQ#F9 60.4R R261 VSSQ#F9 VSSQ#F9
G4 G4 (10) CLKB#0 G4 G4
+MVDDQ VSSQ#G4 VSSQ#G4 VSSQ#G4 VSSQ#G4
G9 G9 G9 G9
VSSQ#G9 VSSQ#G9 VSSQ#G9 VSSQ#G9
K8 H4 K8 H4 K8 H4 K8 H4
60.4R R276 RFU1 VSSQ#H4 RFU1 VSSQ#H4 +MVDDQ RFU1 VSSQ#H4 RFU1 VSSQ#H4
(10) CLKA1 K5 H9 K5 H9 K5 H9 K5 H9
RFU2 VSSQ#H9 RFU2 VSSQ#H9 RFU2 VSSQ#H9 RFU2 VSSQ#H9
D2 J4 D2 J4 D2 J4 D2 J4
RFU3 VSSQ#J4 RFU3 VSSQ#J4 60.4R R262 RFU3 VSSQ#J4 RFU3 VSSQ#J4
D11 J9 D11 J9 (10) CLKB1 D11 J9 D11 J9
+MVDDQ RFU4 VSSQ#J9 +MVDDQ RFU4 VSSQ#J9 +MVDDQ RFU4 VSSQ#J9 +MVDDQ RFU4 VSSQ#J9
L7 A3 L7 A3 L7 A3 L7 A3
60.4R R278 RFU5 VSSQ#A3 RFU5 VSSQ#A3 RFU5 VSSQ#A3 RFU5 VSSQ#A3
(10) CLKA#1 A10 A10 A10 A10
R938 243R VSSQ#A10 R939 243R VSSQ#A10 R940 243R VSSQ#A10 R941 243R VSSQ#A10
D4 D4 D4 D4
VSS VSS 60.4R R263 VSS VSS
L8 D6 L8 D6 (10) CLKB#1 L8 D6 L8 D6
R277 ZQ VSS#D6 R270 ZQ VSS#D6 R279 ZQ VSS#D6 R272 ZQ VSS#D6
D7 D7 D7 D7
2.37K VSS#D7 2.37K VSS#D7 2.37K VSS#D7 2.37K VSS#D7
D9 D9 D9 D9
VSS#D9 VSS#D9 VSS#D9 VSS#D9
J5 J5 J5 J5
VSS#J5 VSS#J5 VSS#J5 VSS#J5
L1 J6 L1 J6 L1 J6 L1 J6
C208 VREF VSS#J6 C200 VREF VSS#J6 C210 VREF VSS#J6 C201 VREF VSS#J6
J7 J7 J7 J7
+MVDDQ R281 100nF VSS#J7 R271 100nF VSS#J7 +MVDDQ R283 100nF VSS#J7 R273 100nF VSS#J7
J8 J8 J8 J8
B
5.49K VSS#J8 5.49K VSS#J8 5.49K VSS#J8 5.49K VSS#J8 B
K4 K4 K4 K4
VSS#K4 +MVDDQ VSS#K4 VSS#K4 VSS#K4
L12 K9 L12 K9 L12 K9 L12 K9
VREF#L12 VSS#K9 VREF#L12 VSS#K9 VREF#L12 VSS#K9 +MVDDQ VREF#L12 VSS#K9
R315 R319
2.37K HYB18T256321F-2.0 HYB18T256321F-2.0 2.37K HYB18T256321F-2.0 HYB18T256321F-2.0
R317
2.37K R321
C199 C197 2.37K
R316 100nF R320 100nF
5.49K C198 5.49K
R318 100nF C196
5.49K R322 100nF
+MVDDQ +MVDDQ +MVDDQ 5.49K
+MVDDQ
C1844 C1845 C1846 C1847 C1848 C1849 C1850 C1851 C1852 C1853 C1854 C1855 C1856 C1857 C1858 C1859 C1860 C1861 C1862 C1863 C1864 C1865 C1866 C1867
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF C1868 C1869 C1870 C1871 C1872 C1873 C1874 C1875
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
+MVDDC +MVDDC +MVDDC

+MVDDC
+MVDDC +MVDDQ +MVDDC +MVDDQ +MVDDC +MVDDQ

+MVDDC +MVDDQ
C1908 C1909 C1910 C1911 C1912 C1913 C1914 C1915 C1916 C1917 C1918 C1919
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF C1920 C1921 C1922 C1923
100nF 100nF 100nF 100nF
C1924 C1925 C1926 C1927 C1928 C1929
10uf 10uf 10uf 10uf 10uf 10uf C1930 C1931
A 10uf 10uf A
C1932 C1933 C1934 C1935 C1936 C1937 C1938 C1939 C1940 C1941 C1942 C1943
1nF 1nF 1nF 1nF

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
C 105-A474XX-10 2
5 4 3 2 1
5 4 3 2 1
256 Mbit GDDRIII Channels A and B Channel C Channel D

MDC[63..0] MDD[63..0]
(11) MDC[63..0] (11) MDD[63..0]
(11) MAC[13..0] U56 U57 (11) MAD[13..0] U58 U59
MAC13 M9 A7 MDC0 MAC13 M9 A7 MDC63 MAD13 M9 A7 MDD0 MAD13 M9 A7 MDD39
MAC0 MAC12 BA1 DQ31 MDC1 MAC12 BA1 DQ31 MDC61 MAD0 MAD12 BA1 DQ31 MDD1 MAD12 BA1 DQ31 MDD38
M4 B8 M4 B8 M4 B8 M4 B8
MAC1 BA0 DQ30 MDC2 BA0 DQ30 MDC62 MAD1 BA0 DQ30 MDD2 BA0 DQ30 MDD37
A8 A8 A8 A8
MAC2 MAC11 DQ29 MDC3 MAC11 DQ29 MDC60 MAD2 MAD11 DQ29 MDD3 MAD11 DQ29 MDD36
M3 A9 M3 A9 M3 A9 M3 A9
MAC3 MAC10 A11 DQ28 MDC4 MAC10 A11 DQ28 MDC58 MAD3 MAD10 A11 DQ28 MDD4 MAD10 A11 DQ28 MDD35
L3 B12 L3 B12 L3 B12 L3 B12
L10 C11 L10 C11 L10 C11 L10 C11
M10 C12 M10 C12 M10 C12 M10 C12
MAC6 MAC7 A8/AP DQ25 MDC7 MAC7 A8/AP DQ25 MDC57 MAD6 MAD7 A8/AP DQ25 MDD7 MAD7 A8/AP DQ25 MDD32
M12 D12 M12 D12 M12 D12 M12 D12
M11 K1 M11 K1 M11 K1 M11 K1
L11 J2 L11 J2 L11 J2 L11 J2
K11 J1 K11 J1 K11 J1 K11 J1
K2 H1 K2 H1 K2 H1 K2 H1
L2 F1 L2 F1 L2 F1 L2 F1
D
MAC12 MAC1 A2 DQ19 MDC26 MAC1 A2 DQ19 MDC44 MAD12 MAD1 A2 DQ19 MDD25 MAD1 A2 DQ19 MDD59 D
M2 F2 M2 F2 M2 F2 M2 F2
M1 E1 M1 E1 M1 E1 M1 E1
A0 DQ17 MDC25 A0 DQ17 MDC45 A0 DQ17 MDD26 A0 DQ17 MDD57
E2 E2 E2 E2
WEC# RESET DQ16 MDC8 RESET DQ16 MDC55 WED# RESET DQ16 MDD16 RESET DQ16 MDD46
(11) WEC# L5 E11 L5 E11 (11) WED# L5 E11 L5 E11
CASC# RESET DQ15 MDC9 RESET DQ15 MDC54 CASD# RESET DQ15 MDD17 RESET DQ15 MDD47
(11) CASC# E12 E12 (11) CASD# E12 E12
RASC# DQ14 MDC10 DQ14 MDC53 RASD# DQ14 MDD18 DQ14 MDD44
(11) RASC# F11 F11 (11) RASD# F11 F11
RESET CLKC#0 DQ13 MDC11 CLKC#1 DQ13 MDC52 CSD#0 CLKD#0 DQ13 MDD19 CLKD#1 DQ13 MDD45
(11,12) RESET M7 F12 M7 F12 (11) CSD#0 M7 F12 M7 F12
CSC#0 CLKC0 CK DQ12 MDC14 R300 CLKC1 CK DQ12 MDC51 CLKD0 CK DQ12 MDD20 CLKD1 CK DQ12 MDD43
(11) CSC#0 M6 H12 M6 H12 M6 H12 M6 H12
CK DQ11 MDC13 CK DQ11 MDC50 CK DQ11 MDD21 CK DQ11 MDD42
J12 J12 J12 J12
CKEC DQ10 MDC12 CKEC DQ10 MDC49 CKED CKED DQ10 MDD23 CKED DQ10 MDD41
L6 J11 L6 J11 (11) CKED L6 J11 L6 J11
CKEC CKE DQ9 MDC15 CKE DQ9 MDC48 CLKD0 CKE DQ9 MDD22 CKE DQ9 MDD40
(11) CKEC K12 K12 (11) CLKD0 K12 K12
CLKC0 DQ8 MDC22 DQ8 MDC39 CLKD1 DQ8 MDD15 DQ8 MDD55
(11) CLKC0 D1 D1 (11) CLKD1 D1 D1
CLKC1 CSC#0 DQ7 MDC23 CSC#0 DQ7 MDC38 CLKD#0 CSD#0 DQ7 MDD14 CSD#0 DQ7 MDD54
(11) CLKC1 L9 C1 L9 C1 (11) CLKD#0 L9 C1 L9 C1
CLKC#0 CS DQ6 MDC20 CS DQ6 MDC37 CLKD#1 CS DQ6 MDD13 CS DQ6 MDD53
(11) CLKC#0 C2 C2 (11) CLKD#1 C2 C2
CLKC#1 WEC# DQ5 MDC21 WEC# DQ5 MDC36 WED# DQ5 MDD12 WED# DQ5 MDD52
(11) CLKC#1 M8 B1 M8 B1 M8 B1 M8 B1
WE DQ4 MDC19 WE DQ4 MDC35 WE DQ4 MDD10 WE DQ4 MDD51
A4 A4 (11) DQMD#[7..0] A4 A4
RASC# DQ3 MDC17 RASC# DQ3 MDC34 RASD# DQ3 MDD8 RASD# DQ3 MDD50
(11) DQMC#[7..0] L4 A5 L4 A5 L4 A5 L4 A5
RAS DQ2 MDC18 RAS DQ2 MDC33 RAS DQ2 MDD11 RAS DQ2 MDD49
B5 B5 B5 B5
CASC# DQ1 MDC16 CASC# DQ1 MDC32 DQMD#0 CASD# DQ1 MDD9 CASD# DQ1 MDD48
M5 A6 M5 A6 M5 A6 M5 A6
DQMC#0 CAS DQ0 CAS DQ0 DQMD#1 CAS DQ0 CAS DQ0
DQMC#1 B3 B3 DQMD#2 B3 B3
DQMC#2 DQMC#0 VDDQ DQMC#7 VDDQ DQMD#3 DQMD#0 VDDQ DQMD#4 VDDQ
B11 B4 B11 B4 B11 B4 B11 B4
DQMC#3 DQMC#3 DM3 VDDQ#B4 DQMC#5 DM3 VDDQ#B4 DQMD#4 DQMD#3 DM3 VDDQ#B4 DQMD#7 DM3 VDDQ#B4
H2 B6 H2 B6 H2 B6 H2 B6
H11 B7 H11 B7 H11 B7 H11 B7
B2 B9 B2 B9 B2 B9 B2 B9
DQMC#6 DM0 VDDQ#B9 +MVDDQ DM0 VDDQ#B9 +MVDDQ DQMD#7 DM0 VDDQ#B9 +MVDDQ DM0 VDDQ#B9 +MVDDQ
B10 B10 (11) QSD#[7..0] B10 B10
DQMC#7 VDDQ#B10 VDDQ#B10 VDDQ#B10 VDDQ#B10
(11) QSC#[7..0] G3 G3 G3 G3
QSC#0 VDDQ#G3 QSC#7 VDDQ#G3 QSD#0 VDDQ#G3 QSD#4 VDDQ#G3
A12 G10 A12 G10 A12 G10 A12 G10
QSC#3 WDQS3 VDDQ#G10 QSC#5 WDQS3 VDDQ#G10 QSD#0 QSD#3 WDQS3 VDDQ#G10 QSD#7 WDQS3 VDDQ#G10
G1 E3 G1 E3 G1 E3 G1 E3
QSC#0 QSC#1 WDQS2 VDDQ#E3 QSC#6 WDQS2 VDDQ#E3 QSD#1 QSD#2 WDQS2 VDDQ#E3 QSD#5 WDQS2 VDDQ#E3
G12 E10 G12 E10 G12 E10 G12 E10
QSC#1 QSC#2 WDQS1 VDDQ#E10 QSC#4 WDQS1 VDDQ#E10 QSD#2 QSD#1 WDQS1 VDDQ#E10 QSD#6 WDQS1 VDDQ#E10
A1 F3 A1 F3 A1 F3 A1 F3
QSC#2 WDQS0 VDDQ#F3 WDQS0 VDDQ#F3 QSD#3 WDQS0 VDDQ#F3 WDQS0 VDDQ#F3
F10 F10 F10 F10
QSC#3 VDDQ#F10 VDDQ#F10 QSD#4 VDDQ#F10 VDDQ#F10
H3 H3 H3 H3
QSC#4 QSC0 VDDQ#H3 QSC7 VDDQ#H3 QSD#5 QSD0 VDDQ#H3 QSD4 VDDQ#H3
A11 H10 A11 H10 A11 H10 A11 H10
QSC#5 QSC3 RDQS3 VDDQ#H10 QSC5 RDQS3 VDDQ#H10 QSD#6 QSD3 RDQS3 VDDQ#H10 QSD7 RDQS3 VDDQ#H10
G2 J3 G2 J3 (11) QSD[7..0] G2 J3 G2 J3
QSC#6 QSC1 RDQS2 VDDQ#J3 QSC6 RDQS2 VDDQ#J3 QSD#7 QSD2 RDQS2 VDDQ#J3 QSD5 RDQS2 VDDQ#J3
G11 J10 G11 J10 G11 J10 G11 J10
QSC#7 QSC2 RDQS1 VDDQ#J10 QSC4 RDQS1 VDDQ#J10 QSD1 RDQS1 VDDQ#J10 QSD6 RDQS1 VDDQ#J10
A2 C6 A2 C6 A2 C6 A2 C6
RDQS0 VDD +MVDDC RDQS0 VDD +MVDDC QSD0 RDQS0 VDD +MVDDC RDQS0 VDD +MVDDC
C
(11) QSC[7..0] C7 C7 C7 C7 C
VDD#C7 VDD#C7 QSD1 VDD#C7 VDD#C7
D3 D3 D3 D3
VDD#D3 VDD#D3 QSD2 VDD#D3 VDD#D3
D10 D10 D10 D10
QSC0 VDD#D10 VDD#D10 QSD3 VDD#D10 VDD#D10
E5 K3 E5 K3 E5 K3 E5 K3
QSC1 NC/VSS VDD#K3 NC/VSS VDD#K3 QSD4 NC/VSS VDD#K3 NC/VSS VDD#K3
E6 K6 E6 K6 E6 K6 E6 K6
QSC2 NC/VSS#E6 VDD#K6 NC/VSS#E6 VDD#K6 QSD5 NC/VSS#E6 VDD#K6 NC/VSS#E6 VDD#K6
E7 K7 E7 K7 E7 K7 E7 K7
E8 K10 E8 K10 E8 K10 E8 K10
F5 F5 F5 F5
QSC5 NC/VSS#F5 NC/VSS#F5 NC/VSS#F5 NC/VSS#F5
F6 E4 F6 E4 F6 E4 F6 E4
QSC6 NC/VSS#F6 VSSQ NC/VSS#F6 VSSQ NC/VSS#F6 VSSQ NC/VSS#F6 VSSQ
F7 C3 F7 C3 F7 C3 F7 C3
QSC7 NC/VSS#F7 VSSQ#C3 NC/VSS#F7 VSSQ#C3 +MVDDQ NC/VSS#F7 VSSQ#C3 NC/VSS#F7 VSSQ#C3
F8 C4 F8 C4 F8 C4 F8 C4
NC/VSS#F8 VSSQ#C4 NC/VSS#F8 VSSQ#C4 NC/VSS#F8 VSSQ#C4 NC/VSS#F8 VSSQ#C4
G5 C5 G5 C5 G5 C5 G5 C5
NC/VSS#G5 VSSQ#C5 NC/VSS#G5 VSSQ#C5 60.4R NC/VSS#G5 VSSQ#C5 NC/VSS#G5 VSSQ#C5
G6 C8 G6 C8 (11) CLKD0 G6 C8 G6 C8
+MVDDQ NC/VSS#G6 VSSQ#C8 NC/VSS#G6 VSSQ#C8 NC/VSS#G6 VSSQ#C8 NC/VSS#G6 VSSQ#C8
G7 C9 G7 C9 G7 C9 G7 C9
G8 C10 G8 C10 G8 C10 G8 C10
60.4R R296 NC/VSS#G8 VSSQ#C10 NC/VSS#G8 VSSQ#C10 NC/VSS#G8 VSSQ#C10 NC/VSS#G8 VSSQ#C10
(11) CLKC0 H5 D5 H5 D5 H5 D5 H5 D5
NC/VSS#H5 VSSQ#D5 NC/VSS#H5 VSSQ#D5 60.4R R301 NC/VSS#H5 VSSQ#D5 NC/VSS#H5 VSSQ#D5
H6 D8 H6 D8 (11) CLKD#0 H6 D8 H6 D8
NC/VSS#H6 VSSQ#D8 NC/VSS#H6 VSSQ#D8 NC/VSS#H6 VSSQ#D8 NC/VSS#H6 VSSQ#D8
H7 E9 H7 E9 H7 E9 H7 E9
NC/VSS#H7 VSSQ#E9 NC/VSS#H7 VSSQ#E9 NC/VSS#H7 VSSQ#E9 NC/VSS#H7 VSSQ#E9
H8 F4 H8 F4 H8 F4 H8 F4
60.4R R297 NC/VSS#H8 VSSQ#F4 NC/VSS#H8 VSSQ#F4 +MVDDQ NC/VSS#H8 VSSQ#F4 NC/VSS#H8 VSSQ#F4
(11) CLKC#0 F9 F9 F9 F9
VSSQ#F9 VSSQ#F9 VSSQ#F9 VSSQ#F9
G4 G4 G4 G4
VSSQ#G4 VSSQ#G4 60.4R R302 VSSQ#G4 VSSQ#G4
G9 G9 (11) CLKD1 G9 G9
+MVDDQ VSSQ#G9 VSSQ#G9 VSSQ#G9 VSSQ#G9
K8 H4 K8 H4 K8 H4 K8 H4
RFU1 VSSQ#H4 RFU1 VSSQ#H4 RFU1 VSSQ#H4 RFU1 VSSQ#H4
K5 H9 K5 H9 K5 H9 K5 H9
60.4R R298 RFU2 VSSQ#H9 RFU2 VSSQ#H9 RFU2 VSSQ#H9 RFU2 VSSQ#H9
(11) CLKC1 D2 J4 D2 J4 D2 J4 D2 J4
RFU3 VSSQ#J4 RFU3 VSSQ#J4 60.4R R303 RFU3 VSSQ#J4 RFU3 VSSQ#J4
D11 J9 D11 J9 (11) CLKD#1 D11 J9 D11 J9
+MVDDQ RFU4 VSSQ#J9 +MVDDQ RFU4 VSSQ#J9 +MVDDQ RFU4 VSSQ#J9 +MVDDQ RFU4 VSSQ#J9
L7 A3 L7 A3 L7 A3 L7 A3
RFU5 VSSQ#A3 RFU5 VSSQ#A3 RFU5 VSSQ#A3 RFU5 VSSQ#A3
A10 A10 A10 A10
60.4R R299 R934 243R VSSQ#A10 R935 243R VSSQ#A10 R936 243R VSSQ#A10 R937 243R VSSQ#A10
(11) CLKC#1 D4 D4 D4 D4
VSS VSS VSS VSS
L8 D6 L8 D6 L8 D6 L8 D6
R285 ZQ VSS#D6 R292 ZQ VSS#D6 R288 ZQ VSS#D6 R294 ZQ VSS#D6
D7 D7 D7 D7
2.37K VSS#D7 2.37K VSS#D7 2.37K VSS#D7 2.37K VSS#D7
D9 D9 D9 D9
VSS#D9 VSS#D9 VSS#D9 VSS#D9
J5 J5 J5 J5
VSS#J5 VSS#J5 VSS#J5 VSS#J5
L1 J6 L1 J6 L1 J6 L1 J6
C256 VREF VSS#J6 C308 VREF VSS#J6 R291 C257 VREF VSS#J6 C309 VREF VSS#J6
J7 J7 J7 J7
R289 100nF VSS#J7 R293 100nF VSS#J7 100nF VSS#J7 R295 100nF VSS#J7
J8 J8 J8 J8
+MVDDQ 5.49K VSS#J8 5.49K VSS#J8 +MVDDQ 5.49K VSS#J8 5.49K VSS#J8
K4 K4 K4 K4
VSS#K4 VSS#K4 VSS#K4 VSS#K4
L12 K9 L12 K9 L12 K9 L12 K9
B VREF#L12 VSS#K9 VREF#L12 VSS#K9 VREF#L12 VSS#K9 VREF#L12 VSS#K9 B
+MVDDQ +MVDDQ
R323 HYB18T256321F-2.0 HYB18T256321F-2.0 R327 HYB18T256321F-2.0 HYB18T256321F-2.0
2.37K 2.37K
R325 R329
C195 2.37K C193 2.37K
R324 100nF R328 100nF
5.49K 5.49K
C194 C192
R326 100nF R330 100nF
5.49K 5.49K
+MVDDQ +MVDDQ +MVDDQ
+MVDDQ
+MVDDC +MVDDC +MVDDC

+MVDDC
+MVDDC +MVDDQ +MVDDC +MVDDQ +MVDDC +MVDDQ

+MVDDC +MVDDQ
C1788 C1789 C1790 C1791 C1792 C1793 C1794 C1795 C1796 C1797 C1798 C1799
100nF 100nF 100nF 100nF
C1804 C1805 C1806 C1807 C1808 C1809
10uf 10uf 10uf 10uf 10uf 10uf C1810 C1811
A 10uf 10uf A
C1812 C1813 C1814 C1815 C1816 C1817 C1818 C1819 C1820 C1821 C1822 C1823
1nF 1nF 1nF 1nF
<Variant Name>

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
C 105-A474XX-10 2
5 4 3 2 1
1 2 3 4 5 6 7 8
GPIO[6..0] OPTION STRAPS

(4) GPIO[6..0]
+3.3V_BUS R423 Shared Straps REV. 0.0
STRAPS PIN DESCRIPTION DEFAULT
GPIO0 R331 10K Transmitter Power Savings Enable +3.3V_BUS

FEATURE0 GPIO(0) 0: 50% Tx output swing for mobile mode 0
R332 10K DNI 1: full Tx output swing
(Desktop must have an external pullup) R584 10K
GPIO1 R333 10K R580 10K
Overlap pads to save space Transmitter De-emphasis Enable R576 10K
R334 10K DNI FEATURE1 GPIO(1) 0: Tx de-emphasis disabled for mobile mode
and to prevent assembly of 1: Tx de-emphasis enabled 0
(Desktop must have an external pullup)
both resistors. GPIO2 R205 10K DNI PCIE mode: DC_Strap4 (4)
PAL/NTSC (4)
A
PCIE_MODE GPIO(3:2) 00: PCI Express 1.0A mode DC_Strap2 (4) A
4
R206 10K (ATI Internal) 01: Kyrene-compatible mode
10: PCI Express 1.0 mode 00 SW1A
Layout GPIO3 R335 10K DNI 11: Short-circuit internal loopback and PCI Express 1.0A mode R577 10K DNI(STINGRAY) DIP_SWX2
R581 10K DNI
1
R336 10K R585 10K DNI
REVERSE_LANES GPIO(4) REVERSE_LANES 0
0: normal mode
1: reverse mode
Ground High logic voltage GPIO4 R347 10K
Force chip to get to compliance state quickly for Tester purposes
R348 10K DNI FORCE _COMPLIANCE GPIO(5) 0: Normal operation
Signal 1: Force to compliance state
0
GPIO5 R349 10K DNI
R350 10K PLL_BW GPIO(6) 0: Full PLL Bandwidth 0

(ATI Internal) 1: Reduced PLL bandwidth
GPIO6 R351 10K DNI
R352 10K DEBUG_ACCESS GPIO(8) Strap to set the debug muxes to bring out DEBUG signals even if registers are inaccessible 0 +3.3V_BUS
0: Disable debug access
GPIO[13..8] 1: Enable debug access
(4,8) GPIO[13..8]
R582 10K
GPIO8 R345 10K DNI R578 10K
ROMIDCFG(3:0) GPIO(9,13:11) If no ROM attached, controls chip IDis. If rom attached identifies ROM type. 1100 R574 10K
R346 10K GPIO[9,13,12,11]
000x - No ROM,CHG_ID=00
001x - No ROM, CHG_ID=01 (4) DEMUX_SEL
GPIO9 R343 10K 010x - No ROM, CHG_ID=10 (4,21) DC_Strap3 DC_Strap1
011x - No ROM, CHG_ID=11 (4) GPIO10
R344 10K DNI
1001 - 1M Serial AT25F1024 ROM (Atmel)
1010 - 1M Serial AT45DB011 ROM (Atmel) R575 10K DNI
1011 - 1M Serial M25P10 ROM (ST) R579 10K DNI
GPIO11 R337 10K DNI 1100 - 512K Serial M25P05 ROM (ST) R583 10K DNI
1101 - 1M Serial SST45LF010 ROM (SST)
B R338 10K 1M Serial W45B512 ROM (WinBond) B
512K Serial W45B012 ROM (WinBond)
GPIO12 R339 10K DNI 1110 - 1M Serial SST25VF010 ROM (SST)
R340 10K
512K Serial SST25VF512 ROM (SST)
1111 - 1M NX25F011B ROM (NexFlash)
WARNING
GPIO13 R341 10K Chip IDs:
Chip ID is based on substrate fuses and CHG_ID strap (which comes from ROM if used, Some of those straps must be connected to +VDD_1.8V
R342 10K DNI or pin straps if no ROM is connected): CHG_ID = ROMIDCFG[2:1] = GPIO[13:12]
if ZV_LCDATA bus is set to 1.8 V.
MULTIFUNC(1:0) H2SYNC, V2SYNC Multi-function device select 10
R353 10K DNI 00 - single function device.
(4,17) VSYNC_DAC2
01 - two function device.
R354 10K 10 - two function device.
11 - two function device.
R355 10K
(4,17) HSYNC_DAC2
R356 10K DNI VIP_DEVICE VSYNC Indicates if any slave VIP host devices drove this in low during reset.
0 - Slave VIP host port devices present 1
1 - No slave VIP host port devices reporting presence during reset
R359 10K DNI RFU HSYNC RFU 0

(2,4,16) VSYNC_DAC1
0 - Normal
R360 10K 1 - Not used
+VDD_1.8V
R357 10K DNI

(2,4,16) HSYNC_DAC1
R358 10K R570 10K
R423 Dedicated Straps REV. 0.0
ZV_VOLTAGE_SEL0 DVOVMODE_0 DVOVMODE_0 is for ZV_LCDCNTL and ZV_LCDDATA(11:0}. 0
R361 10K DNI 0 - 3.3 V signaling DVOMODE_1 (4)
(4) DVALID
1 - 1.8 V signaling
R362 10K R571 10K
C C
ZV_VOLTAGE_SEL1 DVOVMODE_1 DVOVMODE_1 is for ZV_LCDDATA(23:12) 0 DNI
R363 10K DNI 0 - 3.3 V signaling
(4) PSYNC
1 - 1.8 V signaling
R364 10K
Board Straps REV. 0.0

STRAPS PIN DESCRIPTION DEFAULT
MEMTYPE(1:0) DVALID, PSYNC. Memory connected to R420 identification for BIOS 000
00 - Samsung GDDR 3 memory 144 Ball BGA package
01 - TBD
10 - TBD
11 - TBD +VDD_1.8V
R572 10K
DC_Strap1 GPIO(10) Internal TMDS Enabled

0 - Disabled 1
1 - Enabled DVOMODE_0 (4)
LCDDATA(13) Video Capture Enabled R573 10K

DC_Strap2 0 - Disabled 0 DNI
1 - Enabled
DC_Strap3 LCDDATA(14) Not defined 0
D DC_Strap4, LCDDATA(15,19) Video capture enable D

DEMUX_SEL 00 - DAC2 Off 01
01 - DAC2 On as CRT
10 - DAC2 On as TVOUT
11 - DAC2 On as TVOUT and CRT
<Variant Name>
PAL/NTSC LCDDATA(18) TVO Standard Default (Resistor pull-up and switch short to GND) 1
0 - PAL (on board resistor pull-down and switch closed) ATI Technologies Inc.
1 -NTSC (on board resistor pull-up)
Markham, Ontario
Canada, L3T 7X6
EXT_PWR GPIO15 External power cable detect NA (905) 882-2600
0 - Cable is properly connected
1 - Cable is not properly connected. Software should prevent the board from booting, should display Title
a warning at screen and should decrease engine and memory clock speed. PCIe R480 GDDR3 256MB 8MX32 DVI-I DVI-I
C 105-A474XX-10 2
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
D D
TEMPERATURE SENSE AND SPEED CONTROLLED FAN
H1
+12V_BUS
B59
PSC
Bead
2
1 Si2301DS R1862 C1134
Q229 0R 1uF
DNI
3
JU1
C 1 DNI C
2 JUl2
1
D40
LL4148
DNI
2
+3.3V_BUS R1863 R1864 DUAL FOOTPRINT
0R 0R
DNI DNI MJU1
1
C1516 C1517 C1518 2 JUl1
R1609 3
10uF 0.1uF 100pF 4.7K
R1573 Header_1X3
R1610 0R
10K DNI
U106 GPU_DPLUS
GPU_DPLUS (4)
R1620 100R SCL_R 8 1
(2,4,19) SCL SMBCLK VDD
R1621 SDA_R 7 2 C1519
(4,19) SDA SMBDAT D+
100R 2.2nF
R1624 0R TACH 6 3 GPU_DMINUS
(4) ThermINT ALERT D- GPU_DMINUS (4)+3.3V_BUS +3.3V_BUS
+12V_BUS
C1525 5 4
C1524 56pF GND PWM
56pF LM63CIMAX DNI Q209
1
R1865 R1681 R1769 ZXM61N03FTA
DNI 1K 1K 1K D39
Do not install R1682 DNI LL4148
0R R1844 10K 1 DNI
This resistor will
2
C1577
2
be shorted in layout. R1684 0R 1uF
3
R1866 DNI
B It is present to control B
PWM 0R 1 Q213 TACH C1520 10nF
where the signal will be R1683 MMBT2222ALT1
connected to digital
DNI 10R
2
3
ground. 1 Q230
MMBT2222ALT1 R1611
DNI 0R
2
+12V_BUS
U107 DNI
+3.3V_BUS 3 2 TACH
NC#3 TACH R1631
4
NC#4 R1612 0R R1628 10K
14
R1613 PWM INT 0R DNI
1
10K PWM DNI DNI
5 12
DNI GPU_DMINUS 9 GND NC
D-
13 11
SCL_R ADD NC#11 DNI R1629
16
R1614 SCL GPU_DPLUS 10K
10
10K DNI R1615 0R D+ +3.3V_BUS
7
DNI DNI R1616 0R THERM
8 6
FAULT VCC
15 SDA_R C1578 C1579 C1580
SDA
ADM1030ARQ 10uF 0.1uF 100pF
DNI DNI DNI
Change to Maxim part

A A
<Variant Name>
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
C 2
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OPTIONAL ESD/HOTPLUG PROTECTION DIODES

+3.3V_BUS +12V_BUS
2
D10 D11 D12 D13 D14 D15 D16
BAT54SLT1
3 3 3 3 3 3 3
1
D D
DAC1 CRT INTERFACE DNI DNI DNI DNI DNI DNI DNI
L51 47nH L54 47nH R_DAC1_F

(4) R_DAC1 R_DAC1_F (18)
L52 47nH L55 47nH G_DAC1_F
(4) G_DAC1 G_DAC1_F (18)
L53 47nH L56 47nH B_DAC1_F
(4) B_DAC1 B_DAC1_F (18)
R465 33R DDCDATA_DAC1_R
DDCDATA_DAC1_R (18)
R403 R402 R401 R466 33R DDCCLK_DAC1_R
DDCCLK_DAC1_R (18)
HSYNC_DAC1_R
VSYNC_DAC1_R HSYNC_DAC1_R (18)
VSYNC_DAC1_R (18)
+3.3V_BUS +5V 75.0R 75.0R 75.0R
C401 C402 C403 C404 C405 C406 DNI DNI DNI DNI DNI
+3.3V_BUS C407 C408 C409 C751 C752
R467 R463 6.8pF 6.8pF 6.8pF 8pF 8pF 8pF 5pF 5pF 5pF 22pF 22pF
F1
BSN20
1
Q12 +5V
4.7K 6.8k DNI DNI DNI
2 3 L7 L8 L9
(2,4) CRT1DDCDATA 750mA
+3.3V_BUS +5V 82nH 82nH 82nH
+3.3V_BUS PLACE CLOSE TO ASIC
PLACE CLOSE TO +5VCON1 (17)
R468
BSN20
R464
CONNECTOR B39
1
Q13 Bead
4.7K 6.8k MJ2 DNI
2 3 R_DAC1_F 1
(2,4) CRT1DDCCLK R
G_DAC1_F 2
SN74ACT86PW B_DAC1_F G
3
U3B B
C 11 C
DDCDATA_DAC1_R MS0
4 12
(2,4,14) HSYNC_DAC1 R859 33R MS1
6 4
DDCCLK_DAC1_R MS2
5 15
MS3
9
(18) +5V_DIN1 HSYNC_DAC1_R NC
13
VSYNC_DAC1_R HS
14
VS
5
U3C R860 33R VSS
6
VSS#6
9 7
VSS#7
8 8
VSS#8
10 10
(2,4,14) VSYNC_DAC1 VSS#10
16
CASE
17
SN74ACT86PW CASE#17
SLIM VGA HT 6.27MM
J2 and MJ2 share the

same area - they are
mutually exclusive.
B B
A A
<Variant Name>

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
C 2
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
OPTIONAL ESD/HOTPLUG PROTECTION DIODES

+3.3V_BUS +12V_BUS
2
D17 D18 D19 D20 D21 D22 D23
3 3 3 3 3 3 3
1
BAT54SLT1
+5VCON1 (16)
DNI DNI DNI DNI DNI DNI DNI
B63
C DNI
MJ4
C
R_DAC2_F 1
G_DAC2_F R
2
B_DAC2_F G
3
B
11 DDC2_MONID0
DDCDATA_DAC2_R MS0
12 DDC2_MONID1(SDA)
MS1
4 DDC2_MONID2
DDCCLK_DAC2_R MS2
15 DDC2_MONID3(SCL)
MS3
(18) +5V_DIN2 9
HSYNC_DAC2_R NC
13
VSYNC_DAC2_R HS
14
VS
5
VSS
6
VSS#6
DNI DNI DNI DNI DNI 7
VSS#7
C573 C574 C575 C749 C750 8
5pF 5pF 5pF VSS#8
10
22pF 22pF VSS#10
16
CASE
17
CASE#17
DNI DNI DNI DB15F_slim_RA
L16 L17 L18
82nH 82nH 82nH
PLACE CLOSE TO J4 and MJ4 share the

CONNECTOR same area - they are
mutually exclusive.
PLACE CLOSE TO ASIC

B B
L71 47nH A_R_DAC2_F1 L74 47nH

(4) R_DAC2 R_DAC2_F (18)
L72 47nH A_G_DAC2_F1 L75 47nH
(4) G_DAC2 G_DAC2_F (18)
L73 47nH A_B_DAC2_F1 L76 47nH
(4) B_DAC2 B_DAC2_F (18)
+3.3V_BUS +5V
C451 C452 C453 C454 C455 C456

6.8pF 6.8pF 6.8pF 8pF 8pF 8pF
R479 6.8k
1
4.7K BSN20 R480 R451 75.0R

R452 75.0R
2 3 R453 75.0R
(4) CRT2DDCDATA
Q14
+3.3V_BUS +5V
R481 6.8k R825 33R

DDCDATA_DAC2_R (18)
1
4.7K BSN20 R482
2 3 R824 33R
(4) CRT2DDCCLK DDCCLK_DAC2_R (18)
Q15
A A
SECONDARY CRT LOGIC

74ACT08MTC CRT2
<Variant Name>
(4,14) HSYNC_DAC2 10
8 74ACT08MTC
+5V 9 ATI Technologies Inc.
5 1 Commerce Valley Drive East
U2C 6 Markham, Ontario
R31 47R 4 Canada, L3T 7X6
HSYNC_DAC2_R (18)
13 (905) 882-2600
11 R32 47R U2B
VSYNC_DAC2_R (18)
12 Title
(4,14) VSYNC_DAC2 PCIe R480 GDDR3 256MB 8MX32 DVI-I DVI-I
U2D Size Document Number Rev
74ACT08MTC C 105-A474XX-10 2
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
PRIMARY DVI-I CONNECTOR (DVI-I1)
DVI-I1
J4
25
CASE
TX2M 1
(4) TX2M TMDS Data2-
TX2P 2
(4) TX2P TMDS Data2+
3
TMDS Data2/4 Shield
4
TMDS Data4-
C 5 C
TMDS Data4+
6
(17) DDCCLK_DAC2_R DDC Clock
7
(17) DDCDATA_DAC2_R DDC Data
(17) VSYNC_DAC2_R 8
TX1M Analog VSYNC
(4) TX1M 9
TX1P TMDS Data1-
(4) TX1P 10
TMDS Data1+
11
TMDS Data1/3 Shield
12
Place close to TMDS Data3-
13
the connector TMDS Data3+
(17) +5V_DIN2 14
+5V Power
15
GND (for +5V)
16
TX0M Hot Plug Detect
(4) TX0M 17
TX0P TMDS Data0-
(4) TX0P 18
TMDS Data0+
19
C558 TMDS Data0/5 Shield
20
TMDS Data5-
21
100nF TMDS Data5+
22
TXCP TMDS Clock Shield
(4) TXCP 23
TXCM TMDS Clock+
(4) TXCM 24
TMDS Clock-
C1
(17) R_DAC2_F Analog Red
C2
(17) G_DAC2_F Analog Green
C3
(17) B_DAC2_F Analog Blue
C4
(17) HSYNC_DAC2_R Analog HYNC
C5
Analog GND
C6
Analog GND#C6
26
CASE#26
27
CASE#27
28
CASE#28
29
R457 20K CASE#29
(4) HPD1 30
CASE#30
1
DVICONNECTOR
R458
100K
D9
B B
2.5V
2
SECONDARY DVI-I CONNECTOR
J2 and MJ2 share the

NOTE: DVI-I2 same area - they are
J2 mutually exclusive.
ALL ITEMS ARE DNI 25
CASE
TX2- 1
(19) TX2- TX2+ TMDS Data2-
2
(19) TX2+ TMDS Data2+
3
TMDS Data2/4 Shield
4
TMDS Data4-
5
TMDS Data4+
6
(16) DDCCLK_DAC1_R DDC Clock
7
(16) DDCDATA_DAC1_R DDC Data
8
(16) VSYNC_DAC1_R TX1- Analog VSYNC
9
(19) TX1- TX1+ TMDS Data1-
10
(19) TX1+ TMDS Data1+
11
Place close to TMDS Data1/3 Shield
12
the connector TMDS Data3-
13
TMDS Data3+
(16) +5V_DIN1 14
+5V Power
15
R405 20K GND (for +5V)
16
(19) HPD2 Hot Plug Detect
1
TX0- 17
D35 (19) TX0- TX0+ TMDS Data0-
18
R408 (19) TX0+ TMDS Data0+
19
2.5V 100K C1701 TMDS Data0/5 Shield
20
TMDS Data5-
21
2
100nF TMDS Data5+

22
TXC+ TMDS Clock Shield
23
(19) TXC+ TXC- TMDS Clock+
24
(19) TXC- TMDS Clock-
C1
(16) R_DAC1_F Analog Red
A C2 A
(16) G_DAC1_F Analog Green
C3
(16) B_DAC1_F Analog Blue
C4
(16) HSYNC_DAC1_R Analog HYNC
C5
Analog GND
C6
Analog GND#C6
26 <Variant Name>
CASE#26
27
28
CASE#27 ATI Technologies Inc.
CASE#28
29 1 Commerce Valley Drive East
CASE#29
30 Markham, Ontario
CASE#30
Canada, L3T 7X6
DVICONNECTOR (905) 882-2600
C 105-A474XX-10 2
8 7 6 5 4 3 2 1
5 4 3 2 1
SILICON IMAGE TMDS TRANSMITTER
NOTE: TX0-
TX0- (18)
ITEMS ON THIS TX0+
TX0+ (18)
PLACE OPTIONAL TERMINATIONS CLOSE TO TRANSMITTER TX1-
PAGE ARE ALL DNI DVO0 RP213A 33R DVOR0 DVOR0
U114 TX1+ TX1- (18)
TX1+ (18)
8 1 18 D0
DVO1 RP213B 7 2 33R DVOR1 DVOR1 17 TX2-
DVO2 RP213C 33R DVOR2 DVOR2 D1 TX0- R1785 330R C1656 100nF TX2+ TX2- (18)
6 3 16 D2 TX0- 35 TX2+ (18)
D DVO3 RP213D 33R DVOR3 DVOR3 TX0+ D
5 4 15 D3 TX0+ 36
DVO4 RP214A 8 1 33R DVOR4 DVOR4 14 TXC-
DVO5 RP214B 33R DVOR5 DVOR5 D4 TX1- R1786 330R C1657 100nF TXC+ TXC- (18)
7 2 13 D5 TX1- 38 TXC+ (18)
DVO6 RP214C 6 3 33R DVOR6 DVOR6 10 39 TX1+
DVO7 RP214D 33R DVOR7 DVOR7 D6 TX1+
5 4 9 D7
DVO8 RP215A 8 1 33R DVOR8 DVOR8 8 41 TX2- R1787 330R C1658 100nF
DVO9 RP215B 33R DVOR9 DVOR9 D8 TX2- TX2+ +3.3V_BUS
7 2 7 D9 TX2+ 42
DVO10 RP215C 6 3 33R DVOR10 DVOR10 6
DVO11 RP215D 33R DVOR11 DVOR11 D10 TXC- R1788 330R C1659 100nF B60 Bead
5 4 5 D11 TXC- 32
33 TXC+
TXC+
(4) DVO[11..0]
PLACE CLOSE TO THE ASIC C499
10uF_16V
C502 C504
C503 100nF
100pF 2.2nF
34 AVCC1
AVCC AVCC2
AVCC#40 40
GND_A
AGND 37
AGND#43 43
C505 C507 C506
100nF
100pF 2.2nF
C C
PLACE CLOSE TO THE ASIC 24 GND_A
CTL3/A2 +VDDR4
R385 33R SI_HS 20 R386 1K GND_A +5V
(4) DVO_HSYNC HDYNC
R388 33R SI_VS 21 2 TMDS_VREF R389 1K
(4) DVO_VSYNC VSYNC VREF
R390 33R SI_DE 19 C508 0.1uF
(4) DVO_DE DE R380
30 EXT_SWING
R394 33R IDCKP EXT_SWING R392 475R
(4) CLK_DVOCLK0 12 IDICK+ 27R
+3.3V_BUS R1870 5.1K TMDS_VREF 11 IDCK- PVCC1 B64 Bead
+PVCC1
PVCC1 28
R1871 0R MSEN 48 46 PVCC2 R381
(4) HPD2_INT MSEN PVCC2
1
C509 C1581 137R
R1872 0R HPD2 44 29 100nF 2.2nF C1582 C501
R400 33K ISEL EDGE/HTPLG PGND 10uF_6.3V 10uF_6.3V
DNI +3.3V_BUS 25 ISEL/RST# PGND#45 45 2
22 VCC1 R382
R1770 33R DSEL VCC#22 VCC2 GND_P REG9 432R
(4,15) SDA 26 SDA VCC 3
R1771 33R BSEL 27 GND_P LM431CCM/N1B
(2,4,15) SCL
3
SCL C1583
R1773 0R 4 100nF C1584
(2,3,20) PERST#_buf GND 2.2nF
GND#23 23
1 RSVD
31 RSVD#31 TH_GND 49
47 GND_P
RSVD#47
B SiI1162 B
+3.3V_BUS
B65 Bead
C510 C511
GND_A GND_P
100nF 2.2nF C500
10uF_6.3V
(18) HPD2
C512 C513
100nF 2.2nF
<Variant Name>
A A
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
B 105-A474XX-10 2
5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE:
ITEMS ON THIS
PAGE ARE ALL DNI
D D
+RTAVDD
+5V REG8
3.3V
3 2
IN OUT
1
GND
R1687 R1688
4 C1589 L79 L80
C1590 CASE C1591 +3.3V_BUS 3.3uH 3.3uH
1.0uF 22uF_16V 1.0uF 10R 10R
1
+RTVDDC +VADCA +VADCD
2
GND_RT GND_RT GND_RT GND_RT C1592
C1596 C1593 C1594
C1595 C1597 C1598 C1599 C1600 C1601
10nF 1.0uF 1.0uF 1.0uF 1.0uF 22uF_16V 1.0uF 22uF_16V 1.0uF
22uF_16V
1
R1689 GND_RT
3.3uH GND_RT GND_RT
L68 1 2 L67
(21) CompR
3.3uH 10R U111
29
71
81
25
76
99
31
41
1
C1602 R1690
330pF 75.0R
VDDR
VDDR#29
VDDR#71
VDDR#81
VDDC
VDDC#76
VDDC#99
VDDR#31
VDDC#41
2
91
SAD0
1
C1603 92
22uF_16V C1604 SAD1
93
L69 1.0uF SAD2
94
3.3uH SAD3
47 95
VAGCVDD SAD4
49 96
R1691 VAGCVSS#49 SAD5
48 97
2
10R VAGCVSS SAD6
98
GND_RT SAD7
66
VDACVDD RP196A
3.3uH 88 1 8 33R CLK_VIPCLK (4)
L70 C1605 DS_VIPCLK RP196B
(21) LumaR 1 2 60 87 2 7 33R VPHCTL (4)
C1606 VDACBVSS AS_HCTL R1692 47K
61 86 +3.3V_BUS
C1607 R1693 22uF_16V 1.0uF VDACJVSS SRDY_IRQB RP196D
84 4 5 33R VHAD0 (4)
330pF 75.0R HAD0 RP196C
33 85 3 6 33R VHAD1 (4)
VIND0 HAD1
C 34 C
VIND1
35 15
GND_RT VIND2 SDA
36 16
VIND3 SCL
37
VIND4
38
VIND5 R1697 10K
39 22
VIND6 ADO
40 24
VIND7 ADIO
27 23
VINGATEA WS
28 21
VINGATEB BITCLK GND_RT
3.3uH 58
L77 1 C1608 0.1uF CF
(21) ChromaR 2 59 19
CR SPDIF
57
C1609 R1694 VAGCCAP R1695 10K
89
330pF 75.0R C1610 BYTCLK R1696
56 75
VIDEOGNDSENSE SYNC 4.7K
55 62
0.068uF VCLAMPCAP Y_RED
63
C1611 +VADCD C_GREEN GND_RT
43 64
22nf +VADCA VADCDVDD COMP_BLUE GND_RT
45 65
VADCAVDD RSET
44
VADCDVSS
46
VADCAVSS
78
GND_VIN CLKOUT0_GPIO0
50 79
COMP0 CLKOUT1_GPIO1
51 20
C1612 2.2uF COMP1 CLKOUT2_GPIO2
52 13
COMP2 GPIO3
53 14
C1613 2.2uF YF_COMP3 GPIO4
54 17
YR_COMP4 GPIO5
80
GPIO6
(4) CLK_RT_XTALIN 69
XTALIN
70
XTALOUT RP194D 33R VID0
73 4 4 5
TESTEN PDATA0 RP194C 33R VID1
74 5 3 6
(2,3,19) PERST#_buf RESETB PDATA1 RP194B 33R VID2
67 6 2 7
PLLVDD PDATA2 RP194A 33R VID3
68 7 1 8
PLLVSS PDATA3 RP195D 33R VID4
8 4 5
PDATA4 RP195C 33R VID5
9 3 6
PDATA5
VSSC#100
R1703 10 RP195B 2 7 33R VID6
VSSC#26
VSSC#77
VSSC#83
VSSR#12
VSSR#30
VSSR#72
VSSR#90
VSSR#32
VSSC#42
PDATA6
VSSR#2
4.7K 11 RP195A 1 8 33R VID7
B PDATA7 B
VSSC
VSSR
3
PCLK
+RTAVDD Place close to the Rage
Theater
18
26
77
83
100
2
12
30
72
82
90
32
42
RAGE_THEATER
1
VID[7..0]
R1701 VID[7..0] (4)
L78
3.3uH R1704 33R CLK_VIDCLK (4)
10R
2
C1614
C1615
22uF_16V 1.0uF GND_RT
Ca1 Ca2
GND_RT
IMPORTANT
Layout Guide line of THEATER Put 2D line as close as possible to pin 56 of Rage Theater
#1 : Ca1 and Ca2 have to be placed as close as possible to the respective pins of Rage THEATER
#2 : GND_VIN should be seperated from Digital or Chassis Ground and have no loops
GND_RT GND_VIN
#3 : GND_VIN should be connected to Digital GND plane at one point as close as possible to
A A
pin 56 of THEATER

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
C 105-A474XX-10 2
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE:
TV-OUT Y_DAC2
L20
TBLuma ALL ITEMS ARE DNI Jm2
(4) Y_DAC2 470nH
MJ8
R912 HDTV_DET# 6
C583 HDTV_OUT_DET#
75.0R
47pF C584 TBLuma_R 3
G 47pF TBChroma_R 4
Y-OUT
C-OUT
Comp_Out 7
D
CompR_MUX_BR B54 CompR_F 5 Comp-out D
GND_TVVSSN Comp-in
PIN1 1
L21 GND
2
C_DAC2 TBChroma GND#2
(4) C_DAC2 470nH LumaR_MUX_BR B56 11
ChromaR_MUX_BR B53 Luma-in
12
R913 Chroma-in
75.0R C585 C586 8
47pF 47pF CASE
9
CASE#9
10
CASE#10
9 PIN MINIDIN
GND_TVVSSN C1141 C1142 C1143
220pF 220pF 120pF
L22 Connector Jm2 uses the
(4) COMP_DAC2
COMP_DAC2 TBComp C same footprint as Jm1
470nH
and Jm3
R914
75.0R C588 C587 B20
47pF 47pF
GND_TVVSSN GND_VIN
NOTE:
Footprint - M1 VI MUX BYPASS DNI
ALL ITEMS ARE DNI
ChromaR 0R R967 ChromaR_MUX_BR
TV Out (SVHS) MiniDIN 7-pin Jm1
JP1 CompR 0R R968 CompR_MUX_BR
ChromaR_MUX_FP B16 120R 1
Conn_DIN_Mini_Circular_7_Pin_with_O_Ring 1 LumaR 0R R969 LumaR_MUX_BR
2
CompR_MUX_FP B17 120R 2
C 3 C
J7 LumaR_MUX_FP B18 120R 3
4
R878 2500R HDTV_DET# 4
6
(4,14) DC_Strap3 HDTV_OUT_DET#
C76
C77
C78
header_1x4_YELLOW 0R R970 ChromaR_MUX_FP
TBLuma R606 0R Rm22 TBLuma_R 3
TBChroma R608 0R Rm23 TBChroma_R Y-OUT B19 0R R971 CompR_MUX_FP
4
TBComp R504 0R Rm24 Comp_Out C-OUT
33pF
33pF
33pF
7 120R
CompR_F Comp_out 0R R972 LumaR_MUX_FP
5
PIN1 1
SYNC
NOTE:
GND
2
GND#2 ALL ITEMS ARE DNI
8
C527 CASE
9
82pF CASE#9
10
DNI CASE#10
VI MUX
NOTE:
+5V
ALL ITEMS ARE DNI +5V
B6
3
SW1B C735
DIP_SWX2 100nF
220R
Connector Jm1 uses the
2
same footprint as Jm2
A and Jm3 U96
1 16
CompR_MUX_BR SEL VCC
2 4 CompR (20)
CompR_MUX_FP 1A0 YA
3 7
1A1 YB
5 9 ChromaR (20)
1B0 YC
6 12 LumaR (20)
ChromaR_MUX_BR 1B1 YD LumaR_MUX_FP
11 13
R365 ChromaR_MUX_FP 1C0 1D1 LumaR_MUX_BR
10 14
1C1 1D0
10K 15 8
B
+5V E GND B
DNI
PI5V330
C753
100nF
14
U3A
R763 0R 1
(4) STEREOSYNC
3
2 Install DNI
7
SN74ACT86PW TV-OUT 7-PIN MiniDIN A B E C

102-00302-00
102-00305-00
U3D
12 VIVO 9-PIN MiniDIN
11
13
102-00303-00 C A B E
102-00306-00
SN74ACT86PW
No Options (Just DB15)
A B C E
A C share the same footprint
A A
<Variant Name>

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
C 105-A474XX-10 2
8 7 6 5 4 3 2 1
5 4 3 2 1
DVI SCREWS DVI SCREWS

D MISC. BOARD PARTS D
ASSY1 ASSY2 ASSY7 REF2

BLANK
SCREW SCREW
LABEL PCB
JACKSCREW JACKSCREW
ASSY ASSY 1.50W_X_0.50H
ASSY
109-A47400-00A
ASSY3 ASSY4
SCREW SCREW
JACKSCREW JACKSCREW ASSY8 REF3
ASSY ASSY
ANTISTATIC ATI LOGO
BAG LABEL
ASSY5
SCREW 6_X_11 ATI_LOGO_LABEL

PAN_HEAD ASSY
MT1
C C
ASSY6 ASSY10 MT_Hole_0.136_in.
BRACKET BRACKET
DUAL
VGA, VID OUT, DVI DUAL, VGA, DIN, DVI
ASSY11
BRACKET
80200365A0
B B
<Variant Name>
A A
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
B 105-A474XX-10 2
5 4 3 2 1
<Variant Name>8 7 6 5 4 3 2 1
Title Schematic No. Date:

PCIe R480 GDDR3 256MB 8MX32 DVI-I DVI-I 105-A474XX-10 Thursday, November 11, 2004
Rev
REVISION HISTORY 2
D D
Sch PCB Date REVISION DESCRIPTION
Rev Rev
0 00A 13/06/04 Initial revision of the schematic based on 105-A319xx-00:
- Added decoupling caps for GDDR3 memory devices
1 00 12/10/04 - Seperated VDDC input power to VIN1 and VIN2 (added B and B)
- Added HPD2_INT for the second DVI connector (using ext TMDS)
2 10 11/11/04 - PCB change only: extended gnd on layer 10 to ensure connection to fan screws
- No electrical changes.
C C
B B
A A
8 7 6 5 4 3 2 1

R423 Stingray: Gddr3 8M X 32 (Bga) Gddr3 8M X 32 (Bga)

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R423 Stingray: Gddr3 8M X 32 (Bga) Gddr3 8M X 32 (Bga)

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5 4 3 2 1

MEMORY CHANNEL A B MEMORY CHANNEL C D

GDDR3 8M X 32 (BGA) GDDR3 8M X 32 (BGA)

From +12V DIRECT:

From +12V DIRECT:

ATI Technologies Inc.

PCI-EXPRESS EDGE CONNECTOR

USE 47uF TANTALUM DNI DO NOT

AM34 AV38 10K R1011

ATI Technologies Inc.

INSTALL TERMINATION RESISTORS

(20) VHAD1 AJ20 AW21 C16

DVO8 ZV_LCDDATA_7 C7 C40 Bead

C668 C667 C666 C665 AG22

GND_VSSRH3 GND_VSSRH2 GND_VSSRH1 GND_VSSRH0

ATI Technologies Inc.

U1H U1I U1J

This resistor will R1619 22nf 10K +5V

+3.3V_BUS +12V_BUS +5V

Q225 Q37 R1596

221R FDS7064N FDS7064N

+12V_BUS +5V +12V_BUS +12VEXT

MVDDQ Switching Regulator for

DNI MVDDC Switching Regulator for

2 7 C1681 C1682 R375

R1841 R1867 5 B81 220R Sense

R874 0R EXT_PWR# 1 Commerce Valley Drive East

Max 400 mA if all 1.8 V analog power supplies are connected

REGULATOR REGULATOR REGULATOR REGULATOR

C147 NC SC431LC5SK-1 NC SC431LC5SK-1 NC SC431LC5SK-1

DNI DNI 1.50K DNI 1.50K DNI 1.50K

+1.8V Regulator for PCIE_PVDD_18

1.50K 1.0K IN VOUT

Q216 R1798 100R 2N7002LT1

R1789 R1845 R1846 R1847

Title PCIe R480 GDDR3 256MB 8MX32 DVI-I DVI-I

R423 MEMORY CHANNELS A and B

ATI Technologies Inc.

R-420 MEMORY CHANNELS C and D

ATI Technologies Inc.

256 Mbit GDDRIII Channels A and B

+MVDDC +MVDDC +MVDDC

+MVDDC +MVDDQ +MVDDC +MVDDQ +MVDDC +MVDDQ

ATI Technologies Inc.

256 Mbit GDDRIII Channels A and B Channel C Channel D

+MVDDC +MVDDC +MVDDC

+MVDDC +MVDDQ +MVDDC +MVDDQ +MVDDC +MVDDQ

ATI Technologies Inc.

GPIO[6..0] OPTION STRAPS

GPIO0 R331 10K Transmitter Power Savings Enable +3.3V_BUS

GPIO5 R349 10K DNI

R350 10K PLL_BW GPIO(6) 0: Full PLL Bandwidth 0

R359 10K DNI RFU HSYNC RFU 0

R357 10K DNI

Board Straps REV. 0.0

DC_Strap1 GPIO(10) Internal TMDS Enabled

LCDDATA(13) Video Capture Enabled R573 10K

DC_Strap3 LCDDATA(14) Not defined 0

D DC_Strap4, LCDDATA(15,19) Video capture enable D

TEMPERATURE SENSE AND SPEED CONTROLLED FAN

Change to Maxim part

OPTIONAL ESD/HOTPLUG PROTECTION DIODES

L51 47nH L54 47nH R_DAC1_F