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13392 Roll No.

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No. of Pages
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Total No. of Questions : 08

M.Tech.(IT) / (CSE Engg.) / (E-Security) (Sem.–1)
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ADVANCED COMPUTER ARCHITECTURE
Subject Code : CS-505
Paper ID : [E0685]
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Time : 3 Hrs. Max. Marks : 100

INSTRUCTION TO CANDIDATES :

m
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1. Attempt any FIVE questions out of EIGHT questions.

o
2. Each question carries T WENT Y marks.

1. a) Explain

.r c
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b) What is pipelining? Name different stages of pipelined architecture. Briefly

13392 2.
13392 What do
13392you understand
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pe
describe basic performance issues in pipelining.
by static and dynamic
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scheduling?13392
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Explain with13392
suitable 13392

a .r c
examples the Tomasulo’s algorithm for MIPS processor.
3. a) Define the terms ILP. Discuss how compiler techniques can be exploited for
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ILP? 13392 13392 13392

e
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b
b) Discuss their advantages and challenges of parallel processing.

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4. 13392
a) What 13392
is a static branch 13392
prediction?
a p
c) What are forbidden and permissible latencies? Give example.
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What are the 13392
various methods available13392
for static 13392

rp
branch prediction?
b) Define the terms : Name dependences, control dependence and data dependence,
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5.
loop dependence. 13392
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b 13392 13392 13392

Why, there is a need to detect loop dependences? How does the compiler detect it?
a) Explain in detail about hardware multithreading techniques.
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b) What are VLIW processors? Discuss the various problems associated with the
VLIW processor and measures for their mitigation.
6. Explain in detail the centralized shared memory architectures and symmetric shared
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memory multiprocessors.
7. a) How performance of parallel processors is measured? With relevant graphs,
discuss the performance of distributed shared memory multiprocessors.
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b) What is cache coherence problem and when do you say a memory system is
coherent? What are cache coherence protocols?
8. Write notes on the following :
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a) Superscalar architectures
b) Intel Multi-core Architecture

13392 1 | M-35406
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