Vala0 La 9411p

A B C D E
COMPAL CONFIDENTIAL
MODEL NAME : VALA0
PCB NO : LA-9411P
GPIO P/N: 2012.12.20 Rev 3.0C
1 1
BOM P/N :
4319L231L01 SMT MB A9411 VALA0 DSC TPM R1
4319L231L02 SMT MB A9411 VALA0 DSC DTP R1
4319L231L03 SMT MB A9411 VALA0 DSC TPM WO EXP R1
4319L231L04 SMT MB A9411 VALA0 DSC DTP WO EXP R1
4319L231L05 SMT MB A9411 VALA0 DSC TPM R1 SALADO 15 HSW
4319L231L06 SMT MB A9411 VALA0 DSC DTP R1
HASWELL + LYNX POINT
4319L231L07 SMT MB A9411 VALA0 DSC TPM WO EXP R1
2
4319L231L08 SMT MB A9411 VALA0 DSC DTP WO EXP R1 2013_04_10 2
REV : 1.0 (A00)

@ : Nopop Component
CONN@ : Connector Component
L01/L02/L5/L6 L03/L04/L7/L8
15MDC@ : MDC V V
15G@ : Only for 15 Discrete V V
3 3
PXDP@ : PCH XDP

EMC@ : EMI/ESD/RF V V
EXP@ : Express Card V V
CXDP@ : CPU XDP
4 4
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
Compal Electronics, Inc.
Title
MB PCB
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Cover Page
www.Vinafix.vn
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Part Number Description
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
1.0
DAA00005Q00 PCB 0LH LA-9411P REV0 M/B DSC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD LA-9411P
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Date: Wednesday, April 10, 2013 Sheet 1 of 77
A B C D E
A B C D E
Block Diagram AMD

VRAM GDD5 X8 Mars M2 PEG Gen3 x8Lane
P56-59
P49-55
Intel DDR3L-DIMM X2
1
LVDS CONN Dual-Channel LVDS eDP to LVDS iEDP 2Lane Memory BUS (DDR3L) 1
P28 RTD2136S
HasWell 1333/1600 MHz BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
P13-14
P27
rPGA CPU
HDMI level shifter DPB
HDMI CONN PS8401A
947 Pins
P26
P26
USB2.0[12] Camera Through LVDS Cable
DPC P28
DPD P6-12
DOCKING Dock VGA
P44 FDI DMI USB3.0[1] USB3.0 Repeater
LANEX2 LANEX4 USB3.0[1]
DAI
PS8713 P40
USB2.0[0] JUSB1
USB2.0 [3,6] SLG55584AVTR USB P40
USB2.0[0]
SATA2 Power Share
DOCK LAN
Intel P40
(PERN1/USBRN3) Lynx Point USB Option

USB3.0 Repeater USB3.0[2]
iVGA USB3.0[2]
VGA Video Switch BGA PS8713 P41
USB2.0[1] JUSB2 P41
CRT CONN TS3V713ELRTGR
695 Pins
2 2
P25 USB3.0 Repeater USB3.0[5]

on IO board
USB3.0[5]
USB2.0[2] JUSB3
P15-23
PS8713 P42
Card Reader USB3.0 Repeater USB3.0[6]

USB3.0[6]
SD4.0/MMC PCIE2 USB2.0[9] JUSB4
OZ777FJ2LN PS8713 P43 P43
P36 P36
(PERN2/USBRN4)
HD Audio I/F
PCIE
SPI
Intel Clarkville
(SATA_TXN4/PETN1)
PCIE7 PCIE6 PCIE3 (SATA_TXN4/PETN1) RP S-ATA 0/1/2/3/4/5 6GB/s
I217LM
P33
EXPRESS 1/2 Mini Card 1/2 Mini Card Full Mini Card
SATA1
SATA0
SATA PCIE Repeater
SATA3
Card Pink Pather WLAN/BT,WiGig WWAN/mSATA W25Q64FV DOCK LAN LAN SWITCH
P39 P37 P37 P38 ASM1467 P38
P18 To Docking side PI3L720 P33
(SATA_TXN4/PETN1) RP 64M 4K sector
USB2.0[10] USB2.0[8] USB2.0[4] USB2.0[5]
W25Q32FV SATA Repeater

3
MAX4951C P38 RJ45 3
P18 P34
Smart Card TDA8034HN USH (SATA_TXN4/PETN1) RP
32M 4K sector
BCM5882
RFID HDD MDC HDA Codec INT.Speaker

P31 P46
Fingerprint FP_USB USB2.0[7] ALC3226 P30
CONN USH Module P30
CPU XDP Port LPC BUS PCIE4 E-Module FFS RJ11

P7 33MHz P32 LNG3DMP31
SMSC SIO Combo Jack
BC BUS on IO board P30
PCH XDP Port
P15
MEC5048
P45
DAI
To Docking side
WiFi ON/OFF SMSC KBC

on SNIFFER board
MEC5075 Discrete TPM
P46 Dig. MIC
DC/DC Interface AT97SC3204
P48
P35
4 Through LVDS Cable 4
LED P24
TP CONN KB CONN
P47 P47
PWM FAN DELL CONFIDENTIAL/PROPRIETARY
P46
PROPRIETARY NOTE:
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Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Block Diagram
1.0
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD LA-9411P
A B C D E
5 4 3 2 1
USB 2.0 USB 3.0

PORT# PORT# DESTINATION
POWER STATES
0 1 Right Side Top (JUSB1)
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
State S3# S4# S5# A# PLANE PLANE PLANE PLANE
1 2 Right Side Middle (JUSB2)
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON 2 5 Right Side bottom (JUSB3)
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF 3 3 (PERN1/USBRN3) DOCKING (JDOCK1)
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF 4 WLAN (JMINI2)
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF 5 WWAN (JMINI1)
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF PCH 6 DOCKING (JDOCK1)
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF 7 USH (JUSH1)
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF 8 Pink Pather (JMINI3)
9 6 Left Side (JUSB4)

PM TABLE
10 Express card (JEXP1)
+PWR_SRC +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M
C C
+PWR_SRC_S +1.35V_MEM +3.3V_RUN +1.05V_M +1.05V_M 11 None
+5V_ALW +1.5V_RUN (M-OFF)
power
plane +3.3V_ALW +0.675V_DDR_VTT 12 CAMERA (JCAM1)
+3.3V_ALW_PCH +VCC_CORE
+3.3V_RTC_LDO +1.05V_RUN 13 None
+GPU_CORE
+1.35V_MEM_GFX
State
+1.8V_RUN_GFX PCI EXPRESS DESTINATION
+VGA_PCIE SATA DESTINATION
+3.3V_RUN_GFX Lane 1 (SATA_TXN4/PETN1) WWAN (JMINI1) SATA by default
+VDDCI SATA 0 HDD (JSATA1)
Lane 2 (SATA_RXN5/PERN2) None
SATA 1 ODD (JSATA2)
S0 ON ON ON ON ON Lane 2 (PERN2/USBRN4) 10/100/1G LOM
SATA 2 Dock (JDOCK1)
S3 ON ON OFF ON OFF Lane 3 WLAN (JMINI2) SATA 3 NA
B S5 S4/AC ON OFF OFF ON OFF Lane 4 E3 Module Bay (JSATA2) B
SATA 4 (SATA_TXN4/PETN1) WWAN (JMINI1)

S5 S4/AC don't exist OFF OFF OFF OFF OFF Lane 5 None SATA by default
Lane 6 Pink Pather (JMINI3)
Lane 7 Express card (JEXP1)
Lane 8 MMI
DISPLAY Ports
Connetion
On CPU
DDIB MB HDMI (JHDMI1)
A
DDIC Dock DP port 1 A
DDID Dock DP port 2

PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Index and Configuration
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1.0
5 4 3 2 1
5 4 3 2 1
EN_INVPWR FDC654P
D +BL_PWR_SRC D
Q21
DGPU_PWR_EN#
MODC_EN
DGPU_PWR_EN# ISL62883CHRTZ-T
+GPU_CORE
(PU600)
+PWR_SRC
RUN_ON
ADAPTER BATTERY
PCH_ALW_ON TP0610K-T1-E3 TPS22966 TPS22966

+PWR_SRC_S SY8036L
(PQ3) (U105) (U105)
(PU602)
+5V_RUN
CHARGER
BQ24717 +5V_MOD +VGA_PCIE
C
(PU700) ALWON C
TPS51225
+5V_ALW
(PU100) +5V_HDD Pop option
+5V_RUN
RUN_ON SYN470DBC
+1.5V_RUN
PU400
ISL95812 RT8207MZQW RT8207MZQW TPS51212DSCR

+3.3V_ALW
MCARD_WWAN_PWREN
(PU500) (PU200) (PU200) (PU300)
MCARD_MISC_PWREN
0.75V_DDR_VTT_ON
DGPU_PWR_EN#
DGPU_PWR_EN#
IMVP_VR_ON
A_ON
AUX_EN_WOWL
SIO_SLP_S4#
EN_LCDPWR
PCH_ALW_ON
B
SUS_ON B
A_ON
RUN_ON
SIO_SLP_LAN#
SYN470D TPS22966 TPS22966 TPS22966 TPS22966 TPS22966 TPS22966 TPS22966 TPS22966 TPS22966 TPS22966
+VCC_CORE +1.35V_MEM +0.675V_DDR_VTT +1.05V_M
(PU603) (U104) (U100) (U103) (U104) (U102) (U101) (U102) (U100) (U101) (U103)
CPU1.5V_S3_GATE
DGPU_PWR_EN# Pop option

RUN_ON
+3.3V_ALW +3.3V_PCIE +3.3V_PCIE

+1.8V_RUN_GFX +LCDVDD +3.3V_WLAN +3.3V_SUS +3.3V_LAN +3.3V_RUN +3.3V_M +3.3V_RUN_GFX
_PCH _FLASH _WWAN
SI4164
AO4304L SI4164DY (Q63)
+0.9V_LAN
(QC6) (QV1)
Pop option
A A
+3.3V_M
+1.05V_RUN DELL CONFIDENTIAL/PROPRIETARY

+1.35V_CPU_VDDQ +1.35V_MEM_GFX PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Power Rail
1.0
5 4 3 2 1
www.Vinafix.vn
5 4 3 2 1
2.2K
SMBUS Address [0x9a]
2.2K
+3.3V_ALW_PCH
R10 MEM_SMBCLK 202
MEM_SMBDATA
2N7002 SMBUS Address [A0]
U11 200 DIMMA
2N7002
2.2K
202
D
PCH D
2.2K
+3.3V_LAN 200 DIMMB SMBUS Address [A4]
U8 LAN_SMBCLK 28
LAN_SMBDATA 31 LOM SMBUS Address [C8]
R7
N11 K6 53
51 XDP1 SMBUS Address [TBD]
2.2K
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH
2.2K 53
51 XDP2
A5 B6 2.2K SMBUS Address [TBD]
SMBUS Address
3A 3A APR_EC: 0x48
2.2K +3.3V_ALW SPR_EC: 0x70 10K
MSLICE_EC: 0x72
B4 127
1A DOCK_SMB_CLK USB: 0x59
129 AUDIO: 0x34 10K
+3.3V_RUN
1A A3 DOCK_SMB_DAT DOCKING
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13 4
G Sensor
@ 2.2K 6 SMBUS Address [0x3B]
C C
+LCD_VDD
@ 2.2K
B5 LCD_SMBCLK
1B
1B A4 LCD_SMDATA
13
2.2K 14 eDP to LVDS CONVERTER SMBUS Address TBD
KBC 2.2K
+3.3V_ALW
100 ohm 7
1C A56 PBAT_SMBCLK
100 ohm 6 BATTERY SMBUS Address [0x16]
1C B59 PBAT_SMBDAT CONN
2.2K
+3.3V_SUS
2.2K
USH_SMBCLK M9
1E A50
L9 USH SMBUS Address [0xa4]
1E B53 USH_SMBDAT
2.2K
B B
+3.3V_SUS
2.2K
MEC 5075 7
2B A49 CARD_SMBCLK
8 Express card SMBUS Address [TBD]
2B B52 CARD_SMBDAT
2.2K
+3.3V_ALW
2.2K
B50 CHARGER_SMBCLK
1G 9
A47 CHARGER_SMBDAT Charger SMBUS Address [0x12]
1G 8
2.2K
+3.3V_ALW
2.2K
B7 BAY_SMBDAT 29
2D
30 E3 Module Bay SMBUS Address [0xd2]
A7 BAY_SMBCLK
2D
100 2
2.2K
100 3 MBATT
A +3.3V_RUN A
2.2K
B49 GPU_SMBCLK 8
2A
B48 GPU_SMBDAT 9 GPU SMBUS Address [0xXX]
2A
PROPRIETARY NOTE:
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Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SMBus block diagram
1.0
5 4 3 2 1
5 4 3 2 1
+VCOMP_OUT
PEG_COMP 2 1
D 24.9_0402_1% RC1 D
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
JCPU1A Haswell rPGA EDS
E23 PEG_COMP
PEG_RCOMP M29 PEG_CRX_GTX_N[0..7] <49>
PEG_CRX_GTX_N0
DMI_CRX_PTX_N0 D21 PEG_RXN_0 K28 PEG_CRX_GTX_N1
<16> DMI_CRX_PTX_N0 C21 DMI_RXN_0 PEG_RXN_1 M31 PEG_CTX_GRX_P[0..7]
DMI_CRX_PTX_N1 PEG_CRX_GTX_N2
<16> DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 B21 DMI_RXN_1 PEG_RXN_2 L30 PEG_CRX_GTX_N3 PEG_CTX_GRX_P[0..7] <49>
<16> DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 A21 DMI_RXN_2 PEG_RXN_3 M33 PEG_CRX_GTX_N4 PEG_CTX_GRX_N[0..7]
<16> DMI_CRX_PTX_N3 DMI_RXN_3 PEG_RXN_4 L32 PEG_CRX_GTX_N5 PEG_CTX_GRX_N[0..7] <49>
DMI_CRX_PTX_P0 D20 PEG_RXN_5 M35 PEG_CRX_GTX_N6
<16> DMI_CRX_PTX_P0 C20 DMI_RXP_0 PEG_RXN_6 L34
DMI_CRX_PTX_P1 PEG_CRX_GTX_N7
<16> DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 B20 DMI_RXP_1 PEG_RXN_7 E29
<16> DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 A20 DMI_RXP_2 PEG_RXN_8 D28
<16> DMI_CRX_PTX_P3
DMI
DMI_RXP_3 PEG_RXN_9 E31
DMI_CTX_PRX_N0 D18 PEG_RXN_10 D30
<16> DMI_CTX_PRX_N0 DMI_TXN_0 PEG_RXN_11
<16> DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 C17 E35
DMI_CTX_PRX_N2 B17 DMI_TXN_1 PEG_RXN_12 D34
<16> DMI_CTX_PRX_N2 DMI_TXN_2 PEG_RXN_13
<16> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 A17 E33
DMI_TXN_3 PEG_RXN_14 E32
D17 PEG_RXN_15 L29 PEG_CRX_GTX_P[0..7] <49> 2 1 0.22U_0402_16V7K
<16> DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 PEG_CRX_GTX_P0 PEG_CTX_GRX_C_P0 15G@ CC1 PEG_CTX_GRX_P0
DMI_CTX_PRX_P1 C18 DMI_TXP_0 PEG_RXP_0 L28 PEG_CRX_GTX_P1 PEG_CTX_GRX_C_N0 15G@ CC2 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N0
<16> DMI_CTX_PRX_P1 DMI_TXP_1 PEG_RXP_1
<16> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 B18 L31 PEG_CRX_GTX_P2
C DMI_CTX_PRX_P3 A18 DMI_TXP_2 PEG_RXP_2 K30 PEG_CRX_GTX_P3 PEG_CTX_GRX_C_P1 15G@ CC3 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P1 C
<16> DMI_CTX_PRX_P3 DMI_TXP_3 PEG_RXP_3 L33 PEG_CRX_GTX_P4 PEG_CTX_GRX_C_N1 15G@ CC4 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N1
PEG_RXP_4 K32 PEG_CRX_GTX_P5
PEG_RXP_5 L35 PEG_CRX_GTX_P6 PEG_CTX_GRX_C_P2 15G@ CC5 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P2
PEG_RXP_6 K34 PEG_CRX_GTX_P7 PEG_CTX_GRX_C_N2 15G@ CC6 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N2
PEG_RXP_7 F29
2 1 0_0402_5% FDI_CSYNC_R H29 PEG_RXP_8 E28 2 1 0.22U_0402_16V7K
PEG
@ RC2 PEG_CTX_GRX_C_P3 15G@ CC7 PEG_CTX_GRX_P3
<16> FDI_CSYNC
FDI
@ RC3 2 1 0_0402_5% FDI_INT_R J29 FDI_CSYNC PEG_RXP_9 F31 PEG_CTX_GRX_C_N3 15G@ CC8 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N3
<16> FDI_INT DISP_INT PEG_RXP_10 E30
PEG_RXP_11 F35 PEG_CTX_GRX_C_P4 15G@ CC9 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P4
PEG_RXP_12 E34 PEG_CTX_GRX_C_N4 15G@ CC10 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N4
PEG_RXP_13 F33
PEG_RXP_14 D32 PEG_CTX_GRX_C_P5 15G@ CC11 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P5
PEG_RXP_15 H35 PEG_CTX_GRX_C_N0 PEG_CTX_GRX_C_N5 15G@ CC12 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N5
PEG_TXN_0 H34 PEG_CTX_GRX_C_N1
PEG_TXN_1 J33 PEG_CTX_GRX_C_N2 PEG_CTX_GRX_C_P6 15G@ CC13 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P6
PEG_TXN_2 H32 PEG_CTX_GRX_C_N3 PEG_CTX_GRX_C_N6 15G@ CC14 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N6
PEG_TXN_3 J31 PEG_CTX_GRX_C_N4
PEG_TXN_4 G30 PEG_CTX_GRX_C_N5 PEG_CTX_GRX_C_P7 15G@ CC15 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P7
PEG_TXN_5 C33 PEG_CTX_GRX_C_N6 PEG_CTX_GRX_C_N7 15G@ CC16 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N7
PEG_TXN_6 B32 PEG_CTX_GRX_C_N7
PEG_TXN_7 B31
PEG_TXN_8 A30
PEG_TXN_9 B29
PEG_TXN_10 A28
PEG_TXN_11 B27
PEG_TXN_12 A26
PEG_TXN_13 B25
PEG_TXN_14 A24
PEG_TXN_15 J35 PEG_CTX_GRX_C_P0
PEG_TXP_0 G34 PEG_CTX_GRX_C_P1
PEG_TXP_1 H33 PEG_CTX_GRX_C_P2
B PEG_TXP_2 G32 PEG_CTX_GRX_C_P3 B
PEG_TXP_5 B33 PEG_CTX_GRX_C_P6
PEG_TXP_6 A32 PEG_CTX_GRX_C_P7
PEG_TXP_7 C31
PEG_TXP_8 B30
PEG_TXP_9 C29
PEG_TXP_10 B28
PEG_TXP_11 C27
PEG_TXP_12 B26
PEG_TXP_13 C25
PEG_TXP_14 B24
PEG_TXP_15
1 OF 9
LOTES_AZIF0012-P002B_HASWELL
CONN@
A A
PROPRIETARY NOTE:
Title
CPU (1/7)
www.Vinafix.vn
1.0
5 4 3 2 1
5 4 3 2 1
SM_DRAMPWROK with DDR Power Gating Topology

+3.3V_ALW +VCCIO_OUT
1 2 PM_DRAM_PWRGD +1.35V_CPU_VDDQ
+PCH_VCCDSW3_3
0.1U_0402_25V6
0.1U_0402_25V6
@ RC4 200_0402_1%
1 1
1
+PCH_VCCDSW3_3 +VCCIO_OUT +VCCIO_OUT
1.8K_0402_1%
CC19 @
CC17
CC18
1 2
RC6
1 2 RUNPWROK_R
RC5 100K_0402_5% 0.1U_0402_25V6 2 2 JXDP1
1 2 1.35V_SUS_PWRGD @ @ 1 2
2
GND0 GND1
5
@ RC9 6.8K_0402_5% XDP_PREQ# 3 4 CFG17 CFG17 <10>
D 2 1 RUNPWROK_R 1 XDP_PRDY# 5 OBSFN_A0 OBSFN_C0 6 CFG16 D
CFG16 <10>
P
<46> RUNPWROK B 4 2 1 7 OBSFN_A1 OBSFN_C1 8
@ RC7 0_0402_5% RUNPWROK_AND PM_DRAM_PWRGD_CPU
2 1 2 O @ RC10 0_0402_5% CFG0 9 GND2 GND3 10 CFG8
<16> PM_DRAM_PWRGD A <10> CFG0 OBSDATA_A0 OBSDATA_C0 CFG8 <10>
G
@ RC13 0_0402_5% UC1 Place near JXDP1 <10> CFG1 CFG1 11 12 CFG9 CFG9 <10>
OBSDATA_A1 OBSDATA_C1
3.3K_0402_1%
1.35V_SUS_PWRGD 2 1 74AHC1G09GW_TSSOP5~D 13 14
39_0402_5%
3
GND4 GND5
1
@ RC15
@ RC14 <10> CFG2 CFG2 15 16 CFG10 CFG10 <10>
OBSDATA_A2 OBSDATA_C2
RC16
0_0402_5% <10> CFG3 17 18 CFG11 CFG11 <10>
19 OBSDATA_A3 OBSDATA_C3 20
XDP_OBS0 21 GND6 GND7 22 CFG19
OBSFN_B0 OBSFN_D0 CFG19 <10>
XDP_OBS1 23 24 CFG18 CFG18 <10>
2
+3.3V_ALW_PCH OBSFN_B1 OBSFN_D1
L2N7002WT1G_SC-70-3
25 26
1 1
GND8 GND9
@ QC1
<10> CFG4 CFG4 27 28 CFG12 CFG12 <10>
1 2 PM_DRAM_PWRGD D CFG5 29 OBSDATA_B0 OBSDATA_D0 30 CFG13
<10> CFG5 OBSDATA_B1 OBSDATA_D1 CFG13 <10>
@ RC12 200_0402_1% 2 31 32
<11,48> RUN_ON_CPU1.5VS3# GND10 GND11
G <10> CFG6 CFG6 33 34 CFG14 CFG14 <10>
CFG7 35 OBSDATA_B2 OBSDATA_D2 36 CFG15
S <10> CFG7 CFG15 <10>
3
37 OBSDATA_B3 OBSDATA_D3 38
@ QC5 RC20 need to close to JCPU1 GND12 GND13
H_CPUPWRGD CXDP@ RC20 1 2 1K_0402_1% H_CPUPWRGD_XDP 39 40 CLK_XDP @ RH1 1 2 0_0402_5%
PWRGOOD/HOOK0 ITPCLK/HOOK4 CLK_CPU_ITP <17>
L2N7002WT1G_SC-70-3 CXDP@ RC21 1 2 0_0402_5% CFD_PWRBTN#_XDP 41 42 CLK_XDP# @ RH2 1 2 0_0402_5%
<15,16> SIO_PWRBTN#_R HOOK1 ITPCLK#/HOOK5 CLK_CPU_ITP# <17>
43 44
RUNPWROK_AND 1 3 PM_DRAM_PWRGD_CPU CXDP@ RC22 1 2 0_0402_5% CPU_PWR_DEBUG_R 45 VCC_OBS_AB VCC_OBS_CD 46 XDP_RST#_R CXDP@ 2 1 CPU_PLTRST#_R
D
S
<11> CPU_PWR_DEBUG HOOK2 RESET#/HOOK6
@ RC24 1 2 0_0402_5% SYS_PWROK_XDP 47 48 XDP_DBRESET# RC23 1K_0402_1%
<16,45> SYS_PWROK HOOK3 DBR#/HOOK7
49 50
CXDP@ RC25 1 2 0_0402_5% DDR_XDP_SMBDAT_R1 51 GND14 GND15 52 XDP_TDO
G
<13,14,15,18,27,31> DDR_XDP_WAN_SMBDAT
2
CXDP@ RC26 1 2 0_0402_5% DDR_XDP_SMBCLK_R1 53 SDA TD0 54 XDP_TRST#
<13,14,15,18,27,31> DDR_XDP_WAN_SMBCLK SCL TRST#
2 1 RUNPWROK_R 55 56 XDP_TDI
<13,14,18> DDR_HVREF_RST_PCH 57 TCK1 TDI 58
@ RC104 0_0402_5% XDP_TCLK XDP_TMS
2 1 Refer CRB 1.0 59 TCK0 TMS 60 CFG3_R 1 2 CFG3
<46,62> 1.35V_SUS_PWRGD GND16 GND17
@ RC103 0_0402_5% CXDP@RC8 1K_0402_1%
SAMTE_BSH-030-01-L-D-A CONN@
1
RC100 @
C 1K_0402_1% C
Refer CRB 1.0
JCPU1B
2
Haswell rPGA EDS
+1.05V_RUN Refer CRB 1.0
Refer CRB 1.2 CPU_DETECT# AP32 MISC AP3 SM_RCOMP0
DDR3L
1 2 H_THERMTRIP# +VCCST <45> CPU_DETECT# SKTOCC SM_RCOMP_0 AR3 SM_RCOMP1
@ RC27 100_0402_1% H_CATERR# AN32 SM_RCOMP_1 AP2 SM_RCOMP2
CATERR SM_RCOMP_2
THERMAL
PECI_EC AR27 AN3 DDR3_DRAMRST#_CPU DDR3_DRAMRST#_CPU <13>
<46> PECI_EC PECI SM_DRAMRST
AK31
+VCCIO_OUT RC30 1 2 56_0402_5% H_PROCHOT#_R AM30 FC_AK31 AR29 XDP_PRDY#
<46,50,65,68,69> H_PROCHOT# PROCHOT PRDY
H_THERMTRIP# @ RC31 1 2 0_0402_5% H_THERMTRIP#_R AM35 AT29 XDP_PREQ#
<46> H_THERMTRIP# THERMTRIP PREQ
place RC31 near CPU AM34 XDP_TCLK
1 2 H_CATERR# TCK AN33 XDP_TMS
@ RC28 49.9_0402_1% TMS AM33 XDP_TRST#
1 2 H_PROCHOT# H_PM_SYNC AT28 TRST AM31 XDP_TDI_R CXDP@ RC32 1 2 0_0402_5% XDP_TDI
JTAG
<16> H_PM_SYNC PM_SYNC TDI
PWR
RC29 62_0402_5% 1 2 VCCPWRGOOD_0_R AL34 AL33 XDP_TDO_R CXDP@ RC34 1 2 0_0402_5% XDP_TDO
<20> H_CPUPWRGD PWRGOOD TDO
@ RC33 0_0402_5% PM_DRAM_PWRGD_CPU AC10 AP33 XDP_DBRESET#_R @ RC35 2 1 0_0402_5% XDP_DBRESET# XDP_DBRESET# <15,16>
CPU_PLTRST#_R AT26 SM_DRAMPWROK DBR
PLTRSTIN AR30 XDP_OBS0_R CXDP@ RC36 1 2 0_0402_5% XDP_OBS0
BPM_N_0 AN31 XDP_OBS1_R CXDP@ RC37 1 2 0_0402_5% XDP_OBS1
Refer CRB 1.0 G28 BPM_N_1 AN29 XDP_OBS2_R
+1.05V_RUN +VCCST <17> CLK_CPU_DPLL# DPLL_REF_CLKN BPM_N_2 @ T21 PAD~D +3.3V_ALW_PCH
CLOCK
H28 AP31 XDP_OBS3_R @ T37
<17> CLK_CPU_DPLL DPLL_REF_CLKP BPM_N_3 PAD~D
@ RC42 2 1 0_0402_5% CPU_SSC_DPLL# F27 AP30 XDP_OBS4_R @ T38
<17> CLK_CPU_SSC_DPLL# 2 1 E27 SSC_DPLL_REF_CLKN BPM_N_4 AN28 PAD~D 1 2
@ RC44 0_0402_5% CPU_SSC_DPLL XDP_OBS5_R @ T47 SYS_PWROK_XDP
<17> CLK_CPU_SSC_DPLL SSC_DPLL_REF_CLKP BPM_N_5 PAD~D
2 1 @ RC46 2 1 0_0402_5% CPU_DMI# D26 AP29 XDP_OBS6_R @ T72 @ RC11 1K_0402_1%
<17> CLK_CPU_DMI# BCLKN BPM_N_6 PAD~D
22U_0805_6.3V6M
22U_0805_6.3V6M
@ RC99 0_0603_5% @ RC48 2 1 0_0402_5% CPU_DMI E26 AP28 XDP_OBS7_R @ T88

<17> CLK_CPU_DMI BCLKP BPM_N_7 PAD~D
1 1
2 OF 9 For ESD concern, please put near CPU
CC47
CC48
2 2 CONN@
B @ @ B
PU/PD for JTAG signals

+3.3V_RUN
XDP_DBRESET# RC52 2 1 1K_0402_1%
+1.05V_RUN
XDP_TMS @ RC53 2 1 51_0402_1%
VCCPWRGOOD_0_R XDP_TDI @ RC54 2 1 51_0402_1%
10K_0402_5%
XDP_PREQ# @ RC55 2 1 51_0402_1%
Buffered reset to CPU
1
+3.3V_RUN
RC56
XDP_TDO RC57 2 1 51_0402_1%
+1.05V_RUN DDR3 COMPENSATION SIGNALS CXDP@
0.1U_0402_25V6
2
1
1K_0402_1%
@ SM_RCOMP0 RC58 1 2 100_0402_1% XDP_TCLK RC59 2 1 51_0402_1%

CC21
RC60
SM_RCOMP1 RC61 1 2 75_0402_1% XDP_TRST# RC62 2 1 51_0402_1%

2
UC2 @ @ SM_RCOMP2 RC63 1 2 100_0402_1%
CAD Note:
2
1 5
2 NC VCC Avoid stub in the PWRGD path
A <15,16> PCH_PLTRST#
3 A 4 PCH_PLTRST#_BUF 1 2 CPU_PLTRST#_R
CAD Note: A
GND Y @ RC64 43_0402_5%
while placing resistors RC33 & RC56 Trace width=12~15 mil, Spcing=20 mils
SN74LVC1G07DCKR_SC70-5~D
@ RC66 2 1 0_0402_5% Max trace length= 500 mil
<20> CPU_PLTRST#
20K_0402_5%
@
1
RC67
PROPRIETARY NOTE:
Title
2
CAD Note: TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU (2/7)
PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
1.0
5 4 3 2 1
www.Vinafix.vn
5 4 3 2 1
D D
JCPU1C Haswell rPGA EDS
<13> DDR_A_D[0..63] DDR_A_D0 AR15 AC7 @ T2 PAD~D JCPU1D Haswell rPGA EDS
AT14 SA_DQ_0 RSVD U4 <14> DDR_B_D[0..63]
DDR_A_D1 M_CLK_DDR#0
DDR_A_D2 AM14 SA_DQ_1 SA_CKN0 V4 M_CLK_DDR0 M_CLK_DDR#0 <13> DDR_B_D0 AR18 AG8 @ T3 PAD~D
DDR_A_D3 AN14 SA_DQ_2 SA_CKP0 AD9 DDR_CKE0_DIMMA M_CLK_DDR0 <13> DDR_B_D1 AT18 SB_DQ_0 RSVD Y4 M_CLK_DDR#2
DDR_A_D4 AT15 SA_DQ_3 SA_CKE_0 U3 M_CLK_DDR#1 DDR_CKE0_DIMMA <13> DDR_B_D2 AM17 SB_DQ_1 SB_CKN0 AA4 M_CLK_DDR2 M_CLK_DDR#2 <14>
AR14 SA_DQ_4 SA_CKN1 V3 M_CLK_DDR#1 <13> AM18 SB_DQ_2 SB_CKP0 AF10 DDR_CKE2_DIMMB M_CLK_DDR2 <14>
DDR_A_D5 M_CLK_DDR1 DDR_B_D3
DDR_A_D6 AN15 SA_DQ_5 SA_CKP1 AC9 DDR_CKE1_DIMMA M_CLK_DDR1 <13> DDR_B_D4 AR17 SB_DQ_3 SB_CKE_0 Y3 M_CLK_DDR#3 DDR_CKE2_DIMMB <14>
DDR_A_D7 AM15 SA_DQ_6 SA_CKE_1 U2 DDR_CKE1_DIMMA <13> DDR_B_D5 AT17 SB_DQ_4 SB_CKN1 AA3 M_CLK_DDR3 M_CLK_DDR#3 <14>
DDR_A_D8 AM9 SA_DQ_7 SA_CKN2 V2 DDR_B_D6 AN17 SB_DQ_5 SB_CKP1 AG10 DDR_CKE3_DIMMB M_CLK_DDR3 <14>
AN9 SA_DQ_8 SA_CKP2 AD8 AN18 SB_DQ_6 SB_CKE_1 Y2 DDR_CKE3_DIMMB <14>
DDR_A_D9 DDR_B_D7
DDR_A_D10 AM8 SA_DQ_9 SA_CKE_2 U1 DDR_B_D8 AT12 SB_DQ_7 SB_CKN2 AA2
DDR_A_D11 AN8 SA_DQ_10 SA_CKN3 V1 DDR_B_D9 AR12 SB_DQ_8 SB_CKP2 AG9
DDR_A_D12 AR9 SA_DQ_11 SA_CKP3 AC8 DDR_B_D10 AN12 SB_DQ_9 SB_CKE_2 Y1
DDR_A_D13 AT9 SA_DQ_12 SA_CKE_3 DDR_B_D11 AM11 SB_DQ_10 SB_CKN3 AA1
DDR_A_D14 AR8 SA_DQ_13 M7 DDR_CS0_DIMMA# DDR_B_D12 AT11 SB_DQ_11 SB_CKP3 AF9
DDR_A_D15 AT8 SA_DQ_14 SA_CS_N_0 L9 DDR_CS1_DIMMA# DDR_CS0_DIMMA# <13> DDR_B_D13 AR11 SB_DQ_12 SB_CKE_3
AJ9 SA_DQ_15 SA_CS_N_1 M9 DDR_CS1_DIMMA# <13> AM12 SB_DQ_13 P4
DDR_A_D16 DDR_B_D14 DDR_CS2_DIMMB#
DDR_A_D17 AK9 SA_DQ_16 SA_CS_N_2 M10 DDR_B_D15 AN11 SB_DQ_14 SB_CS_N_0 R2 DDR_CS3_DIMMB# DDR_CS2_DIMMB# <14>
DDR_A_D18 AJ6 SA_DQ_17 SA_CS_N_3 M8 M_ODT0 DDR_B_D16 AR5 SB_DQ_15 SB_CS_N_1 P3 DDR_CS3_DIMMB# <14>
DDR_A_D19 AK6 SA_DQ_18 SA_ODT_0 L7 M_ODT1 M_ODT0 <13> DDR_B_D17 AR6 SB_DQ_16 SB_CS_N_2 P1
DDR_A_D20 AJ10 SA_DQ_19 SA_ODT_1 L8 M_ODT1 <13> DDR_B_D18 AM5 SB_DQ_17 SB_CS_N_3
DDR_A_D21 AK10 SA_DQ_20 SA_ODT_2 L10 DDR_B_D19 AM6 SB_DQ_18 R4 M_ODT2
DDR_A_D22 AJ7 SA_DQ_21 SA_ODT_3 V5 DDR_A_BS0 DDR_B_D20 AT5 SB_DQ_19 SB_ODT_0 R3 M_ODT3 M_ODT2 <14>
DDR_A_D23 AK7 SA_DQ_22 SA_BS_0 U5 DDR_A_BS1 DDR_A_BS0 <13> DDR_B_D21 AT6 SB_DQ_20 SB_ODT_1 R1 M_ODT3 <14>
DDR_A_D24 AF4 SA_DQ_23 SA_BS_1 AD1 DDR_A_BS2 DDR_A_BS1 <13> DDR_B_D22 AN5 SB_DQ_21 SB_ODT_2 P2
AF5 SA_DQ_24 SA_BS_2 DDR_A_BS2 <13> AN6 SB_DQ_22 SB_ODT_3 R7
DDR_A_D25 DDR_B_D23 DDR_B_BS0
DDR_A_D26 AF1 SA_DQ_25 V10 DDR_B_D24 AJ4 SB_DQ_23 SB_BS_0 P8 DDR_B_BS1 DDR_B_BS0 <14>
DDR_A_D27 AF2 SA_DQ_26 VSS U6 DDR_A_RAS# DDR_B_D25 AK4 SB_DQ_24 SB_BS_1 AA9 DDR_B_BS2 DDR_B_BS1 <14>
C DDR_A_D28 AG4 SA_DQ_27 SA_RAS U7 DDR_A_WE# DDR_A_RAS# <13> DDR_B_D26 AJ1 SB_DQ_25 SB_BS_2 DDR_B_BS2 <14> C
DDR_A_D29 AG5 SA_DQ_28 SA_WE U8 DDR_A_CAS# DDR_A_WE# <13> DDR_B_D27 AJ2 SB_DQ_26 R10
DDR_A_D30 AG1 SA_DQ_29 SA_CAS DDR_A_CAS# <13> DDR_B_D28 AM1 SB_DQ_27 VSS R6 DDR_B_RAS#
DDR_A_D31 AG2 SA_DQ_30 V8 DDR_A_MA0 DDR_A_MA[0..15] <13> DDR_B_D29 AN1 SB_DQ_28 SB_RAS P6 DDR_B_WE# DDR_B_RAS# <14>
DDR_A_D32 J1 SA_DQ_31 SA_MA_0 AC6 DDR_A_MA1 DDR_B_D30 AK2 SB_DQ_29 SB_WE P7 DDR_B_CAS# DDR_B_WE# <14>
DDR_A_D33 J2 SA_DQ_32 SA_MA_1 V9 DDR_A_MA2 DDR_B_D31 AK1 SB_DQ_30 SB_CAS DDR_B_CAS# <14>
J5 SA_DQ_33 SA_MA_2 U9 L2 SB_DQ_31 R8 DDR_B_MA[0..15] <14>
DDR_A_D34 DDR_A_MA3 DDR_B_D32 DDR_B_MA0
DDR_A_D35 H5 SA_DQ_34 SA_MA_3 AC5 DDR_A_MA4 DDR_B_D33 M2 SB_DQ_32 SB_MA_0 Y5 DDR_B_MA1
DDR_A_D36 H2 SA_DQ_35 SA_MA_4 AC4 DDR_A_MA5 DDR_B_D34 L4 SB_DQ_33 SB_MA_1 Y10 DDR_B_MA2
DDR_A_D37 H1 SA_DQ_36 SA_MA_5 AD6 DDR_A_MA6 DDR_B_D35 M4 SB_DQ_34 SB_MA_2 AA5 DDR_B_MA3
DDR_A_D38 J4 SA_DQ_37 SA_MA_6 AC3 DDR_A_MA7 DDR_B_D36 L1 SB_DQ_35 SB_MA_3 Y7 DDR_B_MA4
DDR_A_D39 H4 SA_DQ_38 SA_MA_7 AD5 DDR_A_MA8 DDR_B_D37 M1 SB_DQ_36 SB_MA_4 AA6 DDR_B_MA5
DDR_A_D40 F2 SA_DQ_39 SA_MA_8 AC2 DDR_A_MA9 DDR_B_D38 L5 SB_DQ_37 SB_MA_5 Y6 DDR_B_MA6
DDR_A_D41 F1 SA_DQ_40 SA_MA_9 V6 DDR_A_MA10 DDR_B_D39 M5 SB_DQ_38 SB_MA_6 AA7 DDR_B_MA7
DDR_A_D42 D2 SA_DQ_41 SA_MA_10 AC1 DDR_A_MA11 DDR_B_D40 G7 SB_DQ_39 SB_MA_7 Y8 DDR_B_MA8
DDR_A_D43 D3 SA_DQ_42 SA_MA_11 AD4 DDR_A_MA12 DDR_B_D41 J8 SB_DQ_40 SB_MA_8 AA10 DDR_B_MA9
DDR_A_D44 D1 SA_DQ_43 SA_MA_12 V7 DDR_A_MA13 DDR_B_D42 G8 SB_DQ_41 SB_MA_9 R9 DDR_B_MA10
DDR_A_D45 F3 SA_DQ_44 SA_MA_13 AD3 DDR_A_MA14 DDR_B_D43 G9 SB_DQ_42 SB_MA_10 Y9 DDR_B_MA11
DDR_A_D46 C3 SA_DQ_45 SA_MA_14 AD2 DDR_A_MA15 DDR_B_D44 J7 SB_DQ_43 SB_MA_11 AF7 DDR_B_MA12
DDR_A_D47 B3 SA_DQ_46 SA_MA_15 DDR_B_D45 J9 SB_DQ_44 SB_MA_12 P9 DDR_B_MA13
DDR_A_D48 B5 SA_DQ_47 DDR_B_D46 G10 SB_DQ_45 SB_MA_13 AA8 DDR_B_MA14
E6 SA_DQ_48 AP15 DDR_A_DQS#[0..7] <13> J10 SB_DQ_46 SB_MA_14 AG7
DDR_A_D49 DDR_A_DQS#0 DDR_B_D47 DDR_B_MA15
DDR_A_D50 A5 SA_DQ_49 SA_DQS_N_0 AP8 DDR_A_DQS#1 DDR_B_D48 A8 SB_DQ_47 SB_MA_15
DDR_A_D51 D6 SA_DQ_50 SA_DQS_N_1 AJ8 DDR_A_DQS#2 DDR_B_D49 B8 SB_DQ_48
DDR_A_D52 D5 SA_DQ_51 SA_DQS_N_2 AF3 DDR_A_DQS#3 DDR_B_D50 A9 SB_DQ_49 AP18 DDR_B_DQS#0 DDR_B_DQS#[0..7] <14>
DDR_A_D53 E5 SA_DQ_52 SA_DQS_N_3 J3 DDR_A_DQS#4 DDR_B_D51 B9 SB_DQ_50 SB_DQS_N_0 AP11 DDR_B_DQS#1
DDR_A_D54 B6 SA_DQ_53 SA_DQS_N_4 E2 DDR_A_DQS#5 DDR_B_D52 D8 SB_DQ_51 SB_DQS_N_1 AP5 DDR_B_DQS#2
DDR_A_D55 A6 SA_DQ_54 SA_DQS_N_5 C5 DDR_A_DQS#6 DDR_B_D53 E8 SB_DQ_52 SB_DQS_N_2 AJ3 DDR_B_DQS#3
DDR_A_D56 E12 SA_DQ_55 SA_DQS_N_6 C11 DDR_A_DQS#7 DDR_B_D54 D9 SB_DQ_53 SB_DQS_N_3 L3 DDR_B_DQS#4
DDR_A_D57 D12 SA_DQ_56 SA_DQS_N_7 AP14 DDR_A_DQS0 DDR_A_DQS[0..7] <13> DDR_B_D55 E9 SB_DQ_54 SB_DQS_N_4 H9 DDR_B_DQS#5
DDR_A_D58 B11 SA_DQ_57 SA_DQS_P_0 AP9 DDR_A_DQS1 DDR_B_D56 E15 SB_DQ_55 SB_DQS_N_5 C8 DDR_B_DQS#6
DDR_A_D59 A11 SA_DQ_58 SA_DQS_P_1 AK8 DDR_A_DQS2 DDR_B_D57 D15 SB_DQ_56 SB_DQS_N_6 C14 DDR_B_DQS#7
B E11 SA_DQ_59 SA_DQS_P_2 AG3 A15 SB_DQ_57 SB_DQS_N_7 AP17 DDR_B_DQS[0..7] <14> B
DDR_A_D60 DDR_A_DQS3 DDR_B_D58 DDR_B_DQS0
DDR_A_D61 D11 SA_DQ_60 SA_DQS_P_3 H3 DDR_A_DQS4 DDR_B_D59 B15 SB_DQ_58 SB_DQS_P_0 AP12 DDR_B_DQS1
DDR_A_D62 B12 SA_DQ_61 SA_DQS_P_4 E3 DDR_A_DQS5 DDR_B_D60 E14 SB_DQ_59 SB_DQS_P_1 AP6 DDR_B_DQS2
DDR_A_D63 A12 SA_DQ_62 SA_DQS_P_5 C6 DDR_A_DQS6 DDR_B_D61 D14 SB_DQ_60 SB_DQS_P_2 AK3 DDR_B_DQS3
AM3 SA_DQ_63 SA_DQS_P_6 C12 DDR_A_DQS7 DDR_B_D62 A14 SB_DQ_61 SB_DQS_P_3 M3 DDR_B_DQS4
+SM_VREF SM_VREF SA_DQS_P_7 SB_DQ_62 SB_DQS_P_4
F16 DDR_B_D63 B14 H8 DDR_B_DQS5
+SA_DIMM_VREFDQ SA_DIMM_VREFDQ SB_DQ_63 SB_DQS_P_5
F13 C9 DDR_B_DQS6
+SB_DIMM_VREFDQ SB_DIMM_VREFDQ SB_DQS_P_6 C15 DDR_B_DQS7
SB_DQS_P_7
3 OF 9 4 OF 9
LOTES_AZIF0012-P002B_HASWELL LOTES_AZIF0012-P002B_HASWELL
CONN@ CONN@
A A

Title
www.Vinafix.vn
CPU (3/7)
Size Document Number Rev
1.0
LA-9411P
5 4 3 2
DELL
Date: CONFIDENTIAL/PROPRIETARY
Wednesday, April 10, 2013 Sheet 8 of
1
77
5 4 3 2 1
D D
COMPENSATION PU FOR eDP

+VCOMP_OUT
EDP_COMP 2 1
24.9_0402_1% RC73
CAD Note:Trace width=20 mils ,Spacing=25mil,

Max length=100 mils.
JCPU1H Haswell rPGA EDS
TMDSB_CPU_N2 T28 M27 EDP_CPU_AUX#

<26> TMDSB_CPU_N2 TMDSB_CPU_P2 U28 DDIB_TXN0 EDP_AUXN N27 EDP_CPU_AUX EDP_CPU_AUX# <27>
<26> TMDSB_CPU_P2 TMDSB_CPU_N1 T30 DDIB_TXP0 EDP_AUXP P27 EDP_HPD# EDP_CPU_AUX <27>
C <26> TMDSB_CPU_N1 TMDSB_CPU_P1 U30 DDIB_TXN1 EDP_HPD E24 EDP_COMP C
<26> TMDSB_CPU_P1 TMDSB_CPU_N0 U29 DDIB_TXP1 EDP_RCOMP R27
<26> TMDSB_CPU_N0 TMDSB_CPU_P0 V29 DDIB_TXN2 EDP_DISP_UTIL PAD~D T4 @
<26> TMDSB_CPU_P0 TMDSB_CPU_CLK# U31 DDIB_TXP2
<26> TMDSB_CPU_CLK# TMDSB_CPU_CLK V31 DDIB_TXN3 eDP
<26> TMDSB_CPU_CLK DDIB_TXP3 P35 EDP_CPU_LANE_N0
DPC_CPU_LANE_N0 T34 EDP_TXN_0 R35 EDP_CPU_LANE_P0 EDP_CPU_LANE_N0 <27>
<44> DPC_CPU_LANE_N0 U34 DDIC_TXN0 EDP_TXP_0 N34 EDP_CPU_LANE_P0 <27>
DPC_CPU_LANE_P0 EDP_CPU_LANE_N1
<44> DPC_CPU_LANE_P0 DPC_CPU_LANE_N1 U35 DDIC_TXP0 EDP_TXN_1 P34 EDP_CPU_LANE_P1 EDP_CPU_LANE_N1 <27>
<44> DPC_CPU_LANE_N1 DPC_CPU_LANE_P1 V35 DDIC_TXN1 EDP_TXP_1 P33 FDI_CTX_PRX_N0 EDP_CPU_LANE_P1 <27>
<44> DPC_CPU_LANE_P1 DPC_CPU_LANE_N2 U32 DDIC_TXP1 DDI FDI_TXN_0 R33 FDI_CTX_PRX_P0 FDI_CTX_PRX_N0 <16>
<44> DPC_CPU_LANE_N2 T32 DDIC_TXN2 FDI_TXP_0 N32 FDI_CTX_PRX_P0 <16>
DPC_CPU_LANE_P2 FDI_CTX_PRX_N1
<44> DPC_CPU_LANE_P2 U33 DDIC_TXP2 FDI_TXN_1 P32 FDI_CTX_PRX_N1 <16>
DPC_CPU_LANE_N3 FDI_CTX_PRX_P1
<44> DPC_CPU_LANE_N3 DPC_CPU_LANE_P3 V33 DDIC_TXN3 FDI_TXP_1 FDI_CTX_PRX_P1 <16>
<44> DPC_CPU_LANE_P3 DDIC_TXP3
DPD_CPU_LANE_N0 P29
<44> DPD_CPU_LANE_N0 R29 DDID_TXN0
DPD_CPU_LANE_P0
<44> DPD_CPU_LANE_P0 N28 DDID_TXP0
DPD_CPU_LANE_N1
<44> DPD_CPU_LANE_N1 P28 DDID_TXN1
DPD_CPU_LANE_P1
<44> DPD_CPU_LANE_P1 DPD_CPU_LANE_N2 P31 DDID_TXP1
<44> DPD_CPU_LANE_N2 DPD_CPU_LANE_P2 R31 DDID_TXN2
<44> DPD_CPU_LANE_P2 N30 DDID_TXP2
DPD_CPU_LANE_N3
<44> DPD_CPU_LANE_N3 DPD_CPU_LANE_P3 P30 DDID_TXN3
<44> DPD_CPU_LANE_P3 DDID_TXP3
8 OF 9
+VCCIO_OUT
10K_0402_5%
2
CONN@
RC74
HPD INVERSION FOR EDP
B B
1
EDP_HPD#
L2N7002WT1G_SC-70-3
1
D
QC3
2
<27> CPU_EDP_HPD Follow CRB1.5
G
S
3
100K_0402_5%
1
RC75
2
A A
PROPRIETARY NOTE:
Title
CPU (4/7)
www.Vinafix.vn
1.0
5 4 3 2 1
5 4 3 2 1
CFG STRAPS for CPU

CFG2
1K_0402_1%
1
@ RC76
D D
2
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2 definition matches socket pin map definition
0:Lane Reversed
JCPU1I Haswell rPGA EDS
CFG4
@ T11 PAD~D AT1
@ T5 PAD~D AT2 RSVD_TP C23 PAD~D T12 @
1K_0402_1%
RSVD_TP RSVD_TP
1
@ T6 PAD~D AD10 B23 PAD~D T7 @
RSVD RSVD_TP
RC77
D24 PAD~D T13 @
@ T8 PAD~D A34 RSVD_TP D23 PAD~D T14 @
@ T9 PAD~D A35 RSVD_TP RSVD_TP
RSVD_TP
2
@ T10 PAD~D W29
@ T15 PAD~D W28 RSVD_TP AT31 CFG_RCOMP
H_CPU_RSVD G26 RSVD_TP CFG_RCOMP AR21 CFG16
W33 TESTLO_G26 CFG_16 AR23 CFG16 <7>
CFG18
AL30 VSS CFG_18 AP21 CFG17 CFG18 <7>
@ T16 PAD~D
AL29 RSVD CFG_17 AP23 CFG19 CFG17 <7>
@ T17 PAD~D
C
+VCC_CORE
F25 RSVD CFG_19 CFG19 <7> Display Port Presence Strap C
VCC
@ T18 PAD~D C35 AR33 PAD~D T19 @
@ T20 PAD~D B35 RSVD_TP RSVD G6 FC_G6 1 : Disabled; No Physical Display Port
RSVD_TP FC_G6 AM27 PAD~D T22 @
@ T23 PAD~D AL25 RSVD AM26 PAD~D T24 @ CFG4 attached to Embedded Display Port
RSVD_TP RSVD F5 PAD~D T25 @
@ T26 PAD~D W30 RSVD AM2 PAD~D T27 @ 0 : Enabled; An external Display Port device is
@ T28 PAD~D W31 RSVD_TP RSVD K6 PAD~D T29 @
H_CPU_TESTLO W34 RSVD_TP RSVD connected to the Embedded Display Port
TESTLO_W34 E18 PAD~D T30 @
CFG0 AT20 RSVD
<7> CFG0 AR20 CFG_0 U10
CFG1 PAD~D T31 @ CFG6
<7> CFG1 CFG2 AP20 CFG_1 RSVD P10 PAD~D T32 @
<7> CFG2 CFG3 AP22 CFG_2 RSVD CFG5
<7> CFG3 CFG4 AT22 CFG_3 B1
1K_0402_1%
<7> CFG4 CFG_4 NC
1
1K_0402_1%
CFG5 AN22 A2 PAD~D T33 @ @ @
<7> CFG5 AT25 CFG_5 RSVD AR1
CFG6 PAD~D T34 @
<7> CFG6 CFG_6 RSVD_TP
RC79
RC78
CFG7 AN23
<7> CFG7 CFG8 AR24 CFG_7 E21 PAD~D T35 @
<7> CFG8 CFG9 AT23 CFG_8 RSVD_TP E20 PAD~D T36 @
<7> CFG9
2
CFG10 AN20 CFG_9 RSVD_TP
<7> CFG10 CFG11 AP24 CFG_10 AP27
<7> CFG11 AP26 CFG_11 VSS AR26
CFG12
<7> CFG12 CFG13 AN25 CFG_12 VSS
<7> CFG13 CFG14 AN26 CFG_13 AL31
<7> CFG14 AP25 CFG_14 VSS AL32
CFG15
<7> CFG15 CFG_15 VSS
PCIE Port Bifurcation Straps
9 OF 9 Refer 1.2 CRB
2 1 H_CPU_TESTLO 11: (Default) x16 - Device 1 functions 1 and 2 disabled
RC80 49.9_0402_1% LOTES_AZIF0012-P002B_HASWELL
B 2 1 CFG_RCOMP CONN@ 10: x8, x8 - Device 1 function 1 enabled ; function 2 B
RC81 49.9_0402_1%
2 1 H_CPU_RSVD CFG[6:5] disabled
RC82 49.9_0402_1% 01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG7
Note: Reserve this circuit
1
1K_0402_1%
for future compatibility @
RC83
RESET_OUT#
RESET_OUT# <15,16,46>
2
1
@ RC69
6.04K_0402_1%
2
FC_G6
PEG DEFER TRAINING
1: (Default) PEG Train immediately
1
@ RC68
2.67K_0402_1% CFG7 following xxRESETB de assertion
0: PEG Wait for BIOS for training
2
A A
PROPRIETARY NOTE:
Title
CPU (5/7)
www.Vinafix.vn
1.0
5 4 3 2 1
5 4 3 2 1
+1.35V_CPU_VDDQ Source +PWR_SRC_S +VCC_CORE

JCPU1E
@
+1.35V_MEM QC6 +1.35V_CPU_VDDQ Haswell rPGA EDS
330K_0402_5%
AO4304L_SO8
1
+3.3V_ALW2 8 1 AA26
VCC
RC95 @
10U_0603_6.3V6M
7 2 AA28
VCC
1
20K_0402_5%
6 3 1 @ T39 PAD~D K27 AA34
RSVD VCC
100K_0402_5%
CC135 @
@ RC84
5 @ T40 PAD~D L27 AA30
RSVD VCC
1
@ T41 PAD~D T27 AA32
2
RSVD VCC
RC97 @
@ T42 PAD~D V27 AB26
4
2 RSVD VCC AB29
D D
2
RUN_ON_CPU1.5VS3 +1.35V_CPU_VDDQ VCC AB25
+1.35V_MEM VCC
DMN66D0LDW-7_SOT363-6~D
AB27
2
VCC
0.022U_0402_25V7K
AB28
CC23 2 1 0.1U_0402_10V6K AB11 VCC AB30
VDDQ VCC
1
QC4B @
1M_0402_5%
1 AB2 AB31
VDDQ VCC
RC143 @
RUN_ON_CPU1.5VS3# 5 CC22 2 1 0.1U_0402_10V6K AB5 AB33
VDDQ VCC
CC136 @
AB8 AB34
VDDQ VCC
AE11 AB32
4
2 @ PJP5 AE2 VDDQ VCC AC26
2
VDDQ VCC
6
1 2 AE5 AB35
1 2 AE8 VDDQ VCC AC28
<16,35,39,40,45,48,64,66> SIO_SLP_S3# @ VDDQ VCC
QC4A @
RC98 0_0402_5% PAD-OPEN 4x4m AH11 AD25
1 2 2 K11 VDDQ VCC AC30
<46> CPU1.5V_S3_GATE VDDQ VCC
@
RC96 0_0402_5% @ PJP6 N11 AD28

1 2 N8 VDDQ VCC AC32
1
T11 VDDQ VCC AD31
PAD-OPEN 4x4m T2 VDDQ VCC AC34
T5 VDDQ VCC AD34
RUN_ON_CPU1.5VS3# <7,48> VDDQ VCC
T8 AD26
W11 VDDQ VCC AD27
W2 VDDQ VCC AD29
W5 VDDQ VCC AD30
W8 VDDQ VCC AD32
VDDQ VCC AD33
@ T43 PAD~D N26 VCC AD35
K26 RSVD VCC AE26
+VCC_CORE VCC VCC
AL27 AE32
@ T44 PAD~D AK27 RSVD VCC AE28
+1.05V_RUN @ T45 PAD~D RSVD VCC AE30
VCC AG28
VCC AG34
VCC
150_0402_1%
AE34
VCC
1
AF25
VCC
RC85
AF26
C +1.05V_RUN +VCCIO_OUT VCCSENSE_R AL35 VCC AF27 C
@ T46 PAD~D E17 VCC_SENSE VCC AF28
AN35 RSVD VCC AF29
+VCCIO_OUT
2
2 1 A23 VCCIO_OUT VCC AF30
+VCCIO2PCH_R FC_A23 VCC
@RC86
@ RC86 0_0603_5% +VCOMP_OUT F22 AF31
CPU_PWR_DEBUG W32 VCOMP_OUT VCC AF32
@ T48 PAD~D AL16 RSVD VCC AF33
RSVD VCC
10K_0402_5%
RESISTOR STUFFING OPTIONS ARE @ T49 PAD~D J27 AF34
RSVD VCC
1
@ T50 PAD~D AL13 AF35
PROVIDED FOR TESTING PURPOSES RSVD VCC
@
@ T51 PAD~D AG26
VCC
RC89
AH26
H_CPU_SVIDALRT# AM28 VCC AH29
VIDSCLK AM29 VIDALERT VCC AG30
<65> VIDSCLK
2
VIDSOUT AL28 VIDSCLK VCC AG32
VIDSOUT VCC AH32
+VCCIO_OUT AP35 VCC AH35
SVID ALERT <7> CPU_PWR_DEBUG
H27
AP34
VSS
PWR_DEBUG
VSS
VCC
VCC
VCC
AH25
AH27
75_0402_1%
AT35 AH28
RSVD_TP VCC
1
@ T52 PAD~D AR35 AH30

RSVD_TP VCC
RC87
@ T53 PAD~D AR32 AH31

CAD Note: Place the PU resistors close to CPU @ T54 PAD~D AL26 RSVD_TP VCC AH33
RC87 close to CPU 300 - 1500mils +1.05V_RUN +VCCIO2PCH +VCCIO2PCH_R @ T55 PAD~D AT34 RSVD_TP VCC AH34
AL22 VSS VCC AJ25
2
AT33 VSS VCC AJ26

2 1 H_CPU_SVIDALRT# 2 1 2 1 AM21 VSS VCC AJ27
<65> VIDALERT_N VSS VCC
4.7U_0603_6.3V6K
43_0402_5% RC88 @ RC105 0_0603_5% @ RC106 0_0603_5% AM25 AJ28
AM22 VSS VCC AJ29
1 VSS VCC
CC137
AM20 AJ30
AM24 VSS VCC AJ31
+VCCIO_OUT AL19 VSS VCC AJ32
SVID DATA 2
@
AM23 VSS
VSS
VCC
VCC
AJ33
130_0402_1%
AT32 AJ34
VSS VCC
1
AJ35
CAD Note: Place the PU resistors close to CPU VCC
RC90
B G25 B
RC90 close to CPU 300 - 1500mils VCC H25
VCC J25
VCC K25
2
+VCC_CORE VCC L25

VIDSOUT VCC M25
<65> VIDSOUT VCC
+1.35V_CPU_VDDQ Y25 N25
VDDQ DECOUPLING Y26 VCC VCC P25
Y27 VCC VCC R25
Y28 VCC VCC T25
Y29 VCC VCC
VCC
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
1 1 Y30 U25
VCC VCC
@ CC34
1 1 1 1 1 1 1 1 1 1 Y31 U26
+VCC_CORE @CC26
@ VCC VCC
@CC27
@
@CC28
@
@CC29
@
@CC30
@
@CC31
@
@CC32
@
@CC33
@
CC35
+ + Y32 V25
VCC VCC
CC24
CC25
CC26
CC27
CC28
CC29
CC30
CC31
CC32
CC33
Y33 V26
VCC_SENSE 2 2 2 2 2 2 2 2 2 2 2 2
Y34 VCC
VCC
VCC
100_0402_1%
Y35 W26
VCC VCC
1
W27
VCC
RC91
5 OF 9
CONN@
CAD Note: RC92 SHOULD BE PLACED CLOSE TO CPU
2
VCCSENSE 2 1 VCCSENSE_R
<65> VCCSENSE
0_0402_5% RC92 @
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
CAD Note: RC93 SHOULD BE PLACED CLOSE TO CPU 1 1 1 1 1 1 1 1 1 1 1
@CC41
@
@CC37
@
@CC42
@
@CC43
@
@CC38
@
@CC44
@
@CC39
@
@CC45
@
@CC46
@
CC40
CC36
CC41
CC37
CC42
CC43
CC38
CC44
CC39
CC45
CC46
VSSSENSE 2 1 VSSSENSE_R
<65> VSSSENSE VSSSENSE_R <12> 2 2 2 2 2 2 2 2 2 2 2
0_0402_5% RC93 @
1
100_0402_1%
A A
RC94
2
PROPRIETARY NOTE:
www.Vinafix.vn
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU (6/7)
1.0
5 4 3 2 1
5 4 3 2 1
JCPU1F JCPU1G
Haswell rPGA EDS Haswell rPGA EDS
A10 AK34 B34 K10

A13 VSS VSS AK5 B4 VSS VSS K2
D A16 VSS VSS AL1 B7 VSS VSS K29 D
A19 VSS VSS AL10 C1 VSS VSS K3
A7 VSS VSS AL21 C28 VSS VSS L11
AA11 VSS VSS AL23 C30 VSS VSS L26
AA25 VSS VSS E22 C32 VSS VSS L6
AA27 VSS VSS AL3 C34 VSS VSS M11
AB1 VSS VSS AL6 D10 VSS VSS M30
AB10 VSS VSS AL7 D13 VSS VSS M32
AA33 VSS VSS AL8 D16 VSS VSS M34
AA35 VSS VSS AL9 D19 VSS VSS M6
AB3 VSS VSS AM10 D22 VSS VSS N1
AC25 VSS VSS AM13 D25 VSS VSS N10
AB6 VSS VSS E25 D31 VSS VSS N3
AD11 VSS VSS AN10 D7 VSS VSS N4
AC29 VSS VSS AN13 E1 VSS VSS N5
C AC35 VSS VSS AN2 E16 VSS VSS N9 C
AD7 VSS VSS AN21 E4 VSS VSS P11
AE1 VSS VSS AN24 E7 VSS VSS P26
AE10 VSS VSS AN27 F10 VSS VSS P5
AE25 VSS VSS AN30 F11 VSS VSS R11
AE35 VSS VSS AP1 F17 VSS VSS R32
AE7 VSS VSS AP16 F21 VSS VSS T1
AE9 VSS VSS AP19 F23 VSS VSS T10
AF11 VSS VSS AP4 F24 VSS VSS T29
AF6 VSS VSS AP7 F26 VSS VSS T3
AF8 VSS VSS W25 F28 VSS VSS T31
AG11 VSS VSS AR10 F30 VSS VSS T33
AE31 VSS VSS AR16 F34 VSS VSS T4
AE33 VSS VSS AR2 F6 VSS VSS T7
AH1 VSS VSS AR25 F8 VSS VSS U11
AH10 VSS VSS AR28 F9 VSS VSS U27
AH2 VSS VSS AR31 G1 VSS VSS V11
AG27 VSS VSS AR34 G11 VSS VSS V28
AG29 VSS VSS AR4 G2 VSS VSS V30
AH3 VSS VSS AR7 G27 VSS VSS V32
AG33 VSS VSS AT10 G29 VSS VSS V34
AG35 VSS VSS AT13 G3 VSS VSS W1
AH4 VSS VSS AT16 G31 VSS VSS W10
B AH6 VSS VSS AT21 G35 VSS VSS W35 B
AH9 VSS VSS AT3 H10 VSS VSS W7
AJ11 VSS VSS AT30 H26 VSS VSS W9
AJ5 VSS VSS AT4 H6 VSS VSS Y11
AK11 VSS VSS AT7 H7 VSS VSS H11
AK25 VSS VSS B10 J11 VSS VSS AL24
AK26 VSS VSS B13 J26 VSS VSS F19
AK28 VSS VSS B16 J28 VSS VSS T26
AK29 VSS VSS B19 J30 VSS VSS AK35
AK30 VSS VSS B2 J32 VSS VSS_SENSE AK33 VSSSENSE_R <11>
AK32 VSS VSS B22 J34 VSS RSVD PAD~D T56 @
E19 VSS VSS J6 VSS
VSS K1 VSS
VSS
6 OF 9 7 OF 9
LOTES_AZIF0012-P002B_HASWELL LOTES_AZIF0012-P002B_HASWELL
CONN@ CONN@
A A
PROPRIETARY NOTE:
Title
CPU (7/7)
www.Vinafix.vn
1.0
5 4 3 2 1
5 4 3 2 1
+1.35V_MEM
+SA_DIMM_VREFDQ +SA_DIMM_VREFDQ_Q Populate RD1, De-Populate RD3 for Intel DDR3
VREFDQ multiple methods M1
1
1K_0402_1%
@ RD26
0_0402_5%
2 1 Populate RD7, De-Populate RD1 for Intel DDR3
RD19
+SA_DIMM1_VREFDQ
JDIMM1 H=5.2mm
2
@ QD6A
1 6 RD17 1 2 2_0402_1% +DIMM1_VREF_DQ
@ RD1 1 2 0_0402_5% +1.35V_MEM +1.35V_MEM
+SA_DIMM1_VREFDQ
1K_0402_1%
D 1 JDIMM1 D
1K_0402_1%
@ RD3 1 2 0_0402_5% 1 2
+V_DDR_REF
2
VREF_DQ VSS1
1
RD27
CD47 3 4 DDR_A_D4
VSS2 DQ4
RD18
2.2U_0402_6.3V6M
0.1U_0402_25V6
0.022U_0402_16V7K DDR_A_D0 5 6 DDR_A_D5
2 DDR_A_D1 7 DQ0 DQ5 8
1 1 DQ1 VSS3
@ 9 10 DDR_A_DQS#0
2 VSS4 DQS#0
CD1
CD2
11 12 DDR_A_DQS0
2
DM0 DQS0
1
13 14
RC109 2 @ 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6
DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
24.9_0402_1% DQ3 DQ7
19 20
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12
2
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
DDR_HVREF_RST_PCH 25 DQ9 DQ13 26
<7,14,18> DDR_HVREF_RST_PCH 27 VSS9 VSS10 28
DDR_A_DQS#1
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#_R
31 DQS1 RESET# 32
+1.35V_MEM DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
+SM_VREF +SM_VREF_Q 37 DQ11 DQ15 38
@ RD29 DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DQ16 DQ20
1
1K_0402_1%
0_0402_5% DDR_A_D17 41 42 DDR_A_D21
2 1 43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46
RD22
@ QD7 +SM_VREF_DIMM DDR_A_DQS2 47 DQS#2 DM2 48
L2N7002WT1G_SC-70-3 49 DQS2 VSS17 50 DDR_A_D22
2
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
3 1 RD20 1 2 2_0402_1% 53 DQ18 DQ23 54
S
DDR_A_D19
55 DQ19 VSS19 56 DDR_A_D28
DQ24 DQ29
1K_0402_1%
DDR_A_D25 59 60
G
2
DQ25 VSS21
1
1K_0402_1%
1 61 62 DDR_A_DQS#3
VSS22 DQS#3
1
RD21
63 64 DDR_A_DQS3
DM3 DQS3
RD28
CD48 65 66
0.022U_0402_16V7K DQ26 DQ30
2 DDR_A_D27 69 70 DDR_A_D31
2
@ 71 DQ27 DQ31 72
2
VSS25 VSS26
C C
1
RC110
24.9_0402_1% 73 74 DDR_CKE1_DIMMA
<8> DDR_CKE0_DIMMA 75 CKE0 CKE1 76 DDR_CKE1_DIMMA <8>
DDR_HVREF_RST_PCH 77 VDD1 VDD2 78 DDR_A_MA15
2
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14

<8> DDR_A_BS2 81 BA2 A14 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
+V_DDR_REF, +SA_DIMM1_VREFDQ, +SA_DIMM_VREFDQ, +DIMM1_VREF_DQ DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
traces should be at least 20 mils wide and 20 mils spacing to other signals /planes. DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
<8> M_CLK_DDR0 103 CK0 CK1 104 M_CLK_DDR1 <8>
Layout Note: M_CLK_DDR#0 M_CLK_DDR#1
<8> M_CLK_DDR#0 105 CK0# CK1# 106 M_CLK_DDR#1 <8>
Place near JDIMM1 Layout Note: DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <8>
Place near JDIMM1.203,204 <8> DDR_A_BS0
DDR_A_BS0 109 110 DDR_A_RAS#
111 BA0 RAS# 112 DDR_A_RAS# <8>
DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA#
<8> DDR_A_WE# 115 WE# S0# 116 DDR_CS0_DIMMA# <8>
DDR_A_CAS# M_ODT0
<8> DDR_A_CAS# 117 CAS# ODT0 118 M_ODT0 <8>
+1.35V_MEM DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1 +DIMM1_VREF_CA
121 A13 ODT1 122 M_ODT1 <8>
<8> DDR_CS1_DIMMA# 123 S1# NC2 124
125 VDD17 VDD18 126 2 1
NCTEST VREF_CA +V_DDR_REF
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+0.675V_DDR_VTT 127 128 @ RD5 0_0402_5%

1 1 1 1 DQ32 DQ36
DDR_A_D33 131 132 DDR_A_D37 2 1
DQ33 DQ37 +SM_VREF_DIMM
CD3
CD4
CD5
CD6
133 134 @ RD13 0_0402_5%

VSS29 VSS30
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_A_DQS#4 135 136

2 2 2 2 DDR_A_DQS4 137 DQS#4 DM4 138
1 1 1 1 DQS4 VSS31
2.2U_0402_6.3V6M
0.1U_0402_25V6
139 140 DDR_A_D38
VSS32 DQ38
CD17
CD18
CD19
CD20
B DDR_A_D34 141 142 DDR_A_D39 @ B

DDR_A_D35 143 DQ34 DQ39 144
DQ35 VSS33 1 1
2 2 2 2
CD15
CD16
145 146 DDR_A_D44
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5 2 2
153 VSS36 DQS#5 154 DDR_A_DQS5
+1.35V_MEM 155 DM5 DQS5 156
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162
VSS39 VSS40
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_A_D48 163 164 DDR_A_D52

DQ48 DQ52
330U_2.5V_M
DDR_A_D49 165 166 DDR_A_D53

167 DQ49 DQ53 168
1 VSS41 VSS42
@ CD13
1 1 1 1 1 1 1 DDR_A_DQS#6 169 170

DQS#6 DM6
CD7
CD8
CD9
CD10
CD11
CD12
CD14
+ DDR_A_DQS6 171 172

<8> DDR_A_DQS#[0..7] 173 DQS6 VSS43 174 DDR_A_D54
2 2 2 2 2 2 2 2 <8> DDR_A_D[0..63] 177 DQ50 DQ55 178
DDR_A_D51
179 DQ51 VSS45 180 DDR_A_D60
<8> DDR_A_DQS[0..7] 181 VSS46 DQ60 182
DDR_A_D56 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184
<8> DDR_A_MA[0..15] 185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
+3.3V_RUN 195 DQ59 DQ63 196
All VREF traces should DIMM1_SA0 197 VSS51 VSS52 198
have 10 mil trace width 199 SA0 EVENT# 200
201 VDDSPD SDA 202 DDR_XDP_WAN_SMBDAT <7,14,15,18,27,31>
DIMM1_SA1
+1.35V_MEM SA1 SCL DDR_XDP_WAN_SMBCLK <7,14,15,18,27,31>
0.1U_0402_25V6
2.2U_0402_6.3V6M
1 203 204
+0.675V_DDR_VTT VTT1 VTT2 +0.675V_DDR_VTT
1
CD22
@ RD4 205 206

G1 G2
CD21
0_0402_5%
1
2 1 2 TYCO_2-2013290-1
@ RD2 2 CONN@
A
@ QD9
1K_0402_5% +V_DDR_REF, +SM_VREF_DIMM, +DIMM1_VREF_CA,+SM_VREF, +DIMM1_VREF_CA A
L2N7002WT1G_SC-70-3 traces should be at least 20 mils wide and 20 mils spacing to other signals /planes.
2
3 1 1 2
S
DDR3_DRAMRST#_Q DDR3_DRAMRST#_R
<7> DDR3_DRAMRST#_CPU DDR3_DRAMRST#_R <14>
@ RD25 0_0402_5%
1
2
@ RD24
4.99K_0402_1% DDR_HVREF_RST_PCH
1 2 DIMM1_SA0
1
@ RD6 0_0402_5% PROPRIETARY NOTE: Compal Electronics, Inc.
www.Vinafix.vn
2
CD45 @ 1 2 DIMM1_SA1 Title

@ RD7 0_0402_5%
2
0.047U_0402_16V4Z
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDRIII-SODIMM SLOT1
1.0
5 4 3 2 1
5 4 3 2 1
Populate RD4, De-Populate RD9 for Intel DDR3

Populate RD8, De-Populate RD8 for Intel DDR3
JDIMM2 H=9.2mm
+DIMM2_VREF_DQ
+1.35V_MEM @ RD8 1 2 0_0402_5% +1.35V_MEM +1.35V_MEM
+SB_DIMM_VREFDQ +SB_DIMM_VREFDQ_Q +SB_DIMM2_VREFDQ
JDIMM2
1
1K_0402_1%
@ RD31 +V_DDR_REF @ RD9 1 2 0_0402_5% 1 2
0_0402_5% 3 VREF_DQ VSS1 4 DDR_B_D4
VSS2 DQ4
2.2U_0402_6.3V6M
0.1U_0402_25V6
2 1 DDR_B_D0 5 6 DDR_B_D5
RD15
D DQ0 DQ5 D
DDR_B_D1 7 8
+SB_DIMM2_VREFDQ 9 DQ1 VSS3 10 DDR_B_DQS#0
1 1
2
@ QD6B VSS4 DQS#0
CD24
CD23
11 12 DDR_B_DQS0
DMN66D0LDW-7_SOT363-6~D 13 DM0 DQS0 14
4 3 RD14 1 2 2_0402_1% DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6
2 @ 2 DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
DQ3 DQ7
1K_0402_1%
0.022U_0402_16V7K
19 20
VSS7 VSS8
1
1K_0402_1%
DDR_B_D8 21 22 DDR_B_D12
5
DQ8 DQ12
1
RD30
1 DDR_B_D9 23 24 DDR_B_D13
DQ9 DQ13
RD16
25 26
VSS9 VSS10
CD46
DDR_B_DQS#1 27 28
@ DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#_R
DDR3_DRAMRST#_R <13>
2
2 31 DQS1 RESET# 32
2
DDR_B_D10 33 VSS11 VSS12 34 DDR_B_D14
DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15
37 DQ11 DQ15 38
VSS13 VSS14
1
DQ16 DQ20
24.9_0402_1%
DQ17 DQ21
RC108
43 44
DDR_B_DQS#2 45 VSS15 VSS16 46
<7,13,18> DDR_HVREF_RST_PCH 47 DQS#2 DM2 48
DDR_B_DQS2
2
49 DQS2 VSS17 50 DDR_B_D22

DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
+V_DDR_REF, +SB_DIMM2_VREFDQ, +SB_DIMM_VREFDQ, +DIMM2_VREF_DQ 63 VSS22 DQS#3 64 DDR_B_DQS3
traces should be at least 20 mils wide and 20 mils spacing to other signals /planes. 65 DM3 DQS3 66
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
71 DQ27 DQ31 72
VSS25 VSS26
C DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB C
<8> DDR_B_DQS#[0..7] <8> DDR_CKE2_DIMMB 75 CKE0 CKE1 76 DDR_CKE3_DIMMB <8>
77 VDD1 VDD2 78 DDR_B_MA15
<8> DDR_B_D[0..63] 79 NC1 A15 80
DDR_B_BS2 DDR_B_MA14
<8> DDR_B_BS2 81 BA2 A14 82
<8> DDR_B_DQS[0..7] 83 VDD3 VDD4 84
DDR_B_MA12 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
<8> DDR_B_MA[0..15] 87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
Layout Note: M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
Place near JDIMM2 <8> M_CLK_DDR2 103 CK0 CK1 104 M_CLK_DDR3 <8>
M_CLK_DDR#2 M_CLK_DDR#3
<8> M_CLK_DDR#2 105 CK0# CK1# 106 M_CLK_DDR#3 <8>
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <8>
DDR_B_BS0 109 110 DDR_B_RAS#
<8> DDR_B_BS0 111 BA0 RAS# 112 DDR_B_RAS# <8>
DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS2_DIMMB#
<8> DDR_B_WE# 115 WE# S0# 116 DDR_CS2_DIMMB# <8>
DDR_B_CAS# M_ODT2
<8> DDR_B_CAS# 117 CAS# ODT0 118 M_ODT2 <8>
+1.35V_MEM DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3 +DIMM2_VREF_CA
121 A13 ODT1 122 M_ODT3 <8>
DDR_CS3_DIMMB#
<8> DDR_CS3_DIMMB# 123 S1# NC2 124
125 VDD17 VDD18 126 2 1
NCTEST VREF_CA +V_DDR_REF
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
127 128 @ RD10 0_0402_5%

1 1 1 1 DQ32 DQ36
DDR_B_D33 131 132 DDR_B_D37 2 1 +SM_VREF_DIMM
DQ33 DQ37
CD25
CD26
CD27
CD28
133 134 @ RD23 0_0402_5%

DDR_B_DQS#4 135 VSS29 VSS30 136
2 2 2 2 DQS#4 DM4
2.2U_0402_6.3V6M
0.1U_0402_25V6
DDR_B_DQS4 137 138
139 DQS4 VSS31 140 DDR_B_D38 @
DQ34 DQ39 1 1
CD37
CD38
DDR_B_D35 143 144
145 DQ35 VSS33 146 DDR_B_D44
B DQ40 DQ45 B
DDR_B_D41 149 150 2 2
+1.35V_MEM 153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
161 DQ43 DQ47 162
VSS39 VSS40
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_D48 163 164 DDR_B_D52

DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
1 DQ49 DQ53
@ CD35
330U_2.5V_M
1 1 1 1 1 1 1 167 168
VSS41 VSS42
CD29
CD30
CD31
CD32
CD33
CD34
CD36
+ DDR_B_DQS#6 169 170

DDR_B_DQS6 171 DQS#6 DM6 172
+V_DDR_REF, +SM_VREF_DIMM, +DIMM1_VREF_CA,+SM_VREF, +DIMM1_VREF_CA
173 DQS6 VSS43 174 DDR_B_D54 traces should be at least 20 mils wide and 20 mils spacing to other signals /planes.
2 2 2 2 2 2 2 2 DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D60
DDR_B_D57 183 DQ56 DQ61 184
187 VSS48 DQS#7 188 DDR_B_DQS7
189 DM7 DQS7 190
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
+3.3V_RUN 195 DQ59 DQ63 196
DIMM2_SA0 197 VSS51 VSS52 198
Layout Note: 199 SA0 EVENT# 200
Place near JDIMM2.203,204 2 1 201 VDDSPD SDA 202 DDR_XDP_WAN_SMBDAT <7,13,15,18,27,31>
DIMM2_SA0 DIMM2_SA1
SA1 SCL DDR_XDP_WAN_SMBCLK <7,13,15,18,27,31>
0.1U_0402_25V6
2.2U_0402_6.3V6M
@ RD11 0_0402_5% +0.675V_DDR_VTT

203 204 +0.675V_DDR_VTT
VTT1 VTT2
1 1
CD43
CD44
205 206
G1 G2
TYCO_2-2013311-1
+3.3V_RUN 2 2 CONN@
+0.675V_DDR_VTT 2 1 DIMM2_SA1
@ RD12 0_0402_5%
A A
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
CD39
CD40
CD41
CD42
2 2 2 2 DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: Compal Electronics, Inc.
www.Vinafix.vn
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDRIII-SODIMM SLOT2
1.0
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
PCH XDP
USB_OC0#_R PXDP@ RH3 1 2 0_0402_5% XDP_FN0 +3.3V_ALW_PCH JXDP2
<19> USB_OC0#_R
330K_0402_1%
USB_OC1#_R PXDP@ RH4 1 2 0_0402_5% XDP_FN1 1 2
<19> USB_OC1#_R GND0 GND1
1
USB_OC2# PXDP@ RH6 1 2 0_0402_5% XDP_FN2 +3.3V_ALW_PCH 3 4 XDP_FN16
<19> USB_OC2# OBSFN_A0 OBSFN_C0
RH5
USB_OC3# PXDP@ RH7 1 2 0_0402_5% XDP_FN3 5 6 XDP_FN17
<19> USB_OC3# OBSFN_A1 OBSFN_C1
0.1U_0402_25V6
USB_OC4#_R PXDP@ RH8 1 2 0_0402_5% XDP_FN4 7 8
<19> USB_OC4#_R USB_OC5# PXDP@ RH9 1 2 0_0402_5% XDP_FN5 XDP_FN0 9 GND2 GND3 10 XDP_FN8
<19> USB_OC5# 1 OBSDATA_A0 OBSDATA_C0
PXDP@
USB_OC6# PXDP@ RH17 1 2 0_0402_5% XDP_FN6 XDP_FN1 11 12 XDP_FN9
2
<19> USB_OC6# OBSDATA_A1 OBSDATA_C1
CH2
SIO_EXT_SMI# PXDP@ RH10 1 2 0_0402_5% XDP_FN7 13 14
<19,46> SIO_EXT_SMI# HDD_DET# PXDP@ RH11 1 2 0_0402_5% XDP_FN8 XDP_FN2 15 GND4 GND5 16 XDP_FN10
PCH_INTVRMEN <15,31> HDD_DET# BBS_BIT0_R PXDP@ RH13 1 2 0_0402_5% XDP_FN9 2 XDP_FN3 17 OBSDATA_A2 OBSDATA_C2 18 XDP_FN11
D D
PCH_GPIO36 PXDP@ RH12 1 2 0_0402_5% XDP_FN10 19 OBSDATA_A3 OBSDATA_C3 20
<20> PCH_GPIO36 GND6 GND7
330K_0402_1%
PCH_GPIO37 PXDP@ RH14 1 2 0_0402_5% XDP_FN11 21 22
<20> PCH_GPIO37 OBSFN_B0 OBSFN_D0
1
MCARD_PCIE_SATA# PXDP@ RH16 1 2 0_0402_5% XDP_FN12 23 24

<20,38,45> MCARD_PCIE_SATA# OBSFN_B1 OBSFN_D1
@ RH18
PCH_GPIO49 PXDP@ RH19 1 2 0_0402_5% XDP_FN13 25 26

<20> PCH_GPIO49 GND8 GND9
LANCLK_REQ# PXDP@ RH20 1 2 0_0402_5% XDP_FN14 XDP_FN4 27 28 XDP_FN12
<17,33> LANCLK_REQ# 1 2 29 OBSDATA_B0 OBSDATA_D0 30
MMICLK_REQ# PXDP@ RH22 0_0402_5% XDP_FN15 XDP_FN5 XDP_FN13
<17,36> MMICLK_REQ# SIO_EXT_WAKE# PXDP@ RH24 1 2 0_0402_5% XDP_FN16 31 OBSDATA_B1 OBSDATA_D1 32 +3.3V_ALW_PCH_JTAG
2
<17,20,45> SIO_EXT_WAKE# PCH_GPIO35 PXDP@ RH25 1 2 0_0402_5% XDP_FN17 XDP_FN6 33 GND10 GND11 34 XDP_FN14
<20> PCH_GPIO35 PCH_RSMRST#_Q PXDP@ RH26 1 2 1K_0402_1% RSMRST#_XDP XDP_FN7 35 OBSDATA_B2 OBSDATA_D2 36 XDP_FN15
<16,47> PCH_RSMRST#_Q OBSDATA_B3 OBSDATA_D3
RESET_OUT# PXDP@ RH27 1 2 1K_0402_1% RESET_OUT#_R 37 38
<10,16,46> RESET_OUT# GND12 GND13
1
RSMRST#_XDP 39 40 +1.05V_RUN
1 2 PCH_PWRBTN#_XDP 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42 RH52
INTVRMEN - INTEGRATED SUS 1.05V VRM <7,16> SIO_PWRBTN#_R
PXDP@ RH28 0_0402_5% 43 HOOK1 ITPCLK#/HOOK5 44 210_0402_1%
VCC_OBS_AB VCC_OBS_CD +3.3V_ALW_PCH
ENABLE 45 46 RESET_OUT#_R
47 HOOK2 RESET#/HOOK6 48 XDP_DBRESET#
High - Enable Internal VRs
2
PXDP@ RH30 0_0402_5% 49 HOOK3 DBR#/HOOK7 50 XDP_DBRESET# <7,16>
Low - Enable External VRs 1 2 DDR_XDP_WAN_SMBDAT_R2 51 GND14 GND15 52 PCH_JTAG_TDO
<7,13,14,18,27,31> DDR_XDP_WAN_SMBDAT SDA TD0
1 2 DDR_XDP_WAN_SMBCLK_R2 53 54 PCH_JTAG_RST_R 1 2 PCH_JTAG_RST
<7,13,14,18,27,31> DDR_XDP_WAN_SMBCLK SCL TRST#
PXDP@ RH31 0_0402_5% 55 56 PCH_JTAG_TDI @ RH32 0_0402_5%
PCH_JTAG_TCK 57 TCK1 TDI 58 PCH_JTAG_TMS
TCK0 TMS
1
+3.3V_RUN +3.3V_ALW_PCH 59 60
GND16 GND17 RH56 PXDP@
SAMTE_BSH-030-01-L-D-A CONN@ 100_0402_1%
1 2 SPKR 1 2 PCH_AZ_SDOUT
@ RH34 10K_0402_5% @ RH35 1K_0402_1%
2
+3.3V_RUN
NO REBOOT STRAP FLASH DESCRIPTOR SECURITY OVERRIDE HDD_DET# 1 2
DISABLED WHEN LOW (DEFAULT) LOW = DESABLED (DEFAULT) 10K_0402_5% RH36
BBS_BIT0_R 2 1
CH4
ENABLED WHEN HIGH HIGH = ENABLED 4.7K_0402_5% RH37
1 2 PCH_RTCX1_R 1 2 PCH_RTCX1
@ RH38 0_0402_5%
C C
15P_0402_50V8J
1
+3.3V_ALW_PCH
YH1 RH39 UH1A DH82LPMS-QCG1-B0_FCBGA695~D
+3.3V_RUN 32.768KHZ_12.5PF_Q13FC1350000~D 10M_0402_5%
1 2 PCH_AZ_SYNC BC8 PSATA_PRX_DTX_N0_C
PSATA_PRX_DTX_N0_C <31>
2
1 2 PCH_GPIO33 @ RH41 1K_0402_1% B5 SATA_RXN_0 BE8 PSATA_PRX_DTX_P0_C
PSATA_PRX_DTX_P0_C <31>
2
@ RH40 10K_0402_5% CH5 RTCX1 SATA_RXP_0
HDD
1 2 PCH_RTCX2 B4 AW8 PSATA_PTX_DRX_N0_C
Follow Check list 1.0 RTCX2 SATA_TXN_0 AY8 PSATA_PTX_DRX_P0_C PSATA_PTX_DRX_N0_C <31>
RTC
RH42 1 2 20K_0402_5% 18P_0402_50V8J SRTCRST# B9 SATA_TXP_0 PSATA_PTX_DRX_P0_C <31>
+RTC_CELL SRTCRST# BC10 SATA_ODD_PRX_DTX_N1_C
SATA_RXN_1 SATA_ODD_PRX_DTX_N1_C <32>
RH43 1 2 1M_0402_5% INTRUDER# A8 BE10 SATA_ODD_PRX_DTX_P1_C
INTRUDER# SATA_RXP_1 SATA_ODD_PRX_DTX_P1_C <32>
ODD/ E Module Bay
PCH_INTVRMEN G10 AV10 SATA_ODD_PTX_DRX_N1_C
INTVRMEN SATA_TXN_1 AW10 SATA_ODD_PTX_DRX_P1_C SATA_ODD_PTX_DRX_N1_C <32>
RH44 1 2 20K_0402_5% PCH_RTCRST# D9 SATA_TXP_1 SATA_ODD_PTX_DRX_P1_C <32>
RTCRST# BB9 SATA_PRX_DKTX_N2_C
SATA_RXN_2 SATA_PRX_DKTX_N2_C <44>
BD9 SATA_PRX_DKTX_P2_C
<35> PCH_RTCRST# SATA_RXP_2 SATA_PRX_DKTX_P2_C <44>
CMOS_CLR1 CMOS setting PCH_AZ_BITCLK B25 DOCK
HDA_BCLK AY13 SATA_PTX_DKRX_N2_C
1 2 1 2 PCH_AZ_SYNC A22 SATA_TXN_2 AW13 SATA_PTX_DKRX_P2_C SATA_PTX_DKRX_N2_C <44>
Shunt Clear CMOS 1 2 1 2 HDA_SYNC SATA_TXP_2 SATA_PTX_DKRX_P2_C <44>
Open Keep CMOS SPKR AL10 BC12

<30> SPKR SPKR SATA_RXN_3 BE12
@ @ PCH_AZ_RST# C24 SATA_RXP_3
ME1 SHORT PADS~D CMOS1 SHORT PADS~D HDA_RST# AR13
ME_CLR1 TPM setting 1 2 1 2 L22 SATA_TXN_3 AT13
AZALIA
PCH_AZ_CODEC_SDIN0
SATA
1U_0402_6.3V6K <30> PCH_AZ_CODEC_SDIN0 HDA_SDI0 SATA_TXP_3
Shunt Clear ME RTC Registers CH6 1U_0402_6.3V6K CH7
CMOS place near DIMM PCH_AZ_MDC_SDIN1 K22
<47> PCH_AZ_MDC_SDIN1 HDA_SDI1
Open Keep ME RTC Registers BD13 PCIE_SATA_PRX_WANTX_N4
SATA_RXN4/PERN1 PCIE_SATA_PRX_WANTX_N4 <38>
G22 BB13 PCIE_SATA_PRX_WANTX_P4
HDA_SDI2 SATA_RXP4/PERP1 PCIE_SATA_PRX_WANTX_P4 <38>
WWAN (JMINI1)
F22 AV15 PCIE_SATA_PTX_WANRX_N4
HDA_SDI3 SATA_TXN4/PETN1 AW15 PCIE_SATA_PTX_WANRX_P4 PCIE_SATA_PTX_WANRX_N4 <38>
SATA_TXP4/PETP1 PCIE_SATA_PTX_WANRX_P4 <38> SATA by default
B
<45> ME_FWP 1 2 PCH_AZ_SDOUT A24 B
RH45 1K_0402_1% HDA_SDO BC14
PCH_GPIO33 B17 SATA_RXN5/PERN2 BE14
DOCKEN#/GPIO33 SATA_RXP5/PERP2
+3.3V_ALW_PCH USB30_SMI# C22 AP15
<32> USB30_SMI# HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2 AR15
SATA_TXP5/PETP2
1
0_0603_5%
RH46
PXDP@
AY5 SATA_COMP
SATA_RCOMP
AP3 SATA_ACT#
SATALED# SATA_ACT# <24>
2
RH47 2 1 51_0402_1% PCH_JTAG_TCK AB3 AT1 HDD_DET#

JTAG_TCK SATA0GP/GPIO21 HDD_DET# <15,31>
+3.3V_ALW_PCH_JTAG RH48 1 2 210_0402_1% PCH_JTAG_TMS AD1 AU2 BBS_BIT0_R 1 3
S
JTAG_TMS SATA1GP/GPIO19 PCH_SATA_MOD_EN# <46>
RH50 1 2 210_0402_1% PCH_JTAG_TDI AE2 BD4 SATA_IREF 2 1
JTAG
JTAG_TDI SATA_IREF +1.5V_RUN
0_0402_5% @ RH51 QH2
G
2
PCH_JTAG_TDO AD3 BA2 BSS138W-7-F_SOT323-3~D
JTAG_TDO TP9
PXDP@ RH54
PXDP@ RH55
PAD~D T57 @
<7,16> PCH_PLTRST#
1 2 PCH_TP25 F8 BB2
TP25 TP8
100_0402_1%
100_0402_1%
@ RH53 0_0402_5% PAD~D T58 @

1
C26
@ T59 PAD~D TP22
PCH_JTAG_RST AB6
TP20
SATA Impedance Compensation
2
1 OF 11
HDA for Codec and MDC DH82LPMS-QCG1-B0_FCBGA695~D

SATA_COMP 1 2
+1.5V_RUN
7.5K_0402_1% RH57
1 2 PCH_AZ_SDOUT 1 2 PCH_AZ_SDOUT
UH1 change PN to SA00005NE2L IC A31 DH82LPMS QCG1 B0 FCBGA 695P PCH
<47> PCH_AZ_MDC_SDOUT <30> PCH_AZ_CODEC_SDOUT
RH58 33_0402_5% RH59 33_0402_5% CAD note:
1 2 PCH_AZ_SYNC 1 2 PCH_AZ_SYNC
A <47> PCH_AZ_MDC_SYNC
RH60 33_0402_5%
<30> PCH_AZ_CODEC_SYNC
RH61 33_0402_5%
Place the resistor within 500 mils of the PCH. Avoid A
1 2 PCH_AZ_RST# 1 2 PCH_AZ_RST# routing next to clock pins.

<47> PCH_AZ_MDC_RST# <30> PCH_AZ_CODEC_RST#
RH62 33_0402_5% RH63 33_0402_5%
1 2 PCH_AZ_BITCLK 1 2 PCH_AZ_BITCLK
<47> PCH_AZ_MDC_BITCLK <30> PCH_AZ_CODEC_BITCLK
RH64 33_0402_5% RH65 33_0402_5%
27P_0402_50V8J
27P_0402_50V8J
@ CH8
@ CH9
1 1
PROPRIETARY NOTE:
2 2 Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PCH (1/9)
1.0
5 4 3 2 1
www.Vinafix.vn
5 4 3 2 1
+3.3V_RUN
1 2 RPH4
+PCH_VCCDSW3_3 @ RH66 0_0402_5% PCI_PIRQA# 1 8
+3.3V_RUN +RTC_CELL PCI_PIRQB# 2 7
@ CH10 PCI_PIRQC# 3 6
330K_0402_1%
1 2 PCH_PCIE_WAKE# 1 2 PCI_PIRQD# 4 5
2
RH92 10K_0402_5%
RH67
1 2 SIO_SLP_LAN# 0.1U_0402_25V6 8.2K_8P4R_5%
@ RH80 10K_0402_5% 1
P
<7,15> XDP_DBRESET# B 4 SYS_RESET#
2 1 ME_RESET# 2 O SYS_RESET# <35>
1
A
G
+3.3V_ALW_PCH @ RH70 8.2K_0402_5% @ UC3 +3.3V_ALW2 RPH6
74AHC1G09GW_TSSOP5~D @ CH11 LCD_CBL_DET# 4 5
3
1 2 PCH_GPIO55 PCH_GPIO3 3 6
1 2 PCH_PCIE_WAKE# DSWODVREN CAM_MIC_CBL_DET# 2 7
D @ RH78 10K_0402_5% 0.1U_0402_25V6 1 8 D
1
330K_0402_1%
1K_0402_1%
1 2 SUS_STAT#/LPCPD#
@ RH81
@ RH76
@ RH73 10K_0402_5% SIO_SLP_A# 1 10K_8P4R_5%
P
B
2
1 2 ME_SUS_PWR_ACK PCH_DPWROK 1 2 PCH_RSMRST#_R 4 PM_APWROK_R
RH75 10K_0402_5% @ RH79 0_0402_5% PM_APWROK 2 O
<46> PM_APWROK
G
A PCH_CRT_DDC_CLK 2 1
2
UH2 2.2K_0402_5% RH88
3
TC7SH08FU_SSOP5~D PCH_CRT_DDC_DAT 2 1
1
RESET_OUT# 1 2 SYS_PWROK 2.2K_0402_5% RH89
@ RH85 0_0402_5%
1 2
+3.3V_RUN @ RH87 0_0402_5%
DGPU_PWR_EN# 2 1
1 2 CLKRUN# ME_SUS_PWR_ACK_R 1 2 SUSACK#_R DSWODVREN - ON DIE DSW VR ENABLE A16 SWAP OVERRIDE STRAP 8.2K_0402_5% RH328
RH90 8.2K_0402_5% @ RH91 0_0402_5%
1 2 ME_RESET#
@ RH93 8.2K_0402_5%
HIGH = ENABLED (DEFAULT)
LOW = DISABLED STP_A16OVR LOW = A16 SWAP OVERRIDE PCH_DDPB_CTRLCLK 2 1
HIGH = DEFAULT 2.2K_0402_5% RH255
1 2 PCH_DPWROK PCH_DDPB_CTRLDATA 2 1
RH120 100K_0402_5% 2.2K_0402_5% RH256
UH1B LPT_PCH_M_EDS
DMI_CTX_PRX_N0 AW22
<6> DMI_CTX_PRX_N0 DMI_RXN_0
DMI_CTX_PRX_N1 AR20
<6> DMI_CTX_PRX_N1 DMI_RXN_1 AJ35 FDI_CTX_PRX_N0
FDI_RXN_0 FDI_CTX_PRX_N0 <9>
DMI_CTX_PRX_N2 AP17
<6> DMI_CTX_PRX_N2 DMI_RXN_2
DMI_CTX_PRX_N3 AV20 AL35 FDI_CTX_PRX_N1
<6> DMI_CTX_PRX_N3 DMI_RXN_3 FDI_RXN_1 FDI_CTX_PRX_N1 <9> UH1E LPT_PCH_M_EDS
DMI_CTX_PRX_P0 AY22 AJ36 FDI_CTX_PRX_P0
<6> DMI_CTX_PRX_P0 DMI_RXP_0 FDI_RXP_0 FDI_CTX_PRX_P0 <9>
DMI_CTX_PRX_P1 AP20 PCH_CRT_BLU T45 R40 PCH_DDPB_CTRLCLK PCH_DDPB_CTRLCLK <26>
<6> DMI_CTX_PRX_P1 DMI_RXP_1 <25> PCH_CRT_BLU VGA_BLUE DDPB_CTRLCLK
AL36 FDI_CTX_PRX_P1
FDI_RXP_1 FDI_CTX_PRX_P1 <9>
DMI_CTX_PRX_P2 AR17 PCH_CRT_GRN U44 R39 PCH_DDPB_CTRLDATA
C <6> DMI_CTX_PRX_P2 AW20 DMI_RXP_2 AV43 <25> PCH_CRT_GRN VGA_GREEN DDPB_CTRLDATA PCH_DDPB_CTRLDATA <26> C
DMI_CTX_PRX_P3 PAD~D T62 @
<6> DMI_CTX_PRX_P3 DMI_RXP_3 TP16 V45 R35
PCH_CRT_RED PCH_DDPC_CTRLCLK <29>
<25> PCH_CRT_RED VGA_RED DDPC_CTRLCLK
DMI_CRX_PTX_N0 BD21 AY45 PAD~D T63 @
<6> DMI_CRX_PTX_N0 DMI_TXN_0 TP5
DMI_CRX_PTX_N1 BE20 PCH_CRT_DDC_CLK M43 R36
<6> DMI_CRX_PTX_N1 DMI_TXN_1 DMI FDI <25> PCH_CRT_DDC_CLK VGA_DDC_CLK DDPC_CTRLDATA PCH_DDPC_CTRLDATA <29>
AV45 PAD~D T60 @
DMI_CRX_PTX_N2 BD17 TP15 PCH_CRT_DDC_DAT M45 N40
CRT
<6> DMI_CRX_PTX_N2 DMI_TXN_2 <25> PCH_CRT_DDC_DAT VGA_DDC_DATA DDPD_CTRLCLK PCH_DDPD_CTRLCLK <29>
DMI_CRX_PTX_N3 BE18 AW44 PAD~D T61 @
<6> DMI_CRX_PTX_N3 DMI_TXN_3 TP10 1 2 HSYNC N42 N38
<25> PCH_CRT_HSYNC VGA_HSYNC DDPD_CTRLDATA PCH_DDPD_CTRLDATA <29>
DMI_CRX_PTX_P0 BB21 AL39 FDI_CSYNC RH94 20_0402_1%
<6> DMI_CRX_PTX_P0 DMI_TXP_0 FDI_CSYNC FDI_CSYNC <6>
DMI_CRX_PTX_P1 BC20 1 2 VSYNC N44
<6> DMI_CRX_PTX_P1 DMI_TXP_1 <25> PCH_CRT_VSYNC VGA_VSYNC
AL40 FDI_INT RH95 20_0402_1% H45
DMI_CRX_PTX_P2 BB17 FDI_INT FDI_INT <6> 1 2 CRT_IREF U40 DDPB_AUXN
DISPLAY
<6> DMI_CRX_PTX_P2 DMI_TXP_2 DAC_IREF
DMI_CRX_PTX_P3 BC18 AT45 FDI_IREF 2 1 +1.5V_RUN RH97 649_0402_1% K43
<6> DMI_CRX_PTX_P3 DMI_TXP_3 FDI_IREF DDPC_AUXN DPC_PCH_DOCK_AUX# <29>
0_0402_5% RH96 @ U39
2 1 DMI_IREF BE16 AU42 PAD~D T64 @ VGA_IRTN J42
+1.5V_RUN DMI_IREF TP17 DDPD_AUXN DPD_PCH_DOCK_AUX# <29>
@ RH98 0_0402_5%
AW17 AU44 PAD~D T66 @ BIA_PWM_PCH N36 H43
TP12 TP13 <27> BIA_PWM_PCH EDP_BKLTCTL DDPB_AUXP
@ T65 PAD~D
LVDS
AV17 AR44 FDI_RCOMP 2 1 +1.5V_RUN PANEL_BKEN_PCH K36 K45
TP7 FDI_RCOMP <28> PANEL_BKEN_PCH EDP_BKLTEN DDPC_AUXP DPC_PCH_DOCK_AUX <29>
@ T67 PAD~D 7.5K_0402_1% RH99
+1.5V_RUN
1 2 DMI_RCOMP AY17 ENVDD_PCH G36 J44
DMI_RCOMP <28,45> ENVDD_PCH EDP_VDDEN DDPD_AUXP DPD_PCH_DOCK_AUX <29>
RH100 7.5K_0402_1%
K40
PCI_PIRQA# H20 DDPB_HPD HDMIB_PCH_HPD <26>
1 2 SUSACK#_R R6 C8 DSWODVREN PIRQA# K38
<45> SUSACK# SUSACK# DSWVRMEN DDPC_HPD DPC_PCH_DOCK_HPD <44>
@ RH101 0_0402_5% PCI_PIRQB# L20
SYS_RESET# AM1 L13 PCH_DPWROK PIRQB# H39
SYS_RESET# DPWROK PCH_DPWROK <45> DDPD_HPD DPD_PCH_DOCK_HPD <44>
PCI_PIRQC# K17
1 2 SYS_PWROK_R AD7 K3 PCH_PCIE_WAKE# PIRQC#
<7,45> SYS_PWROK SYS_PWROK WAKE# PCH_PCIE_WAKE# <46>
@ RH102 0_0402_5% PCI_PIRQD# M20
1 2 PCH_PWROK F10 AN7 CLKRUN# PIRQD# G17 LCD_CBL_DET#
<10,15,46> RESET_OUT# PWROK System Power CLKRUN# CLKRUN# <35,45,46> A12 PIRQE#/GPIO2 LCD_CBL_DET# <28>
@ RH103 0_0402_5% DGPU_HOLD_RST#
Management <49> DGPU_HOLD_RST# GPIO50
PM_APWROK_R AB7 U7 SUS_STAT#/LPCPD# F17 PCH_GPIO3
APWROK SUS_STAT#/GPIO61 SUS_STAT#/LPCPD# <35> CPPE# B13 PCI PIRQF#/GPIO3
<37> CPPE# GPIO52
B 1 2 PM_DRAM_PWRGD_R H3 Y6 SUSCLK T68 PAD~D@ L15 CAM_MIC_CBL_DET# B
<7> PM_DRAM_PWRGD DRAMPWROK SUSCLK/GPIO62 PIRQG#/GPIO4 CAM_MIC_CBL_DET# <28>
@ RH104 0_0402_5% T69 PAD~D@ DGPU_PWR_EN# C12
<54> DGPU_PWR_EN# GPIO54
1 2 PCH_RSMRST#_R J2 Y7 SIO_SLP_S5# M15 FFS_PCH_INT 2 1
<15,47> PCH_RSMRST#_Q RSMRST# SLP_S5#/GPIO63 SIO_SLP_S5# <35,46> PIRQH#/GPIO5 HDD_FALL_INT <31>
@ RH105 0_0402_5% BBS_BIT1 C10 0_0402_5% RH106 @
T70 PAD~D @ GPIO51
1 2 ME_SUS_PWR_ACK_R J4 C6 SIO_SLP_S4# AD10 @ T71 PAD~D
<46> ME_SUS_PWR_ACK SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# SIO_SLP_S4# <28,35,45,62> PME#
@ RH107 0_0402_5% A10
<7,15> SIO_PWRBTN#_R <37> USB_MCARD1_DET# GPIO53
1 2 SIO_PWRBTN#_R K1 H1 SIO_SLP_S3# Y11 PCH_PLTRST# 2 1
<46> SIO_PWRBTN# PWRBTN# SLP_S3# SIO_SLP_S3# <11,35,39,40,45,48,64,66> PLTRST# PLTRST_USH# <35>
@ RH108 0_0402_5% PCH_GPIO55 AL6 0_0402_5%2 1 RH109 @
GPIO55 PLTRST_MMI# <36>
AC_PRESENT E6 F3 SIO_SLP_A# 0_0402_5%2 1 RH110 @
<46> AC_PRESENT ACPRESENT/GPIO31 SLP_A# SIO_SLP_A# <35,45,48,63> 5 OF 11 PLTRST_LAN# <33>
0_0402_5%2 1 RH111 @
T73 PAD~D @ PLTRST_EMB# <32>
1 2 PCH_BATLOW# K7 F1 SIO_SLP_SUS# 0_0402_5%2 1 RH113 @
+PCH_VCCDSW3_3
RH112 8.2K_0402_5% BATLOW#/GPIO72 SLP_SUS# SIO_SLP_SUS#
T74 PAD~D @
<45> DH82LPMS-QCG1-B0_FCBGA695~D 0_0402_5% RH114 @
PLTRST_GPU# <49>
PCH_RI# N4 AY3 H_PM_SYNC
<17> PCH_RI# RI# PMSYNCH H_PM_SYNC <7> +3.3V_RUN
@ T75 PAD~D AB10 G5 SIO_SLP_LAN# @ CH12
TP21 SLP_LAN# SIO_SLP_LAN# <45,48> 1 2
SIO_SLP_WLAN# D2
<39,45> SIO_SLP_WLAN# SLP_WLAN#/GPIO29 0.1U_0402_25V6
4 OF 11
1 2 PCH_CRT_BLU
DH82LPMS-QCG1-B0_FCBGA695~D
5
RH115 150_0402_1%
1 2 PCH_CRT_GRN PCH_PLTRST# 1
P
<7,15> PCH_PLTRST# B 4
RH116 150_0402_1% PCH_PLTRST#_EC
O PCH_PLTRST#_EC <35,37,38,39,45,46>
1 2 PCH_CRT_RED 2
A
G
RH117 150_0402_1% UH3
Boot BIOS Strap 1 2 ENVDD_PCH TC7SH08FU_SSOP5~D
3
RH118 100K_0402_5%
SATA_SLPD
BBS_BIT1
BBS_BIT1 (BBS_BIT0) Boot BIOS Location
1K_0402_1%
0 0 LPC
1
@ RH119
A 0 1 Reserved (NAND) A
2
1 0 PCI
* 1 1 SPI DELL CONFIDENTIAL/PROPRIETARY

GPIO51 has internal pull up.
PROPRIETARY NOTE:
Title
1.0
5 4 3 2 1
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5 4 3 2 1
+3.3V_ALW_PCH
RPH8
PEG_B_CLKRQ# 4 5
MINI3CLK_REQ# 3 6
PCH_RI# 2 7
<16> PCH_RI# 1 8
10K_8P4R_5%
+3.3V_ALW_PCH
+3.3V_ALW_PCH
RPH9
2
10K_0402_5%
EXPCLK_REQ# 4 5
D SIO_EXT_WAKE# 3 6 D
<15,20,45> SIO_EXT_WAKE#
RH128
MINI2CLK_REQ# 2 7
EMBCLK_REQ# 1 8
1
10K_8P4R_5%
GFX_CLK_REQ#
L2N7002WT1G_SC-70-3
UH1C
1
LPT_PCH_M_EDS D
QH3
2
<45> 3.3V_RUN_GFX_ON
G
Y43 AB35 CLK_PCIE_VGA# S
3
<38> CLK_PCIE_MINI1# CLKOUT_PCIE_N_0 CLKOUT_PEG_A CLK_PCIE_VGA# <49>
WWAN (Mini Card 1)---> Y45 AB36 CLK_PCIE_VGA
<38> CLK_PCIE_MINI1 RH122 2 1 10K_0402_5% CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P CLK_PCIE_VGA <49>
+3.3V_ALW_PCH
MINI1CLK_REQ# AB1 AF6 GFX_CLK_REQ#
<38> MINI1CLK_REQ# PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47 GFX_CLK_REQ# <50>
AA44 Y39
<33> CLK_PCIE_LAN# AA42 CLKOUT_PCIE_N_1 CLKOUT_PEG_B
<33> CLK_PCIE_LAN 1 2 CLKOUT_PCIE_P_1 Y38
10/100/1G LAN ---> +3.3V_RUN CLKOUT_PEG_B_P
RH125 10K_0402_5% LANCLK_REQ# AF1 RPH5
<15,33> LANCLK_REQ# PCIECLKRQ1#/GPIO18 U4 PEG_B_CLKRQ# CLK_BUF_BCLK# 4 5
AB43 PEGB_CLKRQ#/GPIO56 CLK_BUF_BCLK 3 6
<36> CLK_PCIE_MMI# CLKOUT_PCIE_N_2 AF39 CLK_CPU_DMI# CLK_BUF_DMI# 2 7
AB45 CLKOUT_DMI CLK_CPU_DMI# <7> CLK_BUF_DMI 1 8
MMI---> <36> CLK_PCIE_MMI CLKOUT_PCIE_P_2
RH133 1 2 10K_0402_5% AF40 CLK_CPU_DMI
+3.3V_RUN CLKOUT_DMI_P CLK_CPU_DMI <7>
MMICLK_REQ# AF3 10K_8P4R_5%
<15,36> MMICLK_REQ# PCIECLKRQ2#/GPIO20/SMI# AJ40 CLK_CPU_SSC_DPLL#
AD43 CLKOUT_DP AJ39 CLK_CPU_SSC_DPLL CLK_CPU_SSC_DPLL# <7> CLK_BUF_DOT96# RH1361 2 10K_0402_5%
<37> CLK_PCIE_MINI3# AD45 CLKOUT_PCIE_N_3 CLKOUT_DP_P CLK_CPU_SSC_DPLL <7>
PP (Mini Card 3)---> CLK_BUF_DOT96 RH1381 2 10K_0402_5%
C <37> CLK_PCIE_MINI3 MINI3CLK_REQ# T3 CLKOUT_PCIE_P_3 AF35 CLK_CPU_DPLL# C
<37> MINI3CLK_REQ# PCIECLKRQ3#/GPIO25 CLKOUT_DPNS AF36 CLK_CPU_DPLL CLK_CPU_DPLL# <7>
AF43 CLKOUT_DPNS_P CLK_CPU_DPLL <7> CLK_BUF_CKSSCD# RH1411 2 10K_0402_5%
<39> CLK_PCIE_EXP# AF45 CLKOUT_PCIE_N_4 AY24 CLK_BUF_DMI# CLK_BUF_CKSSCD RH1431 2 10K_0402_5%
<39> CLK_PCIE_EXP EXPCLK_REQ# V3 CLKOUT_PCIE_P_4 CLKIN_DMI AW24 CLK_BUF_DMI
Express card---> <39> EXPCLK_REQ# PCIECLKRQ4#/GPIO26 CLOCK SIGNAL CLKIN_DMI_P
AE44 AR24 CLK_BUF_BCLK# CLK_PCH_14M RH1461 2 10K_0402_5%
<37> CLK_PCIE_MINI2# AE42 CLKOUT_PCIE_N5 CLKIN_GND AT24 CLK_BUF_BCLK
<37> CLK_PCIE_MINI2 MINI2CLK_REQ# AA2 CLKOUT_PCIE_P_5 CLKIN_GND_P
<37> MINI2CLK_REQ# PCIECLKRQ5#/GPIO44 H33 CLK_BUF_DOT96#
WLAN (Mini Card 2)---> CLKIN_DOT96N
AB40 G33 CLK_BUF_DOT96
AB39 CLKOUT_PCIE_N_6 CLKIN_DOT96P
RH197 2 1 10K_0402_5% PCIECLKRQ6# AE4 CLKOUT_PCIE_P_6 BE6 CLK_BUF_CKSSCD#
+3.3V_ALW_PCH PCIECLKRQ6#/GPIO45 CLKIN_SATA BC6 CLK_BUF_CKSSCD
AJ44 CLKIN_SATA_P CLOCK TERMINATION for FCIM and need close to PCH
<32> CLK_PCIE_EMB# CLKOUT_PCIE_N_7 F45 CLK_PCH_14M
AJ42 REFCLK14IN D17 CLK_PCI_LOOPBACK
eModule Bay---> <32> CLK_PCIE_EMB CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK
EMBCLK_REQ# Y3 AM43 XTAL25_IN 2 1
<32> EMBCLK_REQ# PCIECLKRQ7#/GPIO46 XTAL25_IN AL44 XTAL25_OUT 1 2 0_0402_5%
@ RH152
AH43 XTAL25_OUT RH153 1M_0402_5%
XTAL25_IN_R
<7> CLK_CPU_ITP# CLKOUT_ITPXDP C40 PCI_TPM_TCM 2 1 22_0402_5%
RH155
AH45 CLKOUTFLEX0/GPIO64 CLK_PCI_TPM <35>
<7> CLK_CPU_ITP CLKOUT_ITPXDP_P F38 2 1 22_0402_5%
SIO_14M RH157
2 1 22_0402_5% PCI_5048 D44 CLKOUTFLEX1/GPIO65 CLK_SIO_14M <45>
EMC@ RH158
<45> CLK_PCI_5048 CLKOUT_33MHZ0 F36 CLK_80H 2 1 22_0402_5%
RH159 YH2
2 1 22_0402_5% E44 CLKOUTFLEX2/GPIO66 PCLK_80H <37>
EMC@ RH160 PCI_MEC 25MHZ_10PF_Q22FA2380049900~D
<46> CLK_PCI_MEC CLKOUT_33MHZ1 F39 2 1 22_0402_5% 3 1
JETWAY_14M @
@RH161
RH161
2 1 22_0402_5% PCI_DOCK B42 CLKOUTFLEX3/GPIO67 JETWAY_CLK14M <35> OUT IN
EMC@ RH162
<44> CLK_PCI_DOCK CLKOUT_33MHZ2 AM45 ICLK_IREF 1 2 4 2
ICLK_IREF +1.5V_RUN GND GND
10P_0402_50V8J
10P_0402_50V8J
F41 0_0402_5% RH163 @ 2 2
CLKOUT_33MHZ3
CH13
CH14
AD39
B CLK_PCI_LOOPBACK EMC@ RH164 2 1 22_0402_5% PCI_LOOPBACKOUT A40 TP19 AD38 PAD~D T76 @ B
CLKOUT_33MHZ4 TP18 PAD~D T77 @
AN44 PCH_CLK_BIASREF 1 2 1 1
DIFFCLK_BIASREF +1.05V_+1.5V_RUN
7.5K_0402_1% RH165
2 OF 11
PCIECLK REQ Pull UP Power Rail: DH82LPMS-QCG1-B0_FCBGA695~D

SUS Rail : 0 3 4 5 6 7
Core Rail: 1 2
CLK_PCI_5048 CLK_PCI_MEC CLK_PCI_DOCK CLK_PCI_LOOPBACK CLK_PCI_TPM CLK_SIO_14M JETWAY_CLK14M
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
1 1 1 1 1 1 1
@
@
@ CH16
CH15
CH76
CH77
CH78
CH79
CH80
2 2 2 2 2 2 2
A A
PROPRIETARY NOTE:
Title
PCH (3/9)
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1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
2
MEM_SMBCLK 6 1
DDR_XDP_WAN_SMBCLK <7,13,14,15,27,31>
QH4A
5
D +3.3V_ALW_PCH D
MEM_SMBDATA 3 4
DDR_XDP_WAN_SMBDAT <7,13,14,15,27,31> PCH_SMB_ALERT# 2 1
QH4B 10K_0402_5% RH166
+3.3V_RUN DMN66D0LDW-7_SOT363-6~D MEM_SMBCLK 2 1
2.2K_0402_5% RH167
1 2 IRQ_SERIRQ MEM_SMBDATA 2 1
RH168 10K_0402_5% 2.2K_0402_5% RH169
DDR_HVREF_RST_PCH 2 1
1K_0402_1% RH170
UH1D LPT_PCH_M_EDS
TEMP_ALERT# 2 1
10K_0402_5% RH171
SML1_SMBCLK 1 2
2.2K_0402_5% RH172
N7 PCH_SMB_ALERT# SML1_SMBDATA 1 2
LPC_LAD0 A20 SMBALERT#/GPIO11 2.2K_0402_5% RH173
<35,37,45,46> LPC_LAD0 LAD_0 R10 MEM_SMBCLK
SMBus
LPC_LAD1 C20 SMBCLK
<35,37,45,46> LPC_LAD1 LAD_1 U11 MEM_SMBDATA
LPC_LAD2 A18 SMBDATA
LPC
<35,37,45,46> LPC_LAD2 LAD_2 N8 +3.3V_LAN
DDR_HVREF_RST_PCH
LPC_LAD3 C18 SML0ALERT#/GPIO60 DDR_HVREF_RST_PCH <7,13,14>
<35,37,45,46> LPC_LAD3 LAD_3 U8 LAN_SMBCLK LAN_SMBCLK 2 1
LPC_LFRAME# B21 SML0CLK LAN_SMBCLK <33> 2.2K_0402_5% RH174
<35,37,45,46> LPC_LFRAME# LFRAME# R7 LAN_SMBDATA LAN_SMBDATA 2 1
LPC_LDRQ0# D21 SML0DATA LAN_SMBDATA <33>
@ T87 PAD~D 2.2K_0402_5% RH175
LDRQ0# H6 TEMP_ALERT#
LPC_LDRQ1# G20 SML1ALERT#/PCHHOT#/GPIO74 TEMP_ALERT# <45>
<45> LPC_LDRQ1# LDRQ1#/GPIO23 K6 SML1_SMBCLK
AL11 SML1CLK/GPIO58 SML1_SMBCLK <46>
IRQ_SERIRQ
<35,45,46> IRQ_SERIRQ SERIRQ N11 SML1_SMBDATA
SML1DATA/GPIO75 SML1_SMBDATA <46>
C C
AF11 PCH_CL_CLK1
PCH_SPI_CLK AJ11 CL_CLK PCH_CL_CLK1 <37>
SPI_CLK AF10 PCH_CL_DATA1
PCH_SPI_CS0# AJ7 C-Link CL_DATA PCH_CL_DATA1 <37>
SPI_CS0# AF7 PCH_CL_RST1#
PCH_SPI_CS1# AL7 CL_RST# PCH_CL_RST1# <37>
SPI_CS1#
AJ10
SPI_CS2#
SPI
BA45 PAD~D T78 @
PCH_SPI_DO AH1 TP1
SPI_MOSI BC45 PAD~D T79 @
PCH_SPI_DIN AH3 Thermal TP2 SPI_CLK32 SPI_CLK64
SPI_MISO BE43 PAD~D T80 @
TP4
1
PCH_SPI_DO2 AJ4
SPI_IO2 BE44 PAD~D T81 @ @ @
PCH_SPI_DO3 AJ2 TP3 RE2 RE1
SPI_IO3 AY43 PCH_TD_IREF 1 2 33_0402_5% 33_0402_5%
TD_IREF RH176 8.2K_0402_1%
2
1 1
3 OF 11 @ @
CE2 CE1
DH82LPMS-QCG1-B0_FCBGA695~D 27P_0402_50V8J 27P_0402_50V8J
+3.3V_SPI 2 2
1 2 SPI_PCH_DO2_64 +3.3V_SPI
R3664 1K_0402_5%
1 2 SPI_PCH_DO3_64 C746
R3668 1K_0402_5% 200 MIL SO8 1 2
B 64Mb Flash ROM 0.1U_0402_25V6 B

U52
SPI_PCH_CS0# R7 1 2 47_0402_5% SPI_PCH_CS0#_R 1 8 JSPI1
SPI_PCH_DIN R8 1 2 33_0402_5% SPI_DIN64 2 /CS VCC 7 SPI_PCH_DO3_64 R3669 1 2 33_0402_5% SPI_PCH_DO3 2 1 SPI_PCH_CS1# 1
SPI_PCH_DO2 R9 1 2 33_0402_5% SPI_PCH_DO2_64 3 DO(IO1) /HOLD(IO3) 6 SPI_CLK64 R899 1 2 33_0402_5% SPI_PCH_CLK 0_0402_5% RH177 @ PCH_SPI_CS1# 2 1
4 /WP(IO2) CLK 5 SPI_DO64 R901 1 2 33_0402_5% SPI_PCH_DO 2 1 SPI_PCH_DO 3 2
SPI_WP#_SEL 2 1 GND DI(IO0) 0_0402_5% RH178 @ PCH_SPI_DO 4 3
<45> SPI_WP#_SEL 2 1 SPI_PCH_DIN 5 4
@ RH180 0_0402_5% W25Q64FVSSIQ_SO8
0_0402_5% RH179 @ PCH_SPI_DIN 6 5
2 1 SPI_PCH_CLK 7 6
0_0402_5% RH181 @ PCH_SPI_CLK 8 7
2 1 SPI_PCH_CS0# 9 8
0_0402_5% RH182 @ PCH_SPI_CS0# 10 9
2 1 SPI_PCH_DO2 11 10
+3.3V_SPI 0_0402_5% RH183 @ PCH_SPI_DO2 12 11
2 1 SPI_PCH_DO3 13 12
0_0402_5% RH184 @ PCH_SPI_DO3 14 13
1 2 SPI_PCH_DO2_32 15 14
+3.3V_SPI 15
R3665 1K_0402_5% 16
+3.3V_M 16
1 2 SPI_PCH_DO3_32 +3.3V_SPI 17
R3666 1K_0402_5% 2 1 18 17
C1216 0_0402_5% RH185 @ 19 18
200 MIL SO8 1 2 20 19
20
32Mb Flash ROM 0.1U_0402_25V6 21
U53 RPH7 22 GND1
SPI_PCH_CS1# R936 1 2 47_0402_5% SPI_PCH_CS1#_R 1 8 GND2
SPI_PCH_DIN R895 1 2 33_0402_5% SPI_DIN32 2 /CS VCC 7 SPI_PCH_DO3_32 1 8 SPI_PCH_DO3 TYCO_2-2041070-0
SPI_PCH_DO2 R3667 1 2 33_0402_5% SPI_PCH_DO2_32 3 DO/IO1 /HOLD/IO3 6 SPI_CLK32 2 7 SPI_PCH_CLK CONN@
4 /WP/IO2 CLK 5 SPI_DO32 3 6 SPI_PCH_DO
SPI_WP#_SEL 2 1 GND DI/IO0 4 5
@ RH186 0_0402_5% W25Q32FVSSIQ_SO8
A 33_8P4R_5% A
PROPRIETARY NOTE:
Title
PCH (4/9)
www.Vinafix.vn
1.0
5 4 3 2 1
5 4 3 2 1
D D
UH1I LPT_PCH_M_EDS
USB3RN3 AW31 B37 USBP0-

<44> USB3RN3 PERN1/USB3RN3 USB2N0 USBP0- <40>
<44> USB3RP3
USB3RP3 AY31
PERP1/USB3RP3 USB2P0
D37 USBP0+
USBP0+ <40>
----->Right Side Top
MLK DOCK -----> USB2N1
A38 USBP1-
USBP1- <41>
<44> USB3TN3
USB3TN3 BE32
PETN1/USB3TN3 USB2P1
C38 USBP1+
USBP1+ <41>
----->Right Side Middle
USB3TP3 BC32 A36 USBP2-
<44> USB3TP3 PETP1/USB3TP3 USB2N2 USBP2- <42>
USB2P2
C36 USBP2+
USBP2+ <42>
----->Right Side bottom
PCIE_PRX_GLANTX_N2 AT31 A34 USBP3-
<33> PCIE_PRX_GLANTX_N2 PERN2/USB3RN4 USB2N3 USBP3- <44>
<33> PCIE_PRX_GLANTX_P2
PCIE_PRX_GLANTX_P2 AR31
PERP2/USB3RP4 USB2P3
C34 USBP3+
USBP3+ <44>
----->DOCK
10/100/1G LAN ---> B33 USBP4-
USB2N4 USBP4- <37>
<33> PCIE_PTX_GLANRX_N2
PCIE_PTX_GLANRX_N2 BD33
PETN2/USB3TN4 USB2P4
D33 USBP4+
USBP4+ <37>
----->WLAN/WIMAX
PCIE_PTX_GLANRX_P2 BB33 F31 USBP5-
<33> PCIE_PTX_GLANRX_P2 PETP2/USB3TP4 USB2N5 G31 USBP5+ USBP5- <38> ----->WWAN/UWB
USB2P5 K31 USBP6- USBP5+ <38>
PCIE_PRX_WLANTX_N3 AW33 USB2N6 L31 USBP6+ USBP6- <44> ----->DOCK
<37> PCIE_PRX_WLANTX_N3 PERN_3 USB2P6 USBP6+ <44>
PCIE_PRX_WLANTX_P3 AY33 G29 USBP7-
WLAN (JMINI2)--->
<37> PCIE_PRX_WLANTX_P3 PERP_3 USB2N7 H29 USBP7+ USBP7- <35> ----->USH
PCIE_PTX_WLANRX_N3 BE34 USB2P7 A32 USBP8- USBP7+ <35>
<37> PCIE_PTX_WLANRX_N3 PCIE_PTX_WLANRX_P3 BC34 PETN_3 USB2N8 C32 USBP8+
USBP8- <37> ----->WPAN
<37> PCIE_PTX_WLANRX_P3 PETP_3 USB2P8 A30 USBP9- USBP8+ <37>
PCIE_PRX_EMBTX_N4 AT33 USB2N9 C30 USBP9+ USBP9- <43> ----->Left Side USBRBIAS
C <32> PCIE_PRX_EMBTX_N4 PCIE_PRX_EMBTX_P4 AR33 PERN_4 USB2P9 B29 USBP10- USBP9+ <43> C
<32> PCIE_PRX_EMBTX_P4 PERP_4 USB2N10 USBP10- <39>
----->Express Card
22.6_0402_1%
E3 Module Bay---> D29 USBP10+
USB2P10 USBP10+ <39>
1
PCIE_PTX_EMBRX_N4 BE36 A28
<32> PCIE_PTX_EMBRX_N4 PETN_4 USB2N11
RH187
PCIE_PTX_EMBRX_P4 BC36 C28
<32> PCIE_PTX_EMBRX_P4 PETP_4 USB2P11 G26 USBP12-
USB2N12 USBP12- <28>
----->Camera
PCIe
AW36 F26 USBP12+
USB
AV36 PERN_5 USB2P12 F24 USBP12+ <28>
2
PERP_5 USB2N13 G24
BD37 USB2P13
BB37 PETN_5
PETP_5 AR26 USB3RN1
AY38 USB3RN1 AP26 USB3RN1 <40>
PCIE_PRX_WPANTX_N6 USB3RP1 CAD NOTE:
<37> PCIE_PRX_WPANTX_N6 AW38 PERN_6 USB3RP1 BE24 USB3RP1 <40>
PCIE_PRX_WPANTX_P6 USB3TN1
Pink Pather (JMINI3)--->
<37> PCIE_PRX_WPANTX_P6 PERP_6 USB3TN1 BD23 USB3TP1 USB3TN1 <40> ----->Right Side Top Route single-end 50-ohms and max 500-mils length.
PCIE_PTX_WPANRX_N6 BC38 USB3TP1 AW26 USB3RN2 USB3TP1 <40> Avoid routing next to clock pins or under stitching capacitors.
<37> PCIE_PTX_WPANRX_N6 PCIE_PTX_WPANRX_P6 BE38 PETN_6 USB3RN2 AV26 USB3RP2 USB3RN2 <41>
<37> PCIE_PTX_WPANRX_P6 PETP_6 USB3RP2 USB3RP2 <41> Recommended minimum spacing to other signal traces is 15 mils.
BD25 USB3TN2
PCIE_PRX_EXPTX_N7 AT40 USB3TN2 BC24 USB3TP2
USB3TN2 <41> ----->Right Side Middle
<39> PCIE_PRX_EXPTX_N7 AT39 PERN_7 USB3TP2 AW29 USB3TP2 <41>
PCIE_PRX_EXPTX_P7 USB3RN5
<39> PCIE_PRX_EXPTX_P7 PERP_7 USB3RN5 AV29 USB3RP5 USB3RN5 <42>
EXPRESS Card---> USB3RP5 USB3RP5 <42>
<39> PCIE_PTX_EXPRX_N7
PCIE_PTX_EXPRX_N7 BE40
PETN_7 USB3TN5
BE26 USB3TN5
USB3TN5 <42> ----->Right Side bottom
PCIE_PTX_EXPRX_P7 BC40 BC26 USB3TP5
<39> PCIE_PTX_EXPRX_P7 PETP_7 USB3TP5 AR29 USB3RN6 USB3TP5 <42>
AN38 USB3RN6 AP29 USB3RN6 <43>
PCIE_PRX_MMITX_N8 USB3RP6
<36> PCIE_PRX_MMITX_N8 PCIE_PRX_MMITX_P8 AN39 PERN_8 USB3RP6 BD27 USB3TN6 USB3RP6 <43> ----->Left Side
<36> PCIE_PRX_MMITX_P8 PERP_8 USB3TN6 BE28 USB3TP6 USB3TN6 <43>
BD42 USB3TP6 USB3TP6 <43>
MMI ---> PCIE_PTX_MMIRX_N8
<36> PCIE_PTX_MMIRX_N8 PCIE_PTX_MMIRX_P8 BD41 PETN_8 K24 USBRBIAS
<36> PCIE_PTX_MMIRX_P8 PETP_8 USBRBIAS# K26
USBRBIAS
1 2 PCH_PCIE_IREF BE30 M33 PAD~D T82 @
+1.5V_RUN PCIE_IREF TP24
@ RH188 0_0402_5% L33 PAD~D T83 @
B TP23 +3.3V_ALW_PCH B
@ T84 PAD~D BC30 P3 USB_OC0#_R @ RH1891 2 0_0402_5%
TP11 OC0#/GPIO59 V1 USB_OC1#_R USB_OC0# <40,41>
@ RH1901 2 0_0402_5% RPH3
OC1#/GPIO40 U2 USB_OC2# USB_OC1# <42> USB_OC0#_R 4 5
BB29 OC2#/GPIO41 P1 USB_OC3# USB_OC2# <15> 3 6
@ T85 PAD~D USB_OC1#_R
TP6 OC3#/GPIO42 M3USB_OC4#_R USB_OC3# <15>
@ RH1911 2 0_0402_5% USB_OC3# 2 7
OC4#/GPIO43 T1 USB_OC5# USB_OC4# <43> USB_OC4#_R 1 8
1 2 PCH_PCIE_RCOMP BD29 OC5#/GPIO9 N2 USB_OC6# USB_OC5# <15>
+1.5V_RUN PCIE_RCOMP OC6#/GPIO10 USB_OC6# <15>
RH192 7.5K_0402_1% M1 SIO_EXT_SMI# 10K_8P4R_5%
OC7#/GPIO14 SIO_EXT_SMI# <15,46>
9 OF 11 RPH1
USB_OC0#_R <15> 4 5
USB_OC5#
DH82LPMS-QCG1-B0_FCBGA695~D USB_OC1#_R <15> USB_OC6# 3 6
USB_OC4#_R <15> SIO_EXT_SMI# 2 7
USB_OC2# 1 8
10K_8P4R_5%
A A
PROPRIETARY NOTE:
Title
PCH (5/9)
www.Vinafix.vn
1.0
5 4 3 2 1
5 4 3 2 1
+PCH_VCCDSW3_3 Support Deep S3 mode
2 1 EC_WAKE# 1 2
LANWAKE# <33,46>
RH216 10K_0402_5% @RH196
@ RH196 0_0402_5%
2 1 PM_LANPHY_ENABLE
RH217 10K_0402_5% +3.3V_RUN
SIO_A20GATE 2 1
+3.3V_RUN UH1F LPT_PCH_M_EDS 10K_0402_5% RH193
SIO_RCIN# 2 1
1 2 AT8 10K_0402_5% RH194
<46> SIO_EXT_SCI# BMBUSY#/GPIO0
1 2 PCH_GPIO06 @ RH195 0_0402_5%
RH257 10K_0402_5% USH_DET# F13
<35> USH_DET# TACH1/GPIO1
2 1 USH_DET#
RH202 100K_0402_5% PCH_GPIO06 A14
TACH2/GPIO6
D D
G15 CPU/Misc
PCH_GPIO07
2 1 PCH_GPIO07 TACH3/GPIO7
RH203 10K_0402_5% SIO_EXT_WAKE# Y1
<15,17,45> SIO_EXT_WAKE# GPIO8
PM_LANPHY_ENABLE K13
<33> PM_LANPHY_ENABLE LAN_PHY_PWR_CTRL/GPIO12
2 1 PCH_GPIO22 AN10 SIO_A20GATE
TP14 SIO_A20GATE <46>
RH198 10K_0402_5% SMART_DET# AB11
<35> SMART_DET# GPIO15
1 2 TPM_ID0 AY1 PAD~D T86 @
RH199 10K_0402_5% MCARD_PCIE_SATA# AN2 PECI
<15,38,45> MCARD_PCIE_SATA# SATA4GP/GPIO16
1 2 TPM_ID1 AT6 SIO_RCIN#
GPIO RCIN# SIO_RCIN# <46>
RH200 10K_0402_5% DGPU_PWROK C14
<45,66> DGPU_PWROK TACH0/GPIO17
1 2 CONTACTLESS_DET# AV3 H_CPUPWRGD +1.05V_RUN
PROCPWRGD H_CPUPWRGD <7>
RH201 10K_0402_5% PCH_GPIO22 BB4
<35> PCH_GPIO22 SCLOCK/GPIO22
2 1 SIO_EXT_SCI# AV1 PCH_THRMTRIP#_R 2 1
RH204 10K_0402_5% PCH_GPIO24 Y10 THRMTRIP# RH206 56_0402_5%
GPIO24
0.1U_0402_25V6
2 1 PCH_GPIO35 AU4 CPU_PLTRST#
PLTRST_PROC# CPU_PLTRST# <7>
RH205 10K_0402_5% EC_WAKE# R11 1
<46> EC_WAKE# GPIO27
2 1 PCH_GPIO70 N10
VSS
CH17
RH207 10K_0402_5% SLP_ME_CSW_DEV# AD11
<45> SLP_ME_CSW_DEV# GPIO28
2 1 PCH_GPIO71
RH208 10K_0402_5% PCH_GPIO34 AN6 2
2 1 PCH_GPIO69 GPIO34
RH254 10K_0402_5% PCH_GPIO35 AP1
<15> PCH_GPIO35 GPIO35/NMI#
2 1 PCH_GPIO34
RH258 10K_0402_5% PCH_GPIO36 AT3
<15> PCH_GPIO36 SATA2GP/GPIO36
PCH_GPIO37 AK1
<15> PCH_GPIO37 SATA3GP/GPIO37
TPM_ID0 AT7
+3.3V_ALW_PCH SLOAD/GPIO38
TPM_ID1 AM3 A2
SDATAOUT0/GPIO39 VSS A41
FFS_INT2 AN4 VSS A43
<31> FFS_INT2 SDATAOUT1/GPIO48 VSS A44
C
1 2 SMART_DET# PCH_GPIO49 AK3 VSS B1 C
<15> PCH_GPIO49 SATA5GP/GPIO49 VSS
RH211 10K_0402_5% B2
KB_DET# U12 VSS B44
<47> KB_DET# GPIO57 VSS CRB1.2 already change to GND directly at UH1.A44, B45, BD1 pins
2 1 KB_DET# B45
RH212 10K_0402_5% CONTACTLESS_DET# C16 VSS BA1
<35> CONTACTLESS_DET# TACH4/GPIO68 VSS
2 1 PCH_GPIO24 BC1
RH213 10K_0402_5% PCH_GPIO69 D13 VSS BD1
TACH5/GPIO69 VSS BD2
PCH_GPIO70 G13 VSS BD44
TACH6/GPIO70 VSS BD45
PCH_GPIO71 H15 VSS BE2
TACH7/GPIO71 VSS BE3
VSS D1
2 1 PCH_GPIO22 BE41 VSS E1
@ RH248 100K_0402_5% BE5 VSS NCTF VSS E45
C45 VSS VSS A4
2 1 DGPU_PWROK A5 VSS VSS
RH215 10K_0402_5% VSS
6 OF 11
+3.3V_ALW_PCH
+3.3V_RUN
2
4.7K_0402_5%
1 2 MCARD_PCIE_SATA#
RH222
RH224 10K_0402_5%
2 1 PCH_GPIO49
RH225 10K_0402_5% PCH_ GPIO37
1
SLP_ME_CSW_DEV# 2 1 MCARD_PCIE_SATA# 0 = Disable Intel ME Crypto Transport Layer Security

@RH226
@ RH226 10K_0402_5% (TLS) cipher suite (no confidentiality).
B 2 1 PCH_GPIO49 1 = Enable Intel ME Crypto Transport Layer Security B
1
1K_0402_1%
@RH227
@ RH227 10K_0402_5%
(TLS) cipher suite (with confidentiality). Must be pulled
@ RH223
up to support Intel AMT with TLS.

2
+3.3V_RUN
Config GPIO16,49 2 1 PCH_GPIO36
@RH228
@ RH228 200K_0402_1%
PLL ON DIE VR ENABLE 1 2 PCH_GPIO37
USB X4,PCIEX8,SATAX6 11 RH229 1K_0402_1%
ENABLED - HIGH(DEFAULT) 2 1 PCH_GPIO36
DISABLED - LOW * USB X6,PCIEX8,SATAX4 01 RH230 10K_0402_5%
2 1 PCH_GPIO37
@RH231
@ RH231 100K_0402_5%
SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.

WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.
A A
www.Vinafix.vn
Title
1.0
5 4 3 2 1
5 4 3 2 1
LH1
+VCCADAC 2 1
+1.5V_RUN
BLM18PG181SN1_0603~D
0.01U_0402_16V7K
0.1U_0402_10V6K
10U_0603_6.3V6M
D D
1 1 1
CH18
CH19
CH20
2 2 2
PCH Power Rail Table

UH1G LPT_PCH_M_EDS
+1.05V_RUN P45 Voltage Rail Voltage S0 Iccmax Current (A)

VCCADAC1_5 +1.05V_+1.5V_RUN
AA24 P43
AA26 VCC CRT DAC VSS
VCC VCC 1.05V 1.29 A
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
1 1 1 1 AD20 M31
VCC VCCADACBG3_3 +3.3V_RUN +1.05V_RUN
AD22
VCC
CH21
CH22
CH23
CH24
AD24 1 VCCIO 1.05V 3.629 A
VCC
1U_0402_6.3V6K
@ CH26
AD26 BB44
2 2 2 2 AD28 VCC VCCVRM
VCC FDI 1
AE18 AN34 VCCADAC1_5 1.5V 0.070 A
VCC VCCIO +3.3V_RUN 2
CH25
AE20
AE22 VCC AN35
AE24 VCC VCCIO 2
VCC VCCADAC3_3 3.3V 0.0133 A
AE26 R30
VCC HVCMOS VCC3_3_R30
0.1U_0402_10V6K
AG18 R32
AG20 VCC VCC3_3_R32
VCC 1 VCCCLK 1.05V 0.306 A
AG22 Y12 +PCH_USB_DCPSUS1 +3.3V_ALW_PCH
VCC DCPSUS1
CH27
AG24
Y26 VCC AJ30
VCC VCCSUS3_3 2
VCCCLK3_3 3.3V 0.055 A
Core
AJ32
VCCSUS3_3
+1.05V_M AJ26 +PCH_USB_DCPSUS3 +1.05V_+1.5V_RUN VCCVRM 1.5V 0.179 A
C +PCH_VCCDSW U14 USB3 DCPSUS3 AJ28 C
AA18 DCPSUSBYP DCPSUS3 AK20
VCCASW VCCIO +1.05V_RUN
U18 AK26 VCC3_3 3.3V 0.133 A
VCCASW VCCVRM +1.05V_+1.5V_RUN
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
U20 AK28 1
VCCASW VCCVRM
@ CH31
1 1 1 U22
U24 VCCASW BE22
VCCASW VCCVRM VCCASW 1.05V 0.67 A
CH28
CH29
CH30
V18 PCIe/DMI
VCCASW +1.05V_+1.5V_RUN 2
10U_0603_6.3V6M
V20 AK18 1
2 2 2 VCCASW VCCIO +1.05V_RUN
@ CH32
V22 VCCSUSHDA 3.3V 0.01 A
V24 VCCASW AN11
VCCASW VCCVRM
10U_0603_6.3V6M
Y18
Y20 VCCASW SATA AK22 2
VCCASW VCCIO 1 VCCSPI 3.3V 0.022 A
@ CH33
Y22 +1.05V_RUN
VCCASW AM18
VCCIO AM20
VCCIO 2
VCCSUS3_3 3.3V 0.261 A
AM22
VCCMPHY VCCIO AP22
VCCIO
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
AR22 1 1 1 1 1 VCCDSW3_3 3.3V 0.015 A
VCCIO AT22
VCCIO
CH34
CH35
CH36
CH37
CH38
7 OF 11
2 2 2 2 2
V_PROC_IO 1.05V 0.004 A
1 2 +PCH_VCCDSW +1.5V_RUN +1.05V_+1.5V_RUN

RH232 5.11_0402_1% +1.05V_M
+PCH_VCCDSW_R
2 1 +PCH_USB_DCPSUS1 2 1
@RH233
@ RH233 0_0603_5% 0_0402_5% RH234 @
1U_0402_6.3V6K
B +1.05V_RUN B
@CH39
@
2 1
1U_0402_6.3V6K
CH39
@RH235
@ RH235 0_0603_5%
2
1
CH40
+1.05V_M
2
+PCH_USB_DCPSUS3 1 2
0_0603_5% RH236 @
10U_0603_6.3V6M
1U_0402_6.3V6K
1 1
@ CH41
@ CH42
2 2
A A
PROPRIETARY NOTE:
Title
PCH (7/9)
www.Vinafix.vn
1.0
5 4 3 2 1
5 4 3 2 1
Support DEEP SX: populated RH238, de-populated RH237
+3.3V_ALW_PCH
+PCH_VCCDSW3_3
0.1U_0402_10V6K
2 1
UH1H LPT_PCH_M_EDS
0_0603_5% RH237 @
+3.3V_ALW_PCH
0.1U_0402_10V6K
1 2 1 +3.3V_ALW
+3.3V_ALW_PCH
CH43
0_0603_5% RH238 @
1
CH44
R24 R20
R26 VCCSUS3_3 VCCSUS3_3 R22 2
D D
VCCSUS3_3 VCCSUS3_3
0.1U_0402_10V6K
R28
+1.05V_RUN U26 VCCSUS3_3 GPIO/LPC 2
1 VCCSUS3_3 A16 +PCH_VCCDSW3_3
CH45 M24 VCCDSW3_3 +3.3V_RUN PCH Power Rail Table
VSS AA14 +PCH_VCCSST 1 2
2 +3.3V_RUN DCPSST
0.1U_0402_10V6K
U35 CH46 0.1U_0402_10V6K
VCCUSBPLL AE14
1 Voltage Rail Voltage S0 Iccmax Current (A)
USB
L24 VCC3_3 AF12
VCC3_3 VCC3_3
CH47
0.1U_0402_10V6K
AG14
VCC3_3 +3.3V_ALW_PCH
0.1U_0402_10V6K
U30 1 VCC 1.05V 1.29 A
2 +1.05V_RUN V28 VCCIO
1 VCCIO
CH48
CH49
V30 U36 +1.05V_RUN
Y30 VCCIO VCCIO
VCCIO 2
VCCIO 1.05V 3.629 A
2 +3.3V_VCCPRTCSUS
0.1U_0402_10V6K
+1.05V_+1.5V_RUN +PCH_USB_DCPSUS2 Y35 Azalia
DCPSUS2
1U_0402_6.3V6K
1 A26 1 VCCADAC1_5 1.5V 0.070 A
AF34 VCCSUSHDA
VCCVRM
CH50
CH51
+RTC_CELL
10U_0603_6.3V6M
1 +PCH_VCC AP45 K8 VCCADAC3_3 3.3V 0.0133 A
2 VCC VCCSUS3_3 2
1U_0402_6.3V6K
1
CH52
+PCH_VCCCLK Y32 A6
VCCCLK VCCRTC
CH53
2 RTC
VCCCLK 1.05V 0.306 A
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V6K
+PCH_VCCCLK3_3 M29 P14 +PCH_DCPRTC CH54
VCCCLK3_3 DCPRTC P16 1 2 2
DCPRTC 1 1 1
L29 VCCCLK3_3 3.3V 0.055 A
VCCCLK3_3
CH55
CH56
CH57
0.1U_0402_10V6K
L26 AJ12 +VCCIO2PCH
M26 VCCCLK3_3 V_PROC_IO AJ14 +3.3V_M 2 2 2
VCCCLK3_3
CPU
V_PROC_IO VCCVRM 1.5V 0.179 A
+1.05V_M U32
VCCCLK3_3
1U_0402_6.3V6K
V32
ICC
AD12 VCC3_3 3.3V 0.133 A
1 2 +PCH_USB_DCPSUS2 VCCCLK3_3 SPI VCCSPI
@ RH239 0_0402_5% +PCH_VCCCLK AD34 1
VCCCLK
1U_0402_6.3V6K
P18 +PCH_VCCCFUSE VCCASW 1.05V 0.67 A

C VCC C
CH59
1 AA30 P20
VCCCLK VCC
@ CH58
AA32
VCCCLK L17 2
VCCASW +1.05V_M VCCSUSHDA 3.3V 0.01 A
AD35
2 VCCCLK R18
AG30 VCCASW +VCCIO2PCH
VCCCLK VCCSPI 3.3V 0.022 A
AG32
VCCCLK AW40
VCCVRM +1.5V_RUN
AD36 VCCSUS3_3 3.3V 0.261 A
+1.05V_RUN +1.05V_RUN_VCC VCCCLK +3.3V_RUN
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V6K
AK30
AE30 VCC3_3
Thermal 1 1 1
AE32 VCCCLK AK32
VCCCLK VCC3_3 VCCDSW3_3 3.3V 0.015 A
0.1U_0402_10V6K
CH60
CH61
CH62
1 2 1 2 +PCH_VCC
@ RH246 0_0603_5% @ RH241 0_0603_5% 1 2 2 2
10U_0603_6.3V6M
1U_0402_6.3V6K
8 OF 11
V_PROC_IO 1.05V 0.004 A
CH65
1 1 DH82LPMS-QCG1-B0_FCBGA695~D
CH63
CH64
2 @ 2
Place near pin AP45
+PCH_VCCCFUSE 2 1 +3.3V_RUN
+1.05V_RUN +PCH_VCCCLK @ RH242 0_0805_5%
1U_0402_6.3V6K
2 1 +1.05V_RUN
1 2 1 RH243 0_0805_5% @
@ RH244 0_0805_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
CH66
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1 1 1 1 1
CH67
CH68
CH69
CH70
CH71
B B
2 2 2 2 2 @
Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36
Place near pin AG30,AG32,AE30,AE32
+3.3V_RUN +PCH_VCCCLK3_3
+3.3V_VCCPRTCSUS 2 1 +3.3V_ALW_PCH
@ RH240 0_0603_5%
1 2 2 1 +3.3V_ALW
@ RH245 0_0805_5% @ RH247 0_0603_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
CH72
CH73
CH74
CH75
2 2 2 2
Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
A A
Title
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1.0
5 4 3 2 1
5 4 3 2 1
D D
UH1J LPT_PCH_M_EDS
AL34 K39 UH1K LPT_PCH_M_EDS

AL38 VSS VSS L2
AL8 VSS VSS L44 AA16 B19
AM14 VSS VSS M17 AA20 VSS VSS B23
AM24 VSS VSS M22 AA22 VSS VSS B27
AM26 VSS VSS N12 AA28 VSS VSS B31
AM28 VSS VSS N35 AA4 VSS VSS B35
AM30 VSS VSS N39 AB12 VSS VSS B39
AM32 VSS VSS N6 AB34 VSS VSS B7
AM16 VSS VSS P22 AB38 VSS VSS BA40
AN36 VSS VSS P24 AB8 VSS VSS BD11
AN40 VSS VSS P26 AC2 VSS VSS BD15
AN42 VSS VSS P28 AC44 VSS VSS BD19
AN8 VSS VSS P30 AD14 VSS VSS AY36
AP13 VSS VSS P32 AD16 VSS VSS AT43
C AP24 VSS VSS R12 AD18 VSS VSS BD31 C
AP31 VSS VSS R14 AD30 VSS VSS BD35
AP43 VSS VSS R16 AD32 VSS VSS BD39
AR2 VSS VSS R2 AD40 VSS VSS BD7
AK16 VSS VSS R34 AD6 VSS VSS D25
AT10 VSS VSS R38 AD8 VSS VSS AV7
AT15 VSS VSS R44 AE16 VSS VSS F15
AT17 VSS VSS R8 AE28 VSS VSS F20
AT20 VSS VSS T43 AF38 VSS VSS F29
AT26 VSS VSS U10 AF8 VSS VSS F33
AT29 VSS VSS U16 AG16 VSS VSS BC16
AT36 VSS VSS U28 AG2 VSS VSS D4
AT38 VSS VSS U34 AG26 VSS VSS G2
D42 VSS VSS U38 AG28 VSS VSS G38
AV13 VSS VSS U42 AG44 VSS VSS G44
AV22 VSS VSS U6 AJ16 VSS VSS G8
AV24 VSS VSS V14 AJ18 VSS VSS H10
BB25 VSS VSS V43 AJ24 VSS VSS H22
AV40 VSS VSS W2 AJ34 VSS VSS H24
AV6 VSS VSS W44 AJ38 VSS VSS H26
AW2 VSS VSS Y14 AJ6 VSS VSS H31
F43 VSS VSS Y16 AJ8 VSS VSS H36
AY10 VSS VSS Y24 AK14 VSS VSS H40
AY15 VSS VSS Y28 AK24 VSS VSS H7
AY20 VSS VSS Y34 AK43 VSS VSS K10
AY26 VSS VSS Y36 AK45 VSS VSS K15
AY29 VSS VSS Y40 AL12 VSS VSS K20
AY7 VSS VSS Y8 AL2 VSS VSS K29
B11 VSS VSS BC22 VSS VSS K33
B15 VSS BB42 VSS VSS BC28
B VSS VSS VSS B
10 OF 11 11 OF 11
DH82LPMS-QCG1-B0_FCBGA695~D DH82LPMS-QCG1-B0_FCBGA695~D
A A
PROPRIETARY NOTE:
Title
PCH (9/9)
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1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW Q83B Battery LED

HDD LED solution for White LED DMN66D0LDW-7_SOT363-6~D
10K_0402_5%
+5V_ALW 4 3 BAT2_LED#_Q 1 2 BATT_WHITE# <47>
<45> BAT2_LED#
1
R949 1K_0402_5%
R932
BATT_YELLOW# <47>
5
MASK_BASE_LEDS#
3
Q74B
2
DMN66D0LDW-7_SOT363-6~D Q74A
D59 DMN66D0LDW-7_SOT363-6~D
4 3 1 2 1 6 2
<15> SATA_ACT#
RB751V40_SC76-2 Q75 1 2 BATT_WHITE_LED# <28>
PDTA114EU_SC70-3~D R958 680_0402_5%
2
<45> MASK_SATA_LED# BATT_YELLOW_LED# <28>
1
D D
D62 1 2
1 2 MASK_BASE_LEDS# R934 680_0402_5% SATA_LED <47>
<45> LED_SATA_DIAG_OUT#
RB751V40_SC76-2 Q83A
1 6 BAT1_LED#_Q 1 2
<45> BAT1_LED#
R951 330_0402_5%
PANEL_HDD_LED <28>
2
MASK_BASE_LEDS#
3
Q84B
4 3 2
1 2
Q81 R953 330_0402_5%
PDTA114EU_SC70-3~D
1
1 2 Q84A LED1 +5V_ALW
SYS_LED_MASK# R938 680_0402_5% Breath LED DMN66D0LDW-7_SOT363-6~D
1 6 BREATH_LED#_Q 1 2 BREATH_WHITE_LED_SNIFF 1 2
<44,45> BREATH_LED#
R957 220_0402_5%
LTW-193ZDS5_WHITE~D
Place LED1 close to SW1
2
MASK_BASE_LEDS#
+3.3V_ALW
WLAN LED solution for White LED

100K_0402_5%
+5V_ALW
1
1 2 BREATH_WHITE_LED# <28>
R937
R955 680_0402_5%
3
Q100
L2N7002WT1G_SC-70-3
2
C C
S
D
3 1 2
<37,38,45> WIRELESS_LED#
PWR SW
POWER_SW#_MB 2 SW1 1
G
2
Q79 <35,46> POWER_SW#_MB

MASK_BASE_LEDS# PDTA114EU_SC70-3~D
1
3
1
2 4 3
D23 SKRBAAE010_4P~D
@
L30ESDL5V0C3-2_SOT23-3
1 2
R3671 1K_0402_5% WLAN_LED <47> POWER & INSTANT ON SWITCH
+3.3V_ALW
@ C778
1 2
0.1U_0402_25V6
5
SYS_LED_MASK# 1
P
+3.3V_ALW <33,45> SYS_LED_MASK# B 4 MASK_BASE_LEDS#
LID_CL# 2 O
<45,47> LID_CL# A
G
100K_0402_5%
@ U58
+5V_ALW +5V_ALW TC7SH08FU_SSOP5~D
3
1
R940
3
2
B B
2 AUDIO_BACKLITE# 2
<45> AUDIO_BACKLITE#
LED Circuit Control Table
@ Q82 @ Q80
PDTA114EU_SC70-3~D PDTA114EU_SC70-3~D
SYS_LED_MASK# LID_CL#
1
@ R954 @ R3672
1 2 1 2
1.4K_0402_1% VOL_DOWN_LED <47> 1.4K_0402_1% VOL_UP_LED <47> Mask All LEDs (Sniffer Function) 0 X
Mask Base MB LEDs (Lid Closed) 1 0
+5V_ALW Do not Mask LEDs (Lid Opened) 1 1
3
AUDIO_BACKLITE# 2 Fiducial Mark EMI CLIP

CLIP1
@ R988 @ FD1 @ FD2 @ FD3 @ FD4 EMI_CLIP
1 2 1 1 1 1
<45> SPKR_MUTE_LED# VOL_MUTE_YELLOW_LED# <47>
1.4K_0402_1% @ Q86 1
PDTA114EU_SC70-3~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D GND
1
@ R989
1 2
1.4K_0402_1% VOL_MUTE_WHITE_LED <47> @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H11 @ H12 @ H13 @ H14 @ H15
H_2P8 H_6P2 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P3 H_2P3
1
A @ H22 @ H20 @ H30 @ H16 @ H17 @ H18 @ H19 @ H21 @ H23 @ H24 @ H25 @ H26 @ H27 @ H28 @ H29 A
H_4P8 H_2P3 H_2P3 H_3P5 H_3P5 H_3P5 H_3P5 H_2P5X8P0 H_3P5 H_3P5 H_3P5 H_2P8 H_2P8 H_3P8 H_3P8
1
PROPRIETARY NOTE:
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Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PWR SW/LED/PAD/ME
1.0
5 4 3 2 1
2 1
B
SW for MB/DOCK B
+5V_RUN +3.3V_RUN
U6
PCH_CRT_RED 1 16
<16> PCH_CRT_RED PCH_CRT_GRN 2 R 5V VDD
<16> PCH_CRT_GRN PCH_CRT_BLU 5 G 4
<16> PCH_CRT_BLU PCH_CRT_HSYNC 6 B VDD 23
<16> PCH_CRT_HSYNC PCH_CRT_VSYNC 7 H_SOURCE VDD 32
<16> PCH_CRT_VSYNC PCH_CRT_DDC_DAT 9 V_HOURCE VDD
<16> PCH_CRT_DDC_DAT 10 SDA_SOURCE 27
PCH_CRT_DDC_CLK RED_CRT
<16> PCH_CRT_DDC_CLK SCL_SOURCE R1 25 GREEN_CRT RED_CRT <47>
G1 22 BLUE_CRT GREEN_CRT <47>
CRT_SWITCH 30 B1 20 HSYNC_BUF BLUE_CRT <47>
<45> CRT_SWITCH SEL H1_OUT 18 VSYNC_BUF HSYNC_BUF <47>
V1_OUT 12 DAT_DDC2_CRT VSYNC_BUF <47>
29 SDA1 14 CLK_DDC2_CRT DAT_DDC2_CRT <47>
+3.3V_RUN TEST SCL1 CLK_DDC2_CRT <47>
1 2 8 26 RED_DOCK
+3.3V_RUN Reserved R2 RED_DOCK <44>
R61 4.7K_0402_5% 24 GREEN_DOCK
3 G2 21 BLUE_DOCK GREEN_DOCK <44>
11 GND B2 19 HSYNC_DOCK BLUE_DOCK <44>
28 GND H2_OUT 17 VSYNC_DOCK HSYNC_DOCK <44>
31 GND V2_OUT 13 DAT_DDC2_DOCK VSYNC_DOCK <44>
33 GND SDA2 15 CLK_DDC2_DOCK DAT_DDC2_DOCK <44>
GPAD SCL2 CLK_DDC2_DOCK <44>
TS3V713ELRTGR_TQFN32_6X3~D
+3.3V_RUN +5V_RUN
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
SEL1/SEL2 Chanel Source
1 1 1 1 1 1
0 A=B1 MB @ @
C25
C26
C27
C28
C29
C30
1 A=B2 APR/SPR 2 2 2 2 2 2
A A
PROPRIETARY NOTE:
Title
CRT SW
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1.0
2 1
2 1
+1.5V_RUN
1
PAD-OPEN1x1m
@ PJP2
2
+3.3V_RUN
+1.5V_RUN_HDMI
0.01U_0402_16V7K
0.1U_0402_25V6
0.01U_0402_16V7K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1 1 1 1 1
C354
C355
C340
C344
C342
1 1
C31
C32
2 2 2 2 2 1 2
2 2 @ R62 0_0402_5%
L1 EMC@
TMDSE_RP_CLK# 4 3 TMDSE_CON_CLK#
4 3
11
37
12
40
20
31
19
U19 TMDSE_RP_CLK 1 2 TMDSE_CON_CLK
1 2
VDD33
VDD33
VDDRX
VDDRX
VDDTX
VDDTX
VDDTA
C349 2 1 0.1U_0402_10V6K TMDSE_CPU_P2_C 6 DLW21SN900HQ2L_0805_4P~D
<9> TMDSB_CPU_P2 IN_D0p
1.8P_0402_50V8
1.8P_0402_50V8
C348 2 1 0.1U_0402_10V6K TMDSE_CPU_N2_C 7 1 @ 1 @
<9> TMDSB_CPU_N2 2 1 4 IN_D0n 1 2
C347 0.1U_0402_10V6K TMDSE_CPU_P1_C
<9> TMDSB_CPU_P1 IN_D1p
CE7
CE5
C346 2 1 0.1U_0402_10V6K TMDSE_CPU_N1_C 5 @ R63 0_0402_5%
<9> TMDSB_CPU_N1 2 1 1 IN_D1n
C351 0.1U_0402_10V6K TMDSE_CPU_P0_C
<9> TMDSB_CPU_P0 2 1 2 IN_D2p 2 2
C350 0.1U_0402_10V6K TMDSE_CPU_N0_C
<9> TMDSB_CPU_N0 IN_D2n
RB751VM-40TE-17_SOD323-2~D
C352 2 1 0.1U_0402_10V6K TMDSE_CPU_CLK_C 9
<9> TMDSB_CPU_CLK 2 1 IN_CKp
B C353 0.1U_0402_10V6K TMDSE_CPU_CLK#_C 10 1 2 B
<9> TMDSB_CPU_CLK# IN_CKn 25 TMDSE_RP_P2 +5V_RUN @ R64 0_0402_5%
36 OUT_D0p 24 TMDSE_RP_N2
PD# OUT_D0n 27 TMDSE_RP_P1 L2 EMC@
8 OUT_D1p 26 TMDSE_RP_N1 TMDSE_RP_P0 1 2 TMDSE_CON_P0
I2C_CTL_EN OUT_D1n 30 TMDSE_RP_P0 1 2
OUT_D2p
1
0_0402_5%
@ R67
29 TMDSE_RP_N0
OUT_D2n
@ D2
@ R65 1 2 4.7K_0402_5% 13 22 TMDSE_RP_CLK TMDSE_RP_N0 4 3 TMDSE_CON_N0
+3.3V_RUN DCIN_EN/SCL_CTL OUT_CKp 4 3
HDMI_BUF 14 21 TMDSE_RP_CLK#
DDCBUF/SDA_CTL OUT_CKn DLW21SN900HQ2L_0805_4P~D
1.8P_0402_50V8
1.8P_0402_50V8
HDMI_ISET 34 1 @ 1 @
2
ISET 1 2
CE17
CE16
@ R68 0_0402_5%
PCH_DDPB_CTRLCLK 38 32 HDMI_SCL_SINK 1.5K_0402_5% 2 1 R69 +5V_HDMI_DDC
<16> PCH_DDPB_CTRLCLK 39 SCL_SRC SCL_SNK 33 2 1 R70 2 2
PCH_DDPB_CTRLDATA HDMI_SDA_SINK 1.5K_0402_5%
<16> PCH_DDPB_CTRLDATA SDA_SRC SDA_SNK 1 2
@ R71 0_0402_5%
+3.3V_RUN R72 1 2 4.7K_0402_5% 23
CFG 28 HDMI_HPD_SINK L3 EMC@
HPD_SNK TMDSE_RP_P1 1 2 TMDSE_CON_P1
HDMI_EQ 17 1 2
HDMI_PRE 16 EQ//I2C_ADDR0
PRE/I2C_ADDR1 TMDSE_RP_N1 4 3 TMDSE_CON_N1
+3.3V_RUN 4 3
HDMIB_PCH_HPD 3 DLW21SN900HQ2L_0805_4P~D
<16> HDMIB_PCH_HPD HPD_SRC
1.8P_0402_50V8
1.8P_0402_50V8
HDMI_CEC 2 1 1 @ 1 @
10K_0402_5% R73 1 2
GND PAD
CE13
CE18
18 @ R74 0_0402_5%
REXT HDMIB_PCH_HPD 1 2
GND
GND
2 2
4.32K_0402_1%
100K_0402_5% R75
1
1 2
R76
PS8401ATQFN40GTR-A3_TQFN40_5X5 @ R77 0_0402_5%
15
35
41
L4 EMC@
TMDSE_RP_P2 1 2 TMDSE_CON_P2
PS8401ATQFN40GTR2-A4 1 2
2
TMDSE_RP_N2 4 3 TMDSE_CON_N2
4 3
DLW21SN900HQ2L_0805_4P~D
1.8P_0402_50V8
1.8P_0402_50V8
1 @ 1 @
+3.3V_RUN +3.3V_RUN 1 2
CE15
CE14
@ R78 0_0402_5%
2 2
1
1
4.7K_0402_5%
4.7K_0402_5%
@ R79
@ R80
2
HDMI_BUF HDMI_EQ +5V_RUN
+VDISPLAY_VCC
1
1
4.7K_0402_5%
4.7K_0402_5%
@ R81
@ R82
0.1U_0402_10V6K
10U_0805_10V6K
IN
2
U89 1 1
C47
AP2330W-7_SC59-3
C46
2 2
GND
OUT
Enable active DDC buffer; Internal pull up at ~150KΩ, 3.3V I/O Receiver equalization setting; Internal pull down at ~150kΩ, 3.3V I/O.
3
L: default, passive DDC pass-through L: programmable EQ for channel loss up to 5.3dB JHDMI1
HDMI_HPD_SINK 1 2 HDMI_HPD_SINK_R 19
H: active DDC buffer with default threshold H: programmable EQ for channel loss up to 10dB R84 10K_0402_5% 18 HP_DET
M: passive DDC pass-through with internal ~10KΩ pull up M: programmable EQ for channel loss up to 14dB 17 +5V
HDMI_SDA_SINK 16 DDC/CEC_GND
HDMI_SCL_SINK 15 SDA
+3.3V_RUN 14 SCL
A +3.3V_RUN HDMI_CEC 13 Reserved A
TMDSE_CON_CLK# 12 CEC
11 CK-
CK_shield
1
4.7K_0402_5%
TMDSE_CON_CLK 10
CK+
1
4.7K_0402_5%
@ R86
TMDSE_CON_N0 9
D0-
@ R85
8
TMDSE_CON_P0 7 D0_shield
TMDSE_CON_N1 6 D0+
2
5 D1-
2
TMDSE_CON_P1 4 D1_shield 20
HDMI_PRE TMDSE_CON_N2 3 D1+ GND 21
HDMI_ISET 2 D2- GND 22
TMDSE_CON_P2 1 D2_shield GND 23
D2+ GND
1
4.7K_0402_5%
1
4.7K_0402_5%
@ R88
CONCR_099AKAC19NBLCNF
@ R87
CONN@
2
2
TMDS output swing adjustment; Internal pull down at ~150kΩ, 3.3V I/O. Output pre-emphasis setting; Internal pull down at ~150kΩ, 3.3V I/O.
L: default L: no pre-emphasis
H: increase +13% H: 1.6dB pre-emphasis
PROPRIETARY NOTE:
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M: reduce -13% M: 3.0dB pre-emphasis THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDMI CONN
1.0
2 1
5 4 3 2 1
+3.3V_RUN_EDP +3.3V_RUN_EDP
D Power Consumption: D
2
2
R105
EEPROM
R107 @
EEPROM +3.3V_RUN_EDP Pin5 (DPV33) < 20mA
4.7K_0402_5% 4.7K_0402_5% EEROM Pin 11 (DPV12) < 100mA
1
1
MIIC_SCL0 MIIC_SDA0 U26 @
Pin 15 (SWR_VCCK) < 100mA (layout trace > 60 mil)
8
VCC A0
1 Pin 17 (SWR_LX) < 600mA (layout trace > 60 mil)
2
2
7 2
R106 @ R108 MIIC_SCL 6 WP
SCL
A1
A2
3 Pin 18 (SWR_VDD) < 200mA (layout trace > 40 mil)
4.7K_0402_5% ROMLESS 4.7K_0402_5% ROMLESS MIIC_SDA 5 4
SDA GND Pin 22 (PVCC) < 50 mA
CAT24C64WI-GT3_SO8
Pin 43 (VCCK) < 50mA
1
1
Addr: A8 (1010 100X)
+3.3V_RUN +3.3V_RUN_EDP
30mil 30mil
@ PJP67
1 2
C U27 C
PAD-OPEN1x1m
RTD2136S
+AVCC33 35
+3.3V_RUN_EDP 22 TXOC+ 36 CVT_LVDS_ACLK+ <28>
PVCC TXOC- CVT_LVDS_ACLK- <28>
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 0_0805_5% 2 1R3881 @ +DVCC33 40 mils 18 41

SWR_VDD TXO0+ 42 CVT_LVDS_A0+ <28>
TXO0- CVT_LVDS_A0- <28>
C106
C107
C108
PWR
0_0805_5% 2 1R3882 @ +AVCC33 5
DP_V33 39
2 2 2 +SWR_V12 @ R3883 1 20_0805_5% +SW_LX 60 mils 17 TXO1+ 40 CVT_LVDS_A1+ <28>
SWR_LX TXO1- CVT_LVDS_A1- <28>
60 mils 15 37
SWR_VCCK TXO2+ 38 CVT_LVDS_A2+ <28>
43 TXO2- CVT_LVDS_A2- <28>
Close to 5 pin VCCK
60 mils 33
11 TXO3+ 34
+SWR_V12 DP_V12 TXO3-
LVDS
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
25
C100 2 1 0.1U_0402_10V6K EDP_CPU_LANE_P0_C 7 TXEC+ 26 CVT_LVDS_BCLK+ <28>
1 1 1 1 <9> EDP_CPU_LANE_P0 LANE0P TXEC- CVT_LVDS_BCLK- <28>
C101 2 1 0.1U_0402_10V6K EDP_CPU_LANE_N0_C 8
<9> EDP_CPU_LANE_N0 LANE0N
C109
C110
C111
C112
31
C103 2 1 0.1U_0402_10V6K EDP_CPU_LANE_P1_C 9 TXE0+ 32 CVT_LVDS_B0+ <28>
2 2 2 2 <9> EDP_CPU_LANE_P1 LANE1P TXE0- CVT_LVDS_B0- <28>
C118 2 1 0.1U_0402_10V6K EDP_CPU_LANE_N1_C 10
<9> EDP_CPU_LANE_N1 LANE1N
DP
29
C104 2 1 0.1U_0402_10V6K EDP_CPU_AUX_C 4 TXE1+ 30 CVT_LVDS_B1+ <28>
<9> EDP_CPU_AUX AUX-CH_P TXE1- CVT_LVDS_B1- <28>
C105 2 1 0.1U_0402_10V6K EDP_CPU_AUX#_C 3
<9> EDP_CPU_AUX# AUX-CH_N 27
Close to 11 pin Close to 43 pin TXE2+ CVT_LVDS_B2+ <28>
CPU_EDP_HPD 1 28
<9> CPU_EDP_HPD DP_HPD TXE2- CVT_LVDS_B2- <28>
B 23 B
1 2 TXE3+ 24 1 2 MIIC_SDA
+DVCC33 R114 100K_0402_5% TXE3- @ R112 1 2 0_0402_5% MIIC_SCL
1 2 BIA_PWM_PCH_R 21 @ R113 0_0402_5%
<16> BIA_PWM_PCH PWMIN
10U_0603_6.3V6M
0.1U_0402_16V4Z
22U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@ R109 0_0402_5% 1 2 2 46 LCD_EDID_CLK

@ R100 1 2 0_0402_5% 12 TESTMODE MIICSCL1 45 LCD_EDID_DATA LCD_EDID_CLK <28>
1 1 1 1 1 DP_REXT MIICSDA1 LCD_EDID_DATA <28>
OTHERS
R101 12K_0402_1%
C113
C114
C115
C116
C117
20 LCD_ENVDD_CVT
PANEL_VCC 19 BIA_PWM_CVT LCD_ENVDD_CVT <28>
2 2 2 2 2 MIIC_SCL 1 2 MIIC_SCL0 48 PWMOUT 44 PANEL_BKEN_CVT BIA_PWM_CVT <28>
MIIC_SDA @ R102 1 2 0_0402_5% MIIC_SDA0 47 MIICSCL0 BL_EN PANEL_BKEN_CVT <28>
@ R103 0_0402_5% MIICSDA0
Close to 18 pin Close to 22 pin DDR_XDP_WAN_SMBCLK 13 6

<7,13,14,15,18,31> DDR_XDP_WAN_SMBCLK 14 CIICSCL1 DP_GND
DDR_XDP_WAN_SMBDAT
<7,13,14,15,18,31> DDR_XDP_WAN_SMBDAT CIICSDA1
GND
16 +UTLGND 1 2
GND @ R104 0_0402_5%
49
PAD
RTD2136S-CG_QFN48_6X6
+3.3V_RUN_EDP Symbol need to update

1. RTD2136S:SA00004NW10 Populated R102, R103, R107; De-populated R108
1
@ *** 2. RTD2136R SA000067100 : De-Populated R102, R103, R107; Populate R108;

R110
100K_0402_5%
2
A EDP_CPU_AUX A
EDP_CPU_AUX#
1
@
R111
100K_0402_5%
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
eDP to LVDS CONVERTER
www.Vinafix.vn
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
AUX termination NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-9411P
Date: Wednesday, April 10, 2013 Sheet 27 of 77
5 4 3 2 1
5 4 3 2 1
1 2
@ R115 0_0402_5%
+3.3V_ALW
C726 @
JLVDS1 CONN@ +5V_ALW for panel side LED power

2 1
0.1U_0402_25V6
U55 @
TC7SH08FU_SSOP5~D
Power Control for +LCDVDD
5
1
GND +5V_ALW
2 1
P
BATT_WHITE_LED 3 BATT_WHITE_LED# <24> <27> LCD_ENVDD_CVT B 4 2 1 EN_LCDPWR
BATT_YELLOW_LED 4 BATT_YELLOW_LED# <24> 2 O
BREATH_WHITE_LED BREATH_WHITE_LED# <24> <16,45> ENVDD_PCH A
G
5 +BL_PWR_SRC D65
VR_SRC
100K_0402_5%
D
6 1 2 RB751V40_SC76-2 D
3
VR_SRC
2
7 @ C246 0.1U_0603_50V7K +LCDVDD
VR_SRC 8 +3.3V_ALW
R517
NC 9 PANEL_HDD_LED <24>
DISP_ON U104
DISP_ON/OFF# 10 1 2 BIA_PWM_LVDS 1 14 1 2
PWM 11 @ RE32 0_0603_5% 2 VIN1 VOUT1 13 @ C762 10U_0603_6.3V6M
1
CONNTST_GND 12 VIN1 VOUT1
VR_GND 13 2 1 3 12 1 2
VR_GND 14 <45> LCD_VCC_TEST_EN ON1 CT1 C477 470P_0402_50V7K
VR_GND 15 D73 4 11
LCD_B_CLK+ CVT_LVDS_BCLK+ <27> +5V_ALW VBIAS GND
16 RB751V40_SC76-2
LCD_B_CLK- CVT_LVDS_BCLK- <27>
5P_0402_50V8C
5P_0402_50V8C
17 1 2 5 10 1 2
GND 18 <45,62> SUS_ON ON2 CT2
1 @ 1 @ @ R1607 0_0402_5% C486 470P_0402_50V7K
LVDS_B2+ 19 CVT_LVDS_B2+ <27> 1 2 6 9
LVDS_B2- CVT_LVDS_B2- <27> <16,35,45,62> SIO_SLP_S4# VIN2 VOUT2 +3.3V_SUS
C40
C41
20 @ R1608 0_0402_5% 7 8
LVDS_B1+ CVT_LVDS_B1+ <27> VIN2 VOUT2
10U_0603_6.3V6M
21 1 2 1
LVDS_B1- CVT_LVDS_B1- <27> 2 2 <45> USH_PWR_ON
C765
22 @ R1620 0_0402_5% 15
LVDS_B0+ 23 CVT_LVDS_B0+ <27> GPAD
LVDS_B0- 24 CVT_LVDS_B0- <27>
TPS22966DPUR_SON14_2X3~D
GND 25 2 @
LVDS_A_CLK+ 26 CVT_LVDS_ACLK+ <27>
LVDS_A_CLK- 27 CVT_LVDS_ACLK- <27>
GND
5P_0402_50V8C
5P_0402_50V8C
28 1 1
LVDS_A2+ 29 CVT_LVDS_A2+ <27> @ @
LVDS_A2- CVT_LVDS_A2- <27>
Power Control for +3.3V_SUS
C49
C43
30
LVDS_A1+ 31 CVT_LVDS_A1+ <27>
LVDS_A1- 32 CVT_LVDS_A1- <27> 2 2
LVDS_A0+ 33 CVT_LVDS_A0+ <27>
LVDS_A0- 34 CVT_LVDS_A0- <27>
LCD_EDID_DATA
46 EDID_DATA 35 LCD_EDID_DATA <27>
LCD_EDID_CLK
45 MGND6 EDID_CLK 36 LCD_EDID_CLK <27>
LCD_TST
44 MGND5 BIST 37 LCD_TST <45>
MGND4 V_EDID +3.3V_RUN
43 38
42 MGND3 LCD_VDD 39
MGND2 LCD_VDD +LCDVDD
41 40
MGND1 CONNTST LCD_CBL_DET# <16>
C ACES_59003-04006-001 C
+3.3V_ALW
@ C725
1 2
0.1U_0402_25V6
R1139
U54 1 2
TC7SH08FU_SSOP5~D 100K_0402_5%
5
D66 D64 1
P
+3.3V_RUN 1 2 1 2 4 B PANEL_BKEN_CVT <27>
BIA_PWM_LVDS DISP_ON
BIA_PWM_CVT <27> O 2
A PANEL_BKEN_PCH <16>
G
100K_0402_5%
1 2 LCD_EDID_DATA RB751V40_SC76-2 RB751V40_SC76-2
1
10K_0402_5%
R159 2.2K_0402_5%
3
1
R1138
1 2 LCD_EDID_CLK D69
R1137
R160 2.2K_0402_5% D68 1 2
1 2 PANEL_BKEN_EC <45>
BIA_PWM_EC <46>
Place near to JLVDS1 RB751V40_SC76-2
2
2 RB751V40_SC76-2
+LCDVDD +BL_PWR_SRC
0.1U_0402_25V6
0.1U_0603_50V7K
@ 1
1
C298
C247
2
2 @
B Close to JLVDS1.42,43 Close to JLVDS1.42,43 B
FDC654P: P CHANNAL
LCD Backlight +PWR_SRC
Q21
FDC654P-G_SSOT-6~D +BL_PWR_SRC
0.1U_0603_50V7K
4 5
S
1
2
For Webcam
1000P_0402_50V7K
C296
1
100K_0402_5%
G
1
1
2
3
C297
1 2
R422
@ R427 0_0402_5%
2
L10 EMC@
2
USBP12+ 1 2 USBP12_D+
<19> USBP12+ 1 2
USBP12- 4 3 USBP12_D- PWR_SRC_ON

<19> USBP12- 4 3 +CAMERA_VDD Q22
DLW21SN121SQ2L_4P~D L2N7002WT1G_SC-70-3
JCAM1
1 2 1 1 2 1 3
S
<16> CAM_MIC_CBL_DET# 2 1
@ R428 0_0402_5% USBP12_D+ R423 47K_0402_5%
USBP12_D- 3 2
4 3
G
2
5 4
<30> DMIC_CLK 6 5
7 6 EN_INVPWR
<30> DMIC0 8 7 <46> EN_INVPWR
8
100P_0402_50V8J
100P_0402_50V8J
9
Panel backlight power control by EC
Webcam PWR CTRL 1 1 10 G1
G2
2
3
@ C1206
@ C1207
PS_HPW10003-08MR2
CONN@
+CAMERA_VDD +3.3V_RUN 2 2
D8 @
A Q23 A
DMG2301U-7_SOT23-3
1 3
D
S
0.1U_0402_25V6
10U_0805_10V6K
0.1U_0402_25V6
1
G
2
1 1 1
C299
C300
C301
<45> CCD_OFF
2 2 @ 2
PROPRIETARY NOTE:
www.Vinafix.vn
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LVDS/CAM/TS
1.0
5 4 3 2 1
5 4 3 2 1
AUX/DDC GPU for DPC to E-DOCK

+3.3V_RUN
C356
1 2
D 0.1U_0402_25V6 D
U20
1 14
2 1 DPC_PCH_DOCK_AUX_C 2 BE0 VCC 13
<16> DPC_PCH_DOCK_AUX A0 BE3
C357 0.1U_0402_10V6K
DPC_DOCK_AUX 3 12 PCH_DDPC_CTRLCLK
<44> DPC_DOCK_AUX B0 A3 PCH_DDPC_CTRLCLK <16>
4 11
2
1 DPC_PCH_DOCK_AUX#_C 5 BE1 B3 10
<16> DPC_PCH_DOCK_AUX# A1 BE2
C360
0.1U_0402_10V6K
DPC_DOCK_AUX# 6 9 PCH_DDPC_CTRLDATA
<44> DPC_DOCK_AUX# B1 A2 PCH_DDPC_CTRLDATA <16>
7 8
GND B2
PI3C3125LEX_TSSOP14~D
+3.3V_RUN
10K_0402_5%
1
R415
2
DPC_CA_DET#
1
D
C DPC_CA_DET 2 Q5 C
<44> DPC_CA_DET
G L2N7002WT1G_SC-70-3
S
3
1 2 DPD_CA_DET
R491 1M_0402_5% +5V_RUN
1 2 DPC_CA_DET C365 @
R492 1M_0402_5% 1 2
0.1U_0402_25V6
1
P
NC
+3.3V_RUN 2 4
A Y
G
U21 @
TC7SET04FU_SSOP5~D
3
1 2 PCH_DDPC_CTRLCLK
R1539 2.2K_0402_5%
1 2 PCH_DDPC_CTRLDATA +3.3V_RUN
R1530
R1066
1 2
2.2K_0402_5%
PCH_DDPD_CTRLCLK
2.2K_0402_5%
AUX/DDC GPU for DPD to E-DOCK 1
C366
2
1 2 PCH_DDPD_CTRLDATA 0.1U_0402_25V6
R1062 2.2K_0402_5%
U23
1 14
2
1 DPD_PCH_DOCK_AUX_C 2 BE0 VCC 13
<16> DPD_PCH_DOCK_AUX A0 BE3
C367 0.1U_0402_10V6K
B DPD_DOCK_AUX 3 12 PCH_DDPD_CTRLCLK B
<44> DPD_DOCK_AUX B0 A3 PCH_DDPD_CTRLCLK <16>
4 11
2 1 DPD_PCH_DOCK_AUX#_C 5 BE1 B3 10
<16> DPD_PCH_DOCK_AUX# A1 BE2
C368 0.1U_0402_10V6K
DPD_DOCK_AUX# 6 9 PCH_DDPD_CTRLDATA
<44> DPD_DOCK_AUX# B1 A2 PCH_DDPD_CTRLDATA <16>
7 8
GND B2
PI3C3125LEX_TSSOP14~D
+3.3V_RUN
10K_0402_5%
1
R416
2
DPD_CA_DET#
1
D
DPD_CA_DET 2 Q6
<44> DPD_CA_DET
G L2N7002WT1G_SC-70-3
S
3
+5V_RUN
C369 @
1 2
A 0.1U_0402_25V6 A
5
1
P
NC
2 4
A Y U24 @ DELL CONFIDENTIAL/PROPRIETARY
G
TC7SET04FU_SSOP5~D
3
PROPRIETARY NOTE:
Title
DP SW
www.Vinafix.vn
1.0
5 4 3 2 1
2 1
INT_SPK_L+, INT_SPKL_L+ :40 mils trace, keep 10mils spacing

Internal Speakers Header INT_SPK_L-, INT_SPKL_L- :40 mils trace, keep 10mils spacing
INT_SPK_R+, INT_SPKR_R+ :40 mils trace, keep 10mils spacing
INT_SPK_R-, INT_SPKR_R- :40 mils trace, keep 10mils spacing place close to pin27 L77
BLM21PG600SN1D_0805~D +5V_RUN
INT_SPK_L-, INT_SPKL_L- with INT_SPK_R+, INT_SPKR_R+ keep 20mils spacing
JSPK1 +VDDA_AVDD 1 2 +5V_RUN
INT_SPK_L+ EMC@ L113 1 2 PBY160808T-300Y-N_2P INT_SPKL_L+ 1
1
1
0.1U_0402_25V6
10U_0805_10V6K
INT_SPK_L- EMC@ L114 1 2 PBY160808T-300Y-N_2P INT_SPKL_L- 2
INT_SPK_R+ EMC@ L115 1 2 PBY160808T-300Y-N_2P INT_SPKR_R+ 3 2 +3.3V_RUN +3.3V_RUN_DVDD +3.3V_RUN_DVDD PJP80
3 1 C968, C956 place close to pin38
1
INT_SPK_R- EMC@ L116 1 2 PBY160808T-300Y-N_2P INT_SPKR_R- 4 +DVDD_CORE 1 2 +3.3V_RUN
4 PAD-OPEN1x1m
C957
C955
@ PJP60
PJP81
10U_0805_10V6K
0.1U_0402_25V6
10U_0805_10V6K
Need to Link CIS 5 1 2 PAD-OPEN1x1m
2
6 GND 1 2 2
1
2
GND
1
1U_0603_10V6K
0.1U_0402_25V6
1U_0603_10V6K
0.1U_0402_25V6
JUMP_43X79 1 C959, C958 place close to pin39
1
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
C954
C968
C956
ACES_50279-0040N-001
C952
C994
C984 @
C953 @
0.1U_0402_25V6
10U_0805_10V6K
0.1U_0402_25V6
10U_0805_10V6K
@ @ @ @ CONN@
2
2
1 1 1 1 1 1
1
2
C973
C974
C975
C976
U74
C959
C958
C961
C960
1 27
DREG_OUT AVDD1 38 +VDDA_AVDD2
2
2 2 2 2 AVDD2/HVDD(3.3) 2 2
3 45 +VDDA_PVDD C961, C960 place close to pin45
DVDD-IO PVDD2 39
PVDD1
1
1
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
@ @ @ @
R1680
R1681
R1682
R1683
9 13 AUD_SENSE_A
DVDD Sense A 14 AUD_SENSE_B
Sense B
DVDD_IO should match 28 RING2
2
with HDA Bus level PCH_AZ_CODEC_BITCLK 6 LINE1-L/RING2 29 SLEEVE

<15> PCH_AZ_CODEC_BITCLK BIT-CLK LINE1-R/SLEEVE 23 +VREFOUT +VREFOUT
PCH_AZ_CODEC_SDOUT 5 LINE1-VREFO
<15> PCH_AZ_CODEC_SDOUT SDATA-OUT 31 C969 1 2 10U_0805_10V6K
10 HPOUT-L/MIC-CAP 33 AUD_HP_OUT_L
<15> PCH_AZ_CODEC_SYNC SYNC AVSS2/HPOUT-L
Place R1096 close to codec 32 AUD_HP_OUT_R SLEEVE and RING2 Routing 40 mils.
B 1 2 PCH_AZ_SDIN0_R 8 HP-OUT-R B
Close to U74 <15> PCH_AZ_CODEC_SDIN0 R1096 22_0402_5% SDATA-IN 40 INT_SPK_L+
PCH_AZ_CODEC_RST# 11 SPK-L+ 41 INT_SPK_L-
<15> PCH_AZ_CODEC_RST# RESET# SPK-L- 2 1 1 2
SPKR <15>
44 INT_SPK_R+ C1105 0.1U_0402_25V6 R1119 100K_0402_5%
SPK-R+ 43 INT_SPK_R- 2 1 1 2
SPK-R- BEEP <46>
DAI_12MHZ# 1 2 I2S_MCLK 15 AUD_PC_BEEP C1106 0.1U_0402_25V6 R1120 100K_0402_5%
<44> DAI_12MHZ# R1654 22_0402_5% I2S_MCLK 12 1 2
Close to U74 pin5 Close to U74 pin6 PCBEEP C989 place close to pin2
DAI_BCLK# 1 2 I2S_BCLK 16 @ C989 22P_0402_50V8J 1 2
<44> DAI_BCLK# R1668 22_0402_5% I2S_SCLK 2 DMIC_CLK_L 1 2 @ R1141 10K_0402_5%
PCH_AZ_CODEC_SDOUT PCH_AZ_CODEC_BITCLK DAI_DO# 1 2 I2S_DO 17 GPIO0/DMIC-CLK 4 EMC@ LE3 BLM18BB221SN1D_2P DMIC_CLK <28> 1 2
<44> DAI_DO# I2S_DOUT GPIO1/DMIC-DATA DMIC0 <28>
22P_0402_50V8J
22P_0402_50V8J
R1097 33_0402_5%
DMIC1/GPIO2
46 Place LE3 close to codec @ R1142 10K_0402_5%
C986 @
C987 @
1 1 DAI_LRCK# 18 48 1 2
<44> DAI_LRCK# I2S_LRCK GPIO3
1
@ R169 0_0402_5%
@ R1077 @ R1076 DAI_DI 24 37 EN_I2S_NB_CODEC#
<44> DAI_DI I2S_DIN MONO-OUT/CBP EN_I2S_NB_CODEC# <45>
47_0402_5% 33_0402_5% 1
2 2
C962
1 2
1 2
MIC1_L 19 35 2.2U_0603_16V6K
MIC1-L CBN 2
BCLK: Audio serial data bus bit clock input/output
@ C978 @ C977 LRCK: Audio serial data bus word clock MIC1_R 20
0.1U_0402_10V6K 10P_0402_50V8J MIC1-R
2
input/output 36
AUD_NB_MUTE# 47 CBP/AVSS2
<45> AUD_NB_MUTE# EAPD/PD 21
LDO-CAP
1U_0603_10V6K
+3.3V_RUN 1 2 22
R1099 10K_0402_5% 7 JDREF 34
When no external power, it Sleeve will be floating mode and no reference GND. 1 DVSS CPVEE 25
VREF
C967 @
10U_0805_10V6K
42
PVSS
1
2.2U_0603_16V6K
+RTC_CELL
0.1U_0402_25V6
2.2U_0603_16V6K
20K_0402_1%
R1642
30 +MIC1_VREF_OUT 1
MIC1-VREFO
2
C1107
2 49 26
GND AVSS1
C1214
C965
C963
SLEEVE
1
ALC3226-CG_QFN48_7X7
1
2
2
3
RB751VM-40TE-17_SOD323-2~D
RB751VM-40TE-17_SOD323-2~D
R1084
100K_0402_5%
Q327B
2
2
PCH_AZ_CODEC_RST# 1 2 5 +VREFOUT
@ R39
D12
D11
6
0_0402_5%
4
@ @
2 1
2 1
4.7K_0402_5%
4.7K_0402_5%
AUD_NB_MUTE# 1 2 2 SLEEVE R1145 1 2 2.2K_0402_5%
place at AGND and DGND plane
1U_0603_10V6K
Q327A
R209
R210
@ R40 support universal Jack RING2 R1146 1 2 2.2K_0402_5%
1
0_0402_5% 1 1 2 place at Codec bottom side

@ PJP62
@ @
C970 @
@ R5 1 2
1
0_0402_5%
2 1 2 MIC1_L 1 2 MIC1_L_C 1 2 AUD_HP_OUT_L1
PAD-OPEN1x1m @ C195 4.7U_0603_6.3V6K @ R198 1K_0402_5%
@ R6
0_0402_5% MIC1_R 1 2 MIC1_R_C 1 2 AUD_HP_OUT_R1
1 2 @ C196 4.7U_0603_6.3V6K @ R199 1K_0402_5%
@ R15
0_0402_5%
+3.3V_RUN
AUD_SENSE_A
Place closely to Pin 13.
Combo Jack
10K_0402_5%
1
1
39.2K_0402_1%
R1086
R1100
Symbol need update Normal
2
2
Open JHP1
base E-team detect issue , reserve RC to delay time 7
RING2 @ R54 1 2 0_0603_5% RING2_L 3
L2N7002WT1G_SC-70-3
AUD_HP_OUT_L 2 1 AUD_HP_OUT_L1 @ R56 1 2 0_0603_5% AUD_HP_OUT_L2 1

1
D R1677 9.1_0402_1%
2 AUD_HP_NB_SENSE
10U_0805_10V6K
G 5
0.1U_0402_25V6
S Q324
3
A A
1 1
C1247
AUD_HP_NB_SENSE 6
C972
AUD_HP_OUT_R 2 1 AUD_HP_OUT_R1 @ R57 1 2 0_0603_5% AUD_HP_OUT_R2 2

2 2 @ SLEEVE R1679 9.1_0402_1% @ R58 1 2 0_0603_5% EXT_MIC 4
SINGA_2SJ3080-001111F
CONN@
Add for solve pop noise and detect issue
Notes:
2
Place closely to Pin 14 RING2_L, RING2, AUD_HP_NB_SENSE <45>
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
L03ESDL5V0CC3-2_SOT23-3
Keep PVDD supply and speaker traces routed on the DGND plane.
@
AUD_HP_OUT_L2, AUD_HP_OUT_L1, AUD_HP_OUT_L,
0_0402_5%
D82
D83
D81
1
1
Keep away from AGND and other analog signals
C1211
C1212
C1213
C1215
AUD_SENSE_B
AUD_HP_OUT_R2, AUD_HP_OUT_R1, AUD_HP_OUT_R,
EXT_MIC, SLEEVE Trace width to 15mils.
R1676
EMC@
EMC@
2
1
2
@ @ @ @ R1088
1
+3.3V_RUN 100K_0402_5%
1
R1079 R1080 +3.3V_RUN
20K_0402_1%
Resistor SENSE_A SENSE_B
39.2K_0402_1%
2
1
R1081 39.2K PORT A PORT E

2
100K_0402_5%
R1082
100K_0402_5% 20K PORT B PORT F PORT A External MIC
2
2 5
10K NA DMIC0 PORT B HeadPhone Out
PROPRIETARY NOTE:
<45> DOCK_HP_DET DOCK_MIC_DET <45> Title
Q106A Q106B 5.11K SPDIFOUT0 SPDIFOUT1 (DMIC1) PORT C Dock Audio Codec
1
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
2.49K Pull-up to AVDD PORT D Internal SPK 1.0
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2 1
5 4 3 2 1
D D
HDD PWR
+5V_HDD +5V_RUN
@ PJP3
1 2
1 2
JUMP_43X79
SHORT DEFAULT
PJP53
+3.3V_RUN
1 2 +3.3V_RUN_FFS
Free Fall Sensor
10U_0603_6.3V6M
0.1U_0402_25V6
PAD-OPEN1x1m
1 1
U88
C387
C388
LNG3DM 10
2 2 1
14 VDD_IO
VDD
RES
RES
RES
13
15
16
HDD CONN
JSATA1
11 RES 1
<16> HDD_FALL_INT FFS_INT2 9 INT 1 5 C383 2 1 0.01U_0402_16V7K SATA_PTX_DRX_P0 2 GND
INT 2 GND 12 <15> PSATA_PTX_DRX_P0_C RX+
C384 2 1 0.01U_0402_16V7K SATA_PTX_DRX_N0 3
7 GND <15> PSATA_PTX_DRX_N0_C 4 RX-
6 SDO/SA0 C385 2 1 0.01U_0402_16V7K SATA_PRX_DTX_N0 5 GND
<7,13,14,15,18,27> DDR_XDP_WAN_SMBDAT 4 SDA / SDI / SDO <15> PSATA_PRX_DTX_N0_C TX-
C386 2 1 0.01U_0402_16V7K SATA_PRX_DTX_P0 6
<7,13,14,15,18,27> DDR_XDP_WAN_SMBCLK SCL/SPC 2 <15> PSATA_PRX_DTX_P0_C 7 TX+
8 NC 3 PJP64 GND
CS NC 1 2 +3.3V_RUN_HDD 8
C +3.3V_RUN 3.3V C
LNG3DMTR_LGA16_3X3~D 9
PAD-OPEN1x1m 1 2 +3.3V_RUN_HDD_R 10 3.3V
@ R1635 0_0402_5% 11 3.3V
HDD_DET# 12 GND
<15> HDD_DET# 13 GND
14 GND
+5V_HDD 5V
15
16 5V
+5V_HDD 17 5V
FFS_INT2_Q 18 GND 23
Reserved GND1
100K_0402_5%
19 24
GND GND2
1
20
12V
@ R506
21
+3.3V_RUN +5V_HDD +3.3V_RUN_HDD 22 12V
+3.3V_RUN 12V
100K_0402_5%
CONN@
2
1
1000P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
SANTA_196003-1
R508
1 2 DDR_XDP_WAN_SMBDAT
R501 10K_0402_5% FFS_INT2_Q 1 1 1 1
C395
C396
C402
C399
1 2 DDR_XDP_WAN_SMBCLK
3
R502 10K_0402_5% Main SATA +5V Default
2
1 2 HDD_FALL_INT
2 2 2 2 +3.3V_RUN
Q29B
R503 100K_0402_5%
5
6
1 2 +3.3V_RUN_HDD_R
4
@ R516 100K_0402_5%
Q29A
FFS_INT2 2
<20> FFS_INT2
Place near HDD CONN
1
B B
A A
PROPRIETARY NOTE:
Title
HDD
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1.0
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_ALW2
1
R509
100K_0402_5%
2
C C
MODC_EN#
L2N7002WT1G_SC-70-3
1
D
2
<45,48> MODC_EN
G
S
Q78
ODD CONN
3
JSATA2
1
C407 2 1 0.01U_0402_16V7K SATA_ODD_PTX_DRX_P1 2 GND
<15> SATA_ODD_PTX_DRX_P1_C A+
C406 2 1 0.01U_0402_16V7K SATA_ODD_PTX_DRX_N1 3
<15> SATA_ODD_PTX_DRX_N1_C 4 A-
C405 2 1 0.01U_0402_16V7K SATA_ODD_PRX_DTX_N1 5 GND
<15> SATA_ODD_PRX_DTX_N1_C C404 2 1 0.01U_0402_16V7K SATA_ODD_PRX_DTX_P1 6 B-
<15> SATA_ODD_PRX_DTX_P1_C 7 B+
GND
8
<46> DEVICE_DET# 9 DP
+5V_MOD +5V
Q76 10
L2N7002WT1G_SC-70-3 MOD_MD 11 +5V
12 MD
+3.3V_ALW 3 1 13 GND
S
MOD_MD ZODD_WAKE#
ZODD_WAKE# <45> GND
14
15 GND
G
<17> CLK_PCIE_EMB
2
1 2 MOD_SATA_PCIE#_DET MODC_EN# 16 REFCLK+

<17> CLK_PCIE_EMB# 17 REFCLK-
R1183 10K_0402_5%
B 18 GND B
<19> PCIE_PRX_EMBTX_P4 19 PETX+
<19> PCIE_PRX_EMBTX_N4 20 PETX-
Q123B
+3.3V_ALW_PCH DMN66D0LDW-7_SOT363-6~D 21 GND
4 3 USB30_SMI# 0.1U_0402_10V6K 2 1 C409 PCIE_PTX_EMBRX_P4_C 22 GND
USB30_SMI# <15> <19> PCIE_PTX_EMBRX_P4 2 1 C408 PCIE_PTX_EMBRX_N4_C 23 PERX+
0.1U_0402_10V6K
1 2 USB30_SMI# <19> PCIE_PTX_EMBRX_N4 24 PERX-
R514 100K_0402_5% GND
5
1 2 ZODD_WAKE# USB30_EN 25
+5V_MOD +5V
R510 10K_0402_5% 26
1 2 MOD_MD <17> EMBCLK_REQ# 27 CLKREQ#
<36,37,38,39,46> PCIE_WAKE# 28 WAKE#
R513 10K_0402_5%
<16> PLTRST_EMB# 29 PERST# 32
<46,60> BAY_SMBDAT 30 SMB_DATA GND1 33
<46,60> BAY_SMBCLK 31 SMB_CLK GND2
<45> MOD_SATA_PCIE#_DET HPD
+3.3V_ALW
100K_0402_5%
TYCO_2-2129116-3
1
CONN@
R515
+5V_MOD
2
1000P_0402_50V7K
0.1U_0402_25V6
USB30_EN
1 1
C397
C398
6
2 2
Q123A
MOD_SATA_PCIE#_DET 2
A A
1
Place near ODD CONN DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE:
Title
ODD
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1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_LAN
1 2 TP_LAN_JTAG_TMS
Confirm INTEL whether remove R548 +1.05V_M directly.
@ R545 10K_0402_5%
1 2 TP_LAN_JTAG_TCK
@ R546 10K_0402_5% +0.9V_LAN +1.05V_M
U31
@ R1187 1 2 0_0402_5% LANCLK_REQ#_R 48 13 LAN_TX0+ REGCTL_PNP10 1 2 1 2

<15,17> LANCLK_REQ# 36 CLK_REQ_N MDI_PLUS0 14 LAN_TX0- 4.7UH_CBC2012T4R7M_20%~D L29 0_0805_5% @ R548
+3.3V_LAN <16> PLTRST_LAN# PE_RST_N MDI_MINUS0
10U_0603_6.3V6M
0.1U_0402_10V6K
CLK_PCIE_LAN 44 17 LAN_TX1+ 1 1
<17> CLK_PCIE_LAN PE_CLKP MDI_PLUS1
C462
C463
1 2 LANWAKE#_R CLK_PCIE_LAN# 45 18 LAN_TX1-
<17> CLK_PCIE_LAN#
PCIE
PE_CLKN MDI_MINUS1
MDI
@ R558 4.7K_0402_5% 2 1 PCIE_PRX_GLANTX_P2_C
<19> PCIE_PRX_GLANTX_P2
D C458 0.1U_0402_10V6K 38 20 LAN_TX2+ D
+PCH_VCCDSW3_3 Support Deep S3 mode 2 1 PCIE_PRX_GLANTX_N2_C 39 PETp MDI_PLUS2 21 LAN_TX2- 2 2
<19> PCIE_PRX_GLANTX_N2 PETn MDI_MINUS2 Place R548, C462, C463 and L29 close to U31
C459 0.1U_0402_10V6K Pin 6 is SVR_EN in Clarkville
2 1 LANWAKE# +3.3V_LAN 1 2 PCIE_PTX_GLANRX_P2_C 41 23 LAN_TX3+
<19> PCIE_PTX_GLANRX_P2 PERp MDI_PLUS3
@ R566 10K_0402_5% C460 0.1U_0402_10V6K 42 24 LAN_TX3- @ R152 2 1 0_0402_5%
PERn MDI_MINUS3
10K_0402_5%
1 2 PCIE_PTX_GLANRX_N2_C
<19> PCIE_PTX_GLANRX_N2
1
@ R549
C461 0.1U_0402_10V6K
1 2 LAN_SMBCLK_R 28 6 VCT_LAN_R1 @ R556 2 1 4.7K_0402_5%
<18> LAN_SMBCLK
SMBUS
@ R551 0_0402_5% 31 SMB_CLK SVR_EN_N +0.9V_LAN +3.3V_LAN
1 2 LAN_SMBDATA_R SMB_DATA 1 +RSVD_VCC3P3_1 R553 2 1 4.7K_0402_5%
<18> LAN_SMBDATA RSVD_VCC3P3_1 +3.3V_LAN
@ R552 0_0402_5%
2
1 2 LANWAKE#_R 2 5
<20,46> LANWAKE# LANWAKE_N VDD3P3_IN
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
22U_0805_6.3V6M
22U_0805_6.3V6M
1 2 @ R559 0_0402_5% LAN_DISABLE#_R 3
<20> PM_LANPHY_ENABLE LAN_DISABLE_N
@ R555 0_0402_5% SMBus Device Address 0xC8 4 +3.3V_LAN_OUT 2 1 +3.3V_LAN 1 1 1 1 1 1
VDD3P3_4
C1177
C1178
@ R154 0_0603_5%
<45> LAN_DISABLE#_R
10K_0402_5%
1U_0603_10V6K
C466
C467
C468
C469
15 1
VDD3P3_15
1
@ R557
LOM_ACTLED_YEL# 26 19
LED0 VDD3P3_19 2 2 2 2 2 2
C464
LOM_SPD100LED_ORG# 27 29
LED1 VDD3P3_29
LED
LOM_SPD10LED_GRN# 25 +0.9V_LAN
LED2 2
47
2
VDD0P9_47 46
@ T142 PAD~D TP_LAN_JTAG_TDI 32 VDD0P9_46 37
JTAG_TDI VDD0P9_37 Note:
@ T143 PAD~D TP_LAN_JTAG_TDO 34 Place C1178 close to pin5
JTAG_TDO +1.0V_LAN will work at 0.95V to 1.15V
JTAG
TP_LAN_JTAG_TMS 33 43 Pin 2 is WAKE_EN in Clarkville
TP_LAN_JTAG_TCK 35 JTAG_TMS VDD0P9_43
JTAG_TCK 11
VDD0P9_11
@ R1144 1 2 0_0402_5% XTALO 9 40 0.9Vdc POWER OPTIONS
XTALI 10 XTAL_OUT VDD0P9_40 22
XTAL_IN VDD0P9_22
Internal SRV
Y3 16 Shared with PCH
25MHZ_18PF_X3G025000DI1H-H~D VDD0P9_16 8
VDD0P9_8 SI3456DDV 1.05V SVR *
1 3 LAN_TEST_EN 30
IN OUT TEST_EN VDS RDS(on) ID(A)
33P_0402_50V8J
30 0.04ohm at VGS=10V 6.3A

33P_0402_50V8J
2 4 RES_BIAS 12 7 REGCTL_PNP10 STUFF: R548 STUFF: L29

C GND GND RBIAS CTRL0P9 C
2 2 30 0.05ohm at VGS=4.5V 5.7A NO STUFF: L29 NO STUFF: R548
C470
49
VSS_EPAD
1
C471
1K_0402_5%
3.01K_0402_1%
WGI217LM-QPN9-A2_QFN48_6X6~D
1 1
R561
R562
Need update symbol by pin 5
LAN ANALOG SWITCH

+3.3V_LAN
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1 1 1
C472
C473
C474
2 2 2
Layout Notice : Place R as
close PI3L500 as possible
39
30
21
14
8
4
1
U32
VDD
VDD
VDD
VDD
VDD
VDD
VDD
38 SW_LAN_TX0+
B0+ SW_LAN_TX0+ <34>
B 37 SW_LAN_TX0- B
B0- SW_LAN_TX0- <34> +3.3V_LAN
LAN_TX0+ 1 2 LAN_TX0+R 2
@ R25 0_0402_5% A0+ 34 SW_LAN_TX1+
B1+ SW_LAN_TX1+ <34>
LAN_TX0- 1 2 LAN_TX0-R 3 33 SW_LAN_TX1- @ C478
A0- B1- SW_LAN_TX1- <34>
@ R45 0_0402_5% 1 2
29 SW_LAN_TX2+
LAN_TX1+ 1 2 LAN_TX1+R 6 B2+ 28 SW_LAN_TX2- SW_LAN_TX2+ <34> 0.1U_0402_10V6K
A1+ B2- SW_LAN_TX2- <34>
5
@ R46 0_0402_5%
LAN_TX1- 1 2 LAN_TX1-R 7 25 SW_LAN_TX3+ LOM_SPD100LED_ORG# 1
P
A1- B3+ SW_LAN_TX3+ <34> B
@ R47 0_0402_5% 24 SW_LAN_TX3- 4
B3- SW_LAN_TX3- <34> O WLAN_LAN_DISB# <45>
LOM_SPD10LED_GRN# 2
A
G
LAN_TX2+ 1 2 LAN_TX2+R 9 17 LAN_ACTLED_YEL# U15
@ R48 0_0402_5% A2+ LEDB0 18 LED_100_ORG# TC7SH08FU_SSOP5~D
3
LAN_TX2- 1 2 LAN_TX2-R 10 LEDB1 41 LED_10_GRN#
@ R49 0_0402_5% A2- LEDB2
36 DOCK_LOM_TRD0+
C0+ DOCK_LOM_TRD0+ <44>
LAN_TX3+ 1 2 LAN_TX3+R 11 35 DOCK_LOM_TRD0-
A3+ C0- DOCK_LOM_TRD0- <44>
@ R50 0_0402_5% Q326
LAN_TX3- 1 2 LAN_TX3-R 12 32 DOCK_LOM_TRD1+ Q325A L2N7002WT1G_SC-70-3
A3- C1+ DOCK_LOM_TRD1+ <44>
@ R53 0_0402_5% 31 DOCK_LOM_TRD1- DMN66D0LDW-7_SOT363-6~D
C1- DOCK_LOM_TRD1- <44>
D
LAN_ACTLED_YEL# 1 6 LED_10_GRN# 3 1
LAN_ACTLED_YEL#_Q <34> LED_10_GRN#_Q <34>
DOCKED 13 27 DOCK_LOM_TRD2+
<45> DOCKED SEL C2+ 26 DOCK_LOM_TRD2- DOCK_LOM_TRD2+ <44>
C2- DOCK_LOM_TRD2- <44>
G
2
2
LOM_ACTLED_YEL# 15 23 DOCK_LOM_TRD3+
LEDA0 C3+ DOCK_LOM_TRD3+ <44>
LOM_SPD100LED_ORG# 16 22 DOCK_LOM_TRD3- SYS_LED_MASK#
LEDA1 C3- DOCK_LOM_TRD3- <44> SYS_LED_MASK# <24,45>
LOM_SPD10LED_GRN# 42 SYS_LED_MASK#
LEDA2 19 DOCK_LOM_ACTLED_YEL#
LEDC0 DOCK_LOM_ACTLED_YEL# <44>
5 20 DOCK_LOM_SPD100LED_ORG#
PD LEDC1 DOCK_LOM_SPD100LED_ORG# <44>
40 DOCK_LOM_SPD10LED_GRN#
LEDC2 DOCK_LOM_SPD10LED_GRN# <44>
43 Q325B
1: TO DOCK PAD_GND DMN66D0LDW-7_SOT363-6~D
DOCKED LED_100_ORG# 4 3
LED_100_ORG#_Q <34>
0: TO RJ45
A A
PI3L720ZHEX_TQFN42_9X3P5~D
5
SYS_LED_MASK#
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LAN
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1.0
5 4 3 2 1
5 4 3 2 1
D D
T156
SW_LAN_TX0+ 1 1:1 24 NB_LAN_TX0+ +3.3V_LAN

<33> SW_LAN_TX0+ TD1+ TX1+
SW_LAN_TX0- 2
<33> SW_LAN_TX0- TD1- 23 NB_LAN_TX0-
TX1- JLOM1
+TRM_CT1 3 22 Z2805 9
TDCT1 TXCT1 Yellow LED+
1 2 10
C +TRM_CT2 4 21 Z2807 <33> LAN_ACTLED_YEL#_Q Yellow LED- C
R1166 150_0402_5%
TDCT2 TXCT2
0.47U_0603_10V7K
SW_LAN_TX1+ 5 1:1 20 NB_LAN_TX1+ NB_LAN_TX3- 8

<33> SW_LAN_TX1+ TD2+ TX2+ PR4-
0.47U_0603_10V7K
NB_LAN_TX3+ 7
PR4+
1 1
C479
NB_LAN_TX1- 6
PR2-
C480
SW_LAN_TX1- 6 19 NB_LAN_TX1-
<33> SW_LAN_TX1- TD2- TX2- 5
NB_LAN_TX2-
2 2 PR3-
NB_LAN_TX2+ 4
PR3+
NB_LAN_TX1+ 3
SW_LAN_TX2+ 7 1:1 18 NB_LAN_TX2+ PR2+
<33> SW_LAN_TX2+ TD3+ TX3+ NB_LAN_TX0- 2
PR1- 15
NB_LAN_TX0+ 1 GND
SW_LAN_TX2- 8 PR1+ 14
<33> SW_LAN_TX2- TD3- 17 1 2 11 GND
NB_LAN_TX2-
TX3- <33> LED_10_GRN#_Q Green LED-
R1653 150_0402_5%
1 2 13
+TRM_CT3 9 16 Z2806 <33> LED_100_ORG#_Q Orange LED-
R1167 150_0402_5%
TDCT3 TXCT3 12
Green-Orange LED+
+TRM_CT4 10 15 Z2808
TDCT4 TXCT4
75_0402_1%
75_0402_1%
75_0402_1%
75_0402_1%
SW_LAN_TX3+ 11 1:1 14 NB_LAN_TX3+ TE_2041528-1
<33> SW_LAN_TX3+ TD4+ TX4+ +3.3V_LAN
0.47U_0603_10V7K
0.47U_0603_10V7K
CONN@
1 1
C483
C484
SW_LAN_TX3- 12 13 NB_LAN_TX3-
2 2 <33> SW_LAN_TX3- TD4- TX4-
1U_0603_10V6K
0.1U_0402_10V6K
470P_0402_50V7K
1 1 1
1
B B
C481
C482
C1167
350uH_IH-115-F~D
2 2 2
T156 change PN to SP050006Y00 S X'FORM_ NS692417 LAN
GND
R571 2
R572 2
R573 2
R574 2
CHASSIS
1 2 GND_CHASSIS
EMC@ C485 150P_1808_3KV8J
Close to JLOM1
A A
PROPRIETARY NOTE:
Title
RJ45 Conn
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1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN_TPM
+3.3V_RUN +3.3V_RUN_TPM
PJP61 +3.3V_RUN_TPM
0.1U_0402_25V6
4700P_0402_25V7K
D 1 2 D
1 1
ATMEL TPM for E4
C44
C45
PAD-OPEN1x1m
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
CONN@
2 2
1 1 1 1
U39
C550
C551
C552
C553
10
5 VCC_0 19 2 2 2 2
SB3V VCC_1 24
1 2 VCC_2
<16> SUS_STAT#/LPCPD#
@ R1667 0_0402_5%
1 2
<20> PCH_GPIO22
@ R1670 0_0402_5%
1 2 SP_TPM_LPC_EN_R 28 12
<45> SP_TPM_LPC_EN LPCPD# V_BAT 13 JETWAY_CLK14M
@ R1669 0_0402_5%
LPC_LAD0 26 NBO_13 14 JETWAY_CLK14M <17>
<18,37,45,46> LPC_LAD0 LPC_LAD1 23 LAD0 NBO_14
<18,37,45,46> LPC_LAD1 20 LAD1
LPC_LAD2
<18,37,45,46> LPC_LAD2 LPC_LAD3 17 LAD2
<18,37,45,46> LPC_LAD3 LAD3 6
GPIO6
CLK_PCI_TPM 21 9 1 2
CLK_PCI_TPM <17> CLK_PCI_TPM LPC_LFRAME# 22 LCLK TESTBI 8 R657 4.7K_0402_5%
<18,37,45,46> LPC_LFRAME# PCH_PLTRST#_EC 16 LFRAME# TESTI
<16,37,38,39,45,46> PCH_PLTRST#_EC LRESET#
1
33_0402_5%
IRQ_SERIRQ 27
<18,45,46> IRQ_SERIRQ SERIRQ
@ RE5
CLKRUN# 15
<16,45,46> CLKRUN# CLKRUN# 7
NC_7
1 4
2
C 2 ATEST_1 GND_4 11 C
ATEST_2 GND_11
27P_0402_50V8J
1 3 18
ATEST_3 GND_18
@ CE3
25
GND_25
AT97SC3204-X2A14-AB_TSSOP28
2
JUSH1
22
21 GND2
GND1
20
19 20
<19> USBP7- 18 19
USH CONN <46>

<19>
USH_SMBCLK
USBP7+ 17
16
15
18
17
16
<46> USH_SMBDAT 14 15
<45> BCM5882_ALERT# 13 14
+3.3V_SUS +3.3V_SUS 13
12
11 12
USH_SMBCLK 2 1 10 11
2.2K_0402_5% R589 <20> SMART_DET# 9 10
USH_SMBDAT 2 1 8 9
B +3.3V_RUN 8 B
2.2K_0402_5% R585 7
+5V_RUN 7
6
Check ME about wire to board PN USH_PWR_STATE# 1 2
<45>
<16> PLTRST_USH#
USH_PWR_STATE#
5 6
5
JAPS1 1M_0402_5% R1640 4
1 <20> CONTACTLESS_DET# 3 4
+3.3V_ALW_PCH 1 3
2 2
<11,16,39,40,45,48,64,66> SIO_SLP_S3# 3 2 1 2
+PCH_VCCDSW3_3 3 <20> USH_DET# 1
JAPS1_4 4
5 4 TYCO_2-2041070-0
<16,28,45,62> SIO_SLP_S4# 6 5 CONN@
<16,45,48,63> SIO_SLP_A# JAPS1_7 7 6
8 7
9 8
<15> PCH_RTCRST# 10 9
11 10
<24,46> POWER_SW#_MB 12 11 +3.3V_SUS +3.3V_RUN +5V_RUN
13 12
<16> SYS_RESET# 14 13
14
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
15
16 15
16
1 1 1
C53
C51
C52
17
18 GND
GND @ @ @
1 2 JAPS1_4 TYCO_1-2041070-6~D 2 2 2
+3.3V_ALW_PCH
@ R17 0_0402_5% CONN@
1 2
<16,46> SIO_SLP_S5#
@ R23 0_0402_5%
1 2 JAPS1_7
Close to JUSH1
+3.3V_ALW
@ R24 0_0402_5%
A A
PROPRIETARY NOTE:
Title
USH board conn / TPM
www.Vinafix.vn
1.0
5 4 3 2 1
A B C D E
C575 must close to U38.35 within 50mils

C576 must close to U38.9 within 50mils
C577 must close to U38.9 with 100mils
+3.3V_RUN L45 must close to U38.9 within 200mils Close to U38.11
+3.3V_RUN +3.3V_RUN_OZVCC trace width 30mils
L45 +3.3V_RUN
2 1 +3.3V_RUN_OZVCC
BLM18BD601SN1D_0603~D
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
close to U38.23
close to U38.42
4.7U_0603_6.3V6K
0.1U_0402_25V6
@
1
1
C581
C574
1
C578
C573
C577
C576
C575
2
2
C1502
C1503
2
2
1 1
1
+1.2V_OZ_AUX_LDO
+3.3V_OZ_IO_LDO
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
1U_0603_10V6K
+1.2V_LDO +3.3V_RUN
2
C564
C800
C566
C801
U38
Close to U38.13
4.7U_0603_6.3V6K
1
1
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
OZ777FJ2LN
9 12
PE_33VCCAIN AUX_LDO_CAP @
close to U38.10
close to U38.41
close to U38.10
2
27
2 UHSII_33VCCAIN/NC
2
C1507
C1506
C1505
25
SD_IO_LDO_CAP
C1504
C1501
1
42
1
1
SD_33VCCD
trace width 30mils 23 Close to U38.25 Close to U38.12
SD_SKT_33VIN
trace width 30mils 13 22
AUX _33VIN SD_SKT_33VOUT +3.3V_RUN_CARD
11 24
+1.2V_LDO +3.3V_RUN MAIN_LDO_VIN SD_SKT_18VOUT +1.8V_RUN_CARD
L47 close to U38.31 within 200mils 10 C559 1 2 1U_0603_10V6K
L47 2 1 +1.2V_LDO, +1.2V_LDO_OZ trace width 30mils MAIN_LDO_12VOUT C560 1 2 4.7U_0603_6.3V6K
BLM18BD601SN1D_0603~D @ C1511 1 2 0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
41
CORE_12VCCD
close to U38.31
close to U38.26
close to U38.31
close to U38.34
close to U38.1
20 SD_WPI
SD_WPI
2
+1.2V_LDO_OZ 36 21 SD_CD#
UHSII_12VCCAIN/NC SD_CD#
C561
C562
C1510
C1509
C1508
31
2 28 UHSII_12VCCAIN/NC 43 SD_CLK_R EMC@ R676 1 2 10_0402_1% SD_CLK 2
1
UHSII_12VCCAIN/NC SD_CLK 45 SD_CMD

SD_CMD
33P_0402_50V8J
@ 1
PE_12VCCAIN 39 @
MMC_D7 1
CE759
40
R677 must be close to U38 less than 100mils MMC_D6 44
1 2 OZ_PE_REXT 4 MMC_D5 46
R677 191_0402_1% PE_REXT MMC_D4 47 SD_D3_R 1 2 SD_D3 2
C567 1 2 0.1U_0402_10V6K PCIE_PTX_MMIRX_P8_C 6 SD_D3 48 SD_D2_R @ RE29 1 2 0_0402_5% SD_D2
<19> PCIE_PTX_MMIRX_P8 PE_RXP SD_D2
C568 1 2 0.1U_0402_10V6K PCIE_PTX_MMIRX_N8_C 5 37 @ RE30 0_0402_5%
<19> PCIE_PTX_MMIRX_N8 PE_RXM SD_D1 38
C569 1 2 0.1U_0402_10V6K PCIE_PRX_MMITX_P8_C 7 SD_D0 LE5 @
<19> PCIE_PRX_MMITX_P8 C571 1 2 0.1U_0402_10V6K PCIE_PRX_MMITX_N8_C 8 PE_TXP 29 SD_D1_RCLKR_N 1 2 SD_D1_RCLK_N
<19> PCIE_PRX_MMITX_N8 PE_TXM SD_RCLK_M/NC 30 SD_D0_RCLKR_P 1 2
2 SD_RCLK_P/NC 32 SD_UHS2_D1P_R
<17> CLK_PCIE_MMI# 3 PE_REFCLKM SD_D1P/NC 33 SD_UHS2_D1N_R 4 3 SD_D0_RCLK_P_MMC_D0
<17> CLK_PCIE_MMI PE_REFCLKP SD_D1M/NC 34 4 3
SD_UHS2_D0N_R
15 SD_D0M/NC 35 SD_UHS2_D0P_R DLW21SN900HQ2L_0805_4P~D
<16> PLTRST_MMI# PE_RST#_GATE# SD_D0P/NC 1 2
OZ_LDO_EN 14 26 R1702 1 2 4.7K_0402_1% @ RE27 0_0402_5%
MAIN_LDO_EN SD_REXT/NC
16 R1702 must be close to U38 less than 100mils 1 2
<32,37,38,39,46> PCIE_WAKE# DEV_WAKE# @ RE28 0_0402_5%
17 19
<15,17> MMICLK_REQ# CLKREQ# LED# please routing daisy chain
MULTIO_0 18 49 1. from U38.38 (SD_D0) -> U38.32 (SD_RCLK_P) -> LE5.4
IO0_LDOSEL GND 2. From U38.37 (SD_D1) -> U38.33 (SD_RCLK_N) -> LE5.1
OZ777FJ2LN_QFN48_6X6
+3.3V_RUN_CARD
LE2 @ JSD1 CONN@

3 SD_UHS2_D1P_R 1 2 SD_UHS2_D1P 4 3
+3.3V_RUN 1 2 14 VDD/VDD1
SD_CMD 2 VDD2
4.7U_0603_6.3V6K
0.1U_0402_25V6
CMD
10K_0402_5%
SD_UHS2_D1N_R 4 3 SD_UHS2_D1N SD_CLK 5
4 3 CLK
1
1
R1700 DLW21SN900HQ2L_0805_4P~D SD_CD# 17
C570
R826
C572
100K_0402_5% 1 2 SD_WPI 18 CARD DETECT
WRITE PROTEC
0.1U_0402_25V6
@ RE3 0_0402_5%
1
@
1M_0402_5%
@ @ SD_D0_RCLK_P_MMC_D0 7
2
2
DAT0/RCLK+
R493
MULTIO_0 1 2 SD_D1_RCLK_N 8
DAT1/RCLK-
C802
@ RE4 0_0402_5% SD_D2 9
DAT2
1
+3.3V_RUN SD_D3 1
1
@ R1701 SD_UHS2_D0P 11 CD/DAT3
2
100K_0402_5% LE4 @ SD_UHS2_D0N 12 D0+
SD_UHS2_D0N_R 1 2 SD_UHS2_D0N +1.8V_RUN_CARD SD_UHS2_D1P 16 D0- 19
1 2 OZ_LDO_EN 1 2 SD_UHS2_D1N 15 D1+ GND 20
2
R894 10K_0402_5% D1- GND 21

SD_UHS2_D0P_R 4 3 SD_UHS2_D0P 3 GND 22
4.7U_0603_6.3V6K
0.1U_0402_25V6
4 3 VSS1 GND
10K_0402_5%
6 23
VSS2 GND
1
DLW21SN900HQ2L_0805_4P~D O2 request 10 24
VSS3 GND
1
1 2 13 25
C580
R831
C579
@ RE25 0_0402_5% VSS4 GND
T-SOL_156-1000302606
2
1 2 @ @ @
2
@ RE26 0_0402_5%
4 4
only for MMC/SD

PROPRIETARY NOTE:
Title
Card Reader
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1.0
A B C D E
5 4 3 2 1
1 2
@ R693 0_0402_5%
1 2 WLAN_RADIO_DIS#_R
<45> WLAN_RADIO_DIS#
D31 RB751V40_SC76-2
1 2
@ R694 0_0402_5%
1 2 WIGIG60GHZ_DIS#_R
<45> WIGIG60GHZ_DIS#
D35 RB751V40_SC76-2
1 2
@ R695
1
0_0402_5%
2 BT_RADIO_DIS#_R
Mini WLAN/WIMAX H=9 +3.3V_RUN
<45> BT_RADIO_DIS#
D36 RB751V40_SC76-2
+3.3V_WLAN +3.3V_WLAN 2 1 CPPE#
R737 100K_0402_5%
D JMINI2 CONN@ 2 1 USB_MCARD1_DET# D
PCIE_WAKE# 1 2 R739 100K_0402_5%
<32,36,38,39,46> PCIE_WAKE# 1 2
3 4
5/24 confirmed with Sean can remove 3 4
COEX2_WLAN_ACTIVE and pin4 COEX1_BT_ACTIVE
5 6
7 5 6 8 C595
<17> MINI2CLK_REQ# 9 7 8 10 1 2
11 9 10 12
<17> CLK_PCIE_MINI2# 13 11 12 14 MSDATA 4700P_0402_25V7K
<17> CLK_PCIE_MINI2 15 13 14 16 +3.3V_WLAN
15 16 HOST_DEBUG_TX <46>
2 1 WIGIG60GHZ_DIS#_R
17 18 @ R725 100K_0402_5%
<45,46> EC5048_TX 19 17 18 20 WLAN_RADIO_DIS#_R 2 1 WLAN_RADIO_DIS#_R
<46> MSCLK 21 19 20 22 2 1 PCH_PLTRST#_EC @ R728 100K_0402_5%
23 21 22 24 PCH_PLTRST#_EC <16,35,38,39,45,46> 2 1
PCIE_PRX_WLANTX_N3 @ R703 0_0402_5% BT_RADIO_DIS#_R
<19> PCIE_PRX_WLANTX_N3 PCIE_PRX_WLANTX_P3 25 23 24 26 @ R729 100K_0402_5%
<19> PCIE_PRX_WLANTX_P3 27 25 26 28
C596 0.1U_0402_10V6K 29 27 28 30
1 2 PCIE_PTX_WLANRX_N3_C 31 29 30 32 WIGIG60GHZ_DIS#_R
<19> PCIE_PTX_WLANRX_N3 1 2 PCIE_PTX_WLANRX_P3_C 33 31 32 34
<19> PCIE_PTX_WLANRX_P3 35 33 34 36
C598 0.1U_0402_10V6K USBP4-
37 35 36 38 USBP4- <19>
CPPE# USBP4+
<16> CPPE# 39 37 38 40 USBP4+ <19>
USB_MCARD1_DET#
41 39 40 42 USB_MCARD1_DET# <16>
WIGIG_LED#
43 41 42 44 WLAN_LED#
45 43 44 46 BT_LED#
<18> PCH_CL_CLK1 47 45 46 48 1 2
<18> PCH_CL_DATA1 47 48 MSDATA <46>
@ R707 1 2 0_0402_5% 49 50 @ R706 0_0402_5%
<18> PCH_CL_RST1# 51 49 50 52
BT_RADIO_DIS#_R WIMAX_LED# STUDY FOR DEBUG
53 51 52 54
G1 G2
BELLW_80003-7041
+3.3V_WLAN
100K_0402_5%
100K_0402_5%
100K_0402_5%
C C
2
R720
R718
R705
5
+3.3V_WLAN
1
WIGIG_LED# 4 3 WIRELESS_LED#
WIRELESS_LED# <24,38,45>
Q124B
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
2
1 1 1 2 2 1
@ C603
WLAN_LED# 1 6
C604
C605
C606
C607
C608
Q124A
2 2 2 1 1 2 DMN66D0LDW-7_SOT363-6~D
2
G
BT_LED# 3 1
D
Q89
L2N7002WT1G_SC-70-3
1/2 Minicard Pink Pather/60GHz Card H=9
+3.3V_PCIE_FLASH +3.3V_PCIE_FLASH
B B
JMINI3 CONN@
PCIE_WAKE# 1 2
3 1 2 4
5 3 4 6
MINI3CLK_REQ# 7 5 6 8 LPC_LFRAME#
<17> MINI3CLK_REQ# 9 7 8 10 LPC_LFRAME# <18,35,45,46>
LPC_LAD3
11 9 10 12 LPC_LAD3 <18,35,45,46>
CLK_PCIE_MINI3# LPC_LAD2
<17> CLK_PCIE_MINI3# 13 11 12 14 LPC_LAD2 <18,35,45,46>
CLK_PCIE_MINI3 LPC_LAD1
<17> CLK_PCIE_MINI3 15 13 14 16 LPC_LAD1 <18,35,45,46>
LPC_LAD0
15 16 LPC_LAD0 <18,35,45,46>
PCH_PLTRST#_EC 17 18
PCLK_80H 19 17 18 20
<17> PCLK_80H 21 19 20 22 PCH_PLTRST#_EC
PCIE_PRX_WPANTX_N6 23 21 22 24
<19> PCIE_PRX_WPANTX_N6 PCIE_PRX_WPANTX_P6 25 23 24 26
<19> PCIE_PRX_WPANTX_P6 27 25 26 28
C617 0.1U_0402_10V6K 29 27 28 30
1 2 PCIE_PTX_WPANRX_N6_C 31 29 30 32
<19> PCIE_PTX_WPANRX_N6 1 2 PCIE_PTX_WPANRX_P6_C 33 31 32 34
<19> PCIE_PTX_WPANRX_P6 35 33 34 36
C618 0.1U_0402_10V6K USBP8-
37 35 36 38 USBP8- <19>
USBP8+
39 37 38 40 USBP8+ <19>
41 39 40 42
43 41 42 44
45 43 44 46
47 45 46 48
49 47 48 50
+3.3V_PCIE_FLASH 51 49 50 52
53 51 52 54
G1 G2
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
BELLW_80003-7041
1 1 1 2 2 1
@ C621
C622
C623
C624
C625
C626
A A
2 2 2 1 1 2
PROPRIETARY NOTE:
www.Vinafix.vn
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT WLAN/Pink Pather Mini Card
1.0
5 4 3 2 1
5 4 3 2 1
Mini WWAN/GPS/LTE/UWB H=9

(1) Wake Enabled and Active
+3.3V_PCIE_WWAN +3.3V_PCIE_WWAN
JMINI1 CONN@ (2) Wake NOT Enabled nor Active
<32,36,37,39,46> PCIE_WAKE# PCIE_WAKE# 1 2
3 1 2 4
3 4 D0-D2&D3 hot Power D3 cold Power
5 6 PWR Rail Voltage
MINI1CLK_REQ# 7 5 6 8
<17> MINI1CLK_REQ# 7 8 +SIM_PWR Tolerance
9 10 UIM_DATA Peak(mA) Typ(mA) Peak(mA) Typ(mA)
CLK_PCIE_MINI1# 11 9 10 12 UIM_CLK
<17> CLK_PCIE_MINI1# CLK_PCIE_MINI1 13 11 12 14 UIM_RESET
<17> CLK_PCIE_MINI1 15 13 14 16 +UIM_VPP
15 16 +3.3V_PCIE_WWAN +-9% 2750 800 800 (1) 150 (1)
D
5 (2) D
17 18
19 17 18 20
21 19 20 22 WWAN_RADIO_DIS# <45>
@ R704 1 2 0_0402_5%
23 21 22 24 PCH_PLTRST#_EC <16,35,37,39,45,46>
MSATA_PRX_WANTX_P4_RP_C
MSATA_PRX_WANTX_N4_RP_C 25 23 24 26
27 25 26 28
29 27 28 30
MSATA TX/RX pin out 29 30
MSATA_PTX_WANRX_N4_RP_C 31 32
MSATA_PTX_WANRX_P4_RP_C 33 31 32 34
35 33 34 36 USBP5-
37 35 36 38 USBP5- <19>
USBP5+
39
41
43
37
39
41
38
40
42
40
42
44
LED_WWAN_OUT#
USBP5+ <19>
+SIM_PWR SIM Card Push-Push
45 43 44 46 JSIM1 CONN@
47 45 46 48 1
49 47 48 50 UIM_RESET 2 VCC 11
49 50 RST GND_2
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
HW_GPS_DISABLE2# 51 52 UIM_CLK 3 12
<45> HW_GPS_DISABLE2# 53 51 52 54 +3.3V_PCIE_WWAN 4 CLK GND_3 13
+3.3V_PCIE_WWAN G1 G2 5 D+ GND_4 14
1 1 1 GND_1 GND_5
@ C639
@ C636
+UIM_VPP 6 15
VPP GND_6
C616
BELLW_80003-7041 UIM_DATA 7 16
I/O GND_7
150U_D2_6.3VY_R15M
150U_D2_6.3VY_R15M
100K_0402_5%
8 17
2 2 2 D- GND_8
0.047U_0402_16V4Z
0.047U_0402_16V4Z
33P_0402_50V8J
22U_0805_6.3V6M
33P_0402_50V8J
9 18
DET GND_9
2
1 1 10
COM
@ C1176
R719
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
1 1 1 1 1
C615
+ +
1 1 1 1
C610
C611
C612
C613
C614
@ C631
@ C630
@ C628
@ C629
T-SOL_159-1000302602
2
G
1
2 2 2 2 2 2 2
LED_WWAN_OUT# 3 1 2 2 2 2
WIRELESS_LED# <24,37,45>
D
Q77
L2N7002WT1G_SC-70-3
C C
MOSEL 1: PCIE interface

0: SATA interface
+3.3V_PCIE_WWAN
+3.3V_PCIE_WWAN
100K_0402_5%
+3.3V_PCIE_WWAN
2
100K_0402_5%
R724
2
R727
0.01U_0402_16V7K
0.1U_0402_25V6
0.1U_0402_25V6
1
SATA_PCIE_EN#
1
1
D MCARD_PCIE#_SATA
1 @ 1 1
PCH_PLTRST#_EC 2 Q85
1
D
C400
C412
C401
G L2N7002WT1G_SC-70-3
S MCARD_PCIE_SATA# 2 Q88
<15,20,45> MCARD_PCIE_SATA#
3
2 2 2 G L2N7002WT1G_SC-70-3
S
3
U7
SATA_PCIE_EN# 3 10
CHIP_EN# VCC 20
C416 2 1 0.1U_0402_10V6K PCIE_SATA_PTX_WANRX_P4_C 1 VCC
<15> PCIE_SATA_PTX_WANRX_P4 AIP
C417 2 1 0.1U_0402_10V6K PCIE_SATA_PTX_WANRX_N4_C 2 16 Reserved
<15> PCIE_SATA_PTX_WANRX_N4 AIN Reserved 8 DE_B
DE_B
C422 2 1 0.1U_0402_10V6K PCIE_SATA_PRX_WANTX_P4_C 5 18 SMB_SCK
<15> PCIE_SATA_PRX_WANTX_P4 C424 2 1 0.1U_0402_10V6K PCIE_SATA_PRX_WANTX_N4_C 4 BOP SMB_SCK 19 SMB_SDA
<15> PCIE_SATA_PRX_WANTX_N4 BON SMB_SDA C403 0.1U_0402_10V6K
B B
HW_GPS_DISABLE2# @ R749 2 1 0_0402_5% PCIE#_SATA 17 15 MSATA_PTX_WANRX_P4_RP 2 1 MSATA_PTX_WANRX_P4_RP_C
MCARD_PCIE#_SATA 2 1 DE_A 7 MOSEL AOP 14 MSATA_PTX_WANRX_N4_RP 2 1 MSATA_PTX_WANRX_N4_RP_C
@ R747 0_0402_5% REXT 9 DE_A AON C410 0.1U_0402_10V6K
6 REXT C394 0.1U_0402_10V6K
LOOPBACK 13 GND 11 MSATA_PRX_WANTX_P4_RP 2 1 MSATA_PRX_WANTX_P4_RP_C
21 CMPL_EN BIP 12 MSATA_PRX_WANTX_N4_RP 2 1 MSATA_PRX_WANTX_N4_RP_C
EPAD BIN
ASM1467_QFN20_4X4 C393 0.1U_0402_10V6K
SYMBOL need to update
+3.3V_PCIE_WWAN +3.3V_PCIE_WWAN
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
1
@ R560
@ R550
@ R554
@ R563
@ R564
@ R565
@ R567
2
LOOPBACK Reserved
DE_B SMB_SCK
DE_A SMB_SDA
REXT
A A
1
1
0_0402_5%
@ R1684
0_0402_5%
@ R1685
0_0402_5%
@ R1686
2K_0402_1%
0_0402_5%
@ R1687
0_0402_5%
@ R1689
0_0402_5%
@ R1688
R748
2
www.Vinafix.vn
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT WWAN Mini Card
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-9411P
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN +3.3V_RUN +3.3V_SUS

Express Card PWR S/W +3.3V_CARDAUX +3.3V_CARD +1.5V_CARD
D
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
10U_0603_6.3V6M
0.1U_0402_25V6
10U_0603_6.3V6M
0.1U_0402_25V6
10U_0603_6.3V6M
C635
C634
C633
C642
C643
C640
C641
C637
C638
1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2
U41
17 15
2 AUXIN AUXOUT 3
12 3.3VIN 3.3VOUT 11
1.5VIN 1.5VOUT
@ R734 1 2 0_0402_5% 20 8 CARD_RESET#
<11,16,35,40,45,48,64,66> SIO_SLP_S3# SHDN# PERST#
@ R717 1 2 0_0402_5% EXPRCRD_STBY_R# 1 10 EXPRCRD_CPPE#
<45,48,64> RUN_ON 6 STBY# CPPE# 9
<16,35,37,38,45,46> PCH_PLTRST#_EC PCH_PLTRST#_EC CPUSB#
19 SYSRST# CPUSB#
OC#
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
+3.3V_RUN
4 1 1 1
NC
CE10
CE11
CE12
5 18
+3.3V_CARD NC RCLKEN
13
+1.5V_CARD NC
14 7
+1.5V_RUN NC GND 2 2 2
16 21
NC PAD
TPS2231MRGPR-2_QFN20_4X4~D
C Power Control for +3.3V_RUN +3.3V_RUN

C447 @
Express Card Conn. C
U101 10U_0603_6.3V6M
+3.3V_ALW
1
2 VIN1 VOUT1
14
13
1 2 Note: Add connection on pin4, pin5, pin 13
VIN1 VOUT1
<48> RUN_ON_EN
3
ON1 CT1
12 1 2 and pin14 to support GMT 2nd source part
C448 2200P_0402_50V7K
4 11
+5V_ALW VBIAS GND
5 10 1 2
<45> MCARD_WWAN_PWREN ON2 CT2 C452 470P_0402_50V7K
6 9
2 1 7 VIN2 VOUT2 8
VIN2 VOUT2 +3.3V_PCIE_WWAN
R726 100K_0402_5% 1
15
GPAD C451 @
TPS22966DPUR_SON14_2X3~D 10U_0603_6.3V6M
Power Control for Mini card1 (+3.3V_PCIE_WWAN) 2
Power Control for Mini card2 (+3.3V_WLAN) +3.3V_SUS
B B
2.2K_0402_5%
2.2K_0402_5%
1
1
+3.3V_WLAN
R732
R731
C446 @
U100 10U_0603_6.3V6M
2 1 1 14 1 2 JEXP1
+3.3V_ALW
2
R716 100K_0402_5% 2 VIN1 VOUT1 13 1 2 CPUSB#
VIN1 VOUT1 3 1 2 4
<19> USBP10- 3 4
@ R1631 1 2 0_0402_5% 3 12 1 2 5 6
<45> AUX_EN_WOWL ON1 CT1 <19> USBP10+ 7 5 6 8 CARD_SMBCLK <46>
C445 470P_0402_50V7K
1 2 4 11 9 7 8 10 CARD_SMBDAT <46>
<16,45> SIO_SLP_WLAN# +5V_ALW VBIAS GND <17> CLK_PCIE_EXP# 9 10 +1.5V_CARD
@ R1633 0_0402_5% 11 12
<17> CLK_PCIE_EXP 11 12
0.1U_0402_25V6
5 10 1 2 13 14 1
<45> MCARD_MISC_PWREN ON2 CT2 15 13 14 16 PCIE_WAKE# <32,36,37,38,46>
C450 470P_0402_50V7K <19> PCIE_PRX_EXPTX_N7 +3.3V_CARDAUX
15 16
C645
6 9 17 18 CARD_RESET#
VIN2 VOUT2 <19> PCIE_PRX_EXPTX_P7 17 18
0.1U_0402_25V6
2 1 7 8 C647 0.1U_0402_10V6K 19 20
VIN2 VOUT2 +3.3V_PCIE_FLASH 19 20 2
R733 100K_0402_5% 1 1 2 PCIE_PTX_EXPRX_N7_C 21 22 1
<19> PCIE_PTX_EXPRX_N7 21 22 +3.3V_CARD @
15 1 2 PCIE_PTX_EXPRX_P7_C 23 24
GPAD <19> PCIE_PTX_EXPRX_P7 23 24
C646
C449 @ C648 0.1U_0402_10V6K 25 26
TPS22966DPUR_SON14_2X3 27 25 26 28 EXPRCRD_CPPE#
10U_0603_6.3V6M <17> EXPCLK_REQ# 27 28
2 2
0.1U_0402_25V6
29 30 @
29 30
1
Power Control for Mini card3 (+3.3V_PCIE_FLASH) 31
GND GND
32
C649
2
E-T_1001K-F30C-02L @
CONN@
A A
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PCIE-SATA SW / PCIE PWR
1.0
5 4 3 2 1
www.Vinafix.vn
5 4 3 2 1
Right Side Top (JUSB1) PD#B

+3.3V_RP1 +3.3V_RP1
USB 3.0 repeater change to SA00005OR00
R3703
+3.3V_RP1 +3.3V_RP1
R3720
@
1
10U_0805_10V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.01U_0402_16V7K
@
1
1 @ 1 @ 1 1 @
@
R3704
R3705
R3706
R3707
R3708
R3709
R3723
R3724
R3725
R3726
C1527
C1528
C1529
C1530
4.7K_0402_5%
@ @ @ @ @ @ Pin24 internal pull-down
2
@ @ @ @
(pin control mode)
2K_0402_5%
1
1
2 2 2 2
2
1
1
D @ D
U92
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
25
2
2
1 EPAD 24
2
B_EQ_0B 2 VDD 12C_EN 23 USB3RN1_C @ C1531 2
@C1531 1 0.1U_0402_10V6K USB3RN1
3 B_EQ0 B_OUTn 22 USB3RN1 <19>
B_DE_0B USB3RP1_C C1532 2
@C1532
@ 1 0.1U_0402_10V6K USB3RP1
B_EQ_1B 4 I2C_R0 B_OUTp 21 USB3RP1 <19>
PD#B 5 I2C_R1 GND 20 USB3TN1_C @ C1533 2
@C1533 1 0.1U_0402_10V6K USB3TN1
6 PD# A_INn 19 USB3TN1 <19>
B_DE_1B USB3TP1_C C1534 2
@C1534
@ 1 0.1U_0402_10V6K USB3TP1
7 B_DE1 A_INp 18 USB3TP1 <19>
B_EQ_0B A_EQ_0B REXTB A_DE_1B
B_EQ_1B A_EQ_1B USB3RN1_RP @ R3712 1 2 0_0402_5% USB3RN1_R 8 REXT A_DE1 17 A_EQ_0B
B_DE_0B A_DE_0B USB3RP1_RP @ R3713 1 2 0_0402_5% USB3RP1_R 9 B_INn A_EQ0 16 A_DE_0B +3.3V_RP1
B_DE_1B A_DE_1B 10 B_INp SCL_CTL 15 A_EQ_1B
GND SDA_CTL
0.1U_0402_16V4Z
REXTB @ @ @ @ USB3T_N1 @ C1535 1 2 0.1U_0402_10V6K USB3TN1_RP 11 14 TESTB
R3729 A_OUTn TEST
R3730
R3731
R3732
TESTB USB3T_P1 @ C1536 1 2 0.1U_0402_10V6K USB3TP1_RP 12 13
A_OUTp VDD
1
1
@ @ @ @ @ @ 1 @
R3714
R3715
R3716
R3717
R3718
R3719
1
C1537
PS8710BTQFN24GTR-A0_TQFN24_4X4
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
4.99K_0402_1%
0_0402_5%
2
C C
@ R22 2 1 0_0402_5% USB3RN1_CO @ R27 2 1 0_0402_5%
@ R26 2 1 0_0402_5% USB3RP1_CO @ R28 2 1 0_0402_5%
C1560 1 2 0.1U_0402_10V6K USB3TN1_CO @ R31 2 1 0_0402_5%

1 2
@ R1605 0_0402_5% C1561 1 2 0.1U_0402_10V6K USB3TP1_CO @ R29 2 1 0_0402_5%
R22.2 close to R3712.1 R27.1 close to C1531.1

L95 EMC@ +3.3V_RUN +3.3V_RP1
USB3RN1_RP 1 2 USB3RN1_D-
1 2 C1560.1 close to C1535.1 R31.1 close to C1533.1 @ PJP66
C1561.1 close to C1536.1 Bypass USB3.0 Repeater R29.1 close to C1534.1 1 2
USB3RP1_RP 4 3 USB3RP1_D+
4 3 PAD-OPEN1x1m
+3.3V_ALW_PCH +3.3V_RP1
20mils 20mils
1 2 @ PJP68
@ R1604 0_0402_5% 1 2
1 2
@ R736 0_0402_5% PAD-OPEN1x1m
1 2 D78 EMC@
@ R1606 0_0402_5% USB3TP1_D+ 1 10 USB3TP1_D+
DLW21SN900SQ2L_0805_4P~D
USB3TN1_D- 2 9 USB3TN1_D- USBP0_D- 1 2 USBP0_R_D- +5V_USB_CHG_PWR
L96 EMC@ 1 2 JUSB1
USB3T_N1 1 2 USB3TN1_D- USB3RP1_D+ 4 7 USB3RP1_D+ 1
1 2 USBP0_D+ 4 3 USBP0_R_D+ USBP0_R_D- 2 VBUS
4 3 D-
150U_D2_6.3VY_R15M
0.1U_0402_25V6
USB3RN1_D- 5 6 USB3RN1_D- 1 USBP0_R_D+ 3
USB3T_P1 4 3 USB3TP1_D+ L51 EMC@ 4 D+
4 3 1 GND
C651
B 3 + USB3RN1_D- 5 B
StdA-SSRX-
2
C654
DLW21SN900HQ2L_0805_4P~D USB3RP1_D+ 6 10
8 1 2 7 StdA-SSRX+ GND 11
2 2 GND-DRAIN GND
D72
@ R740 0_0402_5% USB3TN1_D- 8 12
1 2 IP4292CZ10-TBR_XSON10_2.5X1~D USB3TP1_D+ 9 StdA-SSTX- GND 13
@ R1603 0_0402_5% StdA-SSTX+ GND
EMC@
SANTA_373130-1
+5V_ALW CONN@
1
100K_0402_5%
2
R816
1
PWRSHARE_EN#
<45> USB_PWR_SHR_VBUS_EN
<11,16,35,39,45,48,64,66> SIO_SLP_S3#
@ R153 1 2 0_0402_5% +5V_ALW 2.5A +5V_USB_CHG_PWR
1
U2 D U48
1 2 SB# 8 1 2 Q48 1 8
<45> USB_PWR_SHR_EN# 7 CB CEN 2 USBP0_D- 2 GND VOUT 7
@ R1626 0_0402_5% G L2N7002WT1G_SC-70-3
<19> USBP0- TDM DM VIN VOUT
10U_0805_10V6K
0.1U_0402_25V6
6 3 USBP0_D+ +5V_ALW S 3 6
<19> USBP0+
3
5 TDP DP 4 SEL PWRSHARE_EN# 4 VIN VOUT 5

VDD SELCDP EN FLG USB_OC0# <19,41>
+5V_ALW 9 1 1
Thermal Pad
2
10K_0402_5%
G547I2P81U_MSOP8
C676
C675
SLG55584AVTR_TDFN8_2X2
R1614
2 2
0.1U_0402_25V6
A
1 A
1
C715
2
L2N7002WT1G_SC-70-3
1
D
@
Q59
USB_PWR_SHR_EN# 2
G
S
3
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
USB3.0_JUSB1 Right Side Top
www.Vinafix.vn
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-9411P
5 4 3 2 1
5 4 3 2 1
Right Side Middle (JUSB2)

+3.3V_RP2 +3.3V_RP2
R3673
@
1
10U_0805_10V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.01U_0402_16V7K
Pin24 internal pull-down 1 @ 1 @ 1 @ 1 @
(pin control mode)
C1512
C1513
C1514
C1515
4.7K_0402_5%
2
2 2 2 2
U90 @
D D
25
1 EPAD 24
PD#A B_EQ_0A 2 VDD 12C_EN 23 USB3RN2_C @ C1516 2 1 0.1U_0402_10V6K USB3RN2
B_EQ0 B_OUTn USB3RN2 <19>
B_DE_0A 3 22 USB3RP2_C @ C1517 2 1 0.1U_0402_10V6K USB3RP2
I2C_R0 B_OUTp USB3RP2 <19>
B_EQ_1A 4 21
PD#A 5 I2C_R1 GND 20 USB3TN2_C @ C1518 2 1 0.1U_0402_10V6K USB3TN2
6 PD# A_INn 19 2 1 0.1U_0402_10V6K USB3TN2 <19>
@ B_DE_1A USB3TP2_C @ C1519 USB3TP2
B_DE1 A_INp USB3TP2 <19>
1
R3688 2K_0402_5%
REXTA 7 18 A_DE_1A
USB3RN2_RP @ R3680 1 2 0_0402_5% USB3RN2_R 8 REXT A_DE1 17 A_EQ_0A
USB3RP2_RP @ R3681 1 2 0_0402_5% USB3RP2_R 9 B_INn A_EQ0 16 A_DE_0A +3.3V_RP2
10 B_INp SCL_CTL 15 A_EQ_1A
GND SDA_CTL
0.1U_0402_16V4Z
USB3T_N2 @ C1520 1 2 0.1U_0402_10V6K USB3TN2_RP 11 14 TESTA
2
USB3T_P2 @ C1521 1 2 0.1U_0402_10V6K USB3TP2_RP 12 A_OUTn TEST 13

A_OUTp VDD @
1
C1522
2
+3.3V_RUN +3.3V_RP2
@ PJP69
+3.3V_RP2 1 2
PAD-OPEN1x1m
R3674
R3675
R3676
R3677
R3678
R3679
20mils 20mils
@ @ @ @ @ @ @ PJP70
1 2
1
@ R2 2 1 0_0402_5% USB3RN2_CO @ R10 2 1 0_0402_5%

PAD-OPEN1x1m
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
@ R4 2 1 0_0402_5% USB3RP2_CO @ R11 2 1 0_0402_5%

C C
C2 1 2 0.1U_0402_10V6K USB3TN2_CO @ R12 2 1 0_0402_5%

2
C3 1 2 0.1U_0402_10V6K USB3TP2_CO @ R13 2 1 0_0402_5%
R10.1 close to C1516.1.

B_EQ_0A R2.2 close to R3680.1 R11.1 close to C1517.1.
B_EQ_1A R4.2 close to R3681.1 Parade
B_DE_0A
R12.1 close to C1518.1.
B_DE_1A
C2.1 close to C1520.1 Bypass USB3.0 Repeater R13.1 close to C1519.1
REXTA C3.1 close to C1521.1
TESTA
@ @ @ @ @ @ A_EQ0 A_EQ1 B_EQ0 B_EQ1 Recommended EQ
R3682
R3683
R3684
R3685
R3686
R3687
1
0 0 0 0 EQ enable
Pericom
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
4.99K_0402_1%
0_0402_5%
0 1 0 1 loss up to 14.5dB
2
EQ A/B EQ setting
L107 EMC@ ** 1 0 1 0 loss up to 7dB
USBP1- 1 2 USBP1_D-
<19> USBP1- 1 2
** 0 3dB
1 1 1 1 loss up to 11.5dB
USBP1+ 4 3 USBP1_D+
<19> USBP1+ 4 3
OPEN 6dB
DLW21SN900SQ2L_0805_4P~D Both A_EQ&B_EQ have internal pull-down 150k
1 2
+3.3V_RP2
@ R3689 0_0402_5% 1 9dB
Recommended
1 2 A_DE0 A_DE1 B_DE0 B_DE1
@ R3690 0_0402_5%
De-Emphaisis
R3692
R3693
R3694
R3695
B @ @ @ @ DE A/B DE setting ** 0 0 0 0 -3.5dB B

1
USB3RP2_RP 4 3 USB3RP2_D+ 0 0dB 0 1 0 1 -7dB
4 3
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
USB3RN2_RP 1 2 USB3RN2_D- ** OPEN -3dB 1 0 1 0 0dB

2
1 2
L108 EMC@ D88 EMC@ 5dB boost
1 2 USB3RN2_D- 1 10 USB3RN2_D- 1 -6dB 1 1 1 1
@ R3691 0_0402_5% output swing
USB3RP2_D+ 2 9 USB3RP2_D+
A_EQ_0A 1 2 Both A_DE&B_DE have internal pull-down 150k
A_EQ_1A @ R3696 0_0402_5% USB3TN2_D- 4 7 USB3TN2_D-
A_DE_0A
A_DE_1A USB3TP2_D+ 5 6 USB3TP2_D+
@ @ @ @ DLW21SN900HQ2L_0805_4P~D
R3699
R3700
R3701
R3702
USB3T_P2 4 3 USB3TP2_D+ 3
4 3
1
+5V_USB_PWR2_3
8
USB3T_N2 1 2 USB3TN2_D- JUSB2
1 2 IP4292CZ10-TBR_XSON10_2.5X1~D 1
L109 VBUS
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
EMC@ 1 USBP1_D- 2
2
D-
220U_6.3V_M
0.1U_0402_25V6
1 2 1 USBP1_D+ 3
@ R3697 0_0402_5% + 4 D+
GND
C1523
C1524
USB3RN2_D- 5
1 2 USB3RP2_D+ 6 StdA-SSRX- 10
@ R3698 0_0402_5% 2 2 7 StdA-SSRX+ GND 11
D89 EMC@ USB3TN2_D- 8 GND-DRAIN GND 12
USBP1_D- 2 USB3TP2_D+ 9 StdA-SSTX- GND 13
1 StdA-SSTX+ GND
USBP1_D+ 3 SANTA_373130-1
CONN@
A A
+5V_USB_PWR2_3
D88, D89 must be as close as
+5V_ALW U91
possible to JUSB2
1 8
2 GND VOUT 7
3 VIN VOUT 6
VIN VOUT DELL CONFIDENTIAL/PROPRIETARY
10U_0805_10V6K
0.1U_0402_25V6
4 5 USB_OC0#
<42,45> ESATA_USB_PWR_EN# EN FLG USB_OC0# <19,40>
1 1
G547I2P81U_MSOP8
C1525
C1526
Title
2 2 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USB3.0_JUSB2 Right Side Mid
LA-9411P
www.Vinafix.vn
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5 4 3 2 1
5 4 3 2 1
Right Side bottom (JUSB3)

+3.3V_RP3 +3.3V_RP3
PD#D
R3769
D D
+3.3V_RP3 +3.3V_RP3
R3775
@
1
10U_0805_10V6K
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.01U_0402_16V7K
@
1
1 @ 1 1 @ 1
@ @
R3758
R3772
R3767
R3777
R3778
R3771
R3774
R3762
R3780
R3768
C1552
C1559
C1557
C1538
4.7K_0402_5%
@ @ @ @ @ @ Pin24 internal pull-down
2
@ @ @ @
(pin control mode)
2K_0402_5%
1
2 2 2 2
2
1
1
U95 @
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
25
2
1 EPAD 24
2
B_EQ_0D 2 VDD 12C_EN 23 USB3RN5_C @ C1555 2 1 0.1U_0402_10V7K~D USB3RN5
B_EQ0 B_OUTn USB3RN5 <19>
B_DE_0D 3 22 USB3RP5_C @ C1556 2 1 0.1U_0402_10V7K~D USB3RP5
I2C_R0 B_OUTp USB3RP5 <19>
B_EQ_1D 4 21
PD#D 5 I2C_R1 GND 20 USB3TN5_C @ C1562 2 1 0.1U_0402_10V7K~D USB3TN5
PD# A_INn USB3TN5 <19>
B_DE_1D 6 19 USB3TP5_C @ C1554 2 1 0.1U_0402_10V7K~D USB3TP5
B_DE1 A_INp USB3TP5 <19>
B_EQ_0D A_EQ_0D REXTD 7 18 A_DE_1D
B_EQ_1D A_EQ_1D USB3RN5_RP @ R3770 1 2 0_0402_5% USB3RN5_R 8 REXT A_DE1 17 A_EQ_0D
B_DE_0D A_DE_0D USB3RP5_RP @ R3763 1 2 0_0402_5% USB3RP5_R 9 B_INn A_EQ0 16 A_DE_0D +3.3V_RP3
B_DE_1D A_DE_1D 10 B_INp SCL_CTL 15 A_EQ_1D
GND SDA_CTL
0.1U_0402_16V4Z~D
REXTD @ @ @ @ USB3T_N5 @ C1551 1 2 0.1U_0402_10V7K~D USB3TN5_RP 11 14 TESTD
A_OUTn TEST
R3773
R3759
R3779
R3776
TESTD USB3T_P5 @ C1553 1 2 0.1U_0402_10V7K~D USB3TP5_RP 12 13
A_OUTp VDD
1
@ @ @ @ @ @ 1 1 @
R3765
R3766
R3764
R3760
R3757
R3761
1
C1558
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
4.99K_0402_1%
0_0402_5%
2
C C
@ R32 2 1 0_0402_5% USB3RN5_CO @ R34 2 1 0_0402_5%
@ R33 2 1 0_0402_5% USB3RP5_CO @ R35 2 1 0_0402_5%
C1563 1 2 0.1U_0402_10V6K USB3TN5_CO @ R37 2 1 0_0402_5%
C1564 1 2 0.1U_0402_10V6K USB3TP5_CO @ R36 2 1 0_0402_5%

+3.3V_RUN +3.3V_RP3
C1563.1 close to C1551.1 R37.1 close to C1562.1 @ PJP73
C1564.1 close to C1533.1 Bypass USB3.0 Repeater R36.1 close to C1554.1 1 2
PAD-OPEN1x1m
USB3RP5_RP 4 3 USB3RP5_D+ +3.3V_ALW_PCH +3.3V_RP3
4 3 20mils 20mils
D91 EMC@ @ PJP74
USB3RN5_RP 1 2 USB3RN5_D- USB3RN5_D- 1 10 USB3RN5_D- 1 2
1 2
L111 EMC@ USB3RP5_D+ 2 9 USB3RP5_D+ PAD-OPEN1x1m
1 2
@ R3721 0_0402_5% USB3TN5_D- 4 7 USB3TN5_D-
1 2 USB3TP5_D+ 5 6 USB3TP5_D+
B @ R3722 0_0402_5% B
3
DLW21SN900HQ2L_0805_4P~D 8
USB3T_P5 4 3 USB3TP5_D+
4 3 IP4292CZ10-TBR_XSON10_2.5X1~D
USB3T_N5 1 2 USB3TN5_D-
1 2
L112 EMC@ D90 EMC@
1 2 USBP2_D+ 2 +5V_USB_PWR2_3
@ R3727 0_0402_5% 1
USBP2_D- 3 JUSB3
1 2 1
@ R3728 0_0402_5% L30ESDL5V0C3-2_SOT23-3 USBP2_D- 2 VBUS
D-
0.1U_0402_25V6
1 USBP2_D+ 3
4 D+
GND
C1539
USB3RN5_D- 5
USB3RP5_D+ 6 StdA-SSRX- 10
D90, D91 must be as close as 2 StdA-SSRX+ GND
7 11
possible to JUSB3 USB3TN5_D- 8 GND-DRAIN GND 12
DLW21SN900SQ2L_0805_4P~D USB3TP5_D+ 9 StdA-SSTX- GND 13
USBP2+ 4 3 USBP2_D+ StdA-SSTX+ GND
<19> USBP2+ 4 3 SANTA_373130-1
CONN@
USBP2- 1 2 USBP2_D- +5V_USB_PWR2_3
<19> USBP2- 1 2 +5V_ALW U93 @
L110 EMC@ 1 8
1 2 2 GND VOUT 7
@ R3710 0_0402_5% 3 VIN VOUT 6
VIN VOUT 5
10U_0805_10V6K
0.1U_0402_16V4Z~D
<41,45> ESATA_USB_PWR_EN# 4 USB_OC1#

1 2 EN FLG USB_OC1# <19>
1 1
@ R3711 0_0402_5% @ @ G547I2P81U_MSOP8
C1540
C1541
A 2 2 A
PROPRIETARY NOTE:
www.Vinafix.vn
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USB3.0_JUSB3 Right Side bot
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_RP4
R3735
R3750
R3737
R3738
R3744
R3746
@ @ @ @ @ @
1 PD#C
1
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
@ USB 3.0 repeater change to SA00005OR00
1
+3.3V_RP4 +3.3V_RP4
R3755 2K_0402_5%
2
2
@
D D
Pin24 internal pull-down
R3754 4.7K_0402_5%
(pin control mode)
1
10U_0805_10V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.01U_0402_16V7K
B_EQ_0C
B_EQ_1C
B_DE_0C 1 1 1 1
B_DE_1C @ @
C1545
C1544
C1548
C1549
REXTC
2
TESTC
@ @ @ @ @ 2 2 2 2
R3734
R3751
R3748
R3741
R3742
R3749
1
U94
25
EPAD
4.99K_0402_1%
1 24
VDD 12C_EN
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
B_EQ_0C 2 23 USB3RN6_C C1547 2 1 0.1U_0402_10V6K USB3RN6

USB3RN6 <19>
2
B_DE_0C 3 B_EQ0 B_OUTn 22 USB3RP6_C C1543 2 1 0.1U_0402_10V6K USB3RP6

B_EQ_1C 4 I2C_R0 B_OUTp 21 USB3RP6 <19>
PD#C 5 I2C_R1 GND 20 USB3TN6_C C1546 2 1 0.1U_0402_10V6K USB3TN6
B_DE_1C 6 PD# A_INn 19 USB3TP6_C 2 1 0.1U_0402_10V6K USB3TP6 USB3TN6 <19>
C1550
REXTC 7 B_DE1 A_INp 18 A_DE_1C USB3TP6 <19>
USB3RN6_RP @ R3753 1 2 0_0402_5% USB3RN6_R 8 REXT A_DE1 17 A_EQ_0C
USB3RP6_RP @ R3756 1 2 0_0402_5% USB3RP6_R 9 B_INn A_EQ0 16 A_DE_0C +3.3V_RP4
10 B_INp SCL_CTL 15 A_EQ_1C
GND SDA_CTL
0.1U_0402_16V4Z
USB3T_N6 C414 2 1 0.1U_0402_10V6K USB3TN6_RP 11 14 TESTC
USB3T_P6 C415 2 1 0.1U_0402_10V6K USB3TP6_RP 12 A_OUTn TEST 13
+3.3V_RP4 A_OUTp VDD
1
C1542
@ @ @ @ 2
R3752
R3733
R3739
R3747
1
C C
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
2
A_EQ_0C
A_EQ_1C
A_DE_0C 2 1 USB3RN6_CO 2 1
A_DE_1C @ R14 0_0402_5% @ R18 0_0402_5%
@ @ @ @ 2 1 USB3RP6_CO 2 1
R3736
R3745
R3740
R3743
@ R16 0_0402_5% @ R19 0_0402_5%

1
2 1 USB3TN6_CO 2 1
@ C420 0.1U_0402_10V6K @ R21 0_0402_5%
2 1 USB3TP6_CO 2 1
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
@ C421 0.1U_0402_10V6K @ R20 0_0402_5%

R18.1 close to C1547.1
2
R14.2 close to C3753.1 R19.1 close to C1543.1 +3.3V_RUN +3.3V_RP4

R16.2 close to C3756.1 R21.1 close to C1546.1
C420.2 close to C414.2 Bypass USB3.0 Repeater R20.1 close to C1550.1 @ PJP71
C421.2 close to C415.2 1 2
1 2 PAD-OPEN1x1m
@R1609
@ R1609 0_0402_5%
20mils 20mils
DLW21SN900HQ2L_0805_4P~D @ PJP72
USB3RN6_RP 1 2 USB3RN6_D- 1 2
B 1 2 B
PAD-OPEN1x1m
USB3RP6_RP 4 3 USB3RP6_D+
4 3
JUSB4
1 2
L98 EMC@ @R1150
@ R1150 0_0402_5%
1 2 L90 EMC@
@R1610
@ R1610 0_0402_5% 4 3 USBP9_D-
<19> USBP9- 4 3
1 2 USBP9_D+ +5V_USB_PWR4
1 2 <19> USBP9+ 1 2
@R1612
@ R1612 0_0402_5% DLW21SN900SQ2L_0805_4P~D JUSB4
2
1
USBP9_D- 2 VBUS
DLW21SN900HQ2L_0805_4P~D D-
220U_6.3V_M
0.1U_0402_25V6
1 2 USBP9_D+ 3
D+
D74 EMC@
USB3T_N6 1 2 USB3TN6_D- @R1151
@ R1151 0_0402_5% 4
1 2 USB3RN6_D- 5 GND
1 StdA-SSRX-
1 USB3RP6_D+ 6 10
StdA-SSRX+ GND
C667
C668
USB3T_P6 4 3 USB3TP6_D+ + 7 11
4 3 USB3TN6_D- 8 GND-DRAIN GND 12
L97 EMC@ D79 EMC@ USB3TP6_D+ 9 StdA-SSTX- GND 13
1
USB3TP6_D+ 1 10 USB3TP6_D+ 2 2 StdA-SSTX+ GND
SANTA_373130-1
1 2 USB3TN6_D- 2 9 USB3TN6_D- CONN@
@R1613
@ R1613 0_0402_5%
USB3RP6_D+ 4 7 USB3RP6_D+
Place D74 close to JUSB4
USB3RN6_D- 5 6 USB3RN6_D-
A
2.5A 3
A
+5V_ALW
U49 8
1 8
GND VOUT +5V_USB_PWR4
2 7 IP4292CZ10-TBR_XSON10_2.5X1~D
VIN VOUT
10U_0805_10V6K
0.1U_0402_25V6
3 6
<45> USB_SIDE_EN#
4 VIN VOUT
EN FLG
5
USB_OC4# <19> DELL CONFIDENTIAL/PROPRIETARY
1 1
G547I2P81U_MSOP8
C719
C723
PROPRIETARY NOTE:
Title
2 2 THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
USB3.0_JUSB4 Left Side
www.Vinafix.vn
1.0
5 4 3 2 1
5 4 3 2 1
JDOCK1 CONN@
DOCK_DET_1 1 2 DOCK_AC_OFF
3 1 2 4 DOCK_AC_OFF <69>
<33> DOCK_LOM_SPD10LED_GRN# DPD_CA_DET 5 3 4 6 DPC_CA_DET DOCK_LOM_SPD100LED_ORG# <33>
<29> DPD_CA_DET 7 5 6 8 DPC_CA_DET <29>
C690 2 1 0.1U_0402_10V6K DPD_CPU_LANE_P0_C EMC@ 2 RE7 133_0402_5% DPD_DOCK_LANE_P0 9 7 8 10 DPC_DOCK_LANE_P0 EMC@ 1 RE17 2 33_0402_5% DPC_CPU_LANE_P0_C C691 2 1 0.1U_0402_10V6K
D <9> DPD_CPU_LANE_P0 9 10 DPC_CPU_LANE_P0 <9> D
C679 2 1 0.1U_0402_10V6K DPD_CPU_LANE_N0_C EMC@ 2 RE8 133_0402_5% DPD_DOCK_LANE_N0 11 12 DPC_DOCK_LANE_N0 EMC@ 1 RE18 2 33_0402_5% DPC_CPU_LANE_N0_C C680 2 1 0.1U_0402_10V6K
<9> DPD_CPU_LANE_N0 13 11 12 14 DPC_CPU_LANE_N0 <9>
<9> DPD_CPU_LANE_P1 15 16 DPC_CPU_LANE_P1 <9>
DPD_DOCK_AUX 33 31 32 34 DPC_DOCK_AUX
<29> DPD_DOCK_AUX DPD_DOCK_AUX# 35 33 34 36 DPC_DOCK_AUX# DPC_DOCK_AUX <29>
<29> DPD_DOCK_AUX# 37 35 36 38 DPC_DOCK_AUX# <29>
DPD_PCH_DOCK_HPD 39 37 38 40 DPC_PCH_DOCK_HPD
<16> DPD_PCH_DOCK_HPD 41 39 40 42 DPC_PCH_DOCK_HPD <16>
+NBDOCK_DC_IN_SS 41 42 ACAV_DOCK_SRC# <69>
0.033U_0402_16V7K
0.033U_0402_16V7K
1 43 44 1
BLUE_DOCK 45 43 44 46
<25> BLUE_DOCK 45 46 DAT_DDC2_DOCK <25>
C695
C696
47 48
49 47 48 50 CLK_DDC2_DOCK <25>
2 49 50 2
Close to DOCK
51 52
RED_DOCK 53 51 52 54 SATA_PRX_DKTX_P2 2 1 @
Its for Enhance ESD on dock issue.
<25> RED_DOCK 53 54 SATA_PRX_DKTX_P2_C <15>
@
Close to DOCK 55 56 SATA_PRX_DKTX_N2 C697 2 1 0.01U_0402_16V7K
57 55 56 58 SATA_PRX_DKTX_N2_C <15>
C698 0.01U_0402_16V7K
Its for Enhance ESD on dock issue. GREEN_DOCK 59 57 58 60 SATA_PTX_DKRX_P2 1 2
<25> GREEN_DOCK 61 59 60 62 SATA_PTX_DKRX_P2_C <15>
SATA_PTX_DKRX_N2 C699 1 2 0.01U_0402_16V7K
63 61 62 64 C700 0.01U_0402_16V7K SATA_PTX_DKRX_N2_C <15> L99 @
65 63 64 66 USBP6_R_D+ 3 4
<25> HSYNC_DOCK 67 65 66 68 USBP6_R_D- 3 4 USBP6+ <19>
<25> VSYNC_DOCK 69 67 68 70
DPD_PCH_DOCK_HPD 71 69 70 72 2 1
<46> CLK_MSE 73 71 72 74 USBP3+ <19> 2 1 USBP6- <19>
C <46> DAT_MSE 75 73 74 76 USBP3- <19> C
77 75 76 78 1 2
<30> DAI_BCLK# 77 78 CLK_KBD <46>
1
79 80 @ R1672 0_0402_5%
<30> DAI_LRCK# 81 79 80 82 DAT_KBD <46>
R757 83 81 82 84 1 2
<30> DAI_DI 85 83 84 86 USB3RN3 <19>
100K_0402_5% @ R1673 0_0402_5%
<30> DAI_DO# 87 85 86 88 USB3RP3 <19>
2
89 87 88 90
<30> DAI_12MHZ# 91 89 90 92 USB3TN3 <19>
93 91 92 94 USB3TP3 <19>
95 93 94 96
97 95 96 98 DPC_PCH_DOCK_HPD
<45> D_LAD0 99 97 98 100 BREATH_LED# <24,45>
<45> D_LAD1 101 99 100 102 DOCK_LOM_ACTLED_YEL# <33>
101 102
100K_0402_5%
103 104
<45> D_LAD2 103 104 DOCK_LOM_TRD0+ <33>
1
105 106
<45> D_LAD3 105 106 DOCK_LOM_TRD0- <33>
R758
107 108
109 107 108 110
<45> D_LFRAME# 111 109 110 112 DOCK_LOM_TRD1+ <33> +LOM_VCT
<45> D_CLKRUN# 113 111 112 114 DOCK_LOM_TRD1- <33>
2
113 114
1U_0402_6.3V6K
115 116 1
<45> D_SERIRQ 115 116
@ C701
117 118
<45> D_DLDRQ1# 117 118 +LOM_VCT
119 120
121 119 120 122
<17> CLK_PCI_DOCK 123 121 122 124 DOCK_LOM_TRD2+ <33> 2
125 123 124 126 DOCK_LOM_TRD2- <33>
127 125 126 128 +3.3V_ALW
<46> DOCK_SMB_CLK 129 127 128 130 DOCK_LOM_TRD3+ <33>
<46> DOCK_SMB_DAT 131 129 130 132 DOCK_LOM_TRD3- <33>
133 131 132 134 DOCK_DET# 1 2
<45,60,69> DOCK_SMB_ALERT# 135 133 134 136 DOCK_DCIN_IS+ <68>
10K_0402_5% R755
<60> DOCK_PSID 137 135 136 138 DOCK_DCIN_IS- <68>
B 139 137 138 140 D32 B
<46> DOCK_PWR_BTN# 141 139 140 142 DOCK_POR_RST# <46>
RB751V40_SC76-2
SLICE_BAT_PRES# 143 141 142 144 DOCK_DET_R# 1 2
<45,60,69> SLICE_BAT_PRES# 143 144 DOCK_DET# <45,69>
145 149
GND1 PWR2 +DOCK_PWR_BAR
146 150
+DOCK_PWR_BAR PWR1 PWR2
0.1U_0603_50V7K
147 151
PWR1 PWR2
0.1U_0603_50V7K
148 152
PWR1 GND2
3
2
4.7U_0805_25V6-K
L30ESD24VC3-2_SOT23-3
C703
1 1 153 159
Shield_G Shield_G
@
C702
D33
154 160
Shield_G Shield_G
CE6
155 161
@ 156 Shield_G Shield_G 162 2 @
2 2 @ 157 Shield_G Shield_G 163
158 Shield_G Shield_G 164
Shield_G Shield_G
DAI_12MHZ# DAI_BCLK# CLK_PCI_DOCK
1
JAE_WD2F144WB1
1
@ RE11 @ RE12 @ R756
10_0402_1% 10_0402_1% 33_0402_5%
2
1 1 1
@CE8
@CE8 @CE9
@CE9 @ C704
4.7P_0402_50V8C 4.7P_0402_50V8C 12P_0402_50V8J
2 2 2
A A
PROPRIETARY NOTE:
Title
DOCKING CONN
www.Vinafix.vn
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
@ PJP63
+3.3V_ALW_5048 1 2
+3.3V_ALW
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
PAD-OPEN1x1m
1 2 DYN_TURB_PWR_ALRT#
@ R796 10K_0402_5% 1 1 1 1 1 1
1 2 HW_GPS_DISABLE2#
C705
C706
C707
C708
C709
C710
R798 10K_0402_5%
1 2 PROCHOT_GATE
D R761 100K_0402_5% 2 2 2 2 2 2 D
1 2 CPU_DETECT#
R763 100K_0402_5%
A17
B30
A43
A54
1 2 SLICE_BAT_PRES#
B5
R760 100K_0402_5% U46 SMSC feedback disconnect LPC_LDRQ0# at A23 pin
1 2 WWAN_RADIO_DIS#
VCC1
VCC1
VCC1
VCC1
VCC1
R774 100K_0402_5% A23 PAD~D T147 @
1 2 USB_PWR_SHR_EN# CRT_SWITCH B52 GPIOI0 B63 SIO_SLP_A#
<25> CRT_SWITCH GPIOA0 GPIOI1 SIO_SLP_A# <16,35,48,63>
R776 100K_0402_5% MDC_RST_DIS# A49 A60 0.75V_DDR_VTT_ON
<47> MDC_RST_DIS# GPIOA1 GPIOI2/TACH0 0.75V_DDR_VTT_ON <62>
1 2 USB_SIDE_EN# <39> MCARD_MISC_PWREN MCARD_MISC_PWREN B53 A61
GPIOA2 GPIOI3 SIO_SLP_S4# <16,28,35,62>
R768 10K_0402_5% <68,69> PROCHOT_GATE PROCHOT_GATE A50 B65
GPIOA3 GPIOI4 SIO_SLP_S3# <11,16,35,39,40,48,64,66>
1 2 ESATA_USB_PWR_EN# @ T141 PAD~D LID_CL_SIO# B54 A62
GPIOA4 GPIOI5 IMVP_PWRGD <65>
R769 100K_0402_5% DOCK_SMB_ALERT# A51 B66
<44,60,69> DOCK_SMB_ALERT# GPIOA5 GPIOI6 IMVP_VR_ON <65>
1 2 USB_PWR_SHR_VBUS_EN @ T144 PAD~D TOUCH_SCREEN_PD# B55 A63
R778 100K_0402_5% GPU_PWR_LEVEL A52 GPIOA6 GPIOI7 DOCK_AC_OFF_EC <69>
1 2 DOCK_SMB_ALERT# <50> GPU_PWR_LEVEL GPIOA7 B67 AUX_EN_WOWL
R762 10K_0402_5% USB_SIDE_EN# A33 GPIOJ0 A64 WLAN_LAN_DISB# AUX_EN_WOWL <39>
<43> USB_SIDE_EN# GPIOB0 GPIOJ1/TACH1 WLAN_LAN_DISB# <33>
1 2 WIRELESS_ON#/OFF EN_I2S_NB_CODEC# B36 A5 SIO_SLP_LAN#
<30> EN_I2S_NB_CODEC# GPIOB1 GPIOJ2/TACH2 SIO_SLP_LAN# <16,48>
R771 100K_0402_5% USH_PWR_STATE# A34 B6 SIO_SLP_SUS#
<35> USH_PWR_STATE# GPOC2 GPIOJ3 SIO_SLP_SUS# <16>
<69> EN_DOCK_PWR_BAR EN_DOCK_PWR_BAR B37 A6
+3.3V_RUN PANEL_BKEN_EC A35 GPOC3 GPIOJ4 B7 MODC_EN GPIO_PSID_SELECT <60>
<28> PANEL_BKEN_EC GPOC4 GPIOJ5 MODC_EN <32,48>
ENVDD_PCH B38 A7 DOCK_HP_DET
<16,28> ENVDD_PCH GPOC5 GPIOJ6 DOCK_HP_DET <30>
LCD_TST A36 B8 DOCK_MIC_DET
<28> LCD_TST GPOC6/TACH4 GPIOJ7 DOCK_MIC_DET <30>
1 2 SP_TPM_LPC_EN PSID_DISABLE# A37
@ R772 10K_0402_5% <60> PSID_DISABLE# PBAT_PRES# B40 GPIOC7 A8 ME_FWP
<60,69> PBAT_PRES# GPIOD0 GPIOK0 ME_FWP <15>
DOCKED A38 B9 MASK_SATA_LED#
<33> DOCKED GPIOC1 GPIOK1/TACH3 MASK_SATA_LED# <24>
1 2 LCD_TST DOCK_DET# B41 B10 USB_PWR_SHR_EN#
<44,69> DOCK_DET# GPIOC0 GPIOK2 USB_PWR_SHR_EN# <40>
R767 100K_0402_5% AUD_NB_MUTE# A39 A10 LED_SATA_DIAG_OUT# +3.3V_RUN
<30> AUD_NB_MUTE# GPIOB7 GPIOK3 LED_SATA_DIAG_OUT# <24>
1 2 SYS_LED_MASK# MCARD_WWAN_PWREN B42 B11 TEMP_ALERT#_R 1 2
<39> MCARD_WWAN_PWREN GPIOB6 GPIOK4 TEMP_ALERT# <18>
R775 10K_0402_5% LCD_VCC_TEST_EN A40 A11 RUN_ON @ R738 0_0402_5%
<28> LCD_VCC_TEST_EN GPIOB5 GPIOK5 RUN_ON <39,48,64>
CCD_OFF B43 B12 D_CLKRUN# 2 1
<28> CCD_OFF GPIOB4 GPIOK6 AC_DIS <60,69>
AUD_HP_NB_SENSE A41 A12 SPI_WP#_SEL 100K_0402_5% R777
<30> AUD_HP_NB_SENSE GPIOB3 GPIOK7 SPI_WP#_SEL <18>
1 2 GFX_MEM_VTT_ON ESATA_USB_PWR_EN# B44 D_SERIRQ 2 1
<41,42> ESATA_USB_PWR_EN# GPIOB2
@ R1583 10K_0402_5% B60 SUS_ON 100K_0402_5% R780
GPIOL0/PWM7 SUS_ON <28,62>
1 2 CHARGE_EN A57 SPKR_MUTE_LED# D_DLDRQ1# 2 1
C GPIOL1/PWM8 SPKR_MUTE_LED# <24> C
R3 100K_0402_5% MODULE_ON B32 B64 BAT1_LED# trace width 10 mils 100K_0402_5% R782
<69> MODULE_ON GPIOD1 GPIOL2/PWM0 BAT1_LED# <24>
<69> SLICE_BAT_ON SLICE_BAT_ON A31 B68 AUDIO_BACKLITE#
GPIOD2 GPIOL3/PWM1 AUDIO_BACKLITE# <24>
SLICE_BAT_PRES# B33 A9 BAT2_LED# trace width 10 mils
<44,60,69> SLICE_BAT_PRES# GPIOD3 GPIOL4/PWM3 BAT2_LED# <24>
1 2 DP_HDMI_HPD MODULE_BATT_PRES# B15 B1 PAD~D T148 @
@ R1154 100K_0402_5% <60,68,69> MODULE_BATT_PRES# CHARGE_MODULE_BATT A15 GPIOD4 GPIOL5/PWM2 A18 USH_PWR_ON
<69> CHARGE_MODULE_BATT GPIOD5 GPIOL6 USH_PWR_ON <28>
CHARGE_PBATT B16 A44 PAD~D T146 @
<69> CHARGE_PBATT DEFAULT_OVRDE A16 GPIOD6 GPIOL7/PWM5 RUN_ON 2 1
<69> DEFAULT_OVRDE GPIOD7 B34 HW_GPS_DISABLE2# 100K_0402_5% R786
GPIOM1 HW_GPS_DISABLE2# <38>
B39 BREATH_LED# CPU_VTT_ON 2 1
GPIOM3/PWM4 BREATH_LED# <24,44>
WIGIG60GHZ_DIS# A1 B51 DIS_BAT_PROCHOT# 100K_0402_5% R789
<37> WIGIG60GHZ_DIS# GPIOE0/RXD GPIOM4/PWM6 DIS_BAT_PROCHOT# <69>
B2 0.75V_DDR_VTT_ON 2 1
<37,45,46> EC5048_TX GPIOE1/TXD
if EC define output GPIO can remove PU @ T137 PAD~D GFX_MEM_VTT_ON A2 100K_0402_5% R790
B3 GPIOE2/RTS# A27 LPC_LAD0 SLICE_BAT_ON 2 1
<15,20,38> MCARD_PCIE_SATA# GPIOE3/DSR# LAD0 LPC_LAD0 <18,35,37,46>
CPU_DETECT# A3 A26 LPC_LAD1 100K_0402_5% R791
<7> CPU_DETECT# GPIOE4/CTS# LAD1 LPC_LAD1 <18,35,37,46>
EC need define output GPIO @ T136 PAD~D GPIOE4 B45 B26 LPC_LAD2 SUS_ON 2 1
GPIOE5/DTR# LAD2 LPC_LAD2 <18,35,37,46>
MOD_SATA_PCIE#_DET A42 B25 LPC_LAD3 100K_0402_5% R878
<32> MOD_SATA_PCIE#_DET GPIOE6/RI# LAD3 LPC_LAD3 <18,35,37,46>
@ T130 PAD~D DP_HDMI_HPD B4 A21 LPC_LFRAME# USH_PWR_ON 2 1
GPIOE7/DCD# LFRAME# LPC_LFRAME# <18,35,37,46>
B22 PCH_PLTRST#_EC 100K_0402_5% R518 @
LRESET# PCH_PLTRST#_EC <16,35,37,38,39,46>
A28 CLK_PCI_5048
PCICLK CLK_PCI_5048 <17>
ZODD_WAKE# A59 B20 CLKRUN#
<32> ZODD_WAKE# GPIOF0 CLKRUN# CLKRUN# <16,35,46>
BCM5882_ALERT# B62
<35> BCM5882_ALERT# GPIOF1
A58 A22 LPC_LDRQ1#
<16> SUSACK# GPIOF2 LDRQ1# LPC_LDRQ1# <18>
@ T121 PAD~D EDID_SELECT# B61 B21 IRQ_SERIRQ
GPIOF3/TACH8 SER_IRQ IRQ_SERIRQ <18,35,46>
DGPU_PWROK A56 A32 CLK_SIO_14M
<20,66> DGPU_PWROK GPIOF4/TACH7 14.318MHZ/GPIOM0 CLK_SIO_14M <17>
VGA_ID B59 B35 EC_32KHZ_ECE5048 <46>
3.3V_RUN_GFX_ON A55 GPIOF5 CLK32/GPIOM2
<17> 3.3V_RUN_GFX_ON GPIOF6
SLP_ME_CSW_DEV# B58
<20> SLP_ME_CSW_DEV# GPIOF7 B29 D_LAD0
DLAD0 B28 D_LAD1 D_LAD0 <44>
LAN_DISABLE#_R B47 DLAD1 A25 D_LAD2 D_LAD1 <44>
<33> LAN_DISABLE#_R GPIOG0/TACH5 DLAD2 D_LAD2 <44>
CHARGE_EN A45 A24 D_LAD3
SYS_LED_MASK# B48 GPIOG1 DLAD3 B23 D_LFRAME# D_LAD3 <44>
<24,33> SYS_LED_MASK# GPIOG2 DLFRAME# D_LFRAME# <44>
DYN_TURB_PWR_ALRT# A46 A19 D_CLKRUN#
GPIOG3 DCLKRUN# D_CLKRUN# <44>
<15,17,20> SIO_EXT_WAKE# B49 B24 D_DLDRQ1#
GPIOG4 DLDRQ1# D_DLDRQ1# <44>
B A47 A20 D_SERIRQ B
<24,37,38> WIRELESS_LED# GPIOG5 DSER_IRQ D_SERIRQ <44>
USB_PWR_SHR_VBUS_EN B50
<40> USB_PWR_SHR_VBUS_EN WLAN_RADIO_DIS# A48 GPIOG6
<37> WLAN_RADIO_DIS# GPIOG7/TACH6 A29 BC_INT#_ECE5048
BC_INT# BC_INT#_ECE5048 <46>
B31 BC_DAT_ECE5048
+3.3V_ALW BC_DAT BC_DAT_ECE5048 <46>
WIRELESS_ON#/OFF B13 A30 BC_CLK_ECE5048
<47> WIRELESS_ON#/OFF GPIOH0 BC_CLK BC_CLK_ECE5048 <46>
BT_RADIO_DIS# A13
<37> BT_RADIO_DIS# GPIOH1
WWAN_RADIO_DIS# A53
<38> WWAN_RADIO_DIS# SYSOPT1/GPIOH2
1 2 VGA_ID SYS_PWROK B57 A4 AND_PWRGD <46>
<7,16> SYS_PWROK SYSOPT0/GPIOH3 PWRGD
@ R800 100K_0402_5% @ T122 PAD~D B14
A14 GPIOH4 B56 SP_TPM_LPC_EN
<16,39> SIO_SLP_WLAN# GPIOH5 OUT65 SP_TPM_LPC_EN <35>
2 1 VGA_ID CPU_VTT_ON B17
R803 100K_0402_5% 1 2 B18 GPIOH6
<16> PCH_DPWROK GPIOH7
@ R802 0_0402_5% B19 1 2 +3.3V_ALW
TEST_PIN R804 1K_0402_5%
B46 +CAP_LDO
CAP_LDO
4.7U_0603_6.3V6K
100K_0402_5%
1 CLK_SIO_14M CLK_PCI_5048
1
B27
VSS
C714
R805
C1
10_0402_1%
10_0402_1%
EP
1
VGA_ID0
@ R795
@ R794
DB Version 0.4 2
Discrete 0 ECE5048-LZY_DQFN132_11X11~D
2
LID_CL_SIO# 2 1
UMA 1 LID_CL# <24,47>
2
R807 10_0402_1%
0.047U_0402_16V4Z
1
4.7P_0402_50V8C
4.7P_0402_50V8C
+CAP_LDO trace width 20 mils
1 2 USB_PWR_SHR_EN# 1 1
<37,45,46> EC5048_TX
@C712
@
@C713
@
C716
@ R806 0_0402_5%
2
C712
C713
ME_FWP PCH has internal 20K PD. 2 2
ME_FWP
1
A A
1K_0402_5%
@R793
@ R793
2
www.Vinafix.vn
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT ECE5048
LA-9411P
5 4 3 2 1
5 4 3 2 1
+RTC_CELL +RTC_CELL
+3.3V_ALW
100K_0402_5%
100K_0402_5%
1
1
C720 @
R810
R819
1 2 @ C721 @ C733
1 2 1 2
0.1U_0402_25V6
5
1U_0402_6.3V6K 1U_0402_6.3V6K
2
ECE5048_PWRGD 1
P
B 4 +RTC_CELL POWER_SW_IN# 1 2 DOCK_PWR_SW# 1 2
2 O AND_PWRGD <45> POWER_SW#_MB <24,35> DOCK_PWR_BTN# <44>
RUNPWROK R811 10K_0402_5% R825 10K_0402_5%
A
1U_0402_6.3V6K
1U_0402_6.3V6K
U50 @ 1 2 +RTC_CELL_VBAT 1 1
TC7SH08FU_SSOP5~D @ R830 0_0402_5%
0.1U_0402_25V6
C722
C734
2 2
1
C724
+1.05V_RUN
1 2
@ R840 0_0402_5% 2
10K_0402_5%
1 2
1
@ R1179
@ R1180 0_0402_5%
D D
U51
+3.3V_ALW 1 2 +3.3V_VTR
@ R834 0_0402_5% B64 A10 SYSTEM_ID
VBAT GPIO021/RC_ID1 H_PROCHOT# <7,50,65,68,69>
0.1U_0402_25V6
1U_0402_6.3V4Z
1 2 B10 BOARD_ID
+3.3V_M
2
GPIO020/RC_ID2
L2N7002WT1G_SC-70-3
@ R837 0_0402_5% 1 1 B8 R888 1 2 1K_0402_5%
GPIO014/GPTP-IN7/RC_ID3 VOL_UP# <47>
1
1 2 A22 B27 LANWAKE# D
+3.3V_ALW H_VTR GPIO025/UART_CLK LANWAKE# <20,33>
C739
C775
Q47
@ R839 0_0402_5% B44 HOST_DEBUG_TX PROCHOT#_EC 2
GPIO120/UART_TX HOST_DEBUG_TX <37>
0.1U_0402_25V6
1U_0402_6.3V4Z
B46 HOST_DEBUG_RX G
2 2 +3.3V_VTR_ADC A58 GPIO124/GPTP-OUT5/UART_RX B26 RUNPWROK
@
1 1 S
3
VTR_ADC VCC_PWRGD RUNPWROK <7>
100K_0402_5%
A25 EN_INVPWR
GPIO060/KBRST/BCM_B_INT# EN_INVPWR <28>
C736
2
C757
B36 PCH_SATA_MOD_EN#
GPIO101/ECGP_SCLK/GANG_DATA5 PCH_SATA_MOD_EN# <15>
@ R812
B3 B37
+3.3V_ALW 2 2 A11 VTR GPIO103/ECGP_MISO/GANG_DATA7 B38 PCIE_WAKE# SLICE_PERF_EN <69>
A26 VTR GPIO105/ECGP_MOSI A34 PCIE_WAKE# <32,36,37,38,39>
ECE5048_PWRGD
+3.3V_ALW B35 VTR GPIO102/BCM_C_INT#/GANG_DATA6 A35 +PCH_VCCDSW3_3
1
1 2 PCIE_WAKE# @ PJP65 A41 VTR GPIO104 A36 DYN_TUR_CURRNT_SET# <68>
R759 10K_0402_5% 1 2 +3.3V_ALW_VTR A52 VTR GPIO106 A40 MSDATA CPU1.5V_S3_GATE <11> AC_PRESENT 2 1
VTR GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP B43 MSDATA <37>
MSCLK 10K_0402_5% R835
GPIO117/MSCLK/V2P_COUT_HI MSCLK <37>
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
PAD-OPEN1x1m A45 SIO_A20GATE
1 2 GPIO127/A20M B65 SIO_A20GATE <20>
BC_DAT_ECE5048 1 1 1 1 1 1 1 FWP#
R814 100K_0402_5% SML1_SMBDATA A5 NFWP +RTC_CELL
<18> SML1_SMBDATA GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA/GANG_BUSY
C781
C759
C774
C776
C777
C780
C782
1 2 BC_DAT_ECE1117 SML1_SMBCLK B6
<18> SML1_SMBCLK A37 GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_ERROR B57
R817 100K_0402_5% CLK_TP_SIO VOL_DOWN_R# R887 1 2 1K_0402_5% VCI_IN3# 2 1
1 2 PBAT_SMBDAT 2 2 2 2 2 2 2 <47> CLK_TP_SIO DAT_TP_SIO B40 GPIO110/PS2_CLK2/GPTP-IN6 GPIO156/LED0 B1 DEVICE_DET_R# 1 2 DEVICE_DET# VOL_DOWN# <47>
100K_0402_5% R1156
<47> DAT_TP_SIO GPIO111/PS2_DAT2/GPTP-OUT6 GPIO157/LED1 DEVICE_DET# <32>
R818 2.2K_0402_5% CLK_KBD A38 A55 PS_ID @ R1070 0_0402_5% LAT_ON_SW# 2 1
<44> CLK_KBD GPIO112/PS2_CLK1A GPIO153/LED2 PS_ID <60>
1 2 PBAT_SMBCLK DAT_KBD B41 A1 ALW_PWRGD_3V_5V 100K_0402_5% R870
<44> DAT_KBD A39 GPIO113/PS2_DAT1A GPIO027/GPTP-OUT1 B28 ALW_PWRGD_3V_5V <61>
R820 2.2K_0402_5% CLK_MSE 1.05V_A_PWRGD
1 2 <44> CLK_MSE B42 GPIO114/PS2_CLK0A GPIO026/GPTP-IN1 B2 1 2 1.05V_A_PWRGD <63>
CHARGER_SMBDAT DAT_MSE
<44> DAT_MSE PBAT_SMBDAT B59 GPIO115/PS2_DAT0A GPIO001/ECSPI_CS1 A8 VOL_MUTE <47>
R827 10K_0402_5% R884 1K_0402_5%
1 2 <60> PBAT_SMBDAT A56 GPIO154/I2C1C_DATA/PS2_CLK1B GPIO015/GPTP-OUT7/GANG_DATA3 B9 ME_SUS_PWR_ACK <16>
CHARGER_SMBCLK PBAT_SMBCLK 1.35V_SUS_PWRGD
<60> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B GPIO016/GPTP-IN8/GANG_DATA4 A9 1.35V_SUS_PWRGD <7,62>
R828 10K_0402_5% PM_APWROK
GPIO017/GPTP-OUT8 PM_APWROK <16>
JTAG_TDI A51 B39 RESET_OUT#
GPIO145/I2C1K_DATA/JTAG_TDI GPIO107/NRESET_OUT RESET_OUT# <10,15,16>
+5V_RUN JTAG_TDO B55 A44 PCH_PCIE_WAKE#
JTAG_CLK B56 GPIO146/I2C1K_CLK/JTAG_TDO GPIO125/GPTP-IN5 B47 PCH_RSMRST# PCH_PCIE_WAKE# <16>
1 2 A53 GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO126 A54 PCH_RSMRST# <47>
CLK_KBD JTAG_TMS AC_PRESENT +3.3V_ALW
A57 GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO151/GPTP-IN4 B58 AC_PRESENT <16>
R845 4.7K_0402_5% JTAG_RST# SIO_PWRBTN#
1 2 JTAG_RST# GPIO152/GPTP-OUT4 SIO_PWRBTN# <16> 2 1
DAT_KBD LCD_SMBCLK
R846 4.7K_0402_5% DOCK_POR_RST# FAN1_TACH_FB B22 A3 DOCK_SMB_DAT 2.2K_0402_5% R418 @
1 2 CLK_MSE DOCK_POR_RST# A21 GPIO050/FAN_TACH1/GTACH GPIO003/I2C1A_DATA/GANG_MODE B4 DOCK_SMB_CLK DOCK_SMB_DAT <44> LCD_SMBDAT 2 1
<44> DOCK_POR_RST# B23 GPIO051/FAN_TACH2 GPIO004/I2C1A_CLK/GANG_START A4 DOCK_SMB_CLK <44>
R851 4.7K_0402_5% LCD_SMBDAT 2.2K_0402_5% R420 @
1 2 <20> EC_WAKE# B24 GPIO052/FAN_TACH3 GPIO005/I2C1B_DATA/BCM_B_DAT/GANG_STROBE B5 2 1
DAT_MSE LCD_SMBCLK DOCK_SMB_DAT
<48,63> A_ON GPIO053/PWM0 GPIO006/I2C1B_CLK/BCM_B_CLK/GANG_FULL
0.1U_0402_25V6
R852 4.7K_0402_5% PCH_ALW_ON A23 B7 BAY_SMBDAT 2.2K_0402_5% R838
<48,60> PCH_ALW_ON B25 GPIO054/PWM1 GPIO012/I2C1H_DATA/I2C2D_DATA/GANG_DATA1 A7 BAY_SMBDAT <32,60> 2 1
1 <28> BIA_PWM_EC BIA_PWM_EC BAY_SMBCLK DOCK_SMB_CLK
+3.3V_RUN C737 FAN1_PWM A24 GPIO055/PWM2 GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA2 B48 GPU_SMBDAT BAY_SMBCLK <32,60>
2.2K_0402_5% R841
GPIO056/PWM3/GPWM GPIO130/I2C2A_DATA/BCM_C_DAT B49 GPU_SMBCLK BAY_SMBDAT 2 1
1 2 VOL_MUTE GPIO131/I2C2A_CLK/BCM_C_CLK A47 CHARGER_SMBDAT 2.2K_0402_5% R854
2 GPIO132/I2C1G_DATA B50 CHARGER_SMBDAT <68> 2 1
@ R1169 100K_0402_5% CHARGER_SMBCLK BAY_SMBCLK
1 2 A43 GPIO140/I2C1G_CLK B52 CHARGER_SMBCLK <68>
VOL_DOWN# BC_CLK_ECE5048 CARD_SMBDAT 2.2K_0402_5% R856
<45> BC_CLK_ECE5048 BC_DAT_ECE5048 B45 GPIO123/BCM_A_CLK GPIO141/I2C1F_DATA/I2C2B_DATA A49 CARD_SMBCLK CARD_SMBDAT <39> DYN_TUR_CURRNT_SET# 2 1
@ R1197 100K_0402_5%
1 2 <45> BC_DAT_ECE5048 A42 GPIO122/BCM_A_DAT GPIO142/I2C1F_CLK/I2C2B_CLK B53 CARD_SMBCLK <39>
C VOL_UP# BC_INT#_ECE5048 USH_SMBDAT 100K_0402_5% R1171 C
<45> BC_INT#_ECE5048 B20 GPIO121/BCM_A_INT# GPIO143/I2C1E_DATA A50 USH_SMBDAT <35> 2 1
@ R1118 100K_0402_5% ACAV_IN_NB USH_SMBCLK DEVICE_DET#
<68,69> ACAV_IN_NB GPIO032/BCM_E_CLK GPIO144/I2C1E_CLK USH_SMBCLK <35>
1 2 GPU_SMBDAT SIO_SLP_S5# A18 100K_0402_5% R1125
R829 2.2K_0402_5%
Place close pin A21 <16,35> SIO_SLP_S5#
BEEP B19 GPIO031/GPTP-OUT2/BCM_E_DAT A59 SYSPWR_PRES 1 2 HOST_DEBUG_RX 2 1
<30> BEEP GPIO030/GPTP-IN2/BCM_E_INT# SYSPWR_PRES +3.3V_ALW2
100K_0402_5%
1 2 GPU_SMBCLK BC_CLK_ECE1117 A20 R874 1K_0402_5% 10K_0402_5% R855
<47> BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK
1
R822 2.2K_0402_5% <47> BC_DAT_ECE1117 BC_DAT_ECE1117 B21 A64 ACAV_IN
A19 GPIO046/LSBCM_D_DAT VCI_OVRD_IN A60 ACAV_IN <68,69>
BC_INT#_ECE1117 ALWON
<47> BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# VCI_OUT ALWON <61>
1 2 MSDATA B67 POWER_SW_IN#
VCI_IN0#
R876
R869 10K_0402_5% SIO_EXT_SMI# A6 A63 DOCK_PWR_SW#
1 2 <15,19> SIO_EXT_SMI# A27 GPIO011/nSMI/GANG_DATA0 VCI_IN1# B63 1 2
PCH_ALW_ON SIO_RCIN# LAT_ON_SW# R866 close to U51 at least 250mils THERMATRIP3#
2
R880 100K_0402_5% <20> SIO_RCIN# IRQ_SERIRQ A28 GPIO061/LPCPD# VCI_IN2# B68 VCI_IN3# 8.2K_0402_5% R52
1 2 DOCK_POR_RST# <18,35,45> IRQ_SERIRQ PCH_PLTRST#_EC B30 SER_IRQ VCI_IN3#
<16,35,37,38,39,45> PCH_PLTRST#_EC A29 LRESET# B51 1 2
R881 100K_0402_5% CLK_PCI_MEC +PECI_VREF +1.05V_RUN
1 2 <17> CLK_PCI_MEC B31 PCI_CLK VREF_PECI A48 1 2
EN_INVPWR LPC_LFRAME# PECI_EC_R @ R866 0_0402_5%
<18,35,37,45> LPC_LFRAME# LFRAME# PECI_DAT PECI_EC <7>
0.1U_0402_25V6
R882 100K_0402_5% LPC_LAD0 A30 R952 43_0402_5% 1
<18,35,37,45> LPC_LAD0 B32 LAD0
LPC_LAD1
<18,35,37,45> LPC_LAD1 LAD1
C740
LPC_LAD2 A31 B13 REM_DIODE1_N C285 1 2 2200P_0402_50V7K
<18,35,37,45> LPC_LAD2 LAD2 DN1-THERM
1 2 RESET_OUT# LPC_LAD3 B33 A13 REM_DIODE1_P
<18,35,37,45> LPC_LAD3 LAD3 DP1-VREF_T 2
@ R843 8.2K_0402_5% CLKRUN# A32 B14 REM_DIODE2_N C283 1 2 2200P_0402_50V7K
1 2 <16,35,45> CLKRUN# A33 CLKRUN# DN2 A14
CPU1.5V_S3_GATE SIO_EXT_SCI# REM_DIODE2_P
<20> SIO_EXT_SCI# GPIO100/NEC_SCI DP2 A15
R889 100K_0402_5% VGA_THERMDN C287 1 2 2200P_0402_50V7K
1 2 PCH_RSMRST# MEC_XTAL1 A61 DN3 B16 VGA_THERMDP
R892 10K_0402_5% MEC_XTAL2 2 1 MEC_XTAL2_R A62 XTAL1 DP3 A16 REM_DIODE4_N C286 1 2 2200P_0402_50V7K
1 2 A_ON @ R1068 B62 XTAL2 DN4 B17 REM_DIODE4_P
<45> EC_32KHZ_ECE5048 GPIO160/32KHZ_OUT DP4 B15
R424 47K_0402_5% 0_0402_5% C283, C285, C286, C287 Place near U51
VIN A17 VSET_5075 VGA_THERMDN
GPIO MAP 1.8 VSET A12 VGA_THERMDN <50>
VCP VCP <68> VGA_THERMDP
VCP B34 VGA_THERMDP <50>
THERMATRIP2#
THERMTRIP2# A2 THERMATRIP3#
GPIO002/THERMTRIP3# B29 THSEL_STRAP THERMATRIP3# <50>
+3.3V_ALW
VSS_ADC
GPIO024/THSEL_STRAP
VSS_RO
VR_CAP
A46 PROCHOT#_EC
32 KHz Clock
H_VSS
PROCHOT_IN#/PROCHOT_IO#
AGND
CLK_PCI_MEC B61 V_SYS_R 1 2 V_SYS <68>
VSS
V_ISYS R392 4.7K_0402_5%
EP
1
100K_0402_5%
10_0402_1%
1
R920
@ R885
MEC5075-LZY_DQFN132_11X11~D
B66
B11
B60
+VR_CAP B12
B54
B18
C1
MEC_XTAL1 1 2 MEC_XTAL2
C290 Place near U51.A48
15mil PECI_EC_R 1 2 Channel Location
2
4.7P_0402_50V8C
27P_0402_50V8J
27P_0402_50V8J
Y6 @ C290 47P_0402_50V8J
2
32.768KHZ 9PF +-20PPM CM31532768DZCT

1 1 DP1/DN1 CPU
4.7U_0603_6.3V6K
1
C743
C741
JTAG_RST# 1
@ C747
2 2 DP2/DN2 DIMM
C779
Need creat symbol
1
2 THSEL_STRAP 1 2
2
1U_0402_6.3V6K
R1069 1K_0402_5%
DP3/DN3 VGA
1
1
JTAG1 CONN@
@SHORT PADS~D
100_0402_1%
1
@
Place close pin A29 ESR <2ohms

C735
R836
DP4/DN4 V.R
B 2 B
1: Channel 1 will provide Thermistor Readings
2
2
0: Channel 1 will provide Diode Readings

2
+3.3V_ALW +3.3V_ALW +3.3V_ALW +3.3V_ALW +3.3V_RUN

R875 C744 REV
10K_0402_5%
240K 4700p X00
1
1K_0402_5%
1K_0402_5%
10K_0402_5%
1
1
49.9_0402_1%
R799
130K 4700p X01
1
8
7
6
5
+3.3V_ALW
R875
R871
R872
R864
VSET_5075 RPH2
33K 4700p X02
0.1U_0402_25V6
10K_8P4R_5%
2
1.24K_0402_1%
4.3K 4700p ***

2
2
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
1 RUNPWROK
2
1
2
3
4
R407
@ R850
4700P_0402_25V7K
JDEG2 BOARD_ID SYSTEM_ID FWP#
2K 4700p ***
C284
R847
R848
R849
L2N7002WT1G_SC-70-3
1
1
1
2 JTAG_TDI 4700P_0402_25V7K D
2
* 1K 4700p A00 1
2
2
10K_0402_5%
Q45
3 JTAG_TMS 1 2
<48> RUN_ON_ENABLE#
2
C742
4 JTAG_CLK G
4
C744
@ R879
5 JTAG_TDO S
3
11 5 6 MSCLK 2
12 G1 6 7 MSDATA 2
1
G2 7 8 HOST_DEB_TX 1 2 HOST_DEBUG_TX
8 9 @ R853 0_0402_5%
9 EC5048_TX <37,45>
Rest=953 , Tp=88 degree 10
10
TYCO_1-2041070-0~D BOARD_ID rise time is measured from 5%~68%. CHIPSET_ID for BID function
CONN@
+3.3V_ALW
Place under CPU DP4/DN4 for Skin on Q3, place Q3 close to Vcore VR choke. JFAN1
Place C8 close to the Q1 as possible REM_DIODE4_N
+5V_RUN
1
1
100P_0402_50V8J
8.2K_0402_5%
REM_DIODE1_P +3.3V_RUN R30 1 2 10K_0402_5% FAN1_TACH_FB 2

2
1
100P_0402_50V8J
R51
1 R38 1 2 10K_0402_5% FAN1_PWM 3

3
1
3
@ C8
@ C16
RB751V40_SC76-2
22U_0805_6.3V6M
4
E
2 C
4
1
2 2 5
B
1 G5
D1
C7
B 6
E 2 C G6
3
1 Q1 ACES_50273-0040N-001
MMBT3904WT1G_SC70-3~D 2 CONN@
2
REM_DIODE1_N REM_DIODE4_P THERMATRIP2#
A Q3 A
+VCCIO_OUT
PMST3904_SOT323-3~D
MMBT3904WT1G_SC70-3~D
0.1U_0402_25V6
1
C
1 2 2
DP2/DN2 for SODIMM on Q2, place Q2 close to SODIMM and C9 close to Q2 1
Q4
C18
R55 2.2K_0402_5% B
REM_DIODE2_P E When 5075 solution use PWM FAN
3
2
100P_0402_50V8J
1
1
@ C9
C
2
B
2 <7> H_THERMTRIP#
E
3
Q2
REM_DIODE2_N
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PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MEC5075
1.0
5 4 3 2 1
5 4 3 2 1
Touch Pad +3.3V_TP MDC

1 2
+3.3V_RUN
@ R1161
1 2
0_0603_5% MDC CONN. H=5.5, Pitch=0.8
+3.3V_ALW
+3.3V_TP @ R1162 0_0603_5%
JMDC1 ACES_50124-0127N-001
+3.3V_ALW_PCH
JTP1 1 2
GND1 RES0 W=20 mil
4.7K_0402_5%
4.7K_0402_5%
1 <15> PCH_AZ_MDC_SDOUT PCH_AZ_MDC_SDOUT 3 4
1 IAC_SDATA_OUT RES1
1
D TP_CLK 2 5 6 D
2 GND2 3.3V
R903
R902
4.7U_0603_6.3V6K
0.1U_0402_25V6
TP_DATA 3 <15> PCH_AZ_MDC_SYNC 7 8
4 3 1 2 MDC_SDIN 9 IAC_SYNC GND3 10
4 <15> PCH_AZ_MDC_SDIN1 IAC_SDATA_IN GND4
+3.3V_TP 5 15MDC@ RH362 33_0402_5% PCH_AZ_MDC_RST1# 11 12 PCH_AZ_MDC_BITCLK 1
<15> 1
PS2_DAT_TS 6 5 9 IAC_RESET# IAC_BITCLK
2
2
6 G1
C718 15MDC@
C717 @
PS2_CLK_TS 7 10
1 2 TP_DATA 8 7 G2
GND
GND
GND
GND
GND
GND
<46> DAT_TP_SIO 8
2
2 2
@ R1163 0_0603_5%
1 2 TP_CLK PS_HPF05052-081000R
<46> CLK_TP_SIO
@ R1164 0_0603_5% CONN@ CONN@
13
14
15
16
17
18
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
D37
1 1 1 1
C752 @
C751 @
C750 @
C749 @
+3.3V_TP
@
2 2 2 2
0.1U_0402_25V6
15MDC@ Q44
1
L2N7002WT1G_SC-70-3
1
C755
1 3 PCH_AZ_MDC_RST1# @ C677
S
<15> PCH_AZ_MDC_RST#
10P_0402_50V8J
100K_0402_5%
+5V_ALW PCH_AZ_MDC_BITCLK 2 1 BITCLK_TERM 1 2
1
2 @ @ R753 10_0402_5%
G
2
10K_0402_5%
R751
15MDC@
PCH_AZ_MDC_SDOUT 2 1 SDOUT_TERM 1 2
1
@ R754 10_0402_5%
R752
15MDC@
@ C678
Place close to JTP1 10P_0402_50V8J
2
2
<45> MDC_RST_DIS#
1 2
C
+5V_ALW RSMRST# +3.3V_ALW_PCH +3.3V_ALW
@ R1623 0_0402_5%
+3.3V_ALW_PCH
C
+3.3V_ALW
Keyboard Pitch: 1.0
10K_0402_5%
10K_0402_5%
8.2K_0402_5%
1
2
33_0402_5%
@ C288
R1629
R1622
R1630
R1624
1 2 JKB1
1
0.1U_0402_25V6 <20> KB_DET# PS2_CLK_TS 2 1
@ PS2_DAT_TS 3 2
2
1
U8 3
5
+3.3V_ALW +5V_RUN 4
+3.3V_ALW 4
1 5
P
<46> PCH_RSMRST# B +5V_RUN 5
0.1U_0402_25V6
0.1U_0402_25V6
1 4 1 2 PCH_RSMRST#_Q <15,16> 6
VCC 3 RSMRST# 2 O @ R1655 0_0402_5% <46> BC_INT#_ECE1117 7 6
RESET# A 1 1 <46> BC_DAT_ECE1117 7
G
0.01U_0402_16V7K
C756
C758
2 8
GND 8
10K_0402_5%
1 U9 9
<46> BC_CLK_ECE1117
3
9
2
TC7SH08FU_SSOP5~D 10
2 2 10
C289
R1636
RT9818A-44GU3_SC70-3~D @ @
11
2 12 GND
GND
1
ACES_51524-01001-003
CONN@
Place close to JKB1
normal trace 50ohm

B
LID SW power 20mil PITCH 1.0 B
+3.3V_ALW
U1
SNIFFER BOARD
2
VDD 1
I/O Borad C1
1
<24,45> LID_CL#
LID_CL# 3
OUTPUT
GND
<45> WIRELESS_ON#/OFF
1
JSF1
1
2
0.1U_0402_16V4Z 3 2
2 AH180-WG-7_SC59-3~D 4 3
E-T_1001K-F30C-02L 5 4
WIRELESS_ON/OFF#: 6 G1
31 32 LOW: ON (Default) G2
GND GND PS_HPF10052-04M000R
29
29 30
30 +5V_RUN
Dual-lay Hold Switch Sensor HIGH: OFF CONN@
27 28
25 27 28 26
RED_CRT 23 25 26 24 VOL_UP_LED
<25> RED_CRT 23 24 VOL_UP_LED <24>
21 22
GREEN_CRT 19 21 22 20 VOL_DOWN_LED
<25> GREEN_CRT 19 20 VOL_DOWN_LED <24>
17 18
<25> BLUE_CRT
BLUE_CRT 15 17
15
18
16
16 VOL_MUTE_WHITE_LED
+5V_ALW
VOL_MUTE_WHITE_LED <24>
+5V_ALW (PITCH 0.5) Right side LED
13 14 JLED2
DAT_DDC2_CRT 11 13 14 12 VOL_MUTE 1
<25> DAT_DDC2_CRT 11 12 VOL_MUTE <46> 1
0.1U_0402_25V6
CLK_DDC2_CRT 9 10 VOL_DOWN# BATT_YELLOW# 2
<25> CLK_DDC2_CRT 9 10 VOL_DOWN# <46> <24> BATT_YELLOW# 2
7 8 VOL_UP# 1 BATT_WHITE# 3
7 8 VOL_UP# <46> <24> BATT_WHITE# 3
C1004
<25> HSYNC_BUF HSYNC_BUF 5 6 VOL_MUTE_YELLOW_LED# SATA_LED 4
5 6 VOL_MUTE_YELLOW_LED# <24> <24> SATA_LED 4
VSYNC_BUF 3 4 WLAN_LED 5
<25> VSYNC_BUF 3 4 <24> WLAN_LED 5
1 2 6
1 2 @ 2 6 7
JBTB1 GND 8
A
CONN@ GND A
PS_HPF05052-061000R
Close to JLED2 CONN@
+5V_RUN +5V_ALW
0.1U_0402_25V6
0.1U_0402_25V6
1 1 DELL CONFIDENTIAL/PROPRIETARY
C1001
C998
PROPRIETARY NOTE:
2 2 Title
@ THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
@
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Int KB/TP/BT/RSMRST/MDC
www.Vinafix.vn
1.0
Close to JBTB1.28,30 Close to JBTB1.17 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD LA-9411P
5 4 3 2 1
5 4 3 2 1
SI4164DY
VDS RDS(on) ID(A)
30 0.0032ohm at VGS=10V 30A
DC/DC Interface 30 0.0039ohm at VGS=4.5V 26.3A
+1.05V_RUN Source
Power Control for +3.3V_ALW_PCH +3.3V_ALW_PCH +3.3V_ALW2
+PWR_SRC_S
+1.05V_M Q63
SI4164DY-T1-GE3_SO8~D +1.05V_RUN
8 1
1
U103 7 2
10U_0603_6.3V6M
D 1 14 1 2 R930 6 3 D
+3.3V_ALW VIN1 VOUT1
1
@
2 13 C760 10U_0603_6.3V6M 330K_0402_5% 5 1
VIN1 VOUT1
C772
R931
3 12 1 2 R909 20K_0402_5%
<46,60> PCH_ALW_ON
4
ON1 CT1 C465 470P_0402_50V7K 100K_0402_5% 1.05V_RUN_ENABLE
4 11 2
+5V_ALW
2
VBIAS GND
3
1M_0402_5%
100P_0402_50V8J
5 10 1 2
<66,67> DGPU_PWR_EN ON2 CT2
1
C476 470P_0402_50V7K
Q52B
R1611
6 9 1
VIN2 VOUT2 +3.3V_RUN_GFX
7 8 RUN_ON_ENABLE# 5
VIN2 VOUT2 <46> RUN_ON_ENABLE#
C773
1
10U_0603_6.3V6M
C771
15
2
GPAD 2
6
2 1 2 RUN_ON_EN
<11,16,35,39,40,45,64,66> SIO_SLP_S3#
Q52A
@ R735 0_0402_5%
Power Control for +3.3V_RUN_GFX <39,45,64> RUN_ON
1
@ R744
RUN_ON_EN
2
0_0402_5%
2
<39> RUN_ON_EN
1
C
Power Control for +5V_RUN +5V_RUN
Discharge Circuit
C
+5V_ALW
U105
1 14 1 2
2 VIN1 VOUT1 13 @ C761 10U_0805_10V4Z
VIN1 VOUT1 +1.35V_CPU_VDDQ
RUN_ON_EN 3 12 1 2 +0.675V_DDR_VTT
ON1 CT1 C487 470P_0402_50V7K
1
4 11
VBIAS GND R926 @
1
5 10 1 2 220_0402_5%
<32,45> MODC_EN ON2 CT2 C488 470P_0402_50V7K R927 @
1
6 9 22_0603_5%
2
R512 7 VIN2 VOUT2 8
+1.35V_CPU_VDDQ_CHG
VIN2 VOUT2 +5V_MOD
100K_0402_5%
2
15
GPAD
10U_0805_10V6K
2
+DDR_CHG
TPS22966DPUR_SON14_2X3~D 1
C423
Power Control for +5V_MOD 2

@
L2N7002WT1G_SC-70-3
L2N7002WT1G_SC-70-3
@ @
1
D D
Q71
Q72
2 RUN_ON_ENABLE# 2
<7,11> RUN_ON_CPU1.5VS3#
G G
S S
3
B B
Power Control for +3.3V_M U102

+3.3V_M
C454 @
10U_0603_6.3V6M
+1.05V_RUN
1 14 1 2
+3.3V_ALW VIN1 VOUT1
1
2 13
VIN1 VOUT1 @ R925
1 2 3 12 1 2 39_0402_5%
<16,35,45,63> SIO_SLP_A# ON1 CT1
@ R1615 0_0402_5% C455 470P_0402_50V7K
1 2 4 11
<46,63> A_ON +5V_ALW
2
@ R1616 0_0402_5% VBIAS GND
5 10 1 2
+1.05V_RUN_CHG
<16,45> SIO_SLP_LAN# ON2 CT2 C456 470P_0402_50V7K
6 9
7 VIN2 VOUT2 8
VIN2 VOUT2 +3.3V_LAN
1
10U_0603_6.3V6M
15
Power Control for +3.3V_LAN GPAD

C475
2
L2N7002WT1G_SC-70-3
@
1
D
Q70 @
RUN_ON_ENABLE# 2
G
S
3
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
POWER CONTROL
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-9411P
5 4 3 2 1
5 4 3 2 1
UV1A
UV1D
PART 1 0F 9
PART 7 0F 9
PEG_CTX_GRX_P[0..7]
<6> PEG_CTX_GRX_P[0..7]
AK27 GPU_PWM @ RV63 1 210K_0402_5%
PEG_CTX_GRX_N[0..7] RSVD/VARY_BL
AJ27 GPU_PANEL_ON @ RV62 1 210K_0402_5%
<6> PEG_CTX_GRX_N[0..7] RSVD/DIGON
PEG_CTX_GRX_P0AA38 Y33 PEG_CRX_GTX_C_P0
PEG_CRX_GTX_P[0..7] PCIE_RX0P PCIE_TX0P LVDS CONTROL
PEG_CTX_GRX_N0 Y37 Y32 PEG_CRX_GTX_C_N0
<6> PEG_CRX_GTX_P[0..7] PCIE_RX0N PCIE_TX0N
PEG_CRX_GTX_N[0..7]
<6> PEG_CRX_GTX_N[0..7]
PEG_CTX_GRX_P1 Y35 W33 PEG_CRX_GTX_C_P1 AK35
PCIE_RX1P PCIE_TX1P TXCBP_DPB3P
PEG_CTX_GRX_N1 W36 W32 PEG_CRX_GTX_C_N1 AL36
PCIE_RX1N PCIE_TX1N TXCBM_DPB3N
D AJ38 D
TX3P_DPB2P
PEG_CTX_GRX_P2 W38 U33 PEG_CRX_GTX_C_P2 AK37
PCIE_RX2P PCIE_TX2P TX3M_DPB2N
PEG_CRX_GTX_P0 15G@ CV1 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P0 PEG_CTX_GRX_N2 V37 U32 PEG_CRX_GTX_C_N2
PCIE_RX2N PCIE_TX2N
PEG_CRX_GTX_N0 15G@ CV2 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N0 AH35
TX4P_DPB1P
AJ36
TX4M_DPB1N
PEG_CRX_GTX_P1 15G@ CV4 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P1 PEG_CTX_GRX_P3 V35 U30 PEG_CRX_GTX_C_P3
PCIE_RX3P PCIE_TX3P
PEG_CRX_GTX_N1 15G@ CV3 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N1 PEG_CTX_GRX_N3 U36 U29 PEG_CRX_GTX_C_N3 AG38
PCIE_RX3N PCIE_TX3N TX5P_DPB0P
AH37
TX5M_DPB0N
PEG_CRX_GTX_P2 15G@ CV5 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P2
PEG_CRX_GTX_N2 15G@ CV6 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N2 PEG_CTX_GRX_P4 U38 T33 PEG_CRX_GTX_C_P4 AF35
PCIE_RX4P PCIE_TX4P NC#AF35
PEG_CTX_GRX_N4 T37 T32 PEG_CRX_GTX_C_N4 AG36
LVTMDP
PCIE_RX4N PCIE_TX4N NC#AG36
PEG_CRX_GTX_N3 15G@ CV8 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N3
PEG_CTX_GRX_P5 T35 T30 PEG_CRX_GTX_C_P5
PCIE_RX5P PCIE_TX5P
PEG_CRX_GTX_P4 15G@ CV9 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P4 PEG_CTX_GRX_N5 R36 T29 PEG_CRX_GTX_C_N5
PCIE_RX5N PCIE_TX5N
PEG_CRX_GTX_N4 15G@ CV10 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N4 AP34
TXCAP_DPA3P
AR34
TXCAM_DPA3N
PEG_CRX_GTX_P5 15G@ CV11 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P5 PEG_CTX_GRX_P6 R38 P33 PEG_CRX_GTX_C_P6
PCIE_RX6P PCIE_TX6P
PEG_CRX_GTX_N5 15G@ CV12 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N5 PEG_CTX_GRX_N6 P37 P32 PEG_CRX_GTX_C_N6 AW37
PCIE_RX6N PCIE_TX6N TX0P_DPA2P
AU35
TX0M_DPA2N
PEG_CRX_GTX_N6 15G@ CV15 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N6 PEG_CTX_GRX_P7 P35 P30 PEG_CRX_GTX_C_P7 AR37
PCIE_RX7P PCIE_TX7P TX1P_DPA1P
PEG_CTX_GRX_N7 N36 P29 PEG_CRX_GTX_C_N7 AU39
PCIE_RX7N PCIE_TX7N TX1M_DPA1N
PEG_CRX_GTX_N7 15G@ CV17 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N7 AP35
TX2P_DPA0P
N38 N33 AR35
NC NC TX2M_DPA0N
M37 N32
NC NC
PCI EXPRESS INTERFACE

AN36
NC AP37
M35 N30 NC
NC NC
L36 N29
NC NC
C C
L38 L33 15G@ MARS-PRO_FCBGA962~D
NC NC
K37 L32
NC NC
K35 L30
NC NC
J36 L29
NC NC
J38 K33
NC NC
H37 K32
NC NC
H35 J33
NC NC
G36 J32
NC NC
G38 K30
NC NC
F37 K29
NC NC
F35 H33
NC NC
E37 H32
NC NC
CLOCK
AB35
<17> CLK_PCIE_VGA PCIE_REFCLKP
AA36
<17> CLK_PCIE_VGA# PCIE_REFCLKN
CALIBRATION
B Y30 1 2 B
PCIE_CALR_TX +VGA_PCIE
15G@ RV296 1.69K_0402_1%
1 2 AH16 Y29 1 2 +VGA_PCIE
TEST_PG PCIE_CALR_RX
15G@ RV25 1K_0402_5% 15G@ RV298 1K_0402_1%
DGPU_PEX_RST 1 2 AA30
DGPU_PEX_RST_R
PERSTB
@ RV18 0_0402_5%
15G@
MARS-PRO_FCBGA962~D
don't connect to PCH
+3.3V_ALW
+3.3V_RUN
CV87 15G@
0.1U_0402_10V6K
1
1
+3.3V_RUN_GFX
RV33
1
100K_0402_5% 15G@
15G@ 2 RV29
2.2K_0402_5%
2
1
P
<16> DGPU_HOLD_RST#
2
A B 4 DGPU_PEX_RST A
O 15G@ DGPU_PEX_RST <50>
<16> PLTRST_GPU# 2
A
G
74AHC1G09GW_TSSOP5~D
3
UV14
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MARX-PCIE
1.0
www.Vinafix.vn
5 4 3 2 1
5 4 3 2 1
RECOMMENDED SETTINGS
CONFIGURATION STRAPS ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET X = DESIGN DEPENDANT
NA = NOT APPLICABLE
RECOMMENDED
STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS SETTINGS
0: 50% swing
+3.3V_RUN_GFX TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 1: Full swing X
UV1B
PART 2 0F 9 0: disable
2
TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS 1: enable X
MUTI GFX RV84
GENLK_CLK AD29 GENLK_CLK AU24 10K_0402_5% Advertises PCIE speed 0: 2.5GT/s
NC
GENLK_VSYNC AC29 GENLK_VSYNC AV23 @ Populate RV84 for Disable MLPS RSVD GPIO2 when compliance test 1: 5GT/s 0
NC
Populate RV111 for Enable MLPS
1
AT25 TS_FDO
NC
D AJ21 SWAPLOCKA AR24 RSVD GPIO8 RESERVED 0 D
NC
2
AK21 DPA
SWAPLOCKB
AU26 RV111
NC
AV25 10K_0402_5% BIF_VGA DIS GPIO9 VGA ENABLED 0
NC
15G@
AR8 NC AT27
NC
1
AU8 NC AR26 RSVD GPIO21 RESERVED 0
NC
T115 DBG_CNTL0 AP8 DBG_CNTL0
AW8 NC AR30 0: disable
NC
AR3 NC AT29 BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 1: enable X
NC
AR1 NC
T109 DVPDATA_0 AU1 DBG_DATA0 AV31
NC
DVPDATA_1 AU3 AU30 ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT XXX
STRAPS T110
T111 DVPDATA_2 AW3
DBG_DATA1
DBG_DATA2
DPB NC
<45> GPU_PWR_LEVEL GPU_PWR_LEVEL 1 2 GPU_HOT#
GPU_HOT# <66>
T91 DBG_DATA3 AP6 DBG_DATA3 AR32 @ RV76 0_0402_5%
NC
+3.3V_RUN_GFX T92 DBG_DATA4 AW5 DBG_DATA4 AT31 VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0
NC
T93 DBG_DATA5 AU5 DBG_DATA5
1 2 GPU_PSI# T94 DBG_DATA6 AR6 DBG_DATA6 AT33
NC
15G@ RV79 10K_0402_5% T95 DBG_DATA7 AW6 DBG_DATA7 AU32 RSVD H2SYNC 0
NC +VCCIO_OUT
PMST3904_SOT323-3~D
T96 DBG_DATA8 AU6 DBG_DATA8
0.1U_0402_25V6
T97 DBG_DATA9 AT7 DBG_DATA9 AU14
NC
1
T98 DBG_DATA10 AV7 DBG_DATA10 AV13 C RSVD GENERICC 0
NC
1 2 GPU_GPIO21 T99 DBG_DATA11 AN7 DBG_DATA11 1 2 2 1
QV8
CV358
@ RV102 10K_0402_5% T100 DBG_DATA12 AV9 DBG_DATA12 AT15 @ RV78 2.2K_0402_5% B AUD[1] AUD[0]
NC
T101 DBG_DATA13 AT9 DBG_DATA13 AR14 E AUD[1] HSYNC 0 0 No audio function 11
NC
3
T102 DBG_DATA14 AR10 DBG_DATA14 @ 0 1 Audio for DisplayPort and HDMI if dongle is detected
1 2 GPU_HOT# DBG_DATA15 AW10 DPC AU16 2 AUD[0] VSYNC 1 0 Audio for DisplayPort only
T103 DBG_DATA15 NC @
15G@ RV103 4.7K_0402_5% T104 DBG_DATA16 AU10 DBG_DATA16 AV15 1 1 Audio for both DisplayPort and HDMI
NC
T105 DBG_DATA17 AP10 DBG_DATA17
DBG_DATA18 AV11 AT17
T106
T107 DBG_DATA19 AT11
DBG_DATA18
DBG_DATA19
NC
NC
AR16
<7,46,65,68,69> H_PROCHOT#
AMD RESERVED CONFIGURATION STRAPS
1 2 GENLK_CLK T108 DBG_DATA20 AR12 DBG_DATA20 ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
@ RV95 10K_0402_5% T112 DBG_DATA21 AW12 DBG_DATA21 AU20
NC RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
1 2 GENLK_VSYNC T113 DBG_DATA22 AU12 DBG_DATA22 AT19
NC
@ RV96 10K_0402_5% DBG_DATA23 AP12
T114 DBG_DATA23
AT21
NOT CONFLICT DURING RESET
NC
BT0613: GENLK_CLK and CENLK_VSYNC if not use let it NC, AR20
NC
do not stuff RV95 and RV96. GPIO21 H2SYNC GENERICC GPIO2 GPIO8
AJ23 DPD AU22
SMBCLK SMBus NC
AH23 SMBDATA AV21
NC
AT23 PS_3_[3:2:1] for MEMID RV241_PU RV242_PD CV341
NC
AR22
NC
AK26 SCL
001: Hynix H5GQ2H24AFR (1.35V) 8.45K 2K NC
1 2 GPU_7_BLON AJ26 I2C
C SDA C
@ RV113 10K_0402_5% 010: Samsung K4G20325FD (1.35V) 4.53K 2K NC
AD39 GPU_VGA_R 1 2 GPU_PWR_LEVEL
R
GENERAL PURPOSE I/O AD37 @ RV54 0_0402_5% When use Samsung VRAM SA00005B70L, please chnage this RV241 to 4.53Kohm (SD03445318L).
AH20 AVSSN
GPU_PSI# GPIO_0 LOW Low Performance
<66> GPU_PSI# +1.8V_RUN_GFX +1.8V_RUN_GFX +1.8V_RUN_GFX +1.8V_RUN_GFX
T123 GPU_GPIO1 AH18 GPIO_1 AE36 GPU_VGA_G 1 2
G
T124 GPU_GPIO2 AN16 GPIO_2 AD35 @ RV70 0_0402_5% HIGH High Performance
AVSSN
8.45K_0402_1%
8.45K_0402_1%
1
1
AF37 GPU_VGA_B 1 2
8.45K_0402_1%
8.45K_0402_1%
B
1
1 2 AH17 AE38 @ RV71 0_0402_5%
15G@ RV244
15G@ RV237
VDDCI_VID GPU_HOT# GPIO_5_AC_BATT
@ RV64 0_0402_5% AJ17 AVSSN
RV239
15G@ RV241
GPU_GPIO6 GPIO_6_TACH
AK17 DAC1 AC36 1 2
GPU_7_BLON GPIO_7_BLON GPU_VGA_HSYNC
GPU_ROMSO AJ13 HSYNC AC38 GPU_VGA_VSYNC @ RV72 1 20_0402_5%
T118 GPIO_8_ROMSO VSYNC
2
GPU_ROMSI AH15 @ RV73 0_0402_5% @
T119 GPIO_9_ROMSI
2
GPU_VID_4 1 2 GPU_GPIO10 AJ16 GPIO_10_ROMSCK
<66> GPU_VID_4
@ RV40 0_0402_5% T125 GPU_GPIO11 AK16 GPIO_11 AB34 GPU_DAC_RESET 1 2 PS_0 PS_1 PS_2 PS_3
GPU_VID_0 1 2 GPU_GPIO12 AL16 RSET @ RV69 499_0402_1%
<66> GPU_VID_0 GPIO_12
@ RV2 0_0402_5% GPU_GPIO13 AM16 AD34
0.082U_0402_16V7K
0.68U_0402_10V
0.68U_0402_10V
0.68U_0402_10V
2K_0402_1%
T127 GPIO_13 +1.8V_RUN_GFX
2K_0402_1%
2K_0402_1%
AVDD
1
GPU_VID_2 1 2 GPU_GPIO14 AM14 AE34
CV117
CV226
4.75K_0402_1%
0.1U_0402_10V6K
CV116
1 1 1 1
1U_0402_6.3V6K
10U_0603_6.3V6M
<66> GPU_VID_2 T128 GPIO_14_HPD2 AVSSQ
CV341
@ RV38 0_0402_5% GPU_GPIO15 AM13
15G@ RV243
CV342
15G@ RV238
CV357
15G@ CV340
15G@ RV242
1 1 1
15G@ RV240
GPIO_15_PWRCNTL_0
GPU_VID_1 1 2 GPU_GPIO16 AK14 GPIO_16 AC33
<66> GPU_VID_1 VDD1DI
@ RV37 0_0402_5% GPU_THERMAL_INT AG30 GPIO_17_THERMAL_INT AC34
GPU_GPIO19 AN14 VSS1DI 2 2 2 2
@ @ @
@
T129 GPIO_18_HPD3
2
2 2 2
@
THERMTRIP_VGA AM17 GPIO_19_CTF
GPU_VID_3 1 2 GPU_GPIO20 AL13 GPIO_20_PWRCNTL_1 V13
<66> GPU_VID_3 NC
@ RV39 0_0402_5% GPU_GPIO21 AJ14 GPIO_21 U13
NC
T120 GPU_ROMCSB AK13 GPIO_22_ROMCSB AF33
NC
GFX_CLK_REQ# 1 2 GFX_CLK_REQ#_R AN13 CLKREQB AF32
<17> GFX_CLK_REQ# NC
@ RV52 0_0402_5% AA29
NC
AG21
NC
T126 GPU_GPIO29 AG32 GPIO_29 AC32
NC
T138 GPU_GPIO30 AG33 GPIO_30 +1.8V_RUN_GFX
AC31
CV119
CV227
0.1U_0402_10V6K
CV118
1U_0402_6.3V6K
10U_0603_6.3V6M
NC_SVI2
AJ19 GENERICA AD30 1 1 1
NC_SVI2
AK19 GENERICB AD32
NC_SVI2
AJ20 GENERICC
AK20
@
GENERICD 2 2 2
@
AJ24 GENERICE_HPD4 Transmitter Power Saving Enable
AH26 GENERICF_HPD5 TX_PWRS_ENB GPIO0 0: 50% Tx output swing for mobile mode
AH24 GENERICG_HPD6 1: full Tx output swing (Default setting for Desktop)
+1.8V_RUN_GFX AM34 PS_0 PCI Express Transmitter De-emphasis Enable
PS_0
TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled for mobile mode
DBG_VREFG must close to UV1.AH13 AC30 CEC_1 1: Tx de-emphasis enabled (Defailt setting for desktop)
1
B RV68 15G@ AK24 HPD1 PS_1 AD31 PS_1 B

MLPS
499_0402_1%
2
DBG_VREFG AH13 AG31 PS_2 +3.3V_RUN_GFX

DBG_VREFG PS_2
1
1
RV66 15G@ CV115 15G@ BACO
249_0402_1% 0.1U_0402_10V6K 1 2 PX_EN AL21 PX_EN AD33 PS_3
PS_3
@ RV48 0_0402_5%
2
2
@
RV57
DEBUG DDC/AUX AM26
DDC1CLK 20K_0402_5%
AN26
DDC1DATA
3
E
TESTEN AD28 TESTEN
2
B
AM27 15G@ QV4 2
AUX1P
AL27 MMBT3906WT1G_SC70-3~D
AUX1N C
1
GPU_JTAG_TRSTB AM23 JTAG_TRSTB AM19 Change to SB000006J00 CPN THERMATRIP3#
DDC2CLK THERMATRIP3# <46>
GPU_JTAG_TDI AN23 JTAG_TDI AL19 RV59 15G@
DDC2DATA
GPU_JTAG_TCK AK23 JTAG_TCK 20K_0402_5%
PMST3904_SOT323-3~D
0.1U_0402_25V6
GPU_JTAG_TMS AL24 JTAG_TMS AN20 15G@
AUX2P
1
GPU_JTAG_TDO AM24 JTAG_TDO AM20 RV58 C 1
AUX2N
2
1 2 2
QV7 15G@
CV57 15G@
AL30 B
NC
1
AM30 DGPU_PEX_RST 1 2 2.2K_0402_5% E
NC <49> DGPU_PEX_RST
3
2
0.1U_0402_25V6
15G@ D71 RB751V40_SC76-2 RV56 15G@
1K_0402_5%
2
+3.3V_RUN_GFX THERMAL AL29 20K_0402_5%
NC 1
RV60 15G@
VGA_THERMDP AF29 DPLUS AM29
<46> VGA_THERMDP NC
CV53 @
VGA_THERMDN AG29 DMINUS
<46> VGA_THERMDN
1
AN21 C
NC
2
QV3 15G@
AM21 GPU_THERMAL_INT 1 2 1 2 2
NC
1
@
RV41 TS_FDO AK32 GPIO_28_FDO 15G@ RV53 47K_0402_5% RV55 47K_0402_5% B

15G@
0.01U_0402_16V7K
5.11K_0402_1% AK30 E
NC
3
100K_0402_5%
AL31 TS_A AK29 THERMTRIP_VGA 1 2
NC
2
15G@ RV47 47K_0402_5% 1
1
CV52 15G@
TESTEN On-die thermal sensor power. AJ30 GPU_VGA_DDCCLK 1 2
10mil AJ32
RV61 15G@
DDCVGACLK
+1.8V_RUN_GFX 1 2 TSVDD : 1.8V @ 13mA +TSVDD TSVDD AJ31 GPU_VGA_DDCDAT @ RV741 20_0402_5%
DDCVGADATA
1
LV16 15G@ BLM15BD121SN1D_0402 AJ33 TSVSS @ RV75 0_0402_5% 2 1

RV49 15G@ 15G@ RV104 10K_0402_5% 2
CV98
CV92
CV93
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V7K
1
1K_0402_5% 1 1 1
MARS-PRO_FCBGA962~D
2
15G@
15G@
15G@
A 2 2 2 15G@ A
+3.3V_RUN_GFX
1 2
TESTEN T139 RV77 @ 0_0402_5%
GPU_JTAG_TDO 15G@ RV141 2 1 10K_0402_5%
GPU_JTAG_TRSTB 15G@ RV97 2 1 10K_0402_5%
GPU_JTAG_TDI 15G@ RV86 2 1 10K_0402_5%
GPU_JTAG_TMS 15G@ RV87 2 1 10K_0402_5%
GPU_JTAG_TCK 15G@ RV88 2 1 10K_0402_5%
Need to discuss with ME place these parts in door.

PROPRIETARY NOTE:
Title
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MARX-GPIO,HDMI,DP,DAC
1.0
5 4 3 2 1
5 4 3 2 1
+1.8V_RUN_GFX
VDDR1 @ 1.5A at #51241 page 76 UV1E
+1.35V_MEM_GFX PART 5 0F 9
10mil (PCIE_VDDR : 1.8V @ 100mA)
0.01U_0402_16V7K
0.1U_0402_10V6K
VDDR1 @ 2A, GDDR5 1125MHz MEM I/O
10U_0603_6.3V6M
CV51
CV63
CV65
CV64
1U_0402_6.3V6K
AC7 AA31
VDDR1 NC
AD11 AA32 1 1 1 1
VDDR1 NC
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CV173
CV217
CV238
CV163
CV170
CV218
CV237
CV168
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
AF7 AA33
VDDR1 NC
1 1 1 1 1 1 1 1 AG10 AA34
VDDR1 NC
AJ7 W30
VDDR1 NC 2 2 2 2
15G@
15G@
15G@
15G@
AK8 Y31
VDDR1 NC
AL9 V28
2 2 2 2 2 2 2 2 VDDR1 NC_BIF_VDDC
15G@
15G@
15G@
15G@
15G@
15G@
15G@
15G@
D G11 W29 D
VDDR1 NC_BIF_VDDC +VGA_PCIE
G14 AB37
VDDR1 PCIE_PVDD
PCIE
G17
G20
VDDR1
G30
180mil
VDDR1 PCIE_VDDC
G23 G31 PCIE_VDDC : 0.95V @ 4.5A
VDDR1 PCIE_VDDC
10U_0603_6.3V6M
10U_0603_6.3V6M
CV66
CV67
CV68
CV69
CV70
CV71
CV72
CV73
CV74
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
G26 H29
VDDR1 PCIE_VDDC
G29 H30 1 1 1 1 1 1 1 1 1
VDDR1 PCIE_VDDC
H10 J29
VDDR1 PCIE_VDDC
J7 J30
VDDR1 follow Checklist_3-Power J9
VDDR1
VDDR1
PCIE_VDDC
PCIE_VDDC
L28
2 2 2 2 2 2 2 2 2
15G@
15G@
15G@
15G@
15G@
15G@
15G@
15G@
15G@
K11 M28
VDDR1 PCIE_VDDC
K13 N28
VDDR1 PCIE_VDDC
K8 R28
VDDR1 PCIE_VDDC
L12 T28
VDDR1 PCIE_VDDC
L16 U28
VDDR1 PCIE_VDDC +VGA_PCIE
L21
VDDR1
L23
L26
VDDR1
N27
60mil +VGA_PCIE : 0.95V @ 1.4A
VDDR1 BACO BIF_VDDC
L7 T27
VDDR1 BIF_VDDC +GPU_CORE
10U_0603_6.3V6M
CV114
CV113
1U_0402_6.3V6K
M11
VDDR1
N11 1 1
VDDR1
P7 AA15
VDDR1 CORE VDDC
R11 AA17
VDDR1 VDDC
U11 AA20
+1.8V_RUN_GFX +VDDC_CT VDDR1 VDDC 2 2
15G@
15G@
U7 AA22
VDDR1 VDDC
Y11 AA24
VDDR1 VDDC
15G@ LV19 (1.8V@13mA VDD_CT) Y7 AA27
VDDR1 VDDC
1 2 AB16
VDDC
0.1U_0402_10V6K
BLM15BD121SN1D_0402 AB18
VDDC
10U_0603_6.3V6M
CV56
CV55
CV54
1U_0402_6.3V6K AB21
VDDC AB23
1 1 1 VDDC AB26
C 10mil LEVEL
TRANSLATION
VDDC AB28 C
AF26 VDDC AC17
2 2 2 VDD_CT VDDC
15G@
15G@
15G@
AF27 AC20
VDD_CT VDDC
AG26 AC22
VDD_CT VDDC
AG27 AC24
VDD_CT VDDC AC27
+3.3V_RUN_GFX VDDC AD18
15G@ LV30
10mil I/O
VDDC AD21
1 2 +3.3V_RUN_GFX_VDDR3 (3.3V@25mA VDDR3) AF23 VDDC AD23
VDDR3 VDDC
BLM15BD121SN1D_0402 AF24 AD26
VDDR3 VDDC
10U_0603_6.3V6M
CV59
CV58
CV49
CV50
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AG23 AF17
VDDR3 VDDC
1 1 1 1 AG24 AF20
VDDR3 VDDC AF22
20mil DVP
VDDC AG16
AD12 VDDC AG18
2 2 2 2 VDDR4 VDDC
15G@
15G@
15G@
15G@
AF11
VDDR4
AF12 AH22
VDDR4 VDDC
AF13 AH27
VDDR4 VDDC AH28
VDDC M26
AF15 VDDC N24
+1.8V_RUN_GFX VDDR4 VDDC
AG11 R18
VDDR4 VDDC
15G@ LV20 AG13 R21
(1.8V@300mA VDDR4) VDDR4 VDDC
1 2 +1.8V_RUN_GFX_VDDR4 AG15 R23
VDDR4 VDDC
0.1U_0402_10V6K
BLM15BD121SN1D_0402 R26
VDDC
10U_0603_6.3V6M
CV62
CV61
CV60
1U_0402_6.3V6K
Change to 221ohm BEAD T17

VDDC T20
1 1 1 VDDC T22
VDDC T24
VDDC U16
2 2 2 VDDC
15G@
15G@
15G@
U18
VDDC U21
B VDDC U23 B
VDDC U26
VDDC V17
VDDC V20
VDDC V22
VDDC V24
VDDC V27
VDDC Y16
VDDC Y18
VDDC Y21
VDDC Y23
VDDC Y26
VDDC Y28 +GPU_CORE
VDDC
AA13
VDDCI AB13
VDDCI AC12
VDDCI AC15
VDDCI AD13
VDDCI AD16
VDDCI M15
VDDCI M16
GPU_VDD_SENSE/GPU_VSS_SENSE route as differetial pair VDDCI M18
VOLTAGE VDDCI M23
VDDCI
CORE I/O
SENESE N13
ISOLATED
AF28 VDDCI N15

GPU_VDD_SENSE FB_VDDC
<66> GPU_VDD_SENSE VDDCI N17
VDDCI N20
AG28 VDDCI N22
FB_VDDCI VDDCI R12
VDDCI R13
GPU_VSS_SENSE AH29 VDDCI R16
A <66> GPU_VSS_SENSE FB_GND VDDCI A
T12
VDDCI T15
VDDCI V15
VDDCI Y13
VDDCI
15G@ MARS-PRO_FCBGA962~D
PROPRIETARY NOTE:
Title
MARX-Power
www.Vinafix.vn
1.0
5 4 3 2 1
5 4 3 2 1
UV1G
PART 6 0F 9
AB39 A3
E39 GND GND A37
F34 GND GND AA16
F39 GND GND AA18
G33 GND GND AA2
G34 GND GND AA21
H31 GND GND AA23
H34 GND GND AA26
H39 GND GND AA28
J31 GND GND AA6 UV1F
D J34 GND GND AB12 D

K31 GND GND AB15 PART 8 0F 9
GND GND DP/TMDS/LVDS Transmitter Power
K34 AB17 +VGA_PCIE
K39 GND GND AB20 DP_VDDR DP_VDDC 0.95V@280mA per port
L31 GND GND AB22 AP31
GND GND DP_VDDC
0.1U_0402_10V6K
L34 AB24 AP32
GND GND DP_VDDC
10U_0603_6.3V6M
CV213
CV214
CV212
1U_0402_6.3V6K
M34 AB27 AN33
M39 GND GND AC11 DP_VDDC AP33
GND GND DP_VDDC 1 1 1
N31 AC13 AN24 AL33
N34 GND GND AC16 AP24 NC DP_VDDC AM33
P31 GND GND AC18 AP25 NC DP_VDDC AK33
P34 GND GND AC2 AP26 NC DP_VDDC AK34 2 2 2
P39 GND GND AC21 AU28 NC DP_VDDC AN31
R34 GND GND AC23 AV29 NC DP_VDDC
T31 GND GND AC26 NC
T34 GND GND AC28
T39 GND GND AC6 AP20 AP13
GND GND NC NC
0.1U_0402_10V6K
U31 AD15 AP21 AT13
GND GND NC NC
10U_0603_6.3V6M
CV204
CV211
CV206
1U_0402_6.3V6K
U34 AD17 AP22 AP14
V34 GND GND AD20 AP23 NC NC AP15
GND GND NC NC 1 1 1
V39 AD22 AU18
W31 GND GND AD24 AV19 NC
+1.8V_RUN_GFX
W34 GND GND AD27 NC DP GND
Y34 GND GND AD9 AN27 2 2 2
GND GND 1.8V @237 mA /link HDMI DP_VSSR
Y39 AE2 AH34 AP27
GND GND DP_VDDR DP_VSSR
0.1U_0402_10V6K
AE6 AJ34 AP28
GND DP_VDDR DP_VSSR
10U_0603_6.3V6M
CV201
CV203
CV198
1U_0402_6.3V6K
AF10 AF34 AW24
GND AF16 AG34 DP_VDDR DP_VSSR AW26
GND 1 1 1 DP_VDDR DP_VSSR
AF18 AM37 AN29
GND AF21 AL38 DP_VDDR DP_VSSR AP29
GND GND DP_VDDR DP_VSSR
AG17 AM32 AP30
F15 GND AG2 2 2 2 DP_VDDR DP_VSSR AW30
C F17 GND GND AG20 DP_VSSR AW32 C
F19 GND GND DP_VSSR AN17
F21 GND AG6 DP_VSSR AP16
F23 GND GND AG9 DP_VSSR AP17
F25 GND GND AH21 DP_VSSR AW14
F27 GND GND AJ10 DP_VSSR AW16
F29 GND GND AJ11 DP_VSSR AN19
F31 GND GND AJ2 DP_VSSR AP18
F33 GND GND AJ28 DP_VSSR AP19
F7 GND GND AJ6 DP_VSSR AW20
F9 GND GND AK11 CALIBRATION DP_VSSR AW22
G2 GND GND AK31 DP_VSSR AN34
G6 GND GND AK7 DP_VSSR AP39
H9 GND GND AL11 2 1 AW28 DP_VSSR AR39
J2 GND GND AL14 NC DP_VSSR AU37
RV42 150_0402_1%
J27 GND GND AL17 DP_VSSR AF39
J6 GND GND AL2 DP_VSSR AH39
J8 GND GND AL20 2 1 AW18 DP_VSSR AK39
K14 GND GND NC DP_VSSR AL34
RV43 150_0402_1%
K7 GND AL23 DP_VSSR AV27
L11 GND AL26 DP_VSSR AR28
L17 GND GND AL32 2 1 AM39 DP_VSSR AV17
L2 GND GND AL6 DP_CALR DP_VSSR AR18
RV44 150_0402_1%
L22 GND GND AL8 DP_VSSR AN38
L24 GND GND AM11 DP_VSSR AM35
L6 GND GND AM31 DP_VSSR AN32
M17 GND GND AM9 DP_VSSR
M22 GND GND AN11
M24 GND GND AN2
N16 GND GND AN30
N18 GND GND AN6
N2 GND GND AN8
B N21 GND GND AP11 B
N23 GND GND AP7
N26 GND GND AP9
N6 GND GND AR5
R15 GND GND B11
R17 GND GND B13
R2 GND GND B15
R20 GND GND B17
R22 GND GND B19
R24 GND GND B21
R27 GND GND B23
R6 GND GND B25
T11 GND GND B27
T13 GND GND B29
GND GND AMD recommended setting
T16 B31 MLPS Bit
T18 GND GND B33
GND GND strap R_PU R_PD C
T21 B7
T23 GND GND B9
GND GND PS0: 11001 RV243=8.45K RV201=2K CV335=NC
T26 C1
U15 GND GND C39
GND GND PS1: 11000 RV237=NC RV238=4.75K CV329=NC
U17 E35
U2 GND GND E5
GND GND PS2: 00000 RV239=NC RV240=4.75K CV331=0.68u
U20 F11
U22 GND GND F13
GND GND PS3: 11000 RV241=NC RV242=4.75K CV333=NC
U24
U27 GND GND
U6 GND
V11 GND AG22
V16 GND NC
V18 GND
V21 GND
V23 GND
A V26 GND A
W2 GND
W6 GND
Y15 GND
Y17 GND
Y20
Y22
GND
GND A39
Y24 GND VSS_MECH AW1
Y27 GND VSS_MECH AW39 PROPRIETARY NOTE:
GND VSS_MECH Title
MARX-DP Power,GND
www.Vinafix.vn
15G@ MARS-PRO_FCBGA962~D BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
1.0
5 4 3 2 1
5 4 3 2 1
D D
+1.8V_RUN_GFX
1.8V @ 100mA
2 1 +1.8V_MPLL_PVDD
LV17 15G@ BLM15BD121SN1D_0402
0.1U_0402_10V6K
CV216
CV219
CV215
10U_0603_6.3V6M
1U_0402_6.3V6K
Change to 221ohm BEAD UV1C
1 1 1
PART 9 0F 9
2 2 2
15G@
15G@
15G@
XTALOUT 1 2 XTALOUT_R
15G@ RV125 750_0402_5%
+1.8V_RUN_GFX AV33 XTALIN

XTALIN
1.8V @ 75mA RV100 15G@
2 1 +1.8V_SPLL_PVDD XTALIN
C LV18 15G@ BLM15BD121SN1D_0402 0.1U_0402_10V6K C
1M_0402_5%
CV221
CV222
CV220
10U_0603_6.3V6M
1U_0402_6.3V6K
1 1 1 YV1 15G@
AU34 XTALOUT_R 3 1
XTALOUT 3 1
1 GND GND 1
2 2 2
15G@
15G@
15G@
CV94 CV95
12P_0402_50V8J 12P_0402_50V8J
H7 15G@ 4 2 15G@
MPLL_PVDD 2 2
H8 MPLL_PVDD
+VGA_PCIE
0.95V @ 100mA AW34 27MHZ_10PF_7V27000050
XO_IN
2 1 +VGA_PCIE_SPLL_VDDC
LV21 15G@ BLM15BD121SN1D_0402 AM10
0.1U_0402_10V6K
SPLL_PVDD
PLLS/XTAL
CV224
CV225
CV223
10U_0603_6.3V6M
1U_0402_6.3V6K
1 1 1
AN9 SPLL_VDDC AW35
XO_IN2
2 2 2
15G@
15G@
15G@
AN10 SPLL_PVSS
AK10 CLKTESTA
CLKTESTA
AF30 NC_XTAL_PVDD AL10 CLKTESTB
CLKTESTB
AF31 NC_XTAL_PVSS
1
@ @
CV82 CV81
B 0.1U_0402_16V7K 0.1U_0402_16V7K B
2
1
route 50ohms single-ended/100ohms diff
@ @
RV46 RV45 and keep short
51.1_0402_1% 51.1_0402_1%
Debug only, for clock observation,
2
if not needed, DNI 5mil 5mil
A A
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MARX-PLL Power
1.0
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5 4 3 2 1
5 4 3 2 1
D D
GDDR5 CMD Mapping Table

UV1H
C C
DQA0_0[0..31] SI4164DY
DQA0_[0..31] <56> PART 3 0F 9
DQA1_[0..31]
<0..31> <32..63> Memory VDS RDS(on) ID(A)
DQA1_[0..31] <57> GDDR5/DDR3
DQA0_0 C37
DQA0_0 MAA0_0/MAA_0
G24 MAA0_0 CMD12 CMD28 RAS# 30 0.0032ohm at VGS=10V 30A
MAA0_[0..8] DQA0_1 C35 J23 MAA0_1 CMD15 CMD31 CAS# 30 0.0039ohm at VGS=4.5V 26.3A
MAA0_[0..8] <56> DQA0_1 MAA0_1/MAA_1
DQA0_2 A35 H24 MAA0_2 CMD5 CMD21 WE#
DQA0_2 MAA0_2/MAA_2
MAA1_[0..8] DQA0_3 E34 J24 MAA0_3 CMD0 CMD16 CS#
MAA1_[0..8] <57> DQA0_3 MAA0_3/MAA_3
DQA0_4 G32 H26 MAA0_4 CMD8 CMD24 ABI#
DQA0_4 MAA0_4/MAA_4
EDCA0_[0..3] DQA0_5 D33 J26 MAA0_5 CMD10 CMD26 A0_A10
EDCA0_[0..3] <56> DQA0_5 MAA0_5/MAA_5
DQA0_6 F32 H21 MAA0_6 CMD11 CMD27 A1_A9
DQA0_6 MAA0_6/MAA_6
EDCA1_[0..3] DQA0_7 E32 G21 MAA0_7 CMD2 CMD18 A2_BA0
DQA0_7 MAA0_7/MAA_7 +1.35V_MEM_GFX Source
MEMORY INTERFACE A
EDCA1_[0..3] <57> D31 H19

DQA0_8 DQA0_8 MAA1_0/MAA_8 MAA1_0 CMD1 CMD17 A3_BA3
DDBIA0_[0..3] DQA0_9 F30 H20 MAA1_1 CMD3 CMD19 A4_BA2 +PWR_SRC_S
DDBIA0_[0..3] <56> DQA0_9 MAA1_1/MAA_9
DQA0_10 C30 L13 MAA1_2 CMD4 CMD20 A5_BA1 +1.35V_MEM QV1 15G@ +1.35V_MEM_GFX
DQA0_10 MAA1_2/MAA_10
470K_0402_5%
DDBIA1_[0..3] DQA0_11 A30 G16 MAA1_3 CMD7 CMD23 A6_A11 SI4164DY-T1-GE3_SO8~D
DDBIA1_[0..3] <57> DQA0_11 MAA1_3/MAA_11
DQA0_12 F28 DQA0_12 MAA1_4/MAA_12
J16 MAA1_4 CMD6 CMD22 A7_A8 +3.3V_ALW2 8 1
1
DQA0_13 C28 H16 MAA1_5 CMD9 CMD25 A12_FRU 7 2
DQA0_13 MAA1_5/MAA_BA2
10U_0603_6.3V6M
DQA0_14 A28 J17 MAA1_6 CMD14 CMD30 CKE# 6 3
1
RV67
15G@
39_0402_5%
DQA0_15 E28 H17 MAA1_7 CMD13 CMD29 RESET# 5 1
C783 15G@
RV182
15G@
DQA0_16 D27
DQA0_16
2
DQA0_17 F26 A32 WCKA0_0
DQA0_17 WCKA0_0/DQMA_0
4
DQA0_18 C26 C32 WCKA0B_0 WCKA0_0 <56> RV81 15G@ GFX_MEM_VTT_EN 1 2
DQA0_18 WCKA0B_0/DQMA_1 WCKA0B_0 <56> 2
DQA0_19 A26 D23 WCKA0_1 100K_0402_5% @ RV85 0_0402_5%
2
DQA0_20 F24 E22 WCKA0B_1 WCKA0_1 <56> QV5
DQA0_20 WCKA0B_1/DQMA_3 WCKA0B_1 <56>
L2N7002WT1G_SC-70-3
100P_0402_50V8J
DQA0_21 C24 C14 WCKA1_0 L2N7002WT1G_SC-70-3
+1.35V_MEM_GFX_CHG
1
WCKA1_0 <57>
1
D
2.2M_0402_5%
DQA0_22 A24 A14 WCKA1B_0
DQA0_22 WCKA1B_0/DQMA_5 WCKA1B_0 <57>
QV2
E24 E10 3 1 2
D
DQA0_23 DQA0_23 WCKA1_1/DQMA_6 WCKA1_1 DGPU_PWR_EN# DGPU_PWR_EN#_Q 1
WCKA1_1 <57> <16> DGPU_PWR_EN#
RV80
15G@
DQA0_24 C22 DQA0_24 WCKA1B_1/DQMA_7
D9 WCKA1B_1 G
WCKA1B_1 <57>
CV129
15G@
DQA0_25 A22 DQA0_25 S
3
2
DQA0_26 F22 C34 EDCA0_0
G
DQA0_26 EDCA0_0/QSA_0
2
DQA0_27 D21 D29 EDCA0_1 RV82 @ 2
DQA0_27 EDCA0_1/QSA_1 +3.3V_RUN
DQA0_28 A20 D25 EDCA0_2 100K_0402_5%
DQA0_29 F20 E20 EDCA0_3
DQA0_30 D19 E16 EDCA1_0
1
E18 E12
L2N7002WT1G_SC-70-3
DQA0_31 DQA0_31 EDCA1_1
C18 EDCA1_1/QSA_5 J10 <67> DGPU_PWR_EN#_Q
DQA1_0 DQA1_0 EDCA1_2
EDCA1_2/QSA_6
1
DQA1_1 A18 D7 EDCA1_3 D
B DQA1_1 EDCA1_3/QSA_7 B
1
D
QV11 15G@
DQA1_2 F18 2DGPU_PWR_EN#_Q
DQA1_2
DQA1_3 D17 A34 DDBIA0_0 DGPU_PWR_EN# 2 QV6 G
DQA1_3 DDBIA0_0/QSA_0B
DQA1_4 A16 DQA1_4
E30 DDBIA0_1 G L2N7002WT1G_SC-70-3 S
DDBIA0_1/QSA_1B
3
DQA1_5 F16 DQA1_5
E26 DDBIA0_2 S @
DDBIA0_2/QSA_2B
3
DQA1_6 D15 C20 DDBIA0_3
DQA1_7 E14 C16 DDBIA1_0
DQA1_8 F14 C12 DDBIA1_1
DQA1_9 D13 J11 DDBIA1_2
DQA1_10 F12 F8 DDBIA1_3
DQA1_11 A12
DQA1_11
DQA1_12 D11 J21 ADBIA0
DQA1_12 ADBIA0/ODTA0 ADBIA0 <56>
DQA1_13 F10 G19 ADBIA1
DQA1_13 ADBIA1/ODTA1 ADBIA1 <57>
DQA1_14 A10
DQA1_14
DQA1_15 C10 H27 CLKA0
DQA1_15 CLKA0 CLKA0 <56>
DQA1_16 G13 DQA1_16 CLKA0B
G27 CLKA0#
DQA1_17 H13 CLKA0# <56>
DQA1_17
DQA1_18 J13 DQA1_18 CLKA1
J14 CLKA1
DQA1_19 H11 H14 CLKA1# CLKA1 <57>
DQA1_19 CLKA1B CLKA1# <57>
DQA1_20 G10
DQA1_20
DQA1_21 G8 K23 RASA0#
DQA1_21 RASA0B RASA0# <56> +1.35V_MEM_GFX +1.35V_MEM_GFX
DQA1_22 K9 K19 RASA1#
DQA1_22 RASA1B RASA1# <57>
DQA1_23 K10
DQA1_23
DQA1_24 G9 K20 CASA0#
DQA1_24 CASA0B CASA0# <56>
1
DQA1_25 A8 K17 CASA1# +1.35V_MEM_GFX

DQA1_25 CASA1B CASA1# <57>
DQA1_26 C8 RV145 RV148
DQA1_26
DQA1_27 E8 CSA0B_0 K24 CSA0#_0 40.2_0402_1% 40.2_0402_1%
DQA1_27 CSA0#_0 <56>
DQA1_28 A6 CSA0B_1 K27 15G@ 15G@
DQA1_28
DQA1_29 C6 DQA1_29 CLKA0 1 2
2
DQA1_30 E6 DQA1_30 CSA1B_0 M13 CSA1#_0 15G@ RV187 121_0402_1%

DQA1_31 A5 K16 CSA1#_0 <57> +VDD_MEM15_REFDA +VDD_MEM15_REFSA CLKA0# 1 2
DQA1_31 CSA1B_1
15G@ RV188 121_0402_1%
+VDD_MEM15_REFDA L18 CKEA0 K21 CKEA0 1 1 CLKA1 1 2
MVREFDA CKEA0 <56>
1
+1.35V_MEM_GFX +VDD_MEM15_REFSA L20 J20 CKEA1 CV275 CV274 15G@ RV189 121_0402_1%
MVREFSA CKEA1 CKEA1 <57> RV146 1U_0603_10V6K RV147 1U_0603_10V6K CLKA1# 1 2
15G@ RV28 1 2 243_0402_1% L27
NC WEA0B K26 WEA0# 100_0402_1% 15G@ 100_0402_1% 15G@ 15G@ RV190 121_0402_1%
15G@ RV31 1 2 243_0402_1% N12 L15 WEA1# WEA0# <56> 15G@ 2 15G@ 2
NC WEA1B WEA1# <57>
A 15G@ RV32 1 2 243_0402_1% AG12
NC A
2
MAA0_8/MAA_13
H23 MAA0_8
1 2 M27 MEM_CALRP0 MAA1_8/MAA_14
J19 MAA1_8
15G@ RV36 120_0402_1% MAA0_9/MAA_15
M21
15G@ RV34 1 2 243_0402_1% M12 NC MAA1_9/RSVD
M20
15G@ RV35 1 2 243_0402_1% AH12 NC
For Mars DNI RV28, RV31, RV32. RV34, RV35 PROPRIETARY NOTE:
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15G@ MARS-PRO_FCBGA962~D Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MARX-MEM Interface A
1.0
5 4 3 2 1
5 4 3 2 1
UV1I
DQB0_[0..31]
DQB0_[0..31] <58> PART 4 0F 9
DQB1_[0..31]
DQB1_[0..31] <59> DQB0_0 C5 GDDR5/DDR3 P8 MAB0_0
DQB0_0 MAB0_0/MAB_0
MAB0_[0..8] DQB0_1 C3 T9 MAB0_1
MAB0_[0..8] <58> DQB0_1 MAB0_1/MAB_1
DQB0_2 E3 P9 MAB0_2
DQB0_2 MAB0_2/MAB_2
D MAB1_[0..8] DQB0_3 E1 N7 MAB0_3 D
MAB1_[0..8] <59> DQB0_3 MAB0_3/MAB_3
DQB0_4 F1 N8 MAB0_4
DQB0_4 MAB0_4/MAB_4
EDCB0_[0..3] DQB0_5 F3 N9 MAB0_5
EDCB0_[0..3] <58> DQB0_5 MAB0_5/MAB_5
DQB0_6 F5 U9 MAB0_6
DQB0_6 MAB0_6/MAB_6
EDCB1_[0..3] DQB0_7 G4 U8 MAB0_7
EDCB1_[0..3] <59> DQB0_7 MAB0_7/MAB_7
DQB0_8 H5 Y9 MAB1_0
DDBIB0_[0..3] DQB0_8 MAB1_0/MAB_8
DQB0_9 H6 W9 MAB1_1
DDBIB0_[0..3] <58> DQB0_9 MAB1_1/MAB_9
DQB0_10 J4 AC8 MAB1_2
DQB0_10 MAB1_2/MAB_10
DDBIB1_[0..3] DQB0_11 K6 AC9 MAB1_3
DDBIB1_[0..3] <59> DQB0_11 MAB1_3/MAB_11
DQB0_12 K5 MAB1_4/MAB_12
AA7 MAB1_4
DQB0_13 L4 DQB0_12 AA8 MAB1_5
DQB0_13 MAB1_5/BA2
DQB0_14 M6 Y8 MAB1_6
DQB0_14 MAB1_6/BA0
DQB0_15 M1 AA9 MAB1_7
DQB0_15 MAB1_7/BA1
DQB0_16 M3
MEMORY INTERFACE B
DQB0_17 M5 DQB0_16 H3 WCKB0_0
DQB0_17 WCKB0_0/DQMB_0 WCKB0_0 <58>
DQB0_18 N4 H1 WCKB0B_0
DQB0_19 P6 DQB0_18 WCKB0B_0/DQMB_1 T3 WCKB0_1 WCKB0B_0 <58>
DQB0_20 P5 DQB0_19 WCKB0_1/DQMB_2 T5 WCKB0B_1 WCKB0_1 <58>
DQB0_21 R4 DQB0_20 WCKB0B_1/DQMB_3 AE4 WCKB1_0 WCKB0B_1 <58>
DQB0_22 T6 DQB0_21 WCKB1_0/DQMB_4 AF5 WCKB1B_0 WCKB1_0 <59>
DQB0_22 WCKB1B_0/DQMB_5 WCKB1B_0 <59>
DQB0_23 T1 AK6 WCKB1_1
DQB0_24 U4 DQB0_23 WCKB1_1/DQMB_6 AK5 WCKB1B_1 WCKB1_1 <59>
DQB0_25 V6 DQB0_24 WCKB1B_1/DQMB_7 WCKB1B_1 <59>
DQB0_26 V1 DQB0_25 F6 EDCB0_0
DQB0_27 V3 DQB0_26 EDCB0_0/QSB_0 K3 EDCB0_1
DQB0_28 Y6 DQB0_27 EDCB0_1/QSB_1 P3 EDCB0_2
DQB0_29 Y1 DQB0_28 EDCB0_2/QSB_2 V5 EDCB0_3
DQB0_30 Y3 DQB0_29 EDCB0_3/QSB_3 AB5 EDCB1_0
DQB0_31 Y5 DQB0_30 EDCB1_0/QSB_4 AH1 EDCB1_1
DQB0_31 EDCB1_1/QSB_5
DQB1_0 AA4 AJ9 EDCB1_2
DQB1_1 AB6 DQB1_0 EDCB1_2/QSB_6 AM5 EDCB1_3
DQB1_2 AB1 DQB1_1 EDCB1_3/QSB_7
C DQB1_3 AB3 DQB1_2 G7 DDBIB0_0 C
DQB1_4 AD6 DQB1_3 DDBIB0_0/QSB_0B K1 DDBIB0_1
DQB1_5 AD1 DQB1_4 DDBIB0_1/QSB_1B P1 DDBIB0_2
DQB1_6 AD3 DQB1_5 DDBIB0_2/QSB_2B W4 DDBIB0_3
DQB1_7 AD5 DQB1_6 DDBIB0_3/QSB_3B AC4 DDBIB1_0
DQB1_8 AF1 DQB1_7 DDBIB1_0/QSB_4B AH3 DDBIB1_1
DQB1_8 DDBIB1_1/QSB_5B
DQB1_9 AF3 AJ8 DDBIB1_2
DQB1_9 DDBIB1_2/QSB_6B
DQB1_10 AF6 AM3 DDBIB1_3
DQB1_11 AG4 DQB1_10 DDBIB1_3/QSB_7B
DQB1_12 AH5 DQB1_11 T7 ADBIB0
DQB1_13 AH6 DQB1_12 ADBIB0/ODTB0 W7 ADBIB1 ADBIB0 <58>
DQB1_13 ADBIB1/ODTB1 ADBIB1 <59>
DQB1_14 AJ4
DQB1_14
DQB1_15 AK3 L9 CLKB0
DQB1_16 AF8 DQB1_15 CLKB0 L8 CLKB0# CLKB0 <58>
DQB1_17 AF9 DQB1_16 CLKB0B CLKB0# <58> +1.35V_MEM_GFX
DQB1_18 AG8 DQB1_17 AD8 CLKB1
+1.35V_MEM_GFX +1.35V_MEM_GFX DQB1_18 CLKB1 CLKB1 <59>
DQB1_19 AG7 AD7 CLKB1#
DQB1_19 CLKB1B CLKB1# <59>
DQB1_20 AK9
DQB1_20
DQB1_21 AL7 T10 RASB0# CLKB0 1 2
DQB1_21 RASB0B RASB0# <58>
1
DQB1_22 AM8 Y10 RASB1# 15G@ RV206 121_0402_1%

DQB1_23 AM7 DQB1_22 RASB1B RASB1# <59> CLKB0# 1 2
RV155 RV153
DQB1_23
40.2_0402_1% 40.2_0402_1% DQB1_24 AK1 W10 CASB0# 15G@ RV208 121_0402_1%
DQB1_25 AL4 DQB1_24 CASB0B AA10 CASB1# CASB0# <58> CLKB1 1 2
15G@ 15G@
DQB1_25 CASB1B CASB1# <59>
DQB1_26 AM6 15G@ RV209 121_0402_1%
DQB1_26
2
DQB1_27 AM1 P10 CSB0#_0 CLKB1# 1 2

+VDD_MEM15_REFDB +VDD_MEM15_REFSB DQB1_28 AN4 DQB1_27 CSB0B_0 L10 CSB0#_0 <58>
15G@ RV210 121_0402_1%
DQB1_28 CSB0B_1
DQB1_29 AP3
DQB1_29
DQB1_30 AP1 AD10 CSB1#_0
DQB1_30 CSB1B_0 CSB1#_0 <59>
1
CV279 CV278 DQB1_31 AP5 AC10

DQB1_31 CSB1B_1
RV152 0.1U_0402_16V7K RV154 0.1U_0402_16V7K
100_0402_1% 15G@ 100_0402_1% 15G@ U10 CKEB0
CKEB0 CKEB0 <58>
2
15G@ +VDD_MEM15_REFDB Y12 AA11 CKEB1

B 15G@ +VDD_MEM15_REFSB AA12 MVREFDB CKEB1 CKEB1 <59> B
MVREFSB
2
N10 WEB0#
WEB0B AB11 WEB1# WEB0# <58> +1.35V_MEM_GFX
WEB1B WEB1# <59>
T8 MAB0_8
MAB0_8/MAB_13
1
W8 MAB1_8
MAB1_8/MAB_14
U12 RV177 @
MAB0_9/MAB_15
V12 4.7K_0402_5%
MAB1_9/RSVD
AH11 25mm (Max) 5mm (Max) 25mm (Max)
DRAM_RST
2
RV178 1 RV179
DRAM_RST#_R 2 2 1
DRAM_RST# <56,57,58,59>
10_0402_1% 51.1_0402_1%
15G@
15G@
1
15G@ 15G@
RV180 CV343
4.99K_0402_1% 120P_0402_50V9
2
1
This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
A Place all these components very close to GPU (Within A
25mm) and keep all component close to each Other (within
5mm) except Rser2
PROPRIETARY NOTE:
Title
MARX-MEM Interface B
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1.0
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Lower 16 bits 64X32 GDDR5

UV5
MIRROR
MF=0 MF=1 MF=1 MF=0
UV4
NORMAL
A4 DQA0_24
MF=0 MF=1 MF=1 MF=0 EDCA0_3 C2 DQ24 DQ0 A2 DQA0_27
<54> EDCA0_3 C13 EDC0 EDC3 DQ25 DQ1 B4 DQA0_25
A4 DQA0_15 EDCA0_0 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA0_26
EDCA0_1 C2 DQ24 DQ0 A2 DQA0_14 <54> EDCA0_0 R2 EDC2 EDC1 DQ27 DQ3 E4 DQA0_28
<54> EDCA0_1 C13 EDC0 EDC3 DQ25 DQ1 B4 DQA0_13 EDC3 EDC0 DQ28 DQ4 E2 DQA0_30
EDCA0_2 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA0_12 DQ29 DQ5 F4 DQA0_29
<54> EDCA0_2 R2 EDC2 EDC1 DQ27 DQ3 E4 DQA0_9 DDBIA0_3 D2 DQ30 DQ6 F2 DQA0_31
EDC3 EDC0 DQ28 DQ4 E2 DQA0_11 D13 DBI0# DBI3# DQ31 DQ7 A11
DQ29 DQ5 +1.35V_MEM_GFX DBI1# DBI2# DQ16 DQ8
F4 DQA0_8 DDBIA0_0 P13 A13
DDBIA0_1 D2 DQ30 DQ6 F2 DQA0_10 P2 DBI2# DBI1# DQ17 DQ9 B11
D13 DBI0# DBI3# DQ31 DQ7 A11 DBI3# DBI0# DQ18 DQ10 B13
D +1.35V_MEM_GFX DBI1# DBI2# DQ16 DQ8 DQ19 DQ11 D
DDBIA0_2 P13 A13 CLKA0 J12 E11
P2 DBI2# DBI1# DQ17 DQ9 B11 <54,56> CLKA0 J11 CK DQ20 DQ12 E13
CLKA0#
DBI3# DBI0# DQ18 DQ10 B13 <54,56> CLKA0# J3 CK# DQ21 DQ13 F11
CKEA0
J12 DQ19 DQ11 E11 <54,56> CKEA0 CKE# DQ22 DQ14 F13
CLKA0
<54,56> CLKA0 J11 CK DQ20 DQ12 E13 J5 DQ23 DQ15 U11
CLKA0# MAA0_8 DQA0_5
<54,56> CLKA0# J3 CK# DQ21 DQ13 F11 A12/RFU/NC DQ8 DQ16 U13
CKEA0 DQA0_7
<54,56> CKEA0 CKE# DQ22 DQ14 F13 K4 DQ9 DQ17 T11
MAA0_0 DQA0_6
MAA0_8 J5 DQ23 DQ15 U11 DQA0_22 MAA0_1 K5 A8/A7 A10/A0 DQ10 DQ18 T13 DQA0_1
A12/RFU/NC DQ8 DQ16 U13 DQA0_21 MAA0_3 K10 A11/A6 A9/A1 DQ11 DQ19 N11 DQA0_0
MAA0_7 K4 DQ9 DQ17 T11 DQA0_23 MAA0_2 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 DQA0_2
MAA0_6 K5 A8/A7 A10/A0 DQ10 DQ18 T13 DQA0_20 BA2/A4 BA0/A2 DQ13 DQ21 M11 DQA0_3
MAA0_5 K10 A11/A6 A9/A1 DQ11 DQ19 N11 DQA0_19 MAA0_5 H10 DQ14 DQ22 M13 DQA0_4
MAA0_4 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 DQA0_18 DQA0_[0..31] MAA0_4 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4
BA2/A4 BA0/A2 DQ13 DQ21 M11 DQA0_[0..31] <54> H5 BA0/A2 BA2/A4 DQ0 DQ24 U2
DQA0_16 MAA0_6
MAA0_3 H10 DQ14 DQ22 M13 DQA0_17 EDCA0_[0..3] MAA0_7 H4 A9/A1 A11/A6 DQ1 DQ25 T4
H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 EDCA0_[0..3] <54> A10/A0 A8/A7 DQ2 DQ26 T2
MAA0_2
MAA0_1 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 DDBIA0_[0..3] DQ3 DQ27 N4
H4 A9/A1 A11/A6 DQ1 DQ25 T4 DDBIA0_[0..3] <54> A5 DQ4 DQ28 N2
MAA0_0
A10/A0 A8/A7 DQ2 DQ26 T2 MAA0_[0..8] U5 VPP/NC DQ5 DQ29 M4
DQ3 DQ27 N4 MAA0_[0..8] <54> VPP/NC DQ6 DQ30 M2
A5 DQ4 DQ28 N2 DQ7 DQ31
VPP/NC DQ5 DQ29 +1.35V_MEM_GFX +1.35V_MEM_GFX
U5 M4 J1
VPP/NC DQ6 DQ30 M2 J10 MF
DQ7 DQ31 1 2 J13 SEN B1
J1 +1.35V_MEM_GFX 15G@ RV107 ZQ VDDQ D1
J10 MF 121_0402_1% VDDQ F1
15G@ RV108 1 2 121_0402_1% J13 SEN B1 ADBIA0 J4 VDDQ M1
ZQ VDDQ D1 <54,56> ADBIA0 G3 ABI# VDDQ P1
CASA0#
VDDQ F1 <54,56> CASA0# G12 RAS# CAS# VDDQ T1
WEA0#
J4 VDDQ M1 <54,56> WEA0# L3 CS# WE# VDDQ G2
ADBIA0 RASA0#
<54,56> ADBIA0 G3 ABI# VDDQ P1 <54,56> RASA0# L12 CAS# RAS# VDDQ L2
RASA0# +1.35V_MEM_GFX CSA0#_0
<54,56> RASA0# G12 RAS# CAS# VDDQ T1 <54,56> CSA0#_0 WE# CS# VDDQ B3
CSA0#_0
<54,56> CSA0#_0 L3 CS# WE# VDDQ G2 VDDQ D3
CASA0#
<54,56> CASA0# CAS# RAS# VDDQ VDDQ
1U_0402_6.3V6K
2.37K_0402_1%
+1.35V_MEM_GFX WEA0# L12 L2 F3
<54,56> WEA0# WE# CS# VDDQ VDDQ
1
B3 1 WCKA0B_1 D5 H3
VDDQ <54,56> WCKA0B_1 WCK01# WCK23# VDDQ
CV325 15G@
RV140 15G@
D3 WCKA0_1 D4 K3
VDDQ <54,56> WCKA0_1 WCK01 WCK23 VDDQ
1U_0402_6.3V6K
2.37K_0402_1%
C
F3 M3 C
VDDQ VDDQ
1
1 WCKA0B_0 D5 H3 WCKA0B_0 P5 P3
<54,56> WCKA0B_0 WCK01# WCK23# VDDQ 2 <54,56> WCKA0B_0 WCK23# WCK01# VDDQ
CV322 15G@
RV109 15G@
WCKA0_0 D4 K3 WCKA0_0 P4 T3
<54,56> WCKA0_0 <54,56> WCKA0_0
2
WCK01 WCK23 VDDQ M3 WCK23 WCK01 VDDQ E5
VDDQ VDDQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
WCKA0B_1 P5 P3 N5
2 <54,56> WCKA0B_1 P4 WCK23# WCK01# VDDQ T3 A10 VDDQ E10
WCKA0_1 VREFD2_1 1 1 1 1 1 1
<54,56> WCKA0_1
2
WCK23 WCK01 VDDQ VREFD VDDQ
CV139 15G@
CV140 15G@
CV179 15G@
CV182 15G@
E5 VREFD2_2 U10 N10
VDDQ VREFD VDDQ
1U_0402_6.3V6K
5.49K_0402_1%
CV137 15G@
CV138 15G@
N5 VREFC2 J14 B12
VDDQ VREFC VDDQ
1
VREFD1_1 A10 E10 1 D12
VREFD VDDQ VDDQ 2 2 2 2 2 2
CV327 15G@
RV181 15G@
VREFD1_2 U10 N10 F12
VREFD VDDQ VDDQ
1U_0402_6.3V6K
5.49K_0402_1%
VREFC1 J14 B12 H12

VREFC VDDQ VDDQ
1
1 D12 DRAM_RST# J2 K12

VDDQ 2 <55,57,58,59> DRAM_RST# RESET# VDDQ
CV207 15G@
RV128 15G@
F12 M12
2
VDDQ H12 VDDQ P12
DRAM_RST# J2 VDDQ K12 VDDQ T12
2 RESET# VDDQ M12 VDDQ G13
2
VDDQ P12 VDDQ L13

VDDQ T12 VDDQ B14
VDDQ G13 VDDQ D14
VDDQ L13 VDDQ F14
+1.35V_MEM_GFX VDDQ B14 VDDQ M14
VDDQ 10U_0603_6.3V6M VDDQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
D14 G1 P14
VDDQ F14 L1 VDD VDDQ T14
VDDQ 1 1 1 1 1 1 1 VDD VDDQ
CV42 15G@
CV178 15G@
CV188 15G@
CV141 15G@
CV142 15G@
CV143 15G@
CV151 15G@
M14 G4
G1 VDDQ P14 L4 VDD
L1 VDD VDDQ T14 C5 VDD A1
G4 VDD VDDQ 2 2 2 2 2 2 2 R5 VDD VSSQ C1
L4 VDD C10 VDD VSSQ E1
C5 VDD A1 R10 VDD VSSQ N1
R5 VDD VSSQ C1 D11 VDD VSSQ R1
VDD VSSQ VDD VSSQ
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
C10 E1 G11 U1
R10 VDD VSSQ N1 L11 VDD VSSQ H2
1 1 1 1 1 VDD VSSQ VDD VSSQ
CV41 15G@
CV176 15G@
CV177 15G@
CV152 15G@
CV153 15G@
D11 R1 +1.35V_MEM_GFX P11 K2

G11 VDD VSSQ U1 G14 VDD VSSQ A3
L11 VDD VSSQ H2 L14 VDD VSSQ C3
2 2 2 2 2 P11 VDD VSSQ K2 VDD VSSQ E3
VDD VSSQ VSSQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
G14 A3 N3
L14 VDD VSSQ C3 VSSQ R3
B VDD VSSQ 1 1 1 1 VSSQ B
CV154 15G@
CV155 15G@
E3 H1 U3
VSSQ VSS VSSQ
CV130 15G@
CV131 15G@
N3 K1 C4
VSSQ R3 B5 VSS VSSQ R4
H1 VSSQ U3 2 2 2 2 G5 VSS VSSQ F5
K1 VSS VSSQ C4 L5 VSS VSSQ M5
B5 VSS VSSQ R4 T5 VSS VSSQ F10
G5 VSS VSSQ F5 B10 VSS VSSQ M10
L5 VSS VSSQ M5 D10 VSS VSSQ C11
T5 VSS VSSQ F10 G10 VSS VSSQ R11
B10 VSS VSSQ M10 L10 VSS VSSQ A12
D10 VSS VSSQ C11 P10 VSS VSSQ C12
G10 VSS VSSQ R11 T10 VSS VSSQ E12
L10 VSS VSSQ A12 H14 VSS VSSQ N12
P10 VSS VSSQ C12 K14 VSS VSSQ R12
T10 VSS VSSQ E12 VSS170-BALL VSSQ U12
H14 VSS VSSQ N12 VSSQ H13
K14 VSS VSSQ R12 SGRAM GDDR5 VSSQ K13
VSS170-BALL VSSQ U12 VSSQ A14
VSSQ H13 VSSQ C14
SGRAM GDDR5 VSSQ K13 VSSQ E14
VSSQ A14 VSSQ N14
VSSQ C14 VSSQ R14
VSSQ E14 VSSQ U14
VSSQ N14 VSSQ
VSSQ R14 K4G20325FC-HC05_FBGA170~D
VSSQ U14 +1.35V_MEM_GFX +1.35V_MEM_GFX 15G@
VSSQ
K4G20325FC-HC05_FBGA170~D
1U_0402_6.3V6K
2.37K_0402_1%
1U_0402_6.3V6K
2.37K_0402_1%
+1.35V_MEM_GFX +1.35V_MEM_GFX 15G@

1
1 1
CV328 15G@
RV183 15G@
CV330 15G@
RV185 15G@
1U_0402_6.3V6K
2.37K_0402_1%
1U_0402_6.3V6K
2.37K_0402_1%
1
1 1
2 2
CV208 15G@
RV139 15G@
CV323 15G@
RV129 15G@
PROPRIETARY NOTE:
2

2 2 VREFC2 VREFD2_2 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
A A
2

1U_0402_6.3V6K
5.49K_0402_1%
1U_0402_6.3V6K
5.49K_0402_1%
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1
VREFC1 VREFD1_2 1 1
CV329 15G@
RV184 15G@
CV331 15G@
RV186 15G@
1U_0402_6.3V6K
5.49K_0402_1%
1U_0402_6.3V6K
5.49K_0402_1%
1
1 1
2 2
CV326 15G@
RV110 15G@
CV324 15G@
RV131 15G@
2
2 2
2
www.Vinafix.vn
Title
MARX-VRAM_A Lower
1.0
LA-9411P
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Upper 16 bits UV6

NORMAL
UV3
MIRROR MF=0 MF=1 MF=1 MF=0
MF=0 MF=1 MF=1 MF=0 A4 DQA1_7

EDCA1_0 C2 DQ24 DQ0 A2 DQA1_5
A4 DQA1_17 <54> EDCA1_0 C13 EDC0 EDC3 DQ25 DQ1 B4 DQA1_6
EDCA1_2 C2 DQ24 DQ0 A2 DQA1_19 EDCA1_3 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA1_4
<54> EDCA1_2 C13 EDC0 EDC3 DQ25 DQ1 B4 DQA1_18 <54> EDCA1_3 R2 EDC2 EDC1 DQ27 DQ3 E4 DQA1_3
EDCA1_1 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA1_16 EDC3 EDC0 DQ28 DQ4 E2 DQA1_2
<54> EDCA1_1 R2 EDC2 EDC1 DQ27 DQ3 E4 DQA1_21 DQ29 DQ5 F4 DQA1_0
EDC3 EDC0 DQ28 DQ4 E2 DQA1_20 DDBIA1_0 D2 DQ30 DQ6 F2 DQA1_1
DQ29 DQ5 F4 DQA1_22 D13 DBI0# DBI3# DQ31 DQ7 A11
DDBIA1_2 D2 F2 DQA1_23 DDBIA1_3 P13 A13
D13 DBI0# DBI3# DQ31 DQ7 A11 P2 DBI2# DBI1# DQ17 DQ9 B11
+1.35V_MEM_GFX DBI1# DBI2# DQ16 DQ8 DBI3# DBI0# DQ18 DQ10
D DDBIA1_1 P13 A13 B13 D
P2 DBI2# DBI1# DQ17 DQ9 B11 CLKA1 J12 DQ19 DQ11 E11
DBI3# DBI0# DQ18 DQ10 B13 CLKA1# J11 CK DQ20 DQ12 E13
CLKA1 J12 DQ19 DQ11 E11 CKEA1 J3 CK# DQ21 DQ13 F11
<54> CLKA1 J11 CK DQ20 DQ12 E13 CKE# DQ22 DQ14 F13
CLKA1#
<54> CLKA1# J3 CK# DQ21 DQ13 F11 J5 DQ23 DQ15 U11
CKEA1 MAA1_8 DQA1_31
<54> CKEA1 CKE# DQ22 DQ14 F13 A12/RFU/NC DQ8 DQ16 U13 DQA1_30
MAA1_8 J5 DQ23 DQ15 U11 DQA1_9 MAA1_7 K4 DQ9 DQ17 T11 DQA1_29
A12/RFU/NC DQ8 DQ16 U13 DQA1_11 MAA1_6 K5 A8/A7 A10/A0 DQ10 DQ18 T13 DQA1_24
MAA1_0 K4 DQ9 DQ17 T11 DQA1_10 MAA1_5 K10 A11/A6 A9/A1 DQ11 DQ19 N11 DQA1_25
MAA1_1 K5 A8/A7 A10/A0 DQ10 DQ18 T13 DQA1_12 MAA1_4 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 DQA1_28
MAA1_3 K10 A11/A6 A9/A1 DQ11 DQ19 N11 DQA1_8 BA2/A4 BA0/A2 DQ13 DQ21 M11 DQA1_27
MAA1_2 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 DQA1_13 MAA1_3 H10 DQ14 DQ22 M13 DQA1_26
BA2/A4 BA0/A2 DQ13 DQ21 M11 DQA1_14 MAA1_2 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4
MAA1_5 H10 DQ14 DQ22 M13 DQA1_15 MAA1_1 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2
MAA1_4 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 MAA1_0 H4 A9/A1 A11/A6 DQ1 DQ25 T4
MAA1_6 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 A10/A0 A8/A7 DQ2 DQ26 T2
MAA1_7 H4 A9/A1 A11/A6 DQ1 DQ25 T4 DQ3 DQ27 N4
A10/A0 A8/A7 DQ2 DQ26 T2 A5 DQ4 DQ28 N2
DQ3 DQ27 N4 U5 VPP/NC DQ5 DQ29 M4
A5 DQ4 DQ28 N2 VPP/NC DQ6 DQ30 M2
U5 VPP/NC DQ5 DQ29 M4 DQ7 DQ31
VPP/NC DQ6 DQ30 M2 J1 +1.35V_MEM_GFX
+1.35V_MEM_GFX DQ7 DQ31 MF
J10
J1 +1.35V_MEM_GFX 1 2 J13 SEN B1
J10 MF RV117 15G@ ZQ VDDQ D1
15G@ RV118 1 2 121_0402_1% J13 SEN B1 121_0402_1% VDDQ F1
ZQ VDDQ D1 ADBIA1 J4 VDDQ M1
VDDQ F1 RASA1# G3 ABI# VDDQ P1
ADBIA1 J4 VDDQ M1 CSA1#_0 G12 RAS# CAS# VDDQ T1
<54> ADBIA1 G3 ABI# VDDQ P1 L3 CS# WE# VDDQ G2
CASA1# CASA1#
<54> CASA1# G12 RAS# CAS# VDDQ T1 L12 CAS# RAS# VDDQ L2
WEA1# +1.35V_MEM_GFX WEA1#
<54> WEA1# L3 CS# WE# VDDQ G2 WE# CS# VDDQ B3
RASA1#
<54> RASA1# L12 CAS# RAS# VDDQ L2 VDDQ D3
+1.35V_MEM_GFX CSA1#_0
<54> CSA1#_0 WE# CS# VDDQ VDDQ
1U_0402_6.3V6K
2.37K_0402_1%
B3 F3
VDDQ VDDQ
1
D3 1 WCKA1B_0 D5 H3
VDDQ <54,57> WCKA1B_0 WCK01# WCK23# VDDQ
1U_0402_6.3V6K
2.37K_0402_1%
CV352 15G@
RV195 15G@
F3 WCKA1_0 D4 K3
VDDQ <54,57> WCKA1_0 WCK01 WCK23 VDDQ
1
C 1 WCKA1B_1 D5 H3 M3 C
<54,57> WCKA1B_1 WCK01# WCK23# VDDQ VDDQ
CV209 15G@
RV119 15G@
WCKA1_1 D4 K3 WCKA1B_1 P5 P3
<54,57> WCKA1_1 WCK01 WCK23 VDDQ M3 2 <54,57> WCKA1B_1 P4 WCK23# WCK01# VDDQ T3
WCKA1_1
<54,57> WCKA1_1
2
WCKA1B_0 P5 VDDQ P3 WCK23 WCK01 VDDQ E5
2 <54,57> WCKA1B_0 WCK23# WCK01# VDDQ VDDQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
WCKA1_0 P4 T3 N5
<54,57> WCKA1_0
2
WCK23 WCK01 VDDQ E5 VREFD4_1 A10 VDDQ E10

VDDQ VREFD VDDQ 1 1 1 1 1 1
CV147
CV150
CV181
CV185
N5 VREFD4_2 U10 N10
VDDQ VREFD VDDQ
1U_0402_6.3V6K
5.49K_0402_1%
CV149 15G@
CV148 15G@
VREFD3_1 A10 E10 VREFC4 J14 B12
VREFD VDDQ VREFC VDDQ
1
VREFD3_2 U10 N10 1 D12
1U_0402_6.3V6K
5.49K_0402_1%
CV351 15G@
RV196 15G@
VREFC3 J14 B12 F12
VREFC VDDQ VDDQ
1
1 D12 H12
15G@
15G@
15G@
15G@
VDDQ VDDQ
CV210 15G@
RV120 15G@
F12 DRAM_RST# J2 K12

VDDQ H12 2 <55,56,58,59> DRAM_RST# RESET# VDDQ M12
2
DRAM_RST# J2 VDDQ K12 VDDQ P12
2 RESET# VDDQ M12 VDDQ T12
2
VDDQ P12 VDDQ G13

VDDQ T12 VDDQ L13
VDDQ G13 VDDQ B14
VDDQ L13 VDDQ D14
+1.35V_MEM_GFX VDDQ B14 VDDQ F14
VDDQ D14 VDDQ M14
VDDQ VDDQ
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
F14 G1 P14
VDDQ M14 L1 VDD VDDQ T14
CV44 15G@
CV145 15G@
CV146 15G@
CV144 15G@
CV156 15G@
G1 P14 G4
VDD VDDQ VDD
CV180 15G@
CV189 15G@
L1 T14 L4
G4 VDD VDDQ C5 VDD A1
L4 VDD 2 2 2 2 2 2 2 R5 VDD VSSQ C1
C5 VDD A1 C10 VDD VSSQ E1
R5 VDD VSSQ C1 R10 VDD VSSQ N1
VDD VSSQ VDD VSSQ
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
C10 E1 D11 R1
R10 VDD VSSQ N1 G11 VDD VSSQ U1
CV43
CV157 15G@
CV158 15G@
D11 R1 L11 H2
VDD VSSQ VDD VSSQ
CV191
CV192
G11 U1 +1.35V_MEM_GFX P11 K2

L11 VDD VSSQ H2 G14 VDD VSSQ A3
15G@
15G@
P11 K2 L14 C3
15G@
G14 VDD VSSQ A3 VDD VSSQ E3

L14 VDD VSSQ C3 VSSQ N3
VDD VSSQ VSSQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
B
E3 R3 B
VSSQ N3 H1 VSSQ U3
VSSQ 1 1 1 1 VSS VSSQ
CV159 15G@
CV162 15G@
R3 K1 C4
VSSQ VSS VSSQ
CV134 15G@
CV133 15G@
H1 U3 B5 R4
K1 VSS VSSQ C4 G5 VSS VSSQ F5
B5 VSS VSSQ R4 2 2 2 2 L5 VSS VSSQ M5
G5 VSS VSSQ F5 T5 VSS VSSQ F10
L5 VSS VSSQ M5 B10 VSS VSSQ M10
T5 VSS VSSQ F10 D10 VSS VSSQ C11
B10 VSS VSSQ M10 G10 VSS VSSQ R11 DQA1_[0..31]
D10 VSS VSSQ C11 L10 VSS VSSQ A12 DQA1_[0..31] <54>
G10 VSS VSSQ R11 P10 VSS VSSQ C12 EDCA1_[0..3]
L10 VSS VSSQ A12 T10 VSS VSSQ E12 EDCA1_[0..3] <54>
P10 VSS VSSQ C12 H14 VSS VSSQ N12 DDBIA1_[0..3]
T10 VSS VSSQ E12 K14 VSS VSSQ R12 DDBIA1_[0..3] <54>
H14 VSS VSSQ N12 VSS170-BALL VSSQ U12 MAA1_[0..8]
K14 VSS VSSQ R12 VSSQ H13 MAA1_[0..8] <54>
VSS170-BALL VSSQ U12 SGRAM GDDR5 VSSQ K13
VSSQ H13 VSSQ A14
SGRAM GDDR5 VSSQ K13 VSSQ C14
VSSQ A14 VSSQ E14
VSSQ C14 VSSQ N14
VSSQ E14 VSSQ R14
VSSQ N14 VSSQ U14
VSSQ R14 VSSQ
VSSQ U14 K4G20325FC-HC05_FBGA170~D
+1.35V_MEM_GFX +1.35V_MEM_GFX VSSQ 15G@
K4G20325FC-HC05_FBGA170~D +1.35V_MEM_GFX +1.35V_MEM_GFX
15G@
1U_0402_6.3V6K
2.37K_0402_1%
1U_0402_6.3V6K
2.37K_0402_1%
1
1U_0402_6.3V6K
2.37K_0402_1%
1U_0402_6.3V6K
2.37K_0402_1%
1 1
1
1
CV333 15G@
RV191 15G@
CV350 15G@
RV193 15G@
1 1
CV356 15G@
RV203 15G@
CV354 15G@
RV197 15G@
2 2
PROPRIETARY NOTE:
2
2 2
2
A VREFD3_2 VREFC3 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT A
VREFD4_2 VREFC4 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
1U_0402_6.3V6K
5.49K_0402_1%
1U_0402_6.3V6K
5.49K_0402_1%
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1
1U_0402_6.3V6K
5.49K_0402_1%
1U_0402_6.3V6K
5.49K_0402_1%
1 1
1

CV332 15G@
RV192 15G@
CV349 15G@
RV194 15G@
1 1
CV355 15G@
RV205 15G@
CV353 15G@
RV198 15G@
2 2 DELL CONFIDENTIAL/PROPRIETARY
2
2 2
2

Title
www.Vinafix.vn
MARX-VRAM_A Upper
1.0
LA-9411P
5 4 3 2 1
5 4 3 2 1
Memory Partition B - Lower 16 bits DQB0_[0..31]

DQB0_[0..31] <55>
EDCB0_[0..3]
EDCB0_[0..3] <55> MIRROR
DDBIB0_[0..3] UV7
DDBIB0_[0..3] <55>
NORMAL MAB0_[0..8] MF=0 MF=1 MF=1 MF=0
MAB0_[0..8] <55>
UV8
A4 DQB0_24
MF=0 MF=1 MF=1 MF=0 EDCB0_3 C2 DQ24 DQ0 A2 DQB0_27
<55> EDCB0_3 C13 EDC0 EDC3 DQ25 DQ1 B4 DQB0_25
A4 DQB0_12 EDCB0_0 R13 EDC1 EDC2 DQ26 DQ2 B2 DQB0_26
EDCB0_1 C2 DQ24 DQ0 A2 DQB0_13 <55> EDCB0_0 R2 EDC2 EDC1 DQ27 DQ3 E4 DQB0_28
<55> EDCB0_1 C13 EDC0 EDC3 DQ25 DQ1 B4 DQB0_15 EDC3 EDC0 DQ28 DQ4 E2 DQB0_30
EDCB0_2 R13 EDC1 EDC2 DQ26 DQ2 B2 DQB0_14 DQ29 DQ5 F4 DQB0_29
<55> EDCB0_2 R2 EDC2 EDC1 DQ27 DQ3 E4 DQB0_8 DDBIB0_3 D2 DQ30 DQ6 F2 DQB0_31
D EDC3 EDC0 DQ28 DQ4 DBI0# DBI3# DQ31 DQ7 D
E2 DQB0_11 D13 A11
F4 DQB0_9 DDBIB0_0 P13 A13
DDBIB0_1 D2 DQ30 DQ6 F2 DQB0_10 P2 DBI2# DBI1# DQ17 DQ9 B11
D13 DBI0# DBI3# DQ31 DQ7 A11 DBI3# DBI0# DQ18 DQ10 B13
+1.35V_MEM_GFX DBI1# DBI2# DQ16 DQ8 DQ19 DQ11
DDBIB0_2 P13 A13 CLKB0 J12 E11
P2 DBI2# DBI1# DQ17 DQ9 B11 CLKB0# J11 CK DQ20 DQ12 E13
DBI3# DBI0# DQ18 DQ10 B13 CKEB0 J3 CK# DQ21 DQ13 F11
CLKB0 J12 DQ19 DQ11 E11 CKE# DQ22 DQ14 F13
<55> CLKB0 J11 CK DQ20 DQ12 E13 J5 DQ23 DQ15 U11
CLKB0# MAB0_8 DQB0_6
<55> CLKB0# J3 CK# DQ21 DQ13 F11 A12/RFU/NC DQ8 DQ16 U13
CKEB0 DQB0_7
<55> CKEB0 CKE# DQ22 DQ14 F13 K4 DQ9 DQ17 T11
MAB0_0 DQB0_5
MAB0_8 J5 DQ23 DQ15 U11 DQB0_22 MAB0_1 K5 A8/A7 A10/A0 DQ10 DQ18 T13 DQB0_0
A12/RFU/NC DQ8 DQ16 U13 DQB0_21 MAB0_3 K10 A11/A6 A9/A1 DQ11 DQ19 N11 DQB0_3
MAB0_7 K4 DQ9 DQ17 T11 DQB0_23 MAB0_2 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 DQB0_1
MAB0_6 K5 A8/A7 A10/A0 DQ10 DQ18 T13 DQB0_20 BA2/A4 BA0/A2 DQ13 DQ21 M11 DQB0_4
MAB0_5 K10 A11/A6 A9/A1 DQ11 DQ19 N11 DQB0_19 MAB0_5 H10 DQ14 DQ22 M13 DQB0_2
MAB0_4 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 DQB0_18 MAB0_4 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4
BA2/A4 BA0/A2 DQ13 DQ21 M11 DQB0_16 MAB0_6 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2
MAB0_3 H10 DQ14 DQ22 M13 DQB0_17 MAB0_7 H4 A9/A1 A11/A6 DQ1 DQ25 T4
MAB0_2 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 A10/A0 A8/A7 DQ2 DQ26 T2
MAB0_1 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 DQ3 DQ27 N4
MAB0_0 H4 A9/A1 A11/A6 DQ1 DQ25 T4 A5 DQ4 DQ28 N2
A10/A0 A8/A7 DQ2 DQ26 T2 U5 VPP/NC DQ5 DQ29 M4
DQ3 DQ27 N4 VPP/NC DQ6 DQ30 M2
A5 DQ4 DQ28 N2 DQ7 DQ31
VPP/NC DQ5 DQ29 +1.35V_MEM_GFX +1.35V_MEM_GFX
U5 M4 J1
VPP/NC DQ6 DQ30 M2 J10 MF
DQ7 DQ31 1 2 J13 SEN B1
J1 +1.35V_MEM_GFX 15G@ RV162 ZQ VDDQ D1
J10 MF 121_0402_1% VDDQ F1
15G@ RV163 1 2 121_0402_1% J13 SEN B1 ADBIB0 J4 VDDQ M1
ZQ VDDQ D1 CASB0# G3 ABI# VDDQ P1
VDDQ F1 WEB0# G12 RAS# CAS# VDDQ T1
ADBIB0 J4 VDDQ M1 RASB0# L3 CS# WE# VDDQ G2
<55> ADBIB0 G3 ABI# VDDQ P1 L12 CAS# RAS# VDDQ L2
RASB0# +1.35V_MEM_GFX CSB0#_0
<55> RASB0# G12 RAS# CAS# VDDQ T1 WE# CS# VDDQ B3
CSB0#_0
<55> CSB0#_0 L3 CS# WE# VDDQ G2 VDDQ D3
C CASB0# C
<55> CASB0# CAS# RAS# VDDQ VDDQ
1U_0402_6.3V6K
2.37K_0402_1%
+1.35V_MEM_GFX WEB0# L12 L2 F3
<55> WEB0# WE# CS# VDDQ VDDQ
1
B3 1 WCKB0B_1 D5 H3
VDDQ <55,58> WCKB0B_1 WCK01# WCK23# VDDQ
CV24 15G@
RV8 15G@
D3 WCKB0_1 D4 K3
VDDQ <55,58> WCKB0_1 WCK01 WCK23 VDDQ
1U_0402_6.3V6K
2.37K_0402_1%
F3 M3
VDDQ VDDQ
1
1 WCKB0B_0 D5 H3 WCKB0B_0 P5 P3
<55,58> WCKB0B_0 WCK01# WCK23# VDDQ 2 <55,58> WCKB0B_0 WCK23# WCK01# VDDQ
CV18 15G@
RV1 15G@
WCKB0_0 D4 K3 WCKB0_0 P4 T3
<55,58> WCKB0_0 <55,58> WCKB0_0
2
WCK01 WCK23 VDDQ M3 WCK23 WCK01 VDDQ E5
VDDQ VDDQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
WCKB0B_1 P5 P3 N5
2 <55,58> WCKB0B_1 P4 WCK23# WCK01# VDDQ T3 A10 VDDQ E10
WCKB0_1 VREFD6_1 1 1 1 1 1 1
<55,58> WCKB0_1
2
CV202
CV285
CV288
CV296
E5 VREFD6_2 U10 N10
VDDQ VREFD VDDQ
1U_0402_6.3V6K
5.49K_0402_1%
CV290 15G@
CV283 15G@
N5 VREFC6 J14 B12
VDDQ VREFC VDDQ
1
VREFD5_1 A10 E10 1 D12
CV23 15G@
RV7 15G@
VREFD5_2 U10 N10 F12
VREFD VDDQ VDDQ
1U_0402_6.3V6K
5.49K_0402_1%
VREFC5 J14 B12 H12
15G@
15G@
15G@
15G@
VREFC VDDQ VDDQ
1
1 D12 DRAM_RST# J2 K12

VDDQ 2 <55,56,57,59> DRAM_RST# RESET# VDDQ
CV13 15G@
RV65 15G@
F12 M12
2
VDDQ H12 VDDQ P12
DRAM_RST# J2 VDDQ K12 VDDQ T12
2 RESET# VDDQ M12 VDDQ G13
2
VDDQ P12 VDDQ L13

VDDQ T12 VDDQ B14
VDDQ G13 VDDQ D14
VDDQ L13 VDDQ F14
+1.35V_MEM_GFX VDDQ B14 VDDQ M14
VDDQ VDDQ
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
D14 G1 P14
VDDQ F14 L1 VDD VDDQ T14
CV46 15G@
CV284 15G@
CV281 15G@
CV297 15G@
CV291 15G@
M14 G4
VDDQ CV29215G@ VDD
CV29415G@
G1 P14 L4
L1 VDD VDDQ T14 C5 VDD A1
VDD VDDQ 2 2 2 2 2 2 2 VDD VSSQ
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
G4 R5 C1
L4 VDD C10 VDD VSSQ E1
1 1 1 1 1 VDD VDD VSSQ
CV45 15G@
CV286 15G@
CV199
C5 A1 R10 N1
VDD VSSQ VDD VSSQ
CV280 15G@
CV295 15G@
R5 C1 D11 R1
C10 VDD VSSQ E1 G11 VDD VSSQ U1
2 2 2 2 2 R10 VDD VSSQ N1 L11 VDD VSSQ H2
D11 VDD VSSQ R1 +1.35V_MEM_GFX P11 VDD VSSQ K2
15G@
G11 VDD VSSQ U1 G14 VDD VSSQ A3

B VDD VSSQ VDD VSSQ B
L11 H2 L14 C3
P11 VDD VSSQ K2 VDD VSSQ E3
VDD VSSQ VSSQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
G14 A3 N3
L14 VDD VSSQ C3 VSSQ R3
VDD VSSQ 1 1 1 1 VSSQ
CV200
CV287
E3 H1 U3
VSSQ VSS VSSQ
CV135 15G@
CV293 15G@
N3 K1 C4
VSSQ R3 B5 VSS VSSQ R4
H1 VSSQ U3 2 2 2 2 G5 VSS VSSQ F5
K1 VSS VSSQ C4 L5 VSS VSSQ M5
15G@
15G@
B5 VSS VSSQ R4 T5 VSS VSSQ F10
G5 VSS VSSQ F5 B10 VSS VSSQ M10
L5 VSS VSSQ M5 D10 VSS VSSQ C11
T5 VSS VSSQ F10 G10 VSS VSSQ R11
B10 VSS VSSQ M10 L10 VSS VSSQ A12
D10 VSS VSSQ C11 P10 VSS VSSQ C12
G10 VSS VSSQ R11 T10 VSS VSSQ E12
L10 VSS VSSQ A12 H14 VSS VSSQ N12
P10 VSS VSSQ C12 K14 VSS VSSQ R12
T10 VSS VSSQ E12 VSS170-BALL VSSQ U12
H14 VSS VSSQ N12 VSSQ H13
K14 VSS VSSQ R12 SGRAM GDDR5 VSSQ K13
VSS170-BALL VSSQ U12 VSSQ A14
VSSQ H13 VSSQ C14
SGRAM GDDR5 VSSQ K13 VSSQ E14
VSSQ A14 VSSQ N14
VSSQ C14 VSSQ R14
VSSQ E14 VSSQ U14
VSSQ N14 VSSQ
+1.35V_MEM_GFX +1.35V_MEM_GFX VSSQ R14 K4G20325FC-HC05_FBGA170~D
VSSQ U14 +1.35V_MEM_GFX +1.35V_MEM_GFX
VSSQ
15G@
1U_0402_6.3V6K
2.37K_0402_1%
1U_0402_6.3V6K
2.37K_0402_1%
K4G20325FC-HC05_FBGA170~D
1
1U_0402_6.3V6K
2.37K_0402_1%
1U_0402_6.3V6K
2.37K_0402_1%
1 1 15G@
1
1
CV19 15G@
RV3 15G@
CV21 15G@
RV6 15G@
1 1
CV26 15G@
RV10 15G@
CV28 15G@
RV12 15G@
2 2
A A
2
2 2
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VREFD5_2 VREFC5 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
VREFD6_2 VREFC6 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1U_0402_6.3V6K
5.49K_0402_1%
1U_0402_6.3V6K
5.49K_0402_1%
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
1U_0402_6.3V6K
5.49K_0402_1%
1U_0402_6.3V6K
5.49K_0402_1%
1 1
1
1
CV20 15G@
RV4 15G@
CV22 15G@
RV5 15G@
1 1
CV25 15G@
RV9 15G@
CV27 15G@
RV11 15G@
2 2
2
2 2
www.Vinafix.vn
2
Title
MARX-VRAM_B Lower
1.0
LA-9411P
5 4 3 2 1
A B C D E
Memory Partition B - Upper 16 bits UV10

NORMAL
MF=0 MF=1 MF=1 MF=0
UV9
MIRROR A4 DQB1_7
EDCB1_0 C2 DQ24 DQ0 A2 DQB1_4
MF=0 MF=1 MF=1 MF=0 <55> EDCB1_0 C13 EDC0 EDC3 DQ25 DQ1 B4 DQB1_6
EDCB1_3 R13 EDC1 EDC2 DQ26 DQ2 B2 DQB1_5
A4 DQB1_17 <55> EDCB1_3 R2 EDC2 EDC1 DQ27 DQ3 E4 DQB1_3
EDCB1_2 C2 DQ24 DQ0 A2 DQB1_18 EDC3 EDC0 DQ28 DQ4 E2 DQB1_2
<55> EDCB1_2 C13 EDC0 EDC3 DQ25 DQ1 B4 DQB1_16 DQ29 DQ5 F4 DQB1_0
EDCB1_1 R13 EDC1 EDC2 DQ26 DQ2 B2 DQB1_19 DDBIB1_0 D2 DQ30 DQ6 F2 DQB1_1
<55> EDCB1_1 R2 EDC2 EDC1 DQ27 DQ3 E4 DQB1_23 D13 DBI0# DBI3# DQ31 DQ7 A11
EDC3 EDC0 DQ28 DQ4 +1.35V_MEM_GFX DBI1# DBI2# DQ16 DQ8
E2 DQB1_20 DDBIB1_3 P13 A13
DQ29 DQ5 F4 DQB1_21 P2 DBI2# DBI1# DQ17 DQ9 B11
DDBIB1_2 D2 DQ30 DQ6 F2 DQB1_22 DBI3# DBI0# DQ18 DQ10 B13
1 DBI0# DBI3# DQ31 DQ7 DQ19 DQ11 1
D13 A11 CLKB1 J12 E11
+1.35V_MEM_GFX DBI1# DBI2# DQ16 DQ8 CK DQ20 DQ12
DDBIB1_1 P13 A13 CLKB1# J11 E13
P2 DBI2# DBI1# DQ17 DQ9 B11 CKEB1 J3 CK# DQ21 DQ13 F11
DBI3# DBI0# DQ18 DQ10 B13 CKE# DQ22 DQ14 F13
CLKB1 J12 DQ19 DQ11 E11 MAB1_8 J5 DQ23 DQ15 U11 DQB1_31
<55> CLKB1 J11 CK DQ20 DQ12 E13 A12/RFU/NC DQ8 DQ16 U13
CLKB1# DQB1_29
<55> CLKB1# J3 CK# DQ21 DQ13 F11 K4 DQ9 DQ17 T11
CKEB1 MAB1_7 DQB1_28
<55> CKEB1 CKE# DQ22 DQ14 F13 K5 A8/A7 A10/A0 DQ10 DQ18 T13
MAB1_6 DQB1_30
MAB1_8 J5 DQ23 DQ15 U11 DQB1_9 MAB1_5 K10 A11/A6 A9/A1 DQ11 DQ19 N11 DQB1_24
A12/RFU/NC DQ8 DQ16 U13 DQB1_11 MAB1_4 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 DQB1_27
MAB1_0 K4 DQ9 DQ17 T11 DQB1_10 BA2/A4 BA0/A2 DQ13 DQ21 M11 DQB1_25
MAB1_1 K5 A8/A7 A10/A0 DQ10 DQ18 T13 DQB1_12 MAB1_3 H10 DQ14 DQ22 M13 DQB1_26
MAB1_3 K10 A11/A6 A9/A1 DQ11 DQ19 N11 DQB1_8 MAB1_2 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 DQB1_[0..31]
K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 DQB1_[0..31] <55>
MAB1_2 DQB1_13 MAB1_1
BA2/A4 BA0/A2 DQ13 DQ21 M11 DQB1_14 MAB1_0 H4 A9/A1 A11/A6 DQ1 DQ25 T4 EDCB1_[0..3]
H10 DQ14 DQ22 M13 A10/A0 A8/A7 DQ2 DQ26 T2 EDCB1_[0..3] <55>
MAB1_5 DQB1_15
MAB1_4 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 DQ3 DQ27 N4 DDBIB1_[0..3]
H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 A5 DQ4 DQ28 N2 DDBIB1_[0..3] <55>
MAB1_6
MAB1_7 H4 A9/A1 A11/A6 DQ1 DQ25 T4 U5 VPP/NC DQ5 DQ29 M4 MAB1_[0..8]
A10/A0 A8/A7 DQ2 DQ26 T2 VPP/NC DQ6 DQ30 M2 MAB1_[0..8] <55>
DQ3 DQ27 N4 DQ7 DQ31
A5 DQ4 DQ28 N2 J1 +1.35V_MEM_GFX
U5 VPP/NC DQ5 DQ29 M4 J10 MF
VPP/NC DQ6 DQ30 M2 1 2 J13 SEN B1
+1.35V_MEM_GFX DQ7 DQ31 ZQ VDDQ
RV171 15G@ 121_0402_1% D1
J1 +1.35V_MEM_GFX VDDQ F1
J10 MF ADBIB1 J4 VDDQ M1
15G@ RV169 1 2 121_0402_1% J13 SEN B1 RASB1# G3 ABI# VDDQ P1
ZQ VDDQ D1 CSB1#_0 G12 RAS# CAS# VDDQ T1
VDDQ F1 CASB1# L3 CS# WE# VDDQ G2
ADBIB1 J4 VDDQ M1 +1.35V_MEM_GFX WEB1# L12 CAS# RAS# VDDQ L2
<55> ADBIB1 G3 ABI# VDDQ P1 WE# CS# VDDQ B3
CASB1#
<55> CASB1# G12 RAS# CAS# VDDQ T1 VDDQ D3
WEB1#
<55> WEB1# CS# WE# VDDQ VDDQ
1U_0402_6.3V6K
2.37K_0402_1%
RASB1# L3 G2 F3
<55> RASB1# CAS# RAS# VDDQ VDDQ
1
+1.35V_MEM_GFX CSB1#_0 L12 L2 1 WCKB1B_0 D5 H3
<55> CSB1#_0 WE# CS# VDDQ WCK01# WCK23# VDDQ
CV36 15G@
RV21 15G@
B3 WCKB1_0 D4 K3
VDDQ D3 WCK01 WCK23 VDDQ M3
2 VDDQ VDDQ 2
1U_0402_6.3V6K
2.37K_0402_1%
F3 WCKB1B_1 P5 P3
VDDQ WCK23# WCK01# VDDQ
1
WCKB1B_1 D5 H3 2 WCKB1_1 P4 T3
1 <55> WCKB1B_1 15G@ 15G@
2
WCK01# WCK23# VDDQ WCK23 WCK01 VDDQ
CV30 15G@
RV14 15G@
WCKB1_1 D4 K3 E5 15G@ 15G@ 15G@ 15G@

<55> WCKB1_1 WCK01 WCK23 VDDQ VDDQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
M3 N5
WCKB1B_0 P5 VDDQ P3 VREFD8_1 A10 VDDQ E10
2 <55> WCKB1B_0 WCK23# WCK01# VDDQ VREFD VDDQ 1 1 1 1 1 1
CV315
CV312
CV303
CV306
WCKB1_0 P4 T3 VREFD8_2 U10 N10
<55> WCKB1_0
2
1U_0402_6.3V6K
5.49K_0402_1%
CV298
CV310
E5 VREFC8 J14 B12
VDDQ VREFC VDDQ
1
N5 1 D12
VDDQ VDDQ 2 2 2 2 2 2
CV35 15G@
RV20 15G@
VREFD7_1 A10 E10 F12
VREFD7_2 U10 VREFD VDDQ N10 VDDQ H12
VREFD VDDQ VDDQ
1U_0402_6.3V6K
5.49K_0402_1%
VREFC7 J14 B12 DRAM_RST# J2 K12

VREFC VDDQ <55,56,57,58> DRAM_RST# RESET# VDDQ
1
D12 2 M12
1
2
VDDQ VDDQ
CV29 15G@
RV13 15G@
F12 P12
VDDQ H12 VDDQ T12
DRAM_RST# J2 VDDQ K12 VDDQ G13
2 RESET# VDDQ M12 VDDQ L13
2
VDDQ P12 VDDQ B14

VDDQ T12 VDDQ D14
VDDQ G13 VDDQ F14
VDDQ L13 VDDQ M14
+1.35V_MEM_GFX VDDQ B14 G1 VDDQ P14
VDDQ VDD VDDQ
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
D14 L1 T14
VDDQ F14 G4 VDD VDDQ
VDDQ 1 1 1 1 1 1 1 VDD
CV47 15G@
CV309 15G@
CV301 15G@
CV305 15G@
CV319 15G@
M14 L4
VDDQ VDD
CV299 15G@
CV302 15G@
G1 P14 C5 A1
L1 VDD VDDQ T14 R5 VDD VSSQ C1
G4 VDD VDDQ 2 2 2 2 2 2 2 C10 VDD VSSQ E1
L4 VDD R10 VDD VSSQ N1
C5 VDD A1 D11 VDD VSSQ R1
R5 VDD VSSQ C1 G11 VDD VSSQ U1
VDD VSSQ VDD VSSQ
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
C10 E1 L11 H2
R10 VDD VSSQ N1 +1.35V_MEM_GFX P11 VDD VSSQ K2
CV48 15G@
CV318 15G@
CV307 15G@
D11 R1 G14 A3
VDD VSSQ VDD VSSQ
CV304 15G@
CV313 15G@
G11 U1 L14 C3
L11 VDD VSSQ H2 VDD VSSQ E3
2 2 2 2 2 P11 VDD VSSQ K2 VSSQ N3
VDD VSSQ VSSQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
3
G14 A3 R3 3
L14 VDD VSSQ C3 H1 VSSQ U3
VDD VSSQ 1 1 1 1 VSS VSSQ
CV308
CV316
E3 K1 C4
VSSQ CV311 VSS VSSQ
CV320
N3 B5 R4
VSSQ R3 G5 VSS VSSQ F5
H1 VSSQ U3 2 2 2 2 L5 VSS VSSQ M5
K1 VSS VSSQ C4 T5 VSS VSSQ F10
B5 VSS VSSQ R4 B10 VSS VSSQ M10
G5 VSS VSSQ F5 D10 VSS VSSQ C11
L5 VSS VSSQ M5 15G@ 15G@ G10 VSS VSSQ R11
T5 VSS VSSQ F10 15G@ 15G@ L10 VSS VSSQ A12
B10 VSS VSSQ M10 P10 VSS VSSQ C12
D10 VSS VSSQ C11 T10 VSS VSSQ E12
G10 VSS VSSQ R11 H14 VSS VSSQ N12
L10 VSS VSSQ A12 K14 VSS VSSQ R12
P10 VSS VSSQ C12 VSS170-BALL VSSQ U12
T10 VSS VSSQ E12 VSSQ H13
H14 VSS VSSQ N12 SGRAM GDDR5 VSSQ K13
K14 VSS VSSQ R12 VSSQ A14
VSS170-BALL VSSQ U12 VSSQ C14
VSSQ H13 VSSQ E14
SGRAM GDDR5 VSSQ K13 VSSQ N14
VSSQ A14 VSSQ R14
VSSQ C14 VSSQ U14
VSSQ E14 VSSQ
VSSQ N14 K4G20325FC-HC05_FBGA170~D
VSSQ R14
VSSQ U14
VSSQ 15G@
+1.35V_MEM_GFX +1.35V_MEM_GFX K4G20325FC-HC05_FBGA170~D +1.35V_MEM_GFX +1.35V_MEM_GFX
15G@
1U_0402_6.3V6K
2.37K_0402_1%
1U_0402_6.3V6K
2.37K_0402_1%
1U_0402_6.3V6K
2.37K_0402_1%
1U_0402_6.3V6K
2.37K_0402_1%
1
1 1 1 1
CV32 15G@
RV16 15G@
CV34 15G@
RV19 15G@
CV38 15G@
RV23 15G@
CV40 15G@
RV27 15G@
2 2 2 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
4 4
2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
VREFD7_2 VREFC7 VREFD8_2 VREFC8 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1U_0402_6.3V6K
5.49K_0402_1%
1U_0402_6.3V6K
5.49K_0402_1%
1U_0402_6.3V6K
5.49K_0402_1%
1U_0402_6.3V6K
5.49K_0402_1%
1
1 1 1 1
CV31 15G@
RV15 15G@
CV33 15G@
RV17 15G@
CV37 15G@
RV22 15G@
CV39 15G@
RV24 15G@
2 2 2 2
2
www.Vinafix.vn
Title
MARX-VRAM_B Upper
1.0
LA-9411P
A B C D E
5 4 3 2 1
ESD Diodes
1
PD1 @EMC@
6
All de-pop for droop module media battery +COINCELL
V I/O V I/O
2
Ground V BUS
5 COIN RTC Battery
1
3 4
V I/O V I/O PR1
IP4223CZ6_SO6~D @ PL1 +3.3V_ALW 1K_0402_5%
FBMJ4516HS720NT_2P~D +3.3V_RTC_LDO
1 2
2
Media Bay Battery Connector
@ JRTC1
Z4012
1
@ PJP1 1
100K_0402_5%
+COINCELL
+MBATT_C 2 1 2 1
+MBATT
@ MBATT1 @ PR4 3 2
PR2
0.1U_0603_25V7K
4 G1
1
D D
1 100_0402_5%~D @ PR3 PAD-OPEN 1x2m
1 G2
2
2 Z5304 1 2
PC1
100_0402_5%~D @ PR5
BAY_SMBCLK <32,46>
2
2 3 Z5305 1 2 100_0402_5%~D +RTC_CELL ACES_50273-0020N-001
BAY_SMBDAT <32,46>
2
3 4 Z5306 1 2 @
2200P_0402_50V7K
4 MODULE_BATT_PRES# <45,70>
5
5 6
6
1
PC2
PD3
1
7
@ GND 8 BAS40-05W_SC70-3~D 1
2
GND PC3
1U_0603_10V4Z~D
OCTEK_BTJ-06LDFB
2
ESD Diodes
GND
1
PD2 PD4 PL2 EMC@
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3 FBMJ4516HS720NT_2P~D +3.3V_ALW
1 2
Primary Battery Connector

2
3
PL3 EMC@
1
@ FBMJ4516HS720NT_2P~D
100K_0402_5%
PBATT1 1 2
+PBATT_C +PBATT
11
PR6
0.1U_0603_25V7K
GND
1
10
GND 9 PR7
PC4
2
9 8 100_0402_5%~D PR8
2
8 7 Z4304 1 2 100_0402_5%~D
2200P_0402_50V7K
7 PBAT_SMBCLK <46>
6 Z4305 1 2
@EMC@
6 5 1 2 PBAT_SMBDAT <46>
Z4306
5 PBAT_PRES# <45,70>
1
4 PR9
EMC@ PC5
4 3 100_0402_5%~D
3 2
2
2 1
C C
1
OCTEK_BTJ-09WKFB
PQ7 DMG2301U-7_SOT23-3
1 2 1 3
S
DOCK_SMB_ALERT# <45,70>
PD7
GND SDMK0340L-7-F_SOD323-2~D
G
2
PR26
0_0402_5%~D
1 2
<44,45,70> SLICE_BAT_PRES#
1500P_0402_7K~D
1
PC17
2
+3.3V_ALW
@ PR10
2.2K_0402_5%
2
1 2
0_0402_5%~D
PR11
PL4 EMC@ PR12
1
BLM18BD102SN1D_0603~D 33_0402_5% PU1 74LVC1G3157GW_SC-88-6
NB_PSID 2 1 1 3 1 2 NB_PSID_TS5A63157 3 5
S
D
Y0 VCC +5V_ALW
1 4
PQ1 <44> DOCK_PSID Y1 Z PS_ID <46>
6 2
100K_0402_1%
<45> GPIO_PSID_SELECT S GND

2
FDV301N-G_SOT23-3~D
+5V_ALW
PR13
G
2
10K_0402_1%
1
1
B B
C
2 PQ2
PR14
B MMST3904-7-F_SOT323-3~D
E
15K_0402_1%
3
2
2
PR15
PR16
1 2 @ PJP7
PSID_DISABLE# <45> 2 1
1
@ 10K_0402_5%~D
PAD-OPEN 1x2m
+PWR_SRC +PWR_SRC_S
DC_IN+ Source 3 1
100K_0402_1%
0.1U_0603_25V7K
0.22U_0603_25V7K
1
1
@ PC6
@ PC7
+DC_IN PQ4 +DC_IN_SS
@ PR17
PL5 EMC@ FDS6679AZ-G_SO8~D
FBMA-L11-453215800LMA90T_2P
2
1 2 +DC_IN 1 8
@
2 7 PQ3
3
@
3 6 PR19 TP0610K-T1-GE3_SOT23-3
IMD2AT-108_SC74-6~D
5 22K_0402_1%
@
PR21 1 2 VSB_N_001
2
1
0.022U_0805_50V7K~D
2 0_0402_5%
PQ6B
1VSB_N_003
1M_0402_5%
1 2
PC8
100K_0402_5%
<46,48> PCH_ALW_ON
10U_0805_25V6K
0.1U_0603_25V7K
0.1U_0603_25V7K
0.1U_0603_25V7K
1
1
PR18
1
1
PC14 @EMC@
@
PC9
PC12 EMC@
PR24
@ PC10
@ PC11
PR20
PC13
0.1U_0603_25V7K
2
1
PR23 0_0402_5% D
4.7K_0805_5%~D
1000P_0603_50V7K
2
IMD2AT-108_SC74-6~D
1
JESS_UCNR2451M005-0
@
1 2 +3.3V_ALW 1 2VSB_N_002 2 PQ5
SOFT_START_GC <70>
2
5 DMN65D8LW-7 1N SOT323-3
@EMC@
G
2
5 4 -DCIN_JACK 10K_0402_5%
@ PR22
.1U_0402_16V7K
2
3
4 3
1
@ PC15
1M_0402_5%
3 2 +DCIN_JACK 5
PQ6A
AC_DIS <45,70>
2
2 1
PR25
A A
2
1
@ PJPDC1
2
6
@ PJP4
1 2
PAD-OPEN 4x4m
0.1U_0603_25V7K
1

@EMC@ PC16
www.Vinafix.vn
Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D PWR_+DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 0.4
LA-9411P
5 4 3 2 1
A B C D E
VFB2=2V,PR100=(Vout-0.5*Vripple-2)/2*PR102 +3.3V_ALW2
+3.3V_RTC_LDO VFB1=2V,PR101=(Vout-0.5*Vripple-2)/2*PR104
PR100
6.49K_0402_1%
1 2 PR101
15K_0402_1%
1 2 1 1
1U_0603_10V5K
PR102 PR104
2
0_0402_5%~D
10K_0402_1% 10K_0402_1%
1
PR103
PC114
1 2 2 1
2
1
97.6K_0402_1%
2
@ PJP104
115K_0402_1%
+DC1_PWR_SRC
PR106
1 2
PR105
PAD-OPEN 4x4m +DC1_PWR_SRC +3.3V_ALW
1
<35,46> ALW_PWRGD_3V_5V
1
110K_0402_1%
PL103 EMC@
PC103 @EMC@
PC108 @EMC@
1UH_MMD-05CZ-1R0M-M7L_7A_20%
2200P_0402_50V7K
PR119
1 2 PU100
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
1
PC109
PC104
+PWR_SRC
CS2
VFB2
VREG3
VFB1
CS1
PC105 @EMC@
PC106 @EMC@
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
21
SIS412DN-T1-GE3_POWERPAK8-5~D
1
PAD
1
1
PC110
PC107
3V_5V_EN 6
2
EN2
5
PR118 14 @
VO1
5
0_0402_5%~D @ PR111
2
1 2 7 200_0402_1%
PGOOD
PQ101
@ 19 2 1
VCLK
PQ102
4 UG_3V 10 TPS51225CRUKR_QFN20_3X3
PC112 PR108 DRVH2 16 UG_5V 4
0.1U_0603_25V7K 2.2_0603_5% DRVH1 PR107 PC111
1 2 1 2 BST_3V 9 2.2_0603_5% 0.1U_0603_25V7K
VBST2 17 BST_5V 1 2 1 2
1
2
3
2 VBST1 2
3
2
1
SW2 8
SW2 18 SW1
VREG5
DRVL2
DRVL1
PL101 SW1 PL102
+3VALWP +5VALWP
EN1
VIN
2.2UH_FDSD0630-H-2R2M-P3_8.3A_20% 3.3UH_FDSD0630-H-3R3M-P3_6.6A_20%
1 2 1 2
11
12
13
3V_5V_EN 20
15
SIS472DN-T1_POWERPAK1212-8-5
1
1
4.7_1206_5%
4.7_1206_5%
LG_3V LG_5V
@EMC@
@EMC@
PR109
PR112
1
+ PC101 1
PQ103
220U_6.3V_M PC102
1 SNUB_3V 2
1 SNUB_5V 2
PQ104
4 4 + 220U_6.3V_M
2
1U_0603_10V5K
0.1U_0603_25V7K
680P_0603_50V7K
680P_0603_50V7K
1
2
3
3
2
1
1
@EMC@
PC117
PC118
@EMC@
PC116
PC119
2
2
2
2
+DC1_PWR_SRC +5V_ALW2
3 3
3V_5V_EN
PR110
0_0402_5%~D
1 2
<46> ALWON
5VALWP
3VALWP Ripple voltage -
Ripple voltage - Static load 3% / Dynamic load 5%
Static load 3% / Dynamic load 5% Frequency 300kHz
1U_0603_10V6K
Frequency 350kHz TDC 5.613A

1
@ PJP100 @ PJP101
PC120
TDC 7.33A +3VALWP

1 2 +3.3V_ALW +5VALWP
1 2
+5V_ALW Peak Current 8A
2
Peak Current 10.48A @

PAD-OPEN 4x4m PAD-OPEN 4x4m OCP current 9.6A
OCP current 12.57A @ PJP102 @ PJP103 TYP MAX
1 2 1 2
TYP MAX H/S Rds(on) 24mohm , 30mohm
H/S Rds(on) 24mohm , 30mohm PAD-OPEN 4x4m PAD-OPEN 4x4m L/S Rds(on) 10.3mohm , 12.4mohm
L/S Rds(on) 10.3mohm , 12.4mohm Choke DCR Max:28mohm
Choke DCR Max:17mohm Choke Ityp:6.6A / Isat:8.2A
4 Choke Ityp:8.3A / Isat:10.8A Bulk cap ESR 15mohm 4
Bulk cap ESR 15mohm
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/01/17 Deciphered Date 2013/01/16 Title
www.Vinafix.vn
PWR_3VALWP/5VALWP
0.4
LA-9411P
A B C D E
5 4 3 2 1
@
0.675Volt +/- 5%
PJP201
VLDOIN_1.35V 2 1 +1.35V_MEN_P TDC 0.525A
Peak Current 0.75A
+PWR_SRC @ PJP200
PR200
PAD-OPEN1x1m
2 1 1.35V_B+ 1 2 BOOT_1.35V
2 1
2.2_0603_5%
JUMP_43X118
@EMC@
@EMC@
DH_1.35V
10U_0805_25V6K
2200P_0402_50V7K
0.1U_0402_25V6
D D
4.7U_0805_25V6-K
+0.675V_P
2
SIR472DP-T1-GE3_POWERPAK8-5~D
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
PC206 SW _1.35V
5
PC202
PC203
PC204
PC205
0.22U_0603_10V7K
1
2
1
DL_1.35V
PC207
PC208
16
17
18
19
20
@ PU200
PQ201
VLDOIN
PHASE
UGATE
BOOT
VTT
2
4 21
PAD
15 1
LGATE VTTGND
1
2
3
PR201 14 2
+1.35V_MEN_P PL201 8.25K_0402_1% PGND VTTSNS +V_DDR_REF
1UH_FDUE1040D-H-1R0M-P3_21.3A_20%~D 1 2 CS_1.35V
1 2 13 3
PC213 CS RT8207MZQW _W QFN20_3X3 GND
5
PR202 @EMC@
1U_0603_10V6K
4.7_1206_5%
SIRA06DP-T1-GE_POWERPAKSO-8-5
PR203 2 1 VDDP_1.35V 12 4 +V_DDR_REF
5.1_0603_5% VDDP VTTREF
220U_D2_4VM
1 1
+ + 1 2 11 5
PQ203
PC201 VDD_1.35V PC209
PC216
SNUB_1.35V 2 VDD VDDQ +1.35V_MEN_P
PGOOD
390U_2.5V_M 4 0.033U_0402_16V7~D
TON
@ 2 2 +5V_ALW PC210
FB
S5
S3
1U_0603_10V6K
2
PC212 @EMC@
680P_0603_50V7K
3
2
1
10
6
C C
+3.3V_ALW +5V_ALW
1
PC211 220P_0402_50V8J~D
1 2
2
1
PR209
100K_0402_1% PR204
8.06K_0402_1%
1.35V_FB 1 2
2
<7,46> 1.35V_SUS_PW RGD
PR205
1M_0402_1%
2
@ PR206 1.35V_B+ 1 2
1
200K_0402_5% PR207
1 2 S5_1.35V 10K_0402_1% PC214
<16,35,45,48> SIO_SLP_S4#
1
@ .1U_0402_16V7K
2
@ PC215 PR208
1
PR210 1U_0402_6.3VX5R 0_0402_5%~D
2
0_0402_5%~D 1 2 S3_1.35V
<45> 0.75V_DDR_VTT_ON
1 2
<45,48> SUS_ON
1.35VP
Ripple voltage -
B
Static load 3% / Dynamic load 5% +1.35V_MEN_P
B
Frequency 250kHz
TDC 13A @ PJP203
VFB=0.75V, 1.35= 0.75*(1+PR204/PR207)
Peak Current 18.67A 2
2 1
1 FB sense trace
OCP current 22.4A JUMP_1x3m
TYP MAX @ PJP204

+1.35V_MEN_P 2 1 +1.35V_MEM
H/S Rds(on) :12.2mohm , 15mohm 2 1
JUMP_1x3m
L/S Rds(on) :2.75mohm , 3.5mohm
Choke DCR 2.35mohm @
PJP202
Choke Ityp:21.3 / Isat:22.4A +0.675V_P 2 1 +0.675V_DDR_VTT
Bulk cap ESR 10mohm
PAD-OPEN1x1m
A A
PWR_1.35V/0.675VSP
www.Vinafix.vn
0.4
LA-9411P
Date: W ednesday, April 10, 2013 Sheet 62 of 77
5 4 3 2 1
5 4 3 2 1
@ PJP300
+1.05VSP_B+ 2 1
+PWR_SRC
PAD-OPEN 1x2m~D
PC302 @EMC@
PC303 @EMC@
+3.3V_ALW
2200P_0402_50V7K
4.7U_0805_25V6-K
10U_0805_25V6K
0.1U_0402_25V6
1
PC305
PC304
2
D D
2
5
PR300
100K_0402_5% @
PQ301
1
<46> 1.05V_A_PW RGD
4
PC306
PU300 .1U_0603_25V7K
PR301
1 10 BST_+1.05VSP 1 2 2 1
3
2
1
PGOOD VBST
PR302 2.2_0603_5%
1 2 TRIP_+1.05VSP 2 9 UG_+1.05VSP PL301
TRIP DRVH 1UH_FDSD0630-H-1R0M-P3_11A_20%
100K_0402_1%
@ PR303 EN_+1.05VSP 3 8 SW _+1.05VSP 1 2
150K_0402_5% EN SW
+1.05V_MP
1 2 FB_+1.05VSP 4 7 +1.05VSP_5V
<16,35,45,48> SIO_SLP_A# VFB V5IN +5V_ALW
PR308 RF_+1.05VSP 5 6 LG_+1.05VSP 1
TST DRVL
1
0_0402_5%~D 1 2
1 2 11 + PC301
<46,48> A_ON TP
1
PC308 PR304 @EMC@ 390U_2.5V_M

1
@ PC307 TPS51212DSCR_SON10_3X3 1U_0603_10V6K 4.7_1206_5%

2
PQ303
0.22U_0402_16V7K
2
1SNUB_1.05V 2
PR305 4
470K_0402_1%
2
3
2
1
C C
PC309 @EMC@
1000P_0603_50V7K
2
PR306
4.99K_0402_1%
2 1
Vout=0.7*(1+PR306/PR307)
2
PR307 @ PJP301
10K_0402_1% 2 1
PAD-OPEN 1x2m~D
1
@ PJP302
+1.05V_MP 2 1 +1.05V_M
B PAD-OPEN 1x2m~D B
+1.05VSP
Ripple voltage -
Static load 3% / Dynamic load 5%
Frequency 290kHz
TDC 4.64A
Peak Current 6.5A
OCP current 7.8A
TYP MAX
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 10.3mohm ,12.4mohm
Choke DCR 11mohm
Choke Ityp:11A / Isat:14.5A
Bulk cap ESR 10mohm
A A
PWR_1.05VSP
www.Vinafix.vn
0.4
LA-9411P
Date: W ednesday, April 10, 2013 Sheet 63 of 77
5 4 3 2 1
A B C D
+1.5VSP
Ripple voltage -
1
Frequency 1MHz 1
TDC 1.329A
Peak Current 1.9A
@
OCP current 2.3A
PR400
Choke DCR 27mohm
2 1
+3.3V_RUN
Choke Ityp:3.2A / Isat:4A
10K_0402_5%
PU400 PL401
4
@ PJP400 1UH_NRS4018T1R0NDGJ_3.2A_30%
+3.3V_ALW 2 1 1.5VSP_VIN 10 2 1.5VSP_LX 1 2
PG
PVIN LX +1.5V_RUNP
PR401 @EMC@
22P_0402_50V8J
PAD-OPEN 1x2m~D 9 3
PVIN LX
PC405 @EMC@
1
1
4.7_0805_5%
2 2
PC402
PC400 PC401 @EMC@ 8
22U_0805_6.3VAM 0.1U_0402_25V6 SVIN PR402
6 1.5VSP_FB 30.1K_0402_1%
2
FB
47P_0402_50V8J
22U_0805_6.3VAM
22U_0805_6.3VAM
5
2
EN
1
NC
NC
TP
PC403
PC404
11
2
SNUB_1.5VSP
1 2 EN_1.5VSP
<11,16,35,39,40,45,48,66> SIO_SLP_S3#
1
1
.1U_0402_16V7K
@ PR403
PC406
0_0402_5% SYN470DBC_DFN10_3X3 PR405
1
@ PR404 20K_0402_1%
1M_0402_5%
2
PC407 @EMC@
1 2 @
<39,45,48> RUN_ON
680P_0402_50V7K
PR406
0_0402_5%~D
2
<Vo=1.5V> VFB=0.6V
3
Vo=VFB*(1+PR402/PR405)=0.6*(1+30.1K/20K)=1.5V 3
@PJP401
@ PJP401
2 1
+1.5V_RUNP +1.5V_RUN
PAD-OPEN 1x2m~D
4
DELL CONFIDENTIAL/PROPRIETARY 4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_+1.5VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9411P
A B C D
www.Vinafix.vn
5 4 3 2 1
PR507=21K, FW=400KHZ / VBOOT 1.7V

+5V_RUN CPU_B+
PC504 @EMC@
PC507 @EMC@
2
PC548 1U_0402_6.3V6K
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K~D
1 2 PC501 @
5
1U_0603_10V6K
0.22U_0603_16V7K PQ501 PQ502
1
1
2
1
PC502
PC503
PC505
PC506
1
PR501
2
+VCCIO_OUT PR500 130_0402_1% 0_0402_5%~D PR502
2
2 1 2.2_0603_5% 4 4
1
@ PR503 75_0402_5%
2
2 1
D PU501 D
3
2
1
3
2
1
PR504 54.9_0402_1% 6 1 UGATE3
2 1 VCC UGATE PL501
7 2 BOOT3 0.22UH_PCME064T-R22MS_28A_20%
FCCM BOOT
PR505 0_0402_5%~D PWM3 3
PWM PHASE
8 PHASE3 4 1 +VCC_CORE
680P_0603_50V7K
1 2 PR507
<11> VIDSOUT
5
PR506 0_0402_5%~D 21K_0402_1% 4 5 LGATE3 @ PQ503 PQ504 P3_SW 3 2 V3N
GND LGATE
@EMC@ PC508
<11> VIDALERT_N 1 2 1 2 9
PR508 0_0402_5%~D TP PR510
<11> VIDSCLK 1 2 PR509 ISL6208BCRZ-T_QFN8_2X2 100K_0603_1%
2
PR513 @EMC@
3.24K_0402_1% 2 1
1 2 4 4
4.7_1206_5%
3.65K_0603_1%
ISEN3
10_0402_1%
PR511 PR512
PR514
PR515
0_0402_5%~D 16.9K_0402_1% @ PR516
<45> IMVP_VR_ON 1 2 1 2 1_0402_5%
1
2
3
1
2
3
V1N 1 2
+5V_ALW
1
BOOT2 @ PR518
UGATE2 1_0402_5%
ISUMP
PR519 1.91K_0402_1% PHASE2 V2N 1 2
ISUMN
2 1 SDA PR520
+3.3V_RUN ALERT# 0_0402_5%~D VCC_core (Base on PDDG rev 1.1)
<45> IMVP_PWRGD PC509
1U_0603_10V6K TDC 27A
32
31
30
29
28
27
26
25
VCORE_VDDP 1
1 2
PC500 Peak Current 85A Bulk cap 470u 4.5mohm *4
SDA
ALERT#
SLOPE/PROG1
PROG3
PROG2
BOOT2
UGATE2
PHASE2
1 2
DC Load line -1.5mV/A MLCC 10u *11 / 22u *19
1000P_0402_50V8-J PR522
0_0402_5%~D SCLK 1 24 LGATE2 @ Icc_Dyn_VID1 60A
SCLK LGATE2 PR523
PR521
100K_0402_1% 1 2 VCC_PGOOD
VR_ON 2
3 VR_ON VDDP
23
22 PWM3 2 1
OCP current 102A TYP MAX
PGOOD PWM3
C
2 1 IMON 4
IMON LGATE1
21 LGATE1 0_0402_5%~D Choke DCR 0.97m ohm H/S Rds(on) :12.2mohm , 15mohm C
PR524 0_0402_5%~D 5 20 PHASE1
1 2 VR_HOT# NTC 6 VR_HOT#
NTC
PHASE1
UGATE1
19 UGATE1 Choke Ityp:19A / Isat:25A L/S Rds(on) :2.75mohm , 3.5mohm
COMP 7 18 BOOT1
PR525 FB 8 COMP BOOT1 17
<7,46,69,70> H_PROCHOT#
1 2 2 1 FB VIN PR526 +PWR_SRC
FB2/VSEN
PH500 0_0402_5%~D
ISUMN
ISUMP
ISEN3
ISEN2
ISEN1
3.83K_0402_1% 470K_0402_5%_ TSM0B474J4702RE 33 1 2CPU_B+ PL504 @EMC@
VDD
RTN
+1.05V_RUN PAD
PC515 @EMC@
@ PR527 FBMA-L11-453215800LMA90T_2P
0.22U_0603_25V7K
PC516 EMC@
1 2 PR528 CPU_B+ 1 2
470P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K~D
27.4K_0402_1% 9 PU500
10
11
12
13
14
15
16
5
47P_0402_50V8J~D
0_0402_5% 2 1 PR529 ISL95812HRZ-T_QFN32_4x4 @ PJP500

PC510
1 2 PQ505 @ PQ506 2 1
2 1
1
1
PC511
PC512
PC513
PC514
2
6.04K_0402_1% JUMP_43X118
2
2
UGATE2 4 4
2
0_0402_5%
PR530
+5V_ALW
PR531
@ PC517 1_0402_1%
2 1 FB2/VSEN 1 2 PL502
0.22UH_PCME064T-R22MS_28A_20%
3
2
1
3
2
1
4700P_0402_50V7K~D
39P_0402_50V8J @
1
1
PC520 PHASE2 4 1
+VCC_CORE
680P_0603_50V7K
@ PC519 @ PR532 PR533 390PF_0402_50V7K~D PC518
PC524 @EMC@
COMP 2 1 2 1 FB 2 1 2 1 1U_0603_10V6K PR536 3 2
2
1
1
PC521
PR534 @ PQ507 PQ508 3.65K_0603_1% P2_SW V2N

1800P_0402_50V8F~D 130K_0402_1% 10_0402_1% BOOT2 2 1 1 2 1 2
470_0402_1%
PR541 @EMC@
2.2_0603_5% PR538
2
2
1
@ PC523 PR537 PC522 100K_0603_1%

0_0402_5%~D
PR535
2 1 2 1 0.22U_0603_16V7K 1 2
2
1
909_0402_1%
4.7_1206_5%
LGATE2 4 4
2
1
PR540
22P_0402_50V8J~D 2.55K_0402_1% ISEN2

2
2
154K_0402_1%
PR539
@ PR546 PR544
2
2
4.3M_0402_1%
1.5K_0402_1%
ISUMP
PR542
PR543 <BOM Structure> 1_0402_5% 10_0402_1%

2
PR545
PR558
2K_0402_1% V1N 2 1
1
1
2
3
1
2
3
2
B PC525 B
2 1
2
@ 56P_0402_50V8~D @ PR547
1
2 1
4700P_0402_50V7K~D
1_0402_5%
1
ISUMN
PC526
V3N 2 1
PC527
1
330P_0402_50V7K~D
1
PC528
PC536 @EMC@
PC537 @EMC@
0.1U_0402_10V6K CPU_B+
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K~D
1 2 1 1 1
100U_25V_M~D
100U_25V_M~D
100U_25V_M~D
@
PC530
+
PC531
+
PC532
ISEN3 PQ509 PQ510 +
1
PC533
PC534
PC535
PC529
.1U_0603_16V7K~D
ISEN2 PR548 1 2 2 2 2
2
0_0402_5%~D UGATE1 4 4
1 2
ISEN1 PC538
0.033U_0603_16V6K~D PL503
PC539 1 2 0.22UH_PCME064T-R22MS_28A_20%
3
2
1
3
2
1
0.022U_0402_25V7K
<11> VCCSENSE
2 1 PHASE1 4 1
+VCC_CORE
680P_0603_50V7K
PR549
PC543 @EMC@
PC540 11K_0402_1% 3 2
5
1
0.022U_0402_25V7K @ PC541 1 2 PR550 @ PQ511 PQ512 P1_SW V1N
PR554 @EMC@
2 1 ISUMN 1 2 BOOT1 2 1 1 2
0.082U_0402_16V7K
PR551 2.2_0603_5% PR552 PR553
2
PC545
PC544 330P_0402_50V7K PH501 PC542 3.65K_0603_1% 100K_0603_1%

1
0.022U_0402_25V7K 10KB_0402_5%_ERTJ0ER103J 2.61K_0402_1% 0.22U_0603_16V7K 1 2 1 2
1
4.7_1206_5%
2 1 1 2 1 2 LGATE1 4 4
ISEN1
2
1
ISUMP
PC546 @
1 2 @ PR555 PR556
.1U_0402_16V7K
ISUMP V2N 2 1 10_0402_1%

1
2
3
1
2
3
2
1
A A
0.01U_0402_50V7K 1_0402_5%
PC547
ISUMN 2
ISUMN @ PR557
2
V3N 2 1
<11> VSSSENSE
10K_0402_1%
Local sense put on HW site DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
www.Vinafix.vn
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_VCORE_ISL95812 for QC
5 4 3 2 1
5 4 3 2 1
Initial voltage is 0.85V +VGA_B+

+3.3V_RUN_GFX @ PJP600
2 1
2 1 +PWR_SRC
@ PR601 10K_0402_1%~D PR602 10K_0402_1% JUMP_43X118
1 2 1 2
PC601 @EMC@
PC602 @EMC@
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
0.1U_0603_25V7K
@ PR603 10K_0402_1%~D PR604 10K_0402_1%
1
1 2 1 2
PC603
PC604
PR600 PR605 10K_0402_1% @ PR606 10K_0402_1%~D
2
0_0402_5%~D 1 2 1 2
5
1 2
<67,68> DGPU_PWR_EN
@ PR609 10K_0402_1%~D PR608 10K_0402_1%
@ PR607 1 2 1 2
10K_0402_1%
D D
1 2 PR610 10K_0402_1% @ PR611 10K_0402_1%~D
PQ600
PQ601
<11,16,35,39,40,45,48,64> SIO_SLP_S3#
1 2 1 2 4 4
@ PC600
22P_0402_50V8J PR612 10K_0402_1% @ PR613 10K_0402_1%~D
GNDA_GPU_CORE 1 2 1 2 1 2 PR614 PC605 @
2.2_0603_5% 0.22U_0603_10V7K +VGA_COREP
3
2
1
3
2
1
BOOT2_VGA 2 1 BOOT2_2_VGA1 2
DPRSLPVR_R PR615 1K_0402_1% PL600
PR616 2 1 UGATE2_VGA 0.22UH_PCME064T_R22MS_28A_20%
10K_0402_1%
1 2 2 1 PHASE2_VGA 4 1
GNDA_GPU_CORE GPU_VID_4 <50>
@EMC@
0_0402_5%~D PR617 V2P_VGA 3 2 V2N_VGA
5
2 1 PQ602 PQ603
4.7_1206_5%
10K_0402_5%
3.65K_0402_1%
GPU_VID_3 <50>
1
+3.3V_RUN @ PR620 0_0402_5%~D PR618 PR624
PR619
1 1
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1.91K_0402_1% 2 1 1_0402_5%
PR622
PR623
GPU_VID_2 <50> + +
1 2 CLK_ENABLE#_VGA @ PR626
PC606
PC677
0_0402_5%~D PR621 LGATE2_VGA 4 4 0_0402_5%
1SNUB_GPU_P2 2
2
1
2 1 1 2 V1N_VGA
GPU_VID_1 <50> 2 2
PR627
PR629 1.91K_0402_1% 0_0402_5%~D PR625
@EMC@
0_0402_5%~D 2 1 VSUM+_VGA VSUM-_VGA
GPU_VID_0 <50>
1
2
3
1
2
3
680P_0603_50V7K
2
1 2 0_0402_5%~D PR628 ISEN2_VGA

,45,67> DGPU_PWROK
@ PR631 0_0402_5%~D
PC607
<50> GPU_PSI# 1 2
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
2
+3.3V_RUN 2 1 VID6
VID0
PR691 10K_0402_1% PR632
47K_0402_1%
VCC_GFXCORE
GNDA_GPU_CORE
2 1 Frequency 300kHz
@ PR633 PC608 TDC 38A
0_0402_5% 1U_0603_10V6K
VID4 VID3 VID2 VID1 VID0 Vo
40
39
38
37
36
35
34
33
32
31
C 2 1 PU600 1 2 Peak Current 57A C

<50> GPU_HOT#
0 1 1 0 1 1.175 OCP current 68.4A
CLK_EN#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON
BOOT2
30 0 1 1 1 0 1.15 TYP MAX
GNDA_GPU_CORE 29
1 UGATE2 28 0 1 1 1 1 1.125 H/S Rds(on) :12.2mohm , 15mohm
2 PGOOD PHASE2 27
PR634 PH600 3 PSI# VSSP2 26
1 0 0 0 0 1.1 L/S Rds(on) :2.75mohm , 3.5mohm
RBIAS LGATE2
1.4K_0402_1% 470K_0402_5%_TSM0B474J4702RE 4
VR_TT# VCCP
25 PR636 0_0402_5%~D 1 2
+5V_ALW 1 0 0 0 1 1.075 Choke DCR 0.97mohm
2 1 1 2 5 24 1 2
6 NTC
VW
PWM3
LGATE1
23 PR635 1 0 0 1 0 1.05 Choke Ityp:19A / Isat:25A
7 22 0_0402_5%~D
8 COMP VSSP1 21 1 0 0 1 1 1.025
FB PHASE1
1 2 9
ISEN3 1 0 1 0 0 1 Bulk cap 470u 4.5mohm *4
UGATE1
10
BOOT1
ISUM+
ISEN2
1
1 0 1 0 1 0.975
ISEN1
ISUM-
MLCC 1u *30 / 10u *4

VSEN
IMON
@ PC609 PC610
8.06K_0402_1%
VDD
1000P_0402_50V7K
RTN
VIN
22P_0402_50V8J 41 1U_0603_10V6K
249K_0402_1%
AGND 1 0 1 1 0 0.95
2
PC611
ISL62883CHRTZ-T_TQFN40_5X5
@ PR637
PR638
1 0 1 1 1 0.925
11
12
13
14
15
16
17
18
19
20
PR639
2
1
499_0402_1%
2 1
PC612
2
GNDA_GPU_CORE 1 1 0 0 0 0.9
1
1 1 0 0 1 0.875
470P_0402_50V7K
PC613 PR640 PR641 1 1 0 1 0 0.85
47P_0402_50V8J~D 3.57K_0402_1% 0_0402_5%~D 1 1 0 1 1 0.825
1 2 1 2 1 2
+5V_RUN
1 1 1 0 0 0.8
PR643
ISEN2_VGA 0_0402_5%~D 1 1 1 0 1 0.775
1 2 1 2 1 2 +VGA_B+
ISEN1_VGA +VGA_B+
PC614 PR642
0.22U_0402_10V4Z
0.22U_0402_10V4Z
1
150P_0402_50V8J 324K_0402_1% 1 2
+5V_ALW
1
PR645
PC615
PC616
0.22U_0603_25V7K
PR644 1_0402_5%
1U_0603_10V6K
1
249K_0402_1%
PC617
PC618
2200P_0402_50V7K
2
BOOT1_VGA
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K
2
5
B B
2
1
@
PC619
PC620
PC621
PC622
GNDA_GPU_CORE GNDA_GPU_CORE
PQ604
PQ605
2
UGATE1_VGA 4 4
VSUM+_VGA
VSUM-_VGA
@EMC@
@EMC@
1 2
82.5_0402_5%
+VGA_COREP
PR649 PC623
1
PR646 2.2_0603_5% 0.22U_0603_10V7K

PR647
3
2
1
3
2
1
1
10_0402_5% 2 1 BOOT1_1_VGA 1 2
2.61K_0402_1%
PL601 +VGA_COREP
PR648
@ 0.22UH_PCME064T_R22MS_28A_20%
1 2
<51> GPU_VDD_SENSE
2
PHASE1_VGA 4 1
0.01U_0402_25V7K
PR650
0.22U_0603_10V7K
.1U_0402_16V7K~D
1
0_0402_5%~D V1P_VGA 3 2 V1N_VGA

PC625
1
5
PC624 PQ606 PQ607
4.7_1206_5%
1
1
330P_0402_50V7K
PC626
PC627
@EMC@ PR653
10K_0402_5%
3.65K_0402_1%
2
1
@
PR651
1 1
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
PR654
PC678
@ 1_0402_5% + +
PR652
PC628
PC629
GNDA_GPU_CORE
2
LGATE1_VGA 4 4
1SNUB_GPU_P1 2
2
1
@ @ PR656
11K_0402_1%
2
1
PC630 PH601 0_0402_5% 2 2

PR655
1000P_0402_50V7K
PR657 1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ 1 2 V2N_VGA

0_0402_5%~D
2
1
2
3
1
2
3
1 2 VSUM+_VGA VSUM-_VGA
<51> GPU_VSS_SENSE
2
Layout Note:
680P_0603_50V7K
PR658 PR659 Place near Phase1 Choke ISEN1_VGA
@EMC@ PC631
10_0402_5% 1.37K_0402_1%
1 2 1 2 VSUM-_VGA
2
OCP setting
@ PJP601
A Ri = PR659 1 2 A
1
PC632
.1U_0402_16V7K
PAD-OPEN 4x4m
2
@ PJP602 @ PJP603
1 2 +VGA_COREP 1 2 +GPU_CORE
PAD-OPEN1x1m
PAD-OPEN 4x4m
GNDA_GPU_CORE GNDA_GPU_CORE @ PJP604
1 2
www.Vinafix.vn
Title
PAD-OPEN 4x4m
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_+GPU_CORE
5 4 3 2 1
5 4 3 2 1
PCIE_VDDC_PWRGD 2 1 +3.3V_RUN
@ PR679
@PR679
10K_0402_5%
VFB=0.6V Vo=VFB*(1+PR683/PR684)=0.6*(1+5.9K/10K)=0.95V
@ PL603
PJP609 +VGA_PCIEP
4
D PU602 1UH_FDSD0420-H-1R0M-P3T_4.9A_20% D
+5V_ALW 2 1 PCIE_B+ 10 2 LX_PCIE 1 2
PG
2 1 PVIN LX
9 3
JUMP_43X79 PVIN LX
PR680 @EMC@
4.7_1206_5%
1
1
@EMC@ PC680 PC660 8
0.1U_0603_25V7K 22U_0805_10V6M SVIN +VGA_PCIE (0.95V)
6 FB_PCIE Ripple voltage -
2
FB
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
5
2
EN
1
SS
TP
LX
PC661
PC662
PC663
PC664
PR681 SY8036LDBC_DFN10_3x3
<66,67> DGPU_PWR_EN Frequency 1MHz
SNUB_PCIE
0_0402_5%~D
11
PC666 1
2
1 2EN_PCIE
TDC 3.2A
680P_0402_50V7K
0.1U_0402_10V7K
1
PC667 @EMC@
0.1U_0402_10V7K
PR683
Peak Current 4.56A
PC665
1
@ PR682 5.9K_0402_1% OCP current 5.47A
1
47K_0402_5% 2 1
@ Choke DCR 29mohm
2
+3.3V_RUN
2
PC668
1
1
2 1
C C
PR692 PR684 @
+VGA_PCIEP
PJP610
100K_0402_1% 10K_0402_1% 22P_0402_50V8J
2 1
+VGA_PCIEP +VGA_PCIE
2
2
@ PR697
@PR697 PR696 2 1
0_0402_5% 0_0402_5%~D
1 2 1 2 DGPU_PWR_EN JUMP_43X79 1.8Volt
Ripple voltage -
1
0.1U_0402_10V7K
1

110K_0402_1%
PC679
2 PQ610
1
G DMN65D8LW-7_SOT323-3
Frequency 1MHz
PR693
S 1.8V_PWRGD 2 1 +3.3V_RUN
<16,54> DGPU_PWR_EN#_Q
3
@
TDC 1.43A
2
@ PR685
2
@ 10K_0402_5%
Peak Current 2A
OCP current 2.46A
Choke DCR 27mohm
PU603 PL604
4
@ PJP611 1UH_NRS4018T1R0NDGJ_3.2A_30%
+3.3V_ALW 2 1 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
PG
PVIN LX +1.8V_RUNP
22U_0805_6.3VAM
0.1U_0603_25V7K
22P_0402_50V8J
B PAD-OPEN 1x2m~D 9 3 B
PVIN LX
1
4.7_0805_5%~D
1
1
@EMC@
PC669
PC670
@EMC@ PR686
PC671
8
SVIN PR687
6 1.8VSP_FB 20K_0402_1%
2
2
FB
47P_0402_50V8J~D
22U_0805_6.3VAM
22U_0805_6.3VAM
5
SNUB_1.8VSP 1
2
EN
@EMC@ PC674
NC
NC
TP
PC672
PC673
PR688
0_0402_5%~D
11
2
1 2 EN_1.8VSP
<66,67> DGPU_PWR_EN
1
680P_0603_50V7K
PC676 @EMC@
SYN470DBC_DFN10_3X3 PR689
0.1U_0402_10V7K
10K_0402_1%
1
PC675
@ PJP612
2
1
@ PR690 2 1
1M_0402_5%~D +1.8V_RUNP +1.8V_RUN_GFX
@ PAD-OPEN 1x2m~D
2
2
2
A DELL CONFIDENTIAL/PROPRIETARY A
VFB=0.6V Vo=VFB*(1+PR687/PR689)=0.6*(1+20K/10K)=1.8V Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_+VGA_PCIE/+1.8V_RUN_GFX
5 4 3 2 1
www.Vinafix.vn
5 4 3 2 1
@ PD700
2 1 EMC@ PL701
1UH_MMD-05CZ-1R0M-M7L_7A_20%
ES2AA-13-F_SMA2~D 2 1
PQ700 PR701 +PWR_SRC_AC CHAGER_SRC TYP MAX
SI4835DDY-T1-GE3_SO8~D +SDC_IN 0.01_1206_1% H/S Rds(on) 12.2mohm , 15mohm
8 1 @ PJP700
+DC_IN_SS
7 2 4 1 1 2 L/S Rds(on) 2.7mohm , 3.5mohm
6 3
Choke DCR 6.2mohm
22U_0805_25V6K
22U_0805_25V6K
0.1U_0603_25V7K
5 3 2 PAD-OPEN 4x4m
10U_0603_25V7K~D
@
Choke Itye:14.2A / Isat:15A
47P_0402_50V8J~D
1
1
PR700
PC735
PC734
PC701
PC702
4
0_0402_5%~D
PC700
1 2 PR702
DC_BLOCK_GC <70>
2
1
0_0402_5%~D D @ @ @ @
PR710 1 2 2 PQ701
<70> CSS_GC
0_0402_5%~D G NTR4502PT1G_SOT23-3~D
1
D <46,69> VCP D
1 2 D S
3
2 PQ703A
SI3993CDV-T1-GE3_TSOP6
VCP_1
G
PD701
@ PR727 @ PR729 PQ702 S
S
2 NTR4502PT1G_SOT23-3~D 5 6
D
+DOCK_PWR_BAR DOCK_DCIN_IS+ <44>
PU703 150K_0402_1% 100K_0402_1%
1 6 2 1 2 1 1
CSSN_1
REF Out
G
CSSP_1
1
CSSN_1 3 PQ703B
+DC_IN_SS @ PR703 SI3993CDV-T1-GE3_TSOP6
PR744 10K_0402_5%~D
BAT54CW_SOT323~D
S
44.2_0402_1% 2 1 2 4
D
100K_0402_1%
DOCK_DCIN_IS- <44>
2 5 2 1 @ PR708
GND IN-
2
1 2
PR706
0_0402_5%~D
0_0402_5%~D
100K_0402_1%
<70> +CHGR_DC_IN
1
3 4
PR705
G
+SDC_IN
3
V+ IN+ 1_0805_5%~D
PR704
2 1 CSSP_1 PC703 PC704
PR707
1
INA199A1DCKR_SC70-6~D 1U_0603_25V6K 0.1U_0402_25V6K PC705 PR709

0.1U_0603_25V7K
1
1
59_0402_1% PR742 1 2 1 2 1 2 0_0402_5%~D
PC720
2
PR736 10_1206_5% 1 2
DK_CSS_GC <70>
2
0.1U_0402_25V6K
GNDA_CHG
2
+SDC_IN
+PWR_SRC
GNDA_CHG PC706
1
PC707 PU700 1 2 Near PL700
Discrete current monitor circuit
316K_0402_1%
sense adapter 10U_0805_25V6K
ACN
ACP
2
2
2 1 +DCIN 20 16 BQ24715_REGN 1U_0603_10V6K~D
PR713
VCC REGN
PD702
5
PR714 BAT54HT1G_SOD323-2~D
+3.3V_ALW 49.9K_0402_1% 3 17 PR715
22U_0805_25V6K
22U_0805_25V6K
22U_0805_25V6K
22U_0805_25V6K
22U_0805_25V6K
22U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
1
1
2 1 CMSRC BTST 2.2_0603_1%
@ PC736
@ PC737
@ PC738
1 2
1
PQ705
PC710
PC711
PC712
PC713
PC714
PC739
PC740
PC731
PC732
PQ704
2 1 4 18 CHG_UGATE 4 4
ACDRV HIDRV
8
@ PU702A
PC709
2
1
0.047U_0603_25V7K~D
VCP_1 3 PC708 0.1U_0402_25V6 @ @
BQ24715_REGN
P
IN+ 1 GNDA_CHG CHARGER_SMBCLK
@EMC@
C C
2 O VCP 6 19
CHARGER_SMBDAT
3
2
1
3
2
1
IN- ACDET PHASE
G
<46,69> CHG_PHASE
pull up 10K in HW side (R827 R828)
4
<46> CHARGER_SMBDAT 8 15 CHG_LGATE

SDA LODRV +PWR_SRC
1
PR741 9 14 PR716
<46> CHARGER_SMBCLK SCL GND +VCHGR
100K_0402_1% PL700 0.01_1206_1%
PR717 2.2UH_FDVE1040-H-2R2M-P3_14.2A_20%
2
0_0402_5%~D 2 1 4 1
1 2 5 13
<46,70> ACAV_IN ACOK SRP 3 2
PC717 @EMC@
SIRA14DP-T1GE3_POWERPAK-SO8-5
SIRA14DP-T1GE3_POWERPAK-SO8-5
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K
1
7 12
PR743 <46> V_SYS IOUT SRN PC715 EMC@
2SNUB_Charger 2
1
121K_0402_1% sense battery 1000P_0603_50V7K
PQ706
PQ711
PC718
PC719
2
1 2 10 11 4 4
+3.3V_ALW
2
2
PC716 CELL /BATDRV
TP
100P_0402_50V8J @ PR720 10K_0402_1% @
1
BQ24717
21
PR746
3
2
1
3
2
1
10K_0402_1% PR721 EMC@ @ PC721 PC722 PC723
GNDA_CHG BQ24715_REGN 1 2 4.7_1206_5%~D 0.1U_0402_25V6K 0.1U_0402_25V6K 0.1U_0402_25V6K
GNDA_CHG 1 2 1 2 1 2
PR745
0_0402_5%~D
1
1 2 @ PJP701 PR718 GNDA_CHG GNDA_CHG
<70> CHARGER_CELL_PIN 1 2 0_0402_5%~D
@ PR747 1 2
0_0402_5%~D
+3.3V_ALW2 1 2 PAD-OPEN1x1m PR719
GNDA_CHG 0_0402_5%~D
1 2
B B
+5V_ALW
H_PROCHOT# <7,46,65,70>
PR722
100P_0402_50V8J
0.01U_0402_25V7K~D
DYN_TUR_CURRENT_SET# 4.02K_0402_1%
1 2 BATDRV# <70>
1
1
PC724
PC725
221K_0402_1%
2
PR723
90W High (6.61A)

2
+3.3V_ALW2 @ @ PR724 Judge AC form NB side not DOCK side

+5V_ALW PR725 0_0402_5%~D
1.8M_0402_1%
1
1 2
130W Low (8.66A)
1
1
+3.3V_ALW2
PR726 BQ24715_REGN
PROCHOT_AD_POTC <70> +DC_IN
150K_0402_1% PR728
8
20K_0402_1% PR734
10K_0402_1%
VCP 1 2 3 1M_0402_1%
232K_0402_1%
P
48.7K_0402_1%
2
+
6
1
1 1 2
2 O
PR732
PR733
PR735
-
G
PU701A +5V_ALW
PQ707A
PQ707B
AS393MTR-G1_SO8 2 5
220P_0402_50V8J~D
1.3V (90W)
249K_0402_1%
162K_0402_1%
1200P_0402_50V7K
2
1
PC727
1.713V (130W)
100P_0402_50V8J
4
1
8
+3.3V_ALW 1.73V PR737
PC728
<46,70>
1
5 0_0402_5%~D
PR730
PR731
PC726
P
2
+ 7 1 2
2
6 O ACAV_IN_NB
10K_0402_1%
22.6K_0402_1%
42.2K_0402_1%
100P_0402_50V8J
2
G
PU701B
100P_0402_50V8J
2
1
1.47V AS393MTR-G1_SO8
4
1
1
PR748
PC729
PR738
PR739
PC730
PR740
1
D +3.3V_ALW 100K_0402_5%
2 PC733
<46> DYN_TUR_CURRNT_SET#
2
G @ PR749 0.1U_0402_25V4Z~D
2
2
PQ709 S 0_0402_5%~D
3
DMN65D8LW-7_SOT323-3 <46> MODULE_BATT_PRES# 1 2 2 1

5
A Use MODULE_BATT_PRES# to disable H_PROCHOT# funtion when AC+ E5 Battery. PU704 A

1
1 D
P
4 B 2
O ACAV_IN <22,40,53>
2 G
A PROCHOT_GATE <39>
G
S PQ710
3
To preset system to throtlle DMN65D8LW-7_SOT323-3

Adapter Protection Circuit for Turbo Mode DELL CONFIDENTIAL/PROPRIETARY
3
74AHC1G08GW_SSOP5~D switching from AC to DC

Title
www.Vinafix.vn
PWR_Charger for DSC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9411P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, April 10, 2013 Sheet 68 of 77
5 4 3 2 1
5 4 3 2 1
PQ801
@ PD801 @ PD802 NTR4502PT1G_SOT23-3~D +3.3V_ALW
All de-pop for droop module media battery PDS5100H-13_POWERDI5-3~D SDMK0340L-7-F_SOD323-2~D PC801 PR801
D
3 +MPBATT_IN_SS 2 1 3 1 0.1U_0402_10V7K~D 100K_0402_5%
+NBDOCK_DC_IN_SS
+BATT_SUM 1 1 2 2 1
2
Purpose: Trigger PROCHOT# when +3.3V_ALW
47K_0402_5% 240K_0402_5%
1
6
active battery is removed from
G
2
5
@PQ803
@PQ803
PR804
100K_0402_5%
system.
2
SI4835DDY-T1-GE3_SO8~D SLICE_BAT_PRES# 1 PQ802A
P
1 8 B 4 2 DMN66D0LDW-7_SOT363-6~D
PR803
2 7 Allows EC to re-establish SLICE_BAT_ON 2 O
2
A
G
+3.3V_ALW
3 6 system performance for battery H_PROCHOT# <7,46,65,69>
1
@ 5
3
next in line.
2
De-pop for droop module media battery PU801
+3.3V_ALW2 +3.3V_ALW2 74AHC1G08GW_SOT353~D
PR802
4
1
@ PR806 +3.3V_ALW
@ PQ804 330K_0402_5%~D @ PC802 PR807
10K_0402_5%~D
1
3
1 8 1 2 0.1U_0402_10V7K~D
100K_0402_5%
100K_0402_5%
6 1
S D
2
2 7 PR808 1 2
PR800
PR805
+MBATT S D
PD800 3 6 100K_0402_5% PQ805B
2
S D
3
D PDS5100H-13_POWERDI5-3~D 4 5 5 DMN66D0LDW-7_SOT363-6~D D
G D
5
3 @ @ PQ807A
2
1 FDS6679AZ_G_SO8~D DMN66D0LDW-7_SOT363-6~D 2 MODULE_BATT_PRES# 1 PQ802B
P
+VCHGR
4
2 B 4 5 DMN66D0LDW-7_SOT363-6~D
O
2
@ PR809 2
DMN66D0LDW-7 2N_SOT363-6~D
MODULE_ON
1
A
G
3
PQ800 @ PD803 820_0603_1%~D
SDMK0340L-7-F_SOD323-2~D
4
SI4835DDY-T1-GE3_SO8~D SDMK0340L-7-F_SOD323-2~D 1 2 MB_MBSS_GC
PQ808B
3
1 8 2 1 @ PD804 PQ807B
6
2 7 <45,70> SLICE_BAT_ON DMN66D0LDW-7_SOT363-6~D 5 +3.3V_ALW
6 1
1
3 6 @ PC800 SLICE_BAT_PRES# <44,45,70> PU802 @
5 @ 0.01U_0603_25V7K~D 74AHC1G08GW_SOT353~D PQ805A
1
MB_MBSS_GC 5 @ PQ808A De-pop for droop module media battery 2 DMN66D0LDW-7_SOT363-6~D
2
DMN66D0LDW-7 2N_SOT363-6~D PR810
4
2 100K_0402_5%
1
+PWR_SRC_AC +3.3V_ALW
1
@ PD805 @ PC804
2
<69> BATDRV# SDMK0340L-7-F_SOD323-2~D 0.1U_0402_10V7K~D
PC803 @EMC@ 1 2 +3.3V_ALW
MODULE_BATT_PRES# <45,60,70> 1 2 PC805
PD807 0.1U_0402_10V7K~D
5
PD806 SDMK0340L-7-F_SOD323-2~D 0.1U_0603_25V7K @ PU803 1 2
PD818
PDS5100H-13_POWERDI5-3~D PC806 @EMC@ SLICE_BAT_ON 1
PQ806B
PQ806A
P
3 +PBATT_IN_SS 2 1 1 2 INA 4 5 2 1 2
O CHARGER_CELL_PIN <69>
5
1 MODULE_ON 2 PU804
INB
G
2 2200P_0402_50V7K PR811 PBAT_PRES# 1
P
4
1
PC807 0_0402_5%~D 74AHC1G32GW_SOT353-5~D B 4 SDMK0340L-7-F_SOD323-2~D
3
1 2 2 1 2 O
PQ809 A
G
SI4835DDY-T1-GE3_SO8~D
1 8 0.47U_0805_25V7K~D 1 2
<45,70> SLICE_BAT_ON
3
STSTART_DCBLOCK_GC
2 7
3 6 PR888 PR812
1
2
3
5 0_0402_5%~D 0_0402_5%~D 74AHC1G08GW_SOT353~D
PDS5100H-13_POWERDI5-3~D
1
PQ810 1 2
100K_0402_5%
<45> DIS_BAT_PROCHOT#
2
FDS6679AZ-G_SO8~D
4
4
PR813
PD808
@
PD809
1
+3.3V_ALW2
3
1 2 PR814
330K_0402_5% PC808
Purpose: Turn on the PQ817
8
7
6
5
+3.3V_ALW2 2 1 0.1U_0402_10V7K~D
10K_0402_5%
1
2 1 for primary or module bay

PU805
PR815
battery to provide power to

+3.3V_ALW2 74AHC1G08GW_SOT353~D
2
5
C C
PQ811 FDS6679AZ-G_SO8~D PR817 PC810
100K_0402_5%
dock side without AC exist.
2
PR816 330K_0402_5% +DOCK_PWR_BAR 0.1U_0402_10V7K~D 1
P
2 2
1
1 8 @ PC809 2 1 4 SLICE_BAT_PRES# <44,45,70>
PR818
100K_0402_5% +PBATT O
2 7 1 2 1500P_0402_7K~D PU806 2 1 2 +3.3V_ALW2
A
G
3 6 74AHC1G08GW_SOT353~D PR819
PD811
5
5 100K_0402_5%
1
@ PD812 1 D
P
SDMK0340L-7-F_SOD323-2~D 4 B 2 DOCK_DET# <44,45>
6 1
4
O
1 2 2 1 2 ACAV_IN# G
SLICE_BAT_ON <45,70> A
G
3
1
2
3
1
2
3
10K_0402_5%
S
FDS6679AZ-G_SO8~D
FDS6679AZ-G_SO8~D
3
1
PR890 PR821 PR820 PQ817
3
0_0402_5%~D 820_0603_1%~D 0_0402_5%~D DMN65D8LW-7_SOT323-3
PQ812A
PQ812B
PR822
2 5 1 2 1 2 1 2 PB_PBSS_GC 4 4
PQ815
@ PR891
PQ826
0_0402_5%~D
1
2
1
1 2 PB_PBSS_GC 1 2 3301_DSCHRG_FET_GC 2
Purpose: Turn on the PQ815
AO3418_SOT23-3
1
@ PR889 PC811 D
0_0402_5%~D 0.01U_0603_25V7K~D PR892 2 1 +3.3V_ALW2 +3.3V_ALW2 for Slice battery discharge
PQ816
2
8
7
6
5
8
7
6
5
0_0402_5%~D G +3.3V_ALW2
S 3 PC812 without AC exist
2
PBAT_PRES# Vth: 0.5~1.5 0.1U_0402_10V7K~D
<45,60,70> 2 1 PR823 PR824 @
PD814 BAT54CW_SOT323~D PU807 100K_0402_5% 100K_0402_5%
1
74AHC1G08GW_SOT353~D
5
All de-pop for droop module media battery PD816
1
BAT54CW_SOT323~D 1
P
B SLICE_BAT_ON <45,70>
4
O
3
+3.3V_ALW 2 1 2
A
G
2

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A B C D E

REV : 1.0 (A00)

PXDP@ : PCH XDP

Block Diagram AMD

(PERN1/USBRN3) Lynx Point USB Option

P25 USB3.0 Repeater USB3.0[5]

Card Reader USB3.0 Repeater USB3.0[6]

W25Q32FV SATA Repeater

RFID HDD MDC HDA Codec INT.Speaker

CPU XDP Port LPC BUS PCIE4 E-Module FFS RJ11

WiFi ON/OFF SMSC KBC

USB 2.0 USB 3.0

9 6 Left Side (JUSB4)

SATA 4 (SATA_TXN4/PETN1) WWAN (JMINI1)

Lane 6 Pink Pather (JMINI3)

Lane 7 Express card (JEXP1)

DDID Dock DP port 2

PCH_ALW_ON TP0610K-T1-E3 TPS22966 TPS22966

ISL95812 RT8207MZQW RT8207MZQW TPS51212DSCR

DGPU_PWR_EN# Pop option

+3.3V_ALW +3.3V_PCIE +3.3V_PCIE

+1.05V_RUN DELL CONFIDENTIAL/PROPRIETARY

JCPU1A Haswell rPGA EDS

SM_DRAMPWROK with DDR Power Gating Topology

@ RC99 0_0603_5% @ RC48 2 1 0_0402_5% CPU_DMI E26 AP28 XDP_OBS7_R @ T88

PU/PD for JTAG signals

XDP_DBRESET# RC52 2 1 1K_0402_1%

XDP_TMS @ RC53 2 1 51_0402_1%

VCCPWRGOOD_0_R XDP_TDI @ RC54 2 1 51_0402_1%

@ SM_RCOMP0 RC58 1 2 100_0402_1% XDP_TCLK RC59 2 1 51_0402_1%

SM_RCOMP1 RC61 1 2 75_0402_1% XDP_TRST# RC62 2 1 51_0402_1%

JCPU1C Haswell rPGA EDS

Compal Electronics, Inc.

COMPENSATION PU FOR eDP

CAD Note:Trace width=20 mils ,Spacing=25mil,

TMDSB_CPU_N2 T28 M27 EDP_CPU_AUX#

CFG STRAPS for CPU

+1.35V_CPU_VDDQ Source +PWR_SRC_S +VCC_CORE

RC96 0_0402_5% @ PJP6 N11 AD28

@ T52 PAD~D AR35 AH30

@ T53 PAD~D AR32 AH31

AT33 VSS VCC AJ26

+VCC_CORE VCC L25

A10 AK34 B34 K10

DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14

+0.675V_DDR_VTT 127 128 @ RD5 0_0402_5%

133 134 @ RD13 0_0402_5%

DDR_A_DQS#4 135 136

B DDR_A_D34 141 142 DDR_A_D39 @ B

DDR_A_D48 163 164 DDR_A_D52

DDR_A_D49 165 166 DDR_A_D53

1 1 1 1 1 1 1 DDR_A_DQS#6 169 170

+ DDR_A_DQS6 171 172

@ RD4 205 206

CD45 @ 1 2 DIMM1_SA1 Title

Populate RD4, De-Populate RD9 for Intel DDR3

49 DQS2 VSS17 50 DDR_B_D22

127 128 @ RD10 0_0402_5%

133 134 @ RD23 0_0402_5%

DDR_B_D48 163 164 DDR_B_D52

+ DDR_B_DQS#6 169 170

@ RD11 0_0402_5% +0.675V_DDR_VTT

MCARD_PCIE_SATA# PXDP@ RH16 1 2 0_0402_5% XDP_FN12 23 24

PCH_GPIO49 PXDP@ RH19 1 2 0_0402_5% XDP_FN13 25 26