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 Table of Contents
Module 1: Introduction to Tessent MemoryBIST ...................................................... 11

Objectives .......................................................................................................................... 12

Tessent MemoryBIST Solution Components...................................................................... 13

Tessent MemoryBIST Implementation ............................................................................... 14

Memory BIST Hardware: Architecture ................................................................................ 15

Comparator Placement ...................................................................................................... 16

Tessent MemoryBIST Operating Protocol .......................................................................... 18

Scannable Memory Interface (Optional) ............................................................................. 21

Supported Memory Types .................................................................................................. 22

Key Features ...................................................................................................................... 23

Test Algorithms .................................................................................................................. 25

Built-In Standard Algorithms ............................................................................................... 26

Base Capabilities: Fault Coverage Summary ..................................................................... 27

Memory Library File for Each Memory (.tcd_mem_lib) ....................................................... 29

Memory Library Example.................................................................................................... 30

Hierarchical Bottom up Flow Advantages ........................................................................... 32

Tessent MemoryBIST Block Flow ...................................................................................... 33

Example: Design Architecture and Clocking....................................................................... 34

Generic Block Architecture ................................................................................................. 36

Tessent MemoryBIST Flow ................................................................................................ 37

Prerequisites ...................................................................................................................... 38

Tessent Shell Database (TSDB) ........................................................................................ 39

Typical TSDB Structure (First 2 Levels) ............................................................................. 40

Getting Help With Tessent Tools - Manuals ....................................................................... 41

Getting Help With Tessent Tools – Command Completion ................................................ 42

Accessing Support Center Material .................................................................................... 45

Tessent MemoryBIST 3
 Table of Contents
Lab1 ................................................................................................................................... 46

Virtual Lab Setup ................................................................................................................ 47

Module 2: Standard Memory BIST Flow .................................................................... 49

Objectives .......................................................................................................................... 50

Tessent MemoryBIST Flow ................................................................................................ 51

Tool Invocation ................................................................................................................... 53

Load Design: Contexts and Modes .................................................................................... 54

Load Design: System Modes.............................................................................................. 55

Load Design: Reading Design Netlists ............................................................................... 56

Load Design: Reading Libraries ......................................................................................... 57

Load Design: Elaborating the Design ................................................................................. 58

Load Design: Optional Data (after set_current_design) ..................................................... 59

Useful Design Data Reporting Commands ......................................................................... 60

Load Design (Review) ........................................................................................................ 61

Specify Requirements: Design Level .................................................................................. 62

Specify Requirements: Memory BIST Options ................................................................... 64

Specify Requirements: Memory Instance Options .............................................................. 65

add_input_constraints ........................................................................................................ 66

set_attribute_value ............................................................................................................. 67

Specify Requirements: Clocks............................................................................................ 68

Specify Requirements: DRCs ............................................................................................. 69

Specify Requirements: Review........................................................................................... 70

Tessent MemoryBIST Flow ................................................................................................ 71

Create the DftSpecification ................................................................................................. 72

DFTSpecification: report_config_data ................................................................................ 73

DFTSpecification: display_specification ............................................................................. 74

Tessent MemoryBIST 4
 Table of Contents
DFTSpecification: Insert Test Logic .................................................................................... 75

blockA: Design ................................................................................................................... 76

blockA: DFTSpecification ................................................................................................... 77

blockA: Post DFTSpecification Processing Block Diagram ................................................ 78

blockB: Design ................................................................................................................... 79

blockB: DFTSpecification ................................................................................................... 80

blockB: Block Diagram ....................................................................................................... 81

DFTSpecification: Review .................................................................................................. 82

Tessent MemoryBIST Flow ................................................................................................ 83

Extract ICL ......................................................................................................................... 84

Patterns Specification ......................................................................................................... 85

Extract ICL and PatternsSpecification Review ................................................................... 86

Tessent MemoryBIST Flow ................................................................................................ 87

Simulation Validation .......................................................................................................... 88

Basic Flow Review ............................................................................................................. 89

Lab 2 .................................................................................................................................. 90

Module 3: Clocks and Clock DRCs ............................................................................ 91

Objectives .......................................................................................................................... 92

Typical Clocking Network for Memories ............................................................................. 93

Defining Clocks .................................................................................................................. 94

Defining and Managing Clocks – Option 1 ......................................................................... 95

Defining and Managing Clocks – Option 2 ......................................................................... 96

Add / Define Clocks ............................................................................................................ 97

Clock Gating Cells .............................................................................................................. 98

Clock Muxes ...................................................................................................................... 100

Defining and Managing Clocks – Option 3 ........................................................................ 101

Tessent MemoryBIST 5
 Table of Contents
DefaultsSpecification: IjtagNetwork ................................................................................... 126

DefaultsSpecification: BoundaryScan ............................................................................... 128

DefaultsSpecification: MemoryBisr .................................................................................... 131

DefaultsSpecification: MemoryBist .................................................................................... 132

DefaultsSpecification: ControllerOptions ........................................................................... 133

DefaultsSpecification: DiagnosisOptions ........................................................................... 134

DefaultsSpecification: RepairOptions ................................................................................ 135

DefaultsSpecification: AlgorithmResourceOptions ............................................................ 136

DefaultsSpecification: MemoryInterfaceOptions ................................................................ 137

DefaultsSpecifications Editing Options .............................................................................. 138

Specification Editing Options ............................................................................................. 139

Editing in the GUI .............................................................................................................. 140

Editing Using Command Line ............................................................................................ 143

Command Line / Dofile ...................................................................................................... 145

Lab 4 ................................................................................................................................. 147

Module 5: Memory BIST Hierarchical Top Level Flow ............................................ 149

Objectives ......................................................................................................................... 150

Top Level Tessent MemoryBIST Flow .............................................................................. 151

Top Level Flow Differences ............................................................................................... 152

TAP Features .................................................................................................................... 153

BoundaryScan Requirements ........................................................................................... 154

TAP/Boundary Scan Interface ........................................................................................... 155

Boundary Scan Cells ......................................................................................................... 156

BoundaryScan Insertion .................................................................................................... 157

BoundaryScan: Additional Attributes ................................................................................. 158

Tessent MemoryBIST 6
 Table of Contents
Clock Divider / ICL ............................................................................................................ 102

Clock Divider / PDL ........................................................................................................... 103

DFT Specification .............................................................................................................. 104

Core: Design ..................................................................................................................... 105

Core: DFTSpecification ..................................................................................................... 106

Core: Block Diagram ......................................................................................................... 107

PatternsSpecification......................................................................................................... 108

Pre-DFT Clock Rules (DFT_C rules) ................................................................................. 111

Pre-DFT Clock Rule DFT_C1 ............................................................................................ 112

Pre-DFT Clock Rule DFT_C2 ............................................................................................ 113

Pre-DFT Clock Rule DFT_C3 ............................................................................................ 114

Pre-DFT Clock Rule DFT_C4 ............................................................................................ 115

Pre-DFT Clock Rule DFT_C5 ............................................................................................ 116

Lab 3 ................................................................................................................................. 117

Module 4: DefaultsSpecification and DFTSpecification ......................................... 119

Objectives ......................................................................................................................... 120

Specifications .................................................................................................................... 121

DefaultsSpecification ......................................................................................................... 122

DefaultsSpecification Wrappers ........................................................................................ 123

DefaultsSpecification: PatternsSpecification ..................................................................... 124

DefaultsSpecification: DftSpecification .............................................................................. 125

Pin Order File .................................................................................................................... 161

BoundaryScan in DftSpecification ..................................................................................... 164

Bonding Configurations ..................................................................................................... 165

BoundaryScan in PatternsSpecification ............................................................................ 167

Top Level Tessent MemoryBIST Flow .............................................................................. 168

Tessent MemoryBIST 7
 Table of Contents
Load Design ...................................................................................................................... 169

Specify Requirements ....................................................................................................... 170

Top Level Tessent MemoryBIST Flow .............................................................................. 171

DftSpecification ................................................................................................................. 172

Top: Design ....................................................................................................................... 173

Top: DFTSpecification ....................................................................................................... 174

Top: Block Diagram ........................................................................................................... 175

Top Level Tessent MemoryBIST Flow .............................................................................. 176

Extract ICL ........................................................................................................................ 177

Top Level Tessent MemoryBIST Flow .............................................................................. 178

PatternsSpecification......................................................................................................... 179

Tessent MemoryBIST Flow ............................................................................................... 183

Simulation Validation ......................................................................................................... 184

Manufacturing Patterns ..................................................................................................... 185

Lab 5: The Memory BIST Hierarchical Top Flow .............................................................. 189

Module 6: Memory BIST Debug Patterns................................................................. 191

Objectives ......................................................................................................................... 192

Debug and Characterization Patterns ............................................................................... 193

PatternsSpecification: Default ........................................................................................... 194

Creating Debug Patterns: Design loading ......................................................................... 195

Testing a Single Test Step ................................................................................................ 197

Testing a Single Memory ................................................................................................... 199

Review: Define Alternate Algorithms in DftSpecification ................................................... 201

Apply Alternate Algorithms ................................................................................................ 202

Testing Single Memory and Alternate Algorithm ............................................................... 203

Test Time Multiplier ........................................................................................................... 204

Tessent MemoryBIST 8
 Table of Contents
Diagnosis and Debug ........................................................................................................ 205

Identify Failing Memory ..................................................................................................... 206

Memory-Level Only: comparator_location : per_interface ................................................. 207

Identify Failing Memory: comparator_location : shared_in_controller ............................... 208

Identify Failing Memory : comparator_location : shared_in_controller .............................. 209

Memory Address Level / Offline Bit Mapping..................................................................... 210

Lab 6: Debug Patterns...................................................................................................... 212

Module 7: Built-In Self Repair ................................................................................... 213

Objectives ......................................................................................................................... 214

Tessent MemoryBIST Solution Components: BIRA and BISR .......................................... 215

Self-Repair Architecture .................................................................................................... 216

Self-Repair Benefits .......................................................................................................... 220

Repair Analysis ................................................................................................................. 221

Repair Analysis — Row OR Column ................................................................................. 222

Repair Analysis — Row AND Column ............................................................................... 223

RedundancyAnalysis Wrapper .......................................................................................... 224

Repair Analysis — Row AND Column ............................................................................... 225

Fully Autonomous Self-Repair ........................................................................................... 226

Summary: Manufacturing Repair Flow .............................................................................. 228

Support for Power Domains .............................................................................................. 231

Implementing Repair with Tessent MemoryBIST .............................................................. 232

Load Design / Options ....................................................................................................... 233

DftSpecification: RepairOptions......................................................................................... 234

DftSpecification: MemoryBISR .......................................................................................... 235

Design Rule Checks .......................................................................................................... 236

Implementing Repair with Tessent MemoryBIST .............................................................. 237

Tessent MemoryBIST 9
 Table of Contents
DftSpecification ................................................................................................................. 238

Implementing Repair With Tessent MemoryBIST .............................................................. 239

PatternsSpecification......................................................................................................... 240

Implementing Repair With Tessent MemoryBIST .............................................................. 241

Testbench Simulations ...................................................................................................... 242

FuseBox ............................................................................................................................ 243

Fuse Box .tcd_fbox............................................................................................................ 244

Additional BISR Options .................................................................................................... 245

Lab 7: Repair Flow ........................................................................................................... 246

Module 8: Additional Topics ..................................................................................... 247

Objectives ......................................................................................................................... 248

Synthesis ........................................................................................................................... 249

Synthesis / Scan................................................................................................................ 250

IJTAG (IEEE 1687) Motivation .......................................................................................... 251

Tessent IJTAG Use Model of IEEE 1687 .......................................................................... 252

How IJTAG Extends the Use of JTAG ............................................................................... 253

Operation Example: Accessing Instruments ...................................................................... 254

Setup to Enable Access to BLOCK1/TDR ......................................................................... 255

Enable Access BLOCK1/TDR .......................................................................................... 256

Load Data into BLOCK1/TDR — Enable Block2/TDR ...................................................... 257

Load Data into BLOCK2/TDR .......................................................................................... 258

ICL Network Extraction ..................................................................................................... 259

PDL Retargeting ............................................................................................................... 260

Tessent SiliconInsight Overview....................................................................................... 261

Motivation ......................................................................................................................... 262

Tessent SiliconInsight Desktop in Tessent Shell .............................................................. 263

Tessent MemoryBIST 10
 Table of Contents
Tessent SiliconInsight for Memory BIST........................................................................... 264

Interactive Memory BIST Diagnosis ................................................................................. 265

Volume ATE Memory BIST Offline ATE Diagnosis .......................................................... 266

Lab 8 ................................................................................................................................ 267

Tessent Connect: End-To-End DFT Automation .............................................................. 268

Accessing Support Center Material .................................................................................. 270

Customer Support ............................................................................................................ 271

Related Courses............................................................................................................... 272

Tessent MemoryBIST 11